1 /*******************************************************************************
4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *******************************************************************************/
31 * Shared functions for accessing and configuring the MAC
36 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
37 static void e1000_phy_init_script(struct e1000_hw *hw);
38 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
39 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
40 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
41 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
42 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
43 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
45 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
47 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
48 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
49 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
50 uint16_t words, uint16_t *data);
51 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
52 uint16_t offset, uint16_t words,
54 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
55 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
57 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
59 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
61 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
63 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
64 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
65 static void e1000_release_eeprom(struct e1000_hw *hw);
66 static void e1000_standby_eeprom(struct e1000_hw *hw);
67 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
70 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
71 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
72 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
73 static int32_t e1000_check_downshift(struct e1000_hw *hw);
74 static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
75 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
76 static void e1000_clear_vfta(struct e1000_hw *hw);
77 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
78 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
80 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
81 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
82 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
83 static int32_t e1000_get_cable_length(struct e1000_hw *hw,
85 uint16_t *max_length);
86 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
87 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
88 static int32_t e1000_id_led_init(struct e1000_hw * hw);
89 static void e1000_init_rx_addrs(struct e1000_hw *hw);
90 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
91 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
92 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
93 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,
94 uint16_t words, uint16_t *data);
95 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
96 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
97 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
99 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
102 #define E1000_WRITE_REG_IO(a, reg, val) \
103 e1000_write_reg_io((a), E1000_##reg, val)
104 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
106 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
108 /* IGP cable length table */
110 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
111 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
112 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
113 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
114 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
115 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
116 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
117 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
118 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
121 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
122 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
123 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
124 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
125 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
126 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
127 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
128 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
129 104, 109, 114, 118, 121, 124};
132 /******************************************************************************
133 * Set the phy type member in the hw struct.
135 * hw - Struct containing variables accessed by shared code
136 *****************************************************************************/
138 e1000_set_phy_type(struct e1000_hw *hw)
140 DEBUGFUNC("e1000_set_phy_type");
142 if(hw->mac_type == e1000_undefined)
143 return -E1000_ERR_PHY_TYPE;
146 case M88E1000_E_PHY_ID:
147 case M88E1000_I_PHY_ID:
148 case M88E1011_I_PHY_ID:
149 case M88E1111_I_PHY_ID:
150 hw->phy_type = e1000_phy_m88;
152 case IGP01E1000_I_PHY_ID:
153 if(hw->mac_type == e1000_82541 ||
154 hw->mac_type == e1000_82541_rev_2 ||
155 hw->mac_type == e1000_82547 ||
156 hw->mac_type == e1000_82547_rev_2) {
157 hw->phy_type = e1000_phy_igp;
160 case IGP03E1000_E_PHY_ID:
161 hw->phy_type = e1000_phy_igp_3;
164 case IFE_PLUS_E_PHY_ID:
166 hw->phy_type = e1000_phy_ife;
168 case GG82563_E_PHY_ID:
169 if (hw->mac_type == e1000_80003es2lan) {
170 hw->phy_type = e1000_phy_gg82563;
175 /* Should never have loaded on this device */
176 hw->phy_type = e1000_phy_undefined;
177 return -E1000_ERR_PHY_TYPE;
180 return E1000_SUCCESS;
183 /******************************************************************************
184 * IGP phy init script - initializes the GbE PHY
186 * hw - Struct containing variables accessed by shared code
187 *****************************************************************************/
189 e1000_phy_init_script(struct e1000_hw *hw)
192 uint16_t phy_saved_data;
194 DEBUGFUNC("e1000_phy_init_script");
196 if(hw->phy_init_script) {
199 /* Save off the current value of register 0x2F5B to be restored at
200 * the end of this routine. */
201 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
203 /* Disabled the PHY transmitter */
204 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
208 e1000_write_phy_reg(hw,0x0000,0x0140);
212 switch(hw->mac_type) {
215 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
217 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
219 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
221 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
223 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
225 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
227 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
229 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
231 e1000_write_phy_reg(hw, 0x2010, 0x0008);
234 case e1000_82541_rev_2:
235 case e1000_82547_rev_2:
236 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
242 e1000_write_phy_reg(hw, 0x0000, 0x3300);
246 /* Now enable the transmitter */
247 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
249 if(hw->mac_type == e1000_82547) {
250 uint16_t fused, fine, coarse;
252 /* Move to analog registers page */
253 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
255 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
256 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
258 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
259 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
261 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
262 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
263 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
264 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
265 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
267 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
268 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
269 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
271 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
272 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
273 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
279 /******************************************************************************
280 * Set the mac type member in the hw struct.
282 * hw - Struct containing variables accessed by shared code
283 *****************************************************************************/
285 e1000_set_mac_type(struct e1000_hw *hw)
287 DEBUGFUNC("e1000_set_mac_type");
289 switch (hw->device_id) {
290 case E1000_DEV_ID_82542:
291 switch (hw->revision_id) {
292 case E1000_82542_2_0_REV_ID:
293 hw->mac_type = e1000_82542_rev2_0;
295 case E1000_82542_2_1_REV_ID:
296 hw->mac_type = e1000_82542_rev2_1;
299 /* Invalid 82542 revision ID */
300 return -E1000_ERR_MAC_TYPE;
303 case E1000_DEV_ID_82543GC_FIBER:
304 case E1000_DEV_ID_82543GC_COPPER:
305 hw->mac_type = e1000_82543;
307 case E1000_DEV_ID_82544EI_COPPER:
308 case E1000_DEV_ID_82544EI_FIBER:
309 case E1000_DEV_ID_82544GC_COPPER:
310 case E1000_DEV_ID_82544GC_LOM:
311 hw->mac_type = e1000_82544;
313 case E1000_DEV_ID_82540EM:
314 case E1000_DEV_ID_82540EM_LOM:
315 case E1000_DEV_ID_82540EP:
316 case E1000_DEV_ID_82540EP_LOM:
317 case E1000_DEV_ID_82540EP_LP:
318 hw->mac_type = e1000_82540;
320 case E1000_DEV_ID_82545EM_COPPER:
321 case E1000_DEV_ID_82545EM_FIBER:
322 hw->mac_type = e1000_82545;
324 case E1000_DEV_ID_82545GM_COPPER:
325 case E1000_DEV_ID_82545GM_FIBER:
326 case E1000_DEV_ID_82545GM_SERDES:
327 hw->mac_type = e1000_82545_rev_3;
329 case E1000_DEV_ID_82546EB_COPPER:
330 case E1000_DEV_ID_82546EB_FIBER:
331 case E1000_DEV_ID_82546EB_QUAD_COPPER:
332 hw->mac_type = e1000_82546;
334 case E1000_DEV_ID_82546GB_COPPER:
335 case E1000_DEV_ID_82546GB_FIBER:
336 case E1000_DEV_ID_82546GB_SERDES:
337 case E1000_DEV_ID_82546GB_PCIE:
338 case E1000_DEV_ID_82546GB_QUAD_COPPER:
339 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
340 hw->mac_type = e1000_82546_rev_3;
342 case E1000_DEV_ID_82541EI:
343 case E1000_DEV_ID_82541EI_MOBILE:
344 case E1000_DEV_ID_82541ER_LOM:
345 hw->mac_type = e1000_82541;
347 case E1000_DEV_ID_82541ER:
348 case E1000_DEV_ID_82541GI:
349 case E1000_DEV_ID_82541GI_LF:
350 case E1000_DEV_ID_82541GI_MOBILE:
351 hw->mac_type = e1000_82541_rev_2;
353 case E1000_DEV_ID_82547EI:
354 case E1000_DEV_ID_82547EI_MOBILE:
355 hw->mac_type = e1000_82547;
357 case E1000_DEV_ID_82547GI:
358 hw->mac_type = e1000_82547_rev_2;
360 case E1000_DEV_ID_82571EB_COPPER:
361 case E1000_DEV_ID_82571EB_FIBER:
362 case E1000_DEV_ID_82571EB_SERDES:
363 hw->mac_type = e1000_82571;
365 case E1000_DEV_ID_82572EI_COPPER:
366 case E1000_DEV_ID_82572EI_FIBER:
367 case E1000_DEV_ID_82572EI_SERDES:
368 case E1000_DEV_ID_82572EI:
369 hw->mac_type = e1000_82572;
371 case E1000_DEV_ID_82573E:
372 case E1000_DEV_ID_82573E_IAMT:
373 case E1000_DEV_ID_82573L:
374 hw->mac_type = e1000_82573;
376 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
377 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
378 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
379 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
380 hw->mac_type = e1000_80003es2lan;
382 case E1000_DEV_ID_ICH8_IGP_M_AMT:
383 case E1000_DEV_ID_ICH8_IGP_AMT:
384 case E1000_DEV_ID_ICH8_IGP_C:
385 case E1000_DEV_ID_ICH8_IFE:
386 case E1000_DEV_ID_ICH8_IGP_M:
387 hw->mac_type = e1000_ich8lan;
390 /* Should never have loaded on this device */
391 return -E1000_ERR_MAC_TYPE;
394 switch(hw->mac_type) {
396 hw->swfwhw_semaphore_present = TRUE;
397 hw->asf_firmware_present = TRUE;
399 case e1000_80003es2lan:
400 hw->swfw_sync_present = TRUE;
405 hw->eeprom_semaphore_present = TRUE;
409 case e1000_82541_rev_2:
410 case e1000_82547_rev_2:
411 hw->asf_firmware_present = TRUE;
417 return E1000_SUCCESS;
420 /*****************************************************************************
421 * Set media type and TBI compatibility.
423 * hw - Struct containing variables accessed by shared code
424 * **************************************************************************/
426 e1000_set_media_type(struct e1000_hw *hw)
430 DEBUGFUNC("e1000_set_media_type");
432 if(hw->mac_type != e1000_82543) {
433 /* tbi_compatibility is only valid on 82543 */
434 hw->tbi_compatibility_en = FALSE;
437 switch (hw->device_id) {
438 case E1000_DEV_ID_82545GM_SERDES:
439 case E1000_DEV_ID_82546GB_SERDES:
440 case E1000_DEV_ID_82571EB_SERDES:
441 case E1000_DEV_ID_82572EI_SERDES:
442 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
443 hw->media_type = e1000_media_type_internal_serdes;
446 switch (hw->mac_type) {
447 case e1000_82542_rev2_0:
448 case e1000_82542_rev2_1:
449 hw->media_type = e1000_media_type_fiber;
453 /* The STATUS_TBIMODE bit is reserved or reused for the this
456 hw->media_type = e1000_media_type_copper;
459 status = E1000_READ_REG(hw, STATUS);
460 if (status & E1000_STATUS_TBIMODE) {
461 hw->media_type = e1000_media_type_fiber;
462 /* tbi_compatibility not valid on fiber */
463 hw->tbi_compatibility_en = FALSE;
465 hw->media_type = e1000_media_type_copper;
472 /******************************************************************************
473 * Reset the transmit and receive units; mask and clear all interrupts.
475 * hw - Struct containing variables accessed by shared code
476 *****************************************************************************/
478 e1000_reset_hw(struct e1000_hw *hw)
486 uint32_t extcnf_ctrl;
489 DEBUGFUNC("e1000_reset_hw");
491 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
492 if(hw->mac_type == e1000_82542_rev2_0) {
493 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
494 e1000_pci_clear_mwi(hw);
497 if(hw->bus_type == e1000_bus_type_pci_express) {
498 /* Prevent the PCI-E bus from sticking if there is no TLP connection
499 * on the last TLP read/write transaction when MAC is reset.
501 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
502 DEBUGOUT("PCI-E Master disable polling has failed.\n");
506 /* Clear interrupt mask to stop board from generating interrupts */
507 DEBUGOUT("Masking off all interrupts\n");
508 E1000_WRITE_REG(hw, IMC, 0xffffffff);
510 /* Disable the Transmit and Receive units. Then delay to allow
511 * any pending transactions to complete before we hit the MAC with
514 E1000_WRITE_REG(hw, RCTL, 0);
515 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
516 E1000_WRITE_FLUSH(hw);
518 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
519 hw->tbi_compatibility_on = FALSE;
521 /* Delay to allow any outstanding PCI transactions to complete before
522 * resetting the device
526 ctrl = E1000_READ_REG(hw, CTRL);
528 /* Must reset the PHY before resetting the MAC */
529 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
530 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
534 /* Must acquire the MDIO ownership before MAC reset.
535 * Ownership defaults to firmware after a reset. */
536 if(hw->mac_type == e1000_82573) {
539 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
540 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
543 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
544 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
546 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
549 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
556 /* Workaround for ICH8 bit corruption issue in FIFO memory */
557 if (hw->mac_type == e1000_ich8lan) {
558 /* Set Tx and Rx buffer allocation to 8k apiece. */
559 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
560 /* Set Packet Buffer Size to 16k. */
561 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
564 /* Issue a global reset to the MAC. This will reset the chip's
565 * transmit, receive, DMA, and link units. It will not effect
566 * the current PCI configuration. The global reset bit is self-
567 * clearing, and should clear within a microsecond.
569 DEBUGOUT("Issuing a global reset to MAC\n");
571 switch(hw->mac_type) {
577 case e1000_82541_rev_2:
578 /* These controllers can't ack the 64-bit write when issuing the
579 * reset, so use IO-mapping as a workaround to issue the reset */
580 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
582 case e1000_82545_rev_3:
583 case e1000_82546_rev_3:
584 /* Reset is performed on a shadow of the control register */
585 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
588 if (!hw->phy_reset_disable &&
589 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
590 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
591 * at the same time to make sure the interface between
592 * MAC and the external PHY is reset.
594 ctrl |= E1000_CTRL_PHY_RST;
597 e1000_get_software_flag(hw);
598 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
602 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
606 /* After MAC reset, force reload of EEPROM to restore power-on settings to
607 * device. Later controllers reload the EEPROM automatically, so just wait
608 * for reload to complete.
610 switch(hw->mac_type) {
611 case e1000_82542_rev2_0:
612 case e1000_82542_rev2_1:
615 /* Wait for reset to complete */
617 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
618 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
619 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
620 E1000_WRITE_FLUSH(hw);
621 /* Wait for EEPROM reload */
625 case e1000_82541_rev_2:
627 case e1000_82547_rev_2:
628 /* Wait for EEPROM reload */
632 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
634 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
635 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
636 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
637 E1000_WRITE_FLUSH(hw);
643 case e1000_80003es2lan:
644 ret_val = e1000_get_auto_rd_done(hw);
646 /* We don't want to continue accessing MAC registers. */
650 /* Wait for EEPROM reload (it happens automatically) */
655 /* Disable HW ARPs on ASF enabled adapters */
656 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
657 manc = E1000_READ_REG(hw, MANC);
658 manc &= ~(E1000_MANC_ARP_EN);
659 E1000_WRITE_REG(hw, MANC, manc);
662 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
663 e1000_phy_init_script(hw);
665 /* Configure activity LED after PHY reset */
666 led_ctrl = E1000_READ_REG(hw, LEDCTL);
667 led_ctrl &= IGP_ACTIVITY_LED_MASK;
668 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
669 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
672 /* Clear interrupt mask to stop board from generating interrupts */
673 DEBUGOUT("Masking off all interrupts\n");
674 E1000_WRITE_REG(hw, IMC, 0xffffffff);
676 /* Clear any pending interrupt events. */
677 icr = E1000_READ_REG(hw, ICR);
679 /* If MWI was previously enabled, reenable it. */
680 if(hw->mac_type == e1000_82542_rev2_0) {
681 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
682 e1000_pci_set_mwi(hw);
685 if (hw->mac_type == e1000_ich8lan) {
686 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
687 kab |= E1000_KABGTXD_BGSQLBIAS;
688 E1000_WRITE_REG(hw, KABGTXD, kab);
691 return E1000_SUCCESS;
694 /******************************************************************************
695 * Performs basic configuration of the adapter.
697 * hw - Struct containing variables accessed by shared code
699 * Assumes that the controller has previously been reset and is in a
700 * post-reset uninitialized state. Initializes the receive address registers,
701 * multicast table, and VLAN filter table. Calls routines to setup link
702 * configuration and flow control settings. Clears all on-chip counters. Leaves
703 * the transmit and receive units disabled and uninitialized.
704 *****************************************************************************/
706 e1000_init_hw(struct e1000_hw *hw)
711 uint16_t pcix_cmd_word;
712 uint16_t pcix_stat_hi_word;
719 DEBUGFUNC("e1000_init_hw");
721 /* Initialize Identification LED */
722 ret_val = e1000_id_led_init(hw);
724 DEBUGOUT("Error Initializing Identification LED\n");
728 /* Set the media type and TBI compatibility */
729 e1000_set_media_type(hw);
731 /* Disabling VLAN filtering. */
732 DEBUGOUT("Initializing the IEEE VLAN\n");
733 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
734 if (hw->mac_type != e1000_ich8lan) {
735 if (hw->mac_type < e1000_82545_rev_3)
736 E1000_WRITE_REG(hw, VET, 0);
737 e1000_clear_vfta(hw);
740 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
741 if(hw->mac_type == e1000_82542_rev2_0) {
742 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
743 e1000_pci_clear_mwi(hw);
744 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
745 E1000_WRITE_FLUSH(hw);
749 /* Setup the receive address. This involves initializing all of the Receive
750 * Address Registers (RARs 0 - 15).
752 e1000_init_rx_addrs(hw);
754 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
755 if(hw->mac_type == e1000_82542_rev2_0) {
756 E1000_WRITE_REG(hw, RCTL, 0);
757 E1000_WRITE_FLUSH(hw);
759 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
760 e1000_pci_set_mwi(hw);
763 /* Zero out the Multicast HASH table */
764 DEBUGOUT("Zeroing the MTA\n");
765 mta_size = E1000_MC_TBL_SIZE;
766 if (hw->mac_type == e1000_ich8lan)
767 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
768 for(i = 0; i < mta_size; i++) {
769 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
770 /* use write flush to prevent Memory Write Block (MWB) from
771 * occuring when accessing our register space */
772 E1000_WRITE_FLUSH(hw);
775 /* Set the PCI priority bit correctly in the CTRL register. This
776 * determines if the adapter gives priority to receives, or if it
777 * gives equal priority to transmits and receives. Valid only on
778 * 82542 and 82543 silicon.
780 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
781 ctrl = E1000_READ_REG(hw, CTRL);
782 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
785 switch(hw->mac_type) {
786 case e1000_82545_rev_3:
787 case e1000_82546_rev_3:
790 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
791 if(hw->bus_type == e1000_bus_type_pcix) {
792 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
793 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
795 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
796 PCIX_COMMAND_MMRBC_SHIFT;
797 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
798 PCIX_STATUS_HI_MMRBC_SHIFT;
799 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
800 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
801 if(cmd_mmrbc > stat_mmrbc) {
802 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
803 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
804 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
811 /* More time needed for PHY to initialize */
812 if (hw->mac_type == e1000_ich8lan)
815 /* Call a subroutine to configure the link and setup flow control. */
816 ret_val = e1000_setup_link(hw);
818 /* Set the transmit descriptor write-back policy */
819 if(hw->mac_type > e1000_82544) {
820 ctrl = E1000_READ_REG(hw, TXDCTL);
821 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
822 switch (hw->mac_type) {
829 case e1000_80003es2lan:
830 ctrl |= E1000_TXDCTL_COUNT_DESC;
833 E1000_WRITE_REG(hw, TXDCTL, ctrl);
836 if (hw->mac_type == e1000_82573) {
837 e1000_enable_tx_pkt_filtering(hw);
840 switch (hw->mac_type) {
843 case e1000_80003es2lan:
844 /* Enable retransmit on late collisions */
845 reg_data = E1000_READ_REG(hw, TCTL);
846 reg_data |= E1000_TCTL_RTLC;
847 E1000_WRITE_REG(hw, TCTL, reg_data);
849 /* Configure Gigabit Carry Extend Padding */
850 reg_data = E1000_READ_REG(hw, TCTL_EXT);
851 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
852 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
853 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
855 /* Configure Transmit Inter-Packet Gap */
856 reg_data = E1000_READ_REG(hw, TIPG);
857 reg_data &= ~E1000_TIPG_IPGT_MASK;
858 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
859 E1000_WRITE_REG(hw, TIPG, reg_data);
861 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
862 reg_data &= ~0x00100000;
863 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
868 ctrl = E1000_READ_REG(hw, TXDCTL1);
869 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
870 if(hw->mac_type >= e1000_82571)
871 ctrl |= E1000_TXDCTL_COUNT_DESC;
872 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
878 if (hw->mac_type == e1000_82573) {
879 uint32_t gcr = E1000_READ_REG(hw, GCR);
880 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
881 E1000_WRITE_REG(hw, GCR, gcr);
884 /* Clear all of the statistics registers (clear on read). It is
885 * important that we do this after we have tried to establish link
886 * because the symbol error count will increment wildly if there
889 e1000_clear_hw_cntrs(hw);
891 /* ICH8 No-snoop bits are opposite polarity.
892 * Set to snoop by default after reset. */
893 if (hw->mac_type == e1000_ich8lan)
894 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
896 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
897 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
898 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
899 /* Relaxed ordering must be disabled to avoid a parity
900 * error crash in a PCI slot. */
901 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
902 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
908 /******************************************************************************
909 * Adjust SERDES output amplitude based on EEPROM setting.
911 * hw - Struct containing variables accessed by shared code.
912 *****************************************************************************/
914 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
916 uint16_t eeprom_data;
919 DEBUGFUNC("e1000_adjust_serdes_amplitude");
921 if(hw->media_type != e1000_media_type_internal_serdes)
922 return E1000_SUCCESS;
924 switch(hw->mac_type) {
925 case e1000_82545_rev_3:
926 case e1000_82546_rev_3:
929 return E1000_SUCCESS;
932 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
937 if(eeprom_data != EEPROM_RESERVED_WORD) {
938 /* Adjust SERDES output amplitude only. */
939 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
940 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
945 return E1000_SUCCESS;
948 /******************************************************************************
949 * Configures flow control and link settings.
951 * hw - Struct containing variables accessed by shared code
953 * Determines which flow control settings to use. Calls the apropriate media-
954 * specific link configuration function. Configures the flow control settings.
955 * Assuming the adapter has a valid link partner, a valid link should be
956 * established. Assumes the hardware has previously been reset and the
957 * transmitter and receiver are not enabled.
958 *****************************************************************************/
960 e1000_setup_link(struct e1000_hw *hw)
964 uint16_t eeprom_data;
966 DEBUGFUNC("e1000_setup_link");
968 /* In the case of the phy reset being blocked, we already have a link.
969 * We do not have to set it up again. */
970 if (e1000_check_phy_reset_block(hw))
971 return E1000_SUCCESS;
973 /* Read and store word 0x0F of the EEPROM. This word contains bits
974 * that determine the hardware's default PAUSE (flow control) mode,
975 * a bit that determines whether the HW defaults to enabling or
976 * disabling auto-negotiation, and the direction of the
977 * SW defined pins. If there is no SW over-ride of the flow
978 * control setting, then the variable hw->fc will
979 * be initialized based on a value in the EEPROM.
981 if (hw->fc == e1000_fc_default) {
982 switch (hw->mac_type) {
985 hw->fc = e1000_fc_full;
988 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
991 DEBUGOUT("EEPROM Read Error\n");
992 return -E1000_ERR_EEPROM;
994 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
995 hw->fc = e1000_fc_none;
996 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
997 EEPROM_WORD0F_ASM_DIR)
998 hw->fc = e1000_fc_tx_pause;
1000 hw->fc = e1000_fc_full;
1005 /* We want to save off the original Flow Control configuration just
1006 * in case we get disconnected and then reconnected into a different
1007 * hub or switch with different Flow Control capabilities.
1009 if(hw->mac_type == e1000_82542_rev2_0)
1010 hw->fc &= (~e1000_fc_tx_pause);
1012 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1013 hw->fc &= (~e1000_fc_rx_pause);
1015 hw->original_fc = hw->fc;
1017 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1019 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1020 * polarity value for the SW controlled pins, and setup the
1021 * Extended Device Control reg with that info.
1022 * This is needed because one of the SW controlled pins is used for
1023 * signal detection. So this should be done before e1000_setup_pcs_link()
1024 * or e1000_phy_setup() is called.
1026 if (hw->mac_type == e1000_82543) {
1027 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1030 DEBUGOUT("EEPROM Read Error\n");
1031 return -E1000_ERR_EEPROM;
1033 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1035 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1038 /* Call the necessary subroutine to configure the link. */
1039 ret_val = (hw->media_type == e1000_media_type_copper) ?
1040 e1000_setup_copper_link(hw) :
1041 e1000_setup_fiber_serdes_link(hw);
1043 /* Initialize the flow control address, type, and PAUSE timer
1044 * registers to their default values. This is done even if flow
1045 * control is disabled, because it does not hurt anything to
1046 * initialize these registers.
1048 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1050 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1051 if (hw->mac_type != e1000_ich8lan) {
1052 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1053 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1054 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1057 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1059 /* Set the flow control receive threshold registers. Normally,
1060 * these registers will be set to a default threshold that may be
1061 * adjusted later by the driver's runtime code. However, if the
1062 * ability to transmit pause frames in not enabled, then these
1063 * registers will be set to 0.
1065 if(!(hw->fc & e1000_fc_tx_pause)) {
1066 E1000_WRITE_REG(hw, FCRTL, 0);
1067 E1000_WRITE_REG(hw, FCRTH, 0);
1069 /* We need to set up the Receive Threshold high and low water marks
1070 * as well as (optionally) enabling the transmission of XON frames.
1072 if(hw->fc_send_xon) {
1073 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1074 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1076 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1077 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1083 /******************************************************************************
1084 * Sets up link for a fiber based or serdes based adapter
1086 * hw - Struct containing variables accessed by shared code
1088 * Manipulates Physical Coding Sublayer functions in order to configure
1089 * link. Assumes the hardware has been previously reset and the transmitter
1090 * and receiver are not enabled.
1091 *****************************************************************************/
1093 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1099 uint32_t signal = 0;
1102 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1104 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1105 * until explicitly turned off or a power cycle is performed. A read to
1106 * the register does not indicate its status. Therefore, we ensure
1107 * loopback mode is disabled during initialization.
1109 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1110 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1112 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1113 * set when the optics detect a signal. On older adapters, it will be
1114 * cleared when there is a signal. This applies to fiber media only.
1115 * If we're on serdes media, adjust the output amplitude to value set in
1118 ctrl = E1000_READ_REG(hw, CTRL);
1119 if(hw->media_type == e1000_media_type_fiber)
1120 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1122 ret_val = e1000_adjust_serdes_amplitude(hw);
1126 /* Take the link out of reset */
1127 ctrl &= ~(E1000_CTRL_LRST);
1129 /* Adjust VCO speed to improve BER performance */
1130 ret_val = e1000_set_vco_speed(hw);
1134 e1000_config_collision_dist(hw);
1136 /* Check for a software override of the flow control settings, and setup
1137 * the device accordingly. If auto-negotiation is enabled, then software
1138 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1139 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1140 * auto-negotiation is disabled, then software will have to manually
1141 * configure the two flow control enable bits in the CTRL register.
1143 * The possible values of the "fc" parameter are:
1144 * 0: Flow control is completely disabled
1145 * 1: Rx flow control is enabled (we can receive pause frames, but
1146 * not send pause frames).
1147 * 2: Tx flow control is enabled (we can send pause frames but we do
1148 * not support receiving pause frames).
1149 * 3: Both Rx and TX flow control (symmetric) are enabled.
1153 /* Flow control is completely disabled by a software over-ride. */
1154 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1156 case e1000_fc_rx_pause:
1157 /* RX Flow control is enabled and TX Flow control is disabled by a
1158 * software over-ride. Since there really isn't a way to advertise
1159 * that we are capable of RX Pause ONLY, we will advertise that we
1160 * support both symmetric and asymmetric RX PAUSE. Later, we will
1161 * disable the adapter's ability to send PAUSE frames.
1163 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1165 case e1000_fc_tx_pause:
1166 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1167 * software over-ride.
1169 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1172 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1173 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1176 DEBUGOUT("Flow control param set incorrectly\n");
1177 return -E1000_ERR_CONFIG;
1181 /* Since auto-negotiation is enabled, take the link out of reset (the link
1182 * will be in reset, because we previously reset the chip). This will
1183 * restart auto-negotiation. If auto-neogtiation is successful then the
1184 * link-up status bit will be set and the flow control enable bits (RFCE
1185 * and TFCE) will be set according to their negotiated value.
1187 DEBUGOUT("Auto-negotiation enabled\n");
1189 E1000_WRITE_REG(hw, TXCW, txcw);
1190 E1000_WRITE_REG(hw, CTRL, ctrl);
1191 E1000_WRITE_FLUSH(hw);
1196 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1197 * indication in the Device Status Register. Time-out if a link isn't
1198 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1199 * less than 500 milliseconds even if the other end is doing it in SW).
1200 * For internal serdes, we just assume a signal is present, then poll.
1202 if(hw->media_type == e1000_media_type_internal_serdes ||
1203 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1204 DEBUGOUT("Looking for Link\n");
1205 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1207 status = E1000_READ_REG(hw, STATUS);
1208 if(status & E1000_STATUS_LU) break;
1210 if(i == (LINK_UP_TIMEOUT / 10)) {
1211 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1212 hw->autoneg_failed = 1;
1213 /* AutoNeg failed to achieve a link, so we'll call
1214 * e1000_check_for_link. This routine will force the link up if
1215 * we detect a signal. This will allow us to communicate with
1216 * non-autonegotiating link partners.
1218 ret_val = e1000_check_for_link(hw);
1220 DEBUGOUT("Error while checking for link\n");
1223 hw->autoneg_failed = 0;
1225 hw->autoneg_failed = 0;
1226 DEBUGOUT("Valid Link Found\n");
1229 DEBUGOUT("No Signal Detected\n");
1231 return E1000_SUCCESS;
1234 /******************************************************************************
1235 * Make sure we have a valid PHY and change PHY mode before link setup.
1237 * hw - Struct containing variables accessed by shared code
1238 ******************************************************************************/
1240 e1000_copper_link_preconfig(struct e1000_hw *hw)
1246 DEBUGFUNC("e1000_copper_link_preconfig");
1248 ctrl = E1000_READ_REG(hw, CTRL);
1249 /* With 82543, we need to force speed and duplex on the MAC equal to what
1250 * the PHY speed and duplex configuration is. In addition, we need to
1251 * perform a hardware reset on the PHY to take it out of reset.
1253 if(hw->mac_type > e1000_82543) {
1254 ctrl |= E1000_CTRL_SLU;
1255 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1256 E1000_WRITE_REG(hw, CTRL, ctrl);
1258 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1259 E1000_WRITE_REG(hw, CTRL, ctrl);
1260 ret_val = e1000_phy_hw_reset(hw);
1265 /* Make sure we have a valid PHY */
1266 ret_val = e1000_detect_gig_phy(hw);
1268 DEBUGOUT("Error, did not detect valid phy.\n");
1271 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1273 /* Set PHY to class A mode (if necessary) */
1274 ret_val = e1000_set_phy_mode(hw);
1278 if((hw->mac_type == e1000_82545_rev_3) ||
1279 (hw->mac_type == e1000_82546_rev_3)) {
1280 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1281 phy_data |= 0x00000008;
1282 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1285 if(hw->mac_type <= e1000_82543 ||
1286 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1287 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1288 hw->phy_reset_disable = FALSE;
1290 return E1000_SUCCESS;
1294 /********************************************************************
1295 * Copper link setup for e1000_phy_igp series.
1297 * hw - Struct containing variables accessed by shared code
1298 *********************************************************************/
1300 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1306 DEBUGFUNC("e1000_copper_link_igp_setup");
1308 if (hw->phy_reset_disable)
1309 return E1000_SUCCESS;
1311 ret_val = e1000_phy_reset(hw);
1313 DEBUGOUT("Error Resetting the PHY\n");
1317 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1319 if (hw->mac_type != e1000_ich8lan) {
1320 /* Configure activity LED after PHY reset */
1321 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1322 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1323 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1324 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1327 /* disable lplu d3 during driver init */
1328 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1330 DEBUGOUT("Error Disabling LPLU D3\n");
1334 /* disable lplu d0 during driver init */
1335 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1337 DEBUGOUT("Error Disabling LPLU D0\n");
1340 /* Configure mdi-mdix settings */
1341 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1345 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1346 hw->dsp_config_state = e1000_dsp_config_disabled;
1347 /* Force MDI for earlier revs of the IGP PHY */
1348 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1352 hw->dsp_config_state = e1000_dsp_config_enabled;
1353 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1357 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1360 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1364 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1368 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1372 /* set auto-master slave resolution settings */
1374 e1000_ms_type phy_ms_setting = hw->master_slave;
1376 if(hw->ffe_config_state == e1000_ffe_config_active)
1377 hw->ffe_config_state = e1000_ffe_config_enabled;
1379 if(hw->dsp_config_state == e1000_dsp_config_activated)
1380 hw->dsp_config_state = e1000_dsp_config_enabled;
1382 /* when autonegotiation advertisment is only 1000Mbps then we
1383 * should disable SmartSpeed and enable Auto MasterSlave
1384 * resolution as hardware default. */
1385 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1386 /* Disable SmartSpeed */
1387 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1390 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1391 ret_val = e1000_write_phy_reg(hw,
1392 IGP01E1000_PHY_PORT_CONFIG,
1396 /* Set auto Master/Slave resolution process */
1397 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1400 phy_data &= ~CR_1000T_MS_ENABLE;
1401 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1406 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1410 /* load defaults for future use */
1411 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1412 ((phy_data & CR_1000T_MS_VALUE) ?
1413 e1000_ms_force_master :
1414 e1000_ms_force_slave) :
1417 switch (phy_ms_setting) {
1418 case e1000_ms_force_master:
1419 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1421 case e1000_ms_force_slave:
1422 phy_data |= CR_1000T_MS_ENABLE;
1423 phy_data &= ~(CR_1000T_MS_VALUE);
1426 phy_data &= ~CR_1000T_MS_ENABLE;
1430 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1435 return E1000_SUCCESS;
1438 /********************************************************************
1439 * Copper link setup for e1000_phy_gg82563 series.
1441 * hw - Struct containing variables accessed by shared code
1442 *********************************************************************/
1444 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1450 DEBUGFUNC("e1000_copper_link_ggp_setup");
1452 if(!hw->phy_reset_disable) {
1454 /* Enable CRS on TX for half-duplex operation. */
1455 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1460 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1461 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1462 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1464 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1470 * MDI/MDI-X = 0 (default)
1471 * 0 - Auto for all speeds
1474 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1476 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1480 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1484 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1487 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1491 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1496 * disable_polarity_correction = 0 (default)
1497 * Automatic Correction for Reversed Cable Polarity
1501 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1502 if(hw->disable_polarity_correction == 1)
1503 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1504 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1509 /* SW Reset the PHY so all changes take effect */
1510 ret_val = e1000_phy_reset(hw);
1512 DEBUGOUT("Error Resetting the PHY\n");
1515 } /* phy_reset_disable */
1517 if (hw->mac_type == e1000_80003es2lan) {
1518 /* Bypass RX and TX FIFO's */
1519 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1520 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1521 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1525 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1529 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1530 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1535 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1536 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1537 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1539 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1544 /* Do not init these registers when the HW is in IAMT mode, since the
1545 * firmware will have already initialized them. We only initialize
1546 * them if the HW is not in IAMT mode.
1548 if (e1000_check_mng_mode(hw) == FALSE) {
1549 /* Enable Electrical Idle on the PHY */
1550 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1551 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1556 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1561 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1563 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1569 /* Workaround: Disable padding in Kumeran interface in the MAC
1570 * and in the PHY to avoid CRC errors.
1572 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1576 phy_data |= GG82563_ICR_DIS_PADDING;
1577 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1583 return E1000_SUCCESS;
1586 /********************************************************************
1587 * Copper link setup for e1000_phy_m88 series.
1589 * hw - Struct containing variables accessed by shared code
1590 *********************************************************************/
1592 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1597 DEBUGFUNC("e1000_copper_link_mgp_setup");
1599 if(hw->phy_reset_disable)
1600 return E1000_SUCCESS;
1602 /* Enable CRS on TX. This must be set for half-duplex operation. */
1603 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1607 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1610 * MDI/MDI-X = 0 (default)
1611 * 0 - Auto for all speeds
1614 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1616 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1620 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1623 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1626 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1630 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1635 * disable_polarity_correction = 0 (default)
1636 * Automatic Correction for Reversed Cable Polarity
1640 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1641 if(hw->disable_polarity_correction == 1)
1642 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1643 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1647 if (hw->phy_revision < M88E1011_I_REV_4) {
1648 /* Force TX_CLK in the Extended PHY Specific Control Register
1651 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1655 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1657 if ((hw->phy_revision == E1000_REVISION_2) &&
1658 (hw->phy_id == M88E1111_I_PHY_ID)) {
1659 /* Vidalia Phy, set the downshift counter to 5x */
1660 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1661 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1662 ret_val = e1000_write_phy_reg(hw,
1663 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1667 /* Configure Master and Slave downshift values */
1668 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1669 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1670 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1671 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1672 ret_val = e1000_write_phy_reg(hw,
1673 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1679 /* SW Reset the PHY so all changes take effect */
1680 ret_val = e1000_phy_reset(hw);
1682 DEBUGOUT("Error Resetting the PHY\n");
1686 return E1000_SUCCESS;
1689 /********************************************************************
1690 * Setup auto-negotiation and flow control advertisements,
1691 * and then perform auto-negotiation.
1693 * hw - Struct containing variables accessed by shared code
1694 *********************************************************************/
1696 e1000_copper_link_autoneg(struct e1000_hw *hw)
1701 DEBUGFUNC("e1000_copper_link_autoneg");
1703 /* Perform some bounds checking on the hw->autoneg_advertised
1704 * parameter. If this variable is zero, then set it to the default.
1706 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1708 /* If autoneg_advertised is zero, we assume it was not defaulted
1709 * by the calling code so we set to advertise full capability.
1711 if(hw->autoneg_advertised == 0)
1712 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1714 /* IFE phy only supports 10/100 */
1715 if (hw->phy_type == e1000_phy_ife)
1716 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1718 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1719 ret_val = e1000_phy_setup_autoneg(hw);
1721 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1724 DEBUGOUT("Restarting Auto-Neg\n");
1726 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1727 * the Auto Neg Restart bit in the PHY control register.
1729 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1733 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1734 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1738 /* Does the user want to wait for Auto-Neg to complete here, or
1739 * check at a later time (for example, callback routine).
1741 if(hw->wait_autoneg_complete) {
1742 ret_val = e1000_wait_autoneg(hw);
1744 DEBUGOUT("Error while waiting for autoneg to complete\n");
1749 hw->get_link_status = TRUE;
1751 return E1000_SUCCESS;
1755 /******************************************************************************
1756 * Config the MAC and the PHY after link is up.
1757 * 1) Set up the MAC to the current PHY speed/duplex
1758 * if we are on 82543. If we
1759 * are on newer silicon, we only need to configure
1760 * collision distance in the Transmit Control Register.
1761 * 2) Set up flow control on the MAC to that established with
1763 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1765 * hw - Struct containing variables accessed by shared code
1766 ******************************************************************************/
1768 e1000_copper_link_postconfig(struct e1000_hw *hw)
1771 DEBUGFUNC("e1000_copper_link_postconfig");
1773 if(hw->mac_type >= e1000_82544) {
1774 e1000_config_collision_dist(hw);
1776 ret_val = e1000_config_mac_to_phy(hw);
1778 DEBUGOUT("Error configuring MAC to PHY settings\n");
1782 ret_val = e1000_config_fc_after_link_up(hw);
1784 DEBUGOUT("Error Configuring Flow Control\n");
1788 /* Config DSP to improve Giga link quality */
1789 if(hw->phy_type == e1000_phy_igp) {
1790 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1792 DEBUGOUT("Error Configuring DSP after link up\n");
1797 return E1000_SUCCESS;
1800 /******************************************************************************
1801 * Detects which PHY is present and setup the speed and duplex
1803 * hw - Struct containing variables accessed by shared code
1804 ******************************************************************************/
1806 e1000_setup_copper_link(struct e1000_hw *hw)
1813 DEBUGFUNC("e1000_setup_copper_link");
1815 switch (hw->mac_type) {
1816 case e1000_80003es2lan:
1818 /* Set the mac to wait the maximum time between each
1819 * iteration and increase the max iterations when
1820 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1821 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1824 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
1828 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1835 /* Check if it is a valid PHY and set PHY mode if necessary. */
1836 ret_val = e1000_copper_link_preconfig(hw);
1840 switch (hw->mac_type) {
1841 case e1000_80003es2lan:
1842 /* Kumeran registers are written-only */
1843 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1844 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1845 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1854 if (hw->phy_type == e1000_phy_igp ||
1855 hw->phy_type == e1000_phy_igp_3 ||
1856 hw->phy_type == e1000_phy_igp_2) {
1857 ret_val = e1000_copper_link_igp_setup(hw);
1860 } else if (hw->phy_type == e1000_phy_m88) {
1861 ret_val = e1000_copper_link_mgp_setup(hw);
1864 } else if (hw->phy_type == e1000_phy_gg82563) {
1865 ret_val = e1000_copper_link_ggp_setup(hw);
1871 /* Setup autoneg and flow control advertisement
1872 * and perform autonegotiation */
1873 ret_val = e1000_copper_link_autoneg(hw);
1877 /* PHY will be set to 10H, 10F, 100H,or 100F
1878 * depending on value from forced_speed_duplex. */
1879 DEBUGOUT("Forcing speed and duplex\n");
1880 ret_val = e1000_phy_force_speed_duplex(hw);
1882 DEBUGOUT("Error Forcing Speed and Duplex\n");
1887 /* Check link status. Wait up to 100 microseconds for link to become
1890 for(i = 0; i < 10; i++) {
1891 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1894 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1898 if(phy_data & MII_SR_LINK_STATUS) {
1899 /* Config the MAC and PHY after link is up */
1900 ret_val = e1000_copper_link_postconfig(hw);
1904 DEBUGOUT("Valid link established!!!\n");
1905 return E1000_SUCCESS;
1910 DEBUGOUT("Unable to establish link!!!\n");
1911 return E1000_SUCCESS;
1914 /******************************************************************************
1915 * Configure the MAC-to-PHY interface for 10/100Mbps
1917 * hw - Struct containing variables accessed by shared code
1918 ******************************************************************************/
1920 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
1922 int32_t ret_val = E1000_SUCCESS;
1926 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1928 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
1929 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1934 /* Configure Transmit Inter-Packet Gap */
1935 tipg = E1000_READ_REG(hw, TIPG);
1936 tipg &= ~E1000_TIPG_IPGT_MASK;
1937 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1938 E1000_WRITE_REG(hw, TIPG, tipg);
1940 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1945 if (duplex == HALF_DUPLEX)
1946 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1948 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1950 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1956 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1958 int32_t ret_val = E1000_SUCCESS;
1962 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1964 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
1965 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1970 /* Configure Transmit Inter-Packet Gap */
1971 tipg = E1000_READ_REG(hw, TIPG);
1972 tipg &= ~E1000_TIPG_IPGT_MASK;
1973 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1974 E1000_WRITE_REG(hw, TIPG, tipg);
1976 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1981 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1982 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1987 /******************************************************************************
1988 * Configures PHY autoneg and flow control advertisement settings
1990 * hw - Struct containing variables accessed by shared code
1991 ******************************************************************************/
1993 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1996 uint16_t mii_autoneg_adv_reg;
1997 uint16_t mii_1000t_ctrl_reg;
1999 DEBUGFUNC("e1000_phy_setup_autoneg");
2001 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2002 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2006 if (hw->phy_type != e1000_phy_ife) {
2007 /* Read the MII 1000Base-T Control Register (Address 9). */
2008 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2012 mii_1000t_ctrl_reg=0;
2014 /* Need to parse both autoneg_advertised and fc and set up
2015 * the appropriate PHY registers. First we will parse for
2016 * autoneg_advertised software override. Since we can advertise
2017 * a plethora of combinations, we need to check each bit
2021 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2022 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2023 * the 1000Base-T Control Register (Address 9).
2025 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2026 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2028 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2030 /* Do we want to advertise 10 Mb Half Duplex? */
2031 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
2032 DEBUGOUT("Advertise 10mb Half duplex\n");
2033 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2036 /* Do we want to advertise 10 Mb Full Duplex? */
2037 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
2038 DEBUGOUT("Advertise 10mb Full duplex\n");
2039 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2042 /* Do we want to advertise 100 Mb Half Duplex? */
2043 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
2044 DEBUGOUT("Advertise 100mb Half duplex\n");
2045 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2048 /* Do we want to advertise 100 Mb Full Duplex? */
2049 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
2050 DEBUGOUT("Advertise 100mb Full duplex\n");
2051 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2054 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2055 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2056 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2059 /* Do we want to advertise 1000 Mb Full Duplex? */
2060 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2061 DEBUGOUT("Advertise 1000mb Full duplex\n");
2062 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2063 if (hw->phy_type == e1000_phy_ife) {
2064 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2068 /* Check for a software override of the flow control settings, and
2069 * setup the PHY advertisement registers accordingly. If
2070 * auto-negotiation is enabled, then software will have to set the
2071 * "PAUSE" bits to the correct value in the Auto-Negotiation
2072 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2074 * The possible values of the "fc" parameter are:
2075 * 0: Flow control is completely disabled
2076 * 1: Rx flow control is enabled (we can receive pause frames
2077 * but not send pause frames).
2078 * 2: Tx flow control is enabled (we can send pause frames
2079 * but we do not support receiving pause frames).
2080 * 3: Both Rx and TX flow control (symmetric) are enabled.
2081 * other: No software override. The flow control configuration
2082 * in the EEPROM is used.
2085 case e1000_fc_none: /* 0 */
2086 /* Flow control (RX & TX) is completely disabled by a
2087 * software over-ride.
2089 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2091 case e1000_fc_rx_pause: /* 1 */
2092 /* RX Flow control is enabled, and TX Flow control is
2093 * disabled, by a software over-ride.
2095 /* Since there really isn't a way to advertise that we are
2096 * capable of RX Pause ONLY, we will advertise that we
2097 * support both symmetric and asymmetric RX PAUSE. Later
2098 * (in e1000_config_fc_after_link_up) we will disable the
2099 *hw's ability to send PAUSE frames.
2101 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2103 case e1000_fc_tx_pause: /* 2 */
2104 /* TX Flow control is enabled, and RX Flow control is
2105 * disabled, by a software over-ride.
2107 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2108 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2110 case e1000_fc_full: /* 3 */
2111 /* Flow control (both RX and TX) is enabled by a software
2114 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2117 DEBUGOUT("Flow control param set incorrectly\n");
2118 return -E1000_ERR_CONFIG;
2121 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2125 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2127 if (hw->phy_type != e1000_phy_ife) {
2128 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2133 return E1000_SUCCESS;
2136 /******************************************************************************
2137 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2139 * hw - Struct containing variables accessed by shared code
2140 ******************************************************************************/
2142 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2146 uint16_t mii_ctrl_reg;
2147 uint16_t mii_status_reg;
2151 DEBUGFUNC("e1000_phy_force_speed_duplex");
2153 /* Turn off Flow control if we are forcing speed and duplex. */
2154 hw->fc = e1000_fc_none;
2156 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2158 /* Read the Device Control Register. */
2159 ctrl = E1000_READ_REG(hw, CTRL);
2161 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2162 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2163 ctrl &= ~(DEVICE_SPEED_MASK);
2165 /* Clear the Auto Speed Detect Enable bit. */
2166 ctrl &= ~E1000_CTRL_ASDE;
2168 /* Read the MII Control Register. */
2169 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2173 /* We need to disable autoneg in order to force link and duplex. */
2175 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2177 /* Are we forcing Full or Half Duplex? */
2178 if(hw->forced_speed_duplex == e1000_100_full ||
2179 hw->forced_speed_duplex == e1000_10_full) {
2180 /* We want to force full duplex so we SET the full duplex bits in the
2181 * Device and MII Control Registers.
2183 ctrl |= E1000_CTRL_FD;
2184 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2185 DEBUGOUT("Full Duplex\n");
2187 /* We want to force half duplex so we CLEAR the full duplex bits in
2188 * the Device and MII Control Registers.
2190 ctrl &= ~E1000_CTRL_FD;
2191 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2192 DEBUGOUT("Half Duplex\n");
2195 /* Are we forcing 100Mbps??? */
2196 if(hw->forced_speed_duplex == e1000_100_full ||
2197 hw->forced_speed_duplex == e1000_100_half) {
2198 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2199 ctrl |= E1000_CTRL_SPD_100;
2200 mii_ctrl_reg |= MII_CR_SPEED_100;
2201 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2202 DEBUGOUT("Forcing 100mb ");
2204 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2205 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2206 mii_ctrl_reg |= MII_CR_SPEED_10;
2207 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2208 DEBUGOUT("Forcing 10mb ");
2211 e1000_config_collision_dist(hw);
2213 /* Write the configured values back to the Device Control Reg. */
2214 E1000_WRITE_REG(hw, CTRL, ctrl);
2216 if ((hw->phy_type == e1000_phy_m88) ||
2217 (hw->phy_type == e1000_phy_gg82563)) {
2218 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2222 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2223 * forced whenever speed are duplex are forced.
2225 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2226 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2230 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2232 /* Need to reset the PHY or these changes will be ignored */
2233 mii_ctrl_reg |= MII_CR_RESET;
2234 /* Disable MDI-X support for 10/100 */
2235 } else if (hw->phy_type == e1000_phy_ife) {
2236 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2240 phy_data &= ~IFE_PMC_AUTO_MDIX;
2241 phy_data &= ~IFE_PMC_FORCE_MDIX;
2243 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2247 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2248 * forced whenever speed or duplex are forced.
2250 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2254 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2255 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2257 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2262 /* Write back the modified PHY MII control register. */
2263 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2269 /* The wait_autoneg_complete flag may be a little misleading here.
2270 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2271 * But we do want to delay for a period while forcing only so we
2272 * don't generate false No Link messages. So we will wait here
2273 * only if the user has set wait_autoneg_complete to 1, which is
2276 if(hw->wait_autoneg_complete) {
2277 /* We will wait for autoneg to complete. */
2278 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2281 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2282 for(i = PHY_FORCE_TIME; i > 0; i--) {
2283 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2286 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2290 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2294 if(mii_status_reg & MII_SR_LINK_STATUS) break;
2298 ((hw->phy_type == e1000_phy_m88) ||
2299 (hw->phy_type == e1000_phy_gg82563))) {
2300 /* We didn't get link. Reset the DSP and wait again for link. */
2301 ret_val = e1000_phy_reset_dsp(hw);
2303 DEBUGOUT("Error Resetting PHY DSP\n");
2307 /* This loop will early-out if the link condition has been met. */
2308 for(i = PHY_FORCE_TIME; i > 0; i--) {
2309 if(mii_status_reg & MII_SR_LINK_STATUS) break;
2311 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2314 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2318 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2324 if (hw->phy_type == e1000_phy_m88) {
2325 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2326 * Extended PHY Specific Control Register to 25MHz clock. This value
2327 * defaults back to a 2.5MHz clock when the PHY is reset.
2329 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2333 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2334 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2338 /* In addition, because of the s/w reset above, we need to enable CRS on
2339 * TX. This must be set for both full and half duplex operation.
2341 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2345 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2346 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2350 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2352 (hw->forced_speed_duplex == e1000_10_full ||
2353 hw->forced_speed_duplex == e1000_10_half)) {
2354 ret_val = e1000_polarity_reversal_workaround(hw);
2358 } else if (hw->phy_type == e1000_phy_gg82563) {
2359 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2360 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2361 * we're not in a forced 10/duplex configuration. */
2362 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2366 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2367 if ((hw->forced_speed_duplex == e1000_10_full) ||
2368 (hw->forced_speed_duplex == e1000_10_half))
2369 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2371 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2373 /* Also due to the reset, we need to enable CRS on Tx. */
2374 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2376 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2380 return E1000_SUCCESS;
2383 /******************************************************************************
2384 * Sets the collision distance in the Transmit Control register
2386 * hw - Struct containing variables accessed by shared code
2388 * Link should have been established previously. Reads the speed and duplex
2389 * information from the Device Status register.
2390 ******************************************************************************/
2392 e1000_config_collision_dist(struct e1000_hw *hw)
2394 uint32_t tctl, coll_dist;
2396 DEBUGFUNC("e1000_config_collision_dist");
2398 if (hw->mac_type < e1000_82543)
2399 coll_dist = E1000_COLLISION_DISTANCE_82542;
2401 coll_dist = E1000_COLLISION_DISTANCE;
2403 tctl = E1000_READ_REG(hw, TCTL);
2405 tctl &= ~E1000_TCTL_COLD;
2406 tctl |= coll_dist << E1000_COLD_SHIFT;
2408 E1000_WRITE_REG(hw, TCTL, tctl);
2409 E1000_WRITE_FLUSH(hw);
2412 /******************************************************************************
2413 * Sets MAC speed and duplex settings to reflect the those in the PHY
2415 * hw - Struct containing variables accessed by shared code
2416 * mii_reg - data to write to the MII control register
2418 * The contents of the PHY register containing the needed information need to
2420 ******************************************************************************/
2422 e1000_config_mac_to_phy(struct e1000_hw *hw)
2428 DEBUGFUNC("e1000_config_mac_to_phy");
2430 /* 82544 or newer MAC, Auto Speed Detection takes care of
2431 * MAC speed/duplex configuration.*/
2432 if (hw->mac_type >= e1000_82544)
2433 return E1000_SUCCESS;
2435 /* Read the Device Control Register and set the bits to Force Speed
2438 ctrl = E1000_READ_REG(hw, CTRL);
2439 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2440 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2442 /* Set up duplex in the Device Control and Transmit Control
2443 * registers depending on negotiated values.
2445 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2449 if(phy_data & M88E1000_PSSR_DPLX)
2450 ctrl |= E1000_CTRL_FD;
2452 ctrl &= ~E1000_CTRL_FD;
2454 e1000_config_collision_dist(hw);
2456 /* Set up speed in the Device Control register depending on
2457 * negotiated values.
2459 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2460 ctrl |= E1000_CTRL_SPD_1000;
2461 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2462 ctrl |= E1000_CTRL_SPD_100;
2464 /* Write the configured values back to the Device Control Reg. */
2465 E1000_WRITE_REG(hw, CTRL, ctrl);
2466 return E1000_SUCCESS;
2469 /******************************************************************************
2470 * Forces the MAC's flow control settings.
2472 * hw - Struct containing variables accessed by shared code
2474 * Sets the TFCE and RFCE bits in the device control register to reflect
2475 * the adapter settings. TFCE and RFCE need to be explicitly set by
2476 * software when a Copper PHY is used because autonegotiation is managed
2477 * by the PHY rather than the MAC. Software must also configure these
2478 * bits when link is forced on a fiber connection.
2479 *****************************************************************************/
2481 e1000_force_mac_fc(struct e1000_hw *hw)
2485 DEBUGFUNC("e1000_force_mac_fc");
2487 /* Get the current configuration of the Device Control Register */
2488 ctrl = E1000_READ_REG(hw, CTRL);
2490 /* Because we didn't get link via the internal auto-negotiation
2491 * mechanism (we either forced link or we got link via PHY
2492 * auto-neg), we have to manually enable/disable transmit an
2493 * receive flow control.
2495 * The "Case" statement below enables/disable flow control
2496 * according to the "hw->fc" parameter.
2498 * The possible values of the "fc" parameter are:
2499 * 0: Flow control is completely disabled
2500 * 1: Rx flow control is enabled (we can receive pause
2501 * frames but not send pause frames).
2502 * 2: Tx flow control is enabled (we can send pause frames
2503 * frames but we do not receive pause frames).
2504 * 3: Both Rx and TX flow control (symmetric) is enabled.
2505 * other: No other values should be possible at this point.
2510 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2512 case e1000_fc_rx_pause:
2513 ctrl &= (~E1000_CTRL_TFCE);
2514 ctrl |= E1000_CTRL_RFCE;
2516 case e1000_fc_tx_pause:
2517 ctrl &= (~E1000_CTRL_RFCE);
2518 ctrl |= E1000_CTRL_TFCE;
2521 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2524 DEBUGOUT("Flow control param set incorrectly\n");
2525 return -E1000_ERR_CONFIG;
2528 /* Disable TX Flow Control for 82542 (rev 2.0) */
2529 if(hw->mac_type == e1000_82542_rev2_0)
2530 ctrl &= (~E1000_CTRL_TFCE);
2532 E1000_WRITE_REG(hw, CTRL, ctrl);
2533 return E1000_SUCCESS;
2536 /******************************************************************************
2537 * Configures flow control settings after link is established
2539 * hw - Struct containing variables accessed by shared code
2541 * Should be called immediately after a valid link has been established.
2542 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2543 * and autonegotiation is enabled, the MAC flow control settings will be set
2544 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2545 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2546 *****************************************************************************/
2548 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2551 uint16_t mii_status_reg;
2552 uint16_t mii_nway_adv_reg;
2553 uint16_t mii_nway_lp_ability_reg;
2557 DEBUGFUNC("e1000_config_fc_after_link_up");
2559 /* Check for the case where we have fiber media and auto-neg failed
2560 * so we had to force link. In this case, we need to force the
2561 * configuration of the MAC to match the "fc" parameter.
2563 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2564 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
2565 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2566 ret_val = e1000_force_mac_fc(hw);
2568 DEBUGOUT("Error forcing flow control settings\n");
2573 /* Check for the case where we have copper media and auto-neg is
2574 * enabled. In this case, we need to check and see if Auto-Neg
2575 * has completed, and if so, how the PHY and link partner has
2576 * flow control configured.
2578 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2579 /* Read the MII Status Register and check to see if AutoNeg
2580 * has completed. We read this twice because this reg has
2581 * some "sticky" (latched) bits.
2583 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2586 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2590 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2591 /* The AutoNeg process has completed, so we now need to
2592 * read both the Auto Negotiation Advertisement Register
2593 * (Address 4) and the Auto_Negotiation Base Page Ability
2594 * Register (Address 5) to determine how flow control was
2597 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2601 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2602 &mii_nway_lp_ability_reg);
2606 /* Two bits in the Auto Negotiation Advertisement Register
2607 * (Address 4) and two bits in the Auto Negotiation Base
2608 * Page Ability Register (Address 5) determine flow control
2609 * for both the PHY and the link partner. The following
2610 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2611 * 1999, describes these PAUSE resolution bits and how flow
2612 * control is determined based upon these settings.
2613 * NOTE: DC = Don't Care
2615 * LOCAL DEVICE | LINK PARTNER
2616 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2617 *-------|---------|-------|---------|--------------------
2618 * 0 | 0 | DC | DC | e1000_fc_none
2619 * 0 | 1 | 0 | DC | e1000_fc_none
2620 * 0 | 1 | 1 | 0 | e1000_fc_none
2621 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2622 * 1 | 0 | 0 | DC | e1000_fc_none
2623 * 1 | DC | 1 | DC | e1000_fc_full
2624 * 1 | 1 | 0 | 0 | e1000_fc_none
2625 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2628 /* Are both PAUSE bits set to 1? If so, this implies
2629 * Symmetric Flow Control is enabled at both ends. The
2630 * ASM_DIR bits are irrelevant per the spec.
2632 * For Symmetric Flow Control:
2634 * LOCAL DEVICE | LINK PARTNER
2635 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2636 *-------|---------|-------|---------|--------------------
2637 * 1 | DC | 1 | DC | e1000_fc_full
2640 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2641 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2642 /* Now we need to check if the user selected RX ONLY
2643 * of pause frames. In this case, we had to advertise
2644 * FULL flow control because we could not advertise RX
2645 * ONLY. Hence, we must now check to see if we need to
2646 * turn OFF the TRANSMISSION of PAUSE frames.
2648 if(hw->original_fc == e1000_fc_full) {
2649 hw->fc = e1000_fc_full;
2650 DEBUGOUT("Flow Control = FULL.\n");
2652 hw->fc = e1000_fc_rx_pause;
2653 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2656 /* For receiving PAUSE frames ONLY.
2658 * LOCAL DEVICE | LINK PARTNER
2659 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2660 *-------|---------|-------|---------|--------------------
2661 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2664 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2665 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2666 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2667 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2668 hw->fc = e1000_fc_tx_pause;
2669 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2671 /* For transmitting PAUSE frames ONLY.
2673 * LOCAL DEVICE | LINK PARTNER
2674 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2675 *-------|---------|-------|---------|--------------------
2676 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2679 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2680 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2681 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2682 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2683 hw->fc = e1000_fc_rx_pause;
2684 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2686 /* Per the IEEE spec, at this point flow control should be
2687 * disabled. However, we want to consider that we could
2688 * be connected to a legacy switch that doesn't advertise
2689 * desired flow control, but can be forced on the link
2690 * partner. So if we advertised no flow control, that is
2691 * what we will resolve to. If we advertised some kind of
2692 * receive capability (Rx Pause Only or Full Flow Control)
2693 * and the link partner advertised none, we will configure
2694 * ourselves to enable Rx Flow Control only. We can do
2695 * this safely for two reasons: If the link partner really
2696 * didn't want flow control enabled, and we enable Rx, no
2697 * harm done since we won't be receiving any PAUSE frames
2698 * anyway. If the intent on the link partner was to have
2699 * flow control enabled, then by us enabling RX only, we
2700 * can at least receive pause frames and process them.
2701 * This is a good idea because in most cases, since we are
2702 * predominantly a server NIC, more times than not we will
2703 * be asked to delay transmission of packets than asking
2704 * our link partner to pause transmission of frames.
2706 else if((hw->original_fc == e1000_fc_none ||
2707 hw->original_fc == e1000_fc_tx_pause) ||
2708 hw->fc_strict_ieee) {
2709 hw->fc = e1000_fc_none;
2710 DEBUGOUT("Flow Control = NONE.\n");
2712 hw->fc = e1000_fc_rx_pause;
2713 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2716 /* Now we need to do one last check... If we auto-
2717 * negotiated to HALF DUPLEX, flow control should not be
2718 * enabled per IEEE 802.3 spec.
2720 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2722 DEBUGOUT("Error getting link speed and duplex\n");
2726 if(duplex == HALF_DUPLEX)
2727 hw->fc = e1000_fc_none;
2729 /* Now we call a subroutine to actually force the MAC
2730 * controller to use the correct flow control settings.
2732 ret_val = e1000_force_mac_fc(hw);
2734 DEBUGOUT("Error forcing flow control settings\n");
2738 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2741 return E1000_SUCCESS;
2744 /******************************************************************************
2745 * Checks to see if the link status of the hardware has changed.
2747 * hw - Struct containing variables accessed by shared code
2749 * Called by any function that needs to check the link status of the adapter.
2750 *****************************************************************************/
2752 e1000_check_for_link(struct e1000_hw *hw)
2759 uint32_t signal = 0;
2763 DEBUGFUNC("e1000_check_for_link");
2765 ctrl = E1000_READ_REG(hw, CTRL);
2766 status = E1000_READ_REG(hw, STATUS);
2768 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2769 * set when the optics detect a signal. On older adapters, it will be
2770 * cleared when there is a signal. This applies to fiber media only.
2772 if((hw->media_type == e1000_media_type_fiber) ||
2773 (hw->media_type == e1000_media_type_internal_serdes)) {
2774 rxcw = E1000_READ_REG(hw, RXCW);
2776 if(hw->media_type == e1000_media_type_fiber) {
2777 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2778 if(status & E1000_STATUS_LU)
2779 hw->get_link_status = FALSE;
2783 /* If we have a copper PHY then we only want to go out to the PHY
2784 * registers to see if Auto-Neg has completed and/or if our link
2785 * status has changed. The get_link_status flag will be set if we
2786 * receive a Link Status Change interrupt or we have Rx Sequence
2789 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2790 /* First we want to see if the MII Status Register reports
2791 * link. If so, then we want to get the current speed/duplex
2793 * Read the register twice since the link bit is sticky.
2795 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2798 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2802 if(phy_data & MII_SR_LINK_STATUS) {
2803 hw->get_link_status = FALSE;
2804 /* Check if there was DownShift, must be checked immediately after
2806 e1000_check_downshift(hw);
2808 /* If we are on 82544 or 82543 silicon and speed/duplex
2809 * are forced to 10H or 10F, then we will implement the polarity
2810 * reversal workaround. We disable interrupts first, and upon
2811 * returning, place the devices interrupt state to its previous
2812 * value except for the link status change interrupt which will
2813 * happen due to the execution of this workaround.
2816 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2818 (hw->forced_speed_duplex == e1000_10_full ||
2819 hw->forced_speed_duplex == e1000_10_half)) {
2820 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2821 ret_val = e1000_polarity_reversal_workaround(hw);
2822 icr = E1000_READ_REG(hw, ICR);
2823 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2824 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2828 /* No link detected */
2829 e1000_config_dsp_after_link_change(hw, FALSE);
2833 /* If we are forcing speed/duplex, then we simply return since
2834 * we have already determined whether we have link or not.
2836 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2838 /* optimize the dsp settings for the igp phy */
2839 e1000_config_dsp_after_link_change(hw, TRUE);
2841 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2842 * have Si on board that is 82544 or newer, Auto
2843 * Speed Detection takes care of MAC speed/duplex
2844 * configuration. So we only need to configure Collision
2845 * Distance in the MAC. Otherwise, we need to force
2846 * speed/duplex on the MAC to the current PHY speed/duplex
2849 if(hw->mac_type >= e1000_82544)
2850 e1000_config_collision_dist(hw);
2852 ret_val = e1000_config_mac_to_phy(hw);
2854 DEBUGOUT("Error configuring MAC to PHY settings\n");
2859 /* Configure Flow Control now that Auto-Neg has completed. First, we
2860 * need to restore the desired flow control settings because we may
2861 * have had to re-autoneg with a different link partner.
2863 ret_val = e1000_config_fc_after_link_up(hw);
2865 DEBUGOUT("Error configuring flow control\n");
2869 /* At this point we know that we are on copper and we have
2870 * auto-negotiated link. These are conditions for checking the link
2871 * partner capability register. We use the link speed to determine if
2872 * TBI compatibility needs to be turned on or off. If the link is not
2873 * at gigabit speed, then TBI compatibility is not needed. If we are
2874 * at gigabit speed, we turn on TBI compatibility.
2876 if(hw->tbi_compatibility_en) {
2877 uint16_t speed, duplex;
2878 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2880 DEBUGOUT("Error getting link speed and duplex\n");
2883 if (speed != SPEED_1000) {
2884 /* If link speed is not set to gigabit speed, we do not need
2885 * to enable TBI compatibility.
2887 if(hw->tbi_compatibility_on) {
2888 /* If we previously were in the mode, turn it off. */
2889 rctl = E1000_READ_REG(hw, RCTL);
2890 rctl &= ~E1000_RCTL_SBP;
2891 E1000_WRITE_REG(hw, RCTL, rctl);
2892 hw->tbi_compatibility_on = FALSE;
2895 /* If TBI compatibility is was previously off, turn it on. For
2896 * compatibility with a TBI link partner, we will store bad
2897 * packets. Some frames have an additional byte on the end and
2898 * will look like CRC errors to to the hardware.
2900 if(!hw->tbi_compatibility_on) {
2901 hw->tbi_compatibility_on = TRUE;
2902 rctl = E1000_READ_REG(hw, RCTL);
2903 rctl |= E1000_RCTL_SBP;
2904 E1000_WRITE_REG(hw, RCTL, rctl);
2909 /* If we don't have link (auto-negotiation failed or link partner cannot
2910 * auto-negotiate), the cable is plugged in (we have signal), and our
2911 * link partner is not trying to auto-negotiate with us (we are receiving
2912 * idles or data), we need to force link up. We also need to give
2913 * auto-negotiation time to complete, in case the cable was just plugged
2914 * in. The autoneg_failed flag does this.
2916 else if((((hw->media_type == e1000_media_type_fiber) &&
2917 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2918 (hw->media_type == e1000_media_type_internal_serdes)) &&
2919 (!(status & E1000_STATUS_LU)) &&
2920 (!(rxcw & E1000_RXCW_C))) {
2921 if(hw->autoneg_failed == 0) {
2922 hw->autoneg_failed = 1;
2925 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
2927 /* Disable auto-negotiation in the TXCW register */
2928 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2930 /* Force link-up and also force full-duplex. */
2931 ctrl = E1000_READ_REG(hw, CTRL);
2932 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2933 E1000_WRITE_REG(hw, CTRL, ctrl);
2935 /* Configure Flow Control after forcing link up. */
2936 ret_val = e1000_config_fc_after_link_up(hw);
2938 DEBUGOUT("Error configuring flow control\n");
2942 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2943 * auto-negotiation in the TXCW register and disable forced link in the
2944 * Device Control register in an attempt to auto-negotiate with our link
2947 else if(((hw->media_type == e1000_media_type_fiber) ||
2948 (hw->media_type == e1000_media_type_internal_serdes)) &&
2949 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2950 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2951 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2952 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2954 hw->serdes_link_down = FALSE;
2956 /* If we force link for non-auto-negotiation switch, check link status
2957 * based on MAC synchronization for internal serdes media type.
2959 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2960 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2961 /* SYNCH bit and IV bit are sticky. */
2963 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2964 if(!(rxcw & E1000_RXCW_IV)) {
2965 hw->serdes_link_down = FALSE;
2966 DEBUGOUT("SERDES: Link is up.\n");
2969 hw->serdes_link_down = TRUE;
2970 DEBUGOUT("SERDES: Link is down.\n");
2973 if((hw->media_type == e1000_media_type_internal_serdes) &&
2974 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2975 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2977 return E1000_SUCCESS;
2980 /******************************************************************************
2981 * Detects the current speed and duplex settings of the hardware.
2983 * hw - Struct containing variables accessed by shared code
2984 * speed - Speed of the connection
2985 * duplex - Duplex setting of the connection
2986 *****************************************************************************/
2988 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2996 DEBUGFUNC("e1000_get_speed_and_duplex");
2998 if(hw->mac_type >= e1000_82543) {
2999 status = E1000_READ_REG(hw, STATUS);
3000 if(status & E1000_STATUS_SPEED_1000) {
3001 *speed = SPEED_1000;
3002 DEBUGOUT("1000 Mbs, ");
3003 } else if(status & E1000_STATUS_SPEED_100) {
3005 DEBUGOUT("100 Mbs, ");
3008 DEBUGOUT("10 Mbs, ");
3011 if(status & E1000_STATUS_FD) {
3012 *duplex = FULL_DUPLEX;
3013 DEBUGOUT("Full Duplex\n");
3015 *duplex = HALF_DUPLEX;
3016 DEBUGOUT(" Half Duplex\n");
3019 DEBUGOUT("1000 Mbs, Full Duplex\n");
3020 *speed = SPEED_1000;
3021 *duplex = FULL_DUPLEX;
3024 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3025 * if it is operating at half duplex. Here we set the duplex settings to
3026 * match the duplex in the link partner's capabilities.
3028 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3029 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3033 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3034 *duplex = HALF_DUPLEX;
3036 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3039 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3040 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3041 *duplex = HALF_DUPLEX;
3045 if ((hw->mac_type == e1000_80003es2lan) &&
3046 (hw->media_type == e1000_media_type_copper)) {
3047 if (*speed == SPEED_1000)
3048 ret_val = e1000_configure_kmrn_for_1000(hw);
3050 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3055 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3056 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3061 return E1000_SUCCESS;
3064 /******************************************************************************
3065 * Blocks until autoneg completes or times out (~4.5 seconds)
3067 * hw - Struct containing variables accessed by shared code
3068 ******************************************************************************/
3070 e1000_wait_autoneg(struct e1000_hw *hw)
3076 DEBUGFUNC("e1000_wait_autoneg");
3077 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3079 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3080 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3081 /* Read the MII Status Register and wait for Auto-Neg
3082 * Complete bit to be set.
3084 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3087 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3090 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
3091 return E1000_SUCCESS;
3095 return E1000_SUCCESS;
3098 /******************************************************************************
3099 * Raises the Management Data Clock
3101 * hw - Struct containing variables accessed by shared code
3102 * ctrl - Device control register's current value
3103 ******************************************************************************/
3105 e1000_raise_mdi_clk(struct e1000_hw *hw,
3108 /* Raise the clock input to the Management Data Clock (by setting the MDC
3109 * bit), and then delay 10 microseconds.
3111 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3112 E1000_WRITE_FLUSH(hw);
3116 /******************************************************************************
3117 * Lowers the Management Data Clock
3119 * hw - Struct containing variables accessed by shared code
3120 * ctrl - Device control register's current value
3121 ******************************************************************************/
3123 e1000_lower_mdi_clk(struct e1000_hw *hw,
3126 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3127 * bit), and then delay 10 microseconds.
3129 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3130 E1000_WRITE_FLUSH(hw);
3134 /******************************************************************************
3135 * Shifts data bits out to the PHY
3137 * hw - Struct containing variables accessed by shared code
3138 * data - Data to send out to the PHY
3139 * count - Number of bits to shift out
3141 * Bits are shifted out in MSB to LSB order.
3142 ******************************************************************************/
3144 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3151 /* We need to shift "count" number of bits out to the PHY. So, the value
3152 * in the "data" parameter will be shifted out to the PHY one bit at a
3153 * time. In order to do this, "data" must be broken down into bits.
3156 mask <<= (count - 1);
3158 ctrl = E1000_READ_REG(hw, CTRL);
3160 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3161 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3164 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3165 * then raising and lowering the Management Data Clock. A "0" is
3166 * shifted out to the PHY by setting the MDIO bit to "0" and then
3167 * raising and lowering the clock.
3169 if(data & mask) ctrl |= E1000_CTRL_MDIO;
3170 else ctrl &= ~E1000_CTRL_MDIO;
3172 E1000_WRITE_REG(hw, CTRL, ctrl);
3173 E1000_WRITE_FLUSH(hw);
3177 e1000_raise_mdi_clk(hw, &ctrl);
3178 e1000_lower_mdi_clk(hw, &ctrl);
3184 /******************************************************************************
3185 * Shifts data bits in from the PHY
3187 * hw - Struct containing variables accessed by shared code
3189 * Bits are shifted in in MSB to LSB order.
3190 ******************************************************************************/
3192 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3198 /* In order to read a register from the PHY, we need to shift in a total
3199 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3200 * to avoid contention on the MDIO pin when a read operation is performed.
3201 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3202 * by raising the input to the Management Data Clock (setting the MDC bit),
3203 * and then reading the value of the MDIO bit.
3205 ctrl = E1000_READ_REG(hw, CTRL);
3207 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3208 ctrl &= ~E1000_CTRL_MDIO_DIR;
3209 ctrl &= ~E1000_CTRL_MDIO;
3211 E1000_WRITE_REG(hw, CTRL, ctrl);
3212 E1000_WRITE_FLUSH(hw);
3214 /* Raise and Lower the clock before reading in the data. This accounts for
3215 * the turnaround bits. The first clock occurred when we clocked out the
3216 * last bit of the Register Address.
3218 e1000_raise_mdi_clk(hw, &ctrl);
3219 e1000_lower_mdi_clk(hw, &ctrl);
3221 for(data = 0, i = 0; i < 16; i++) {
3223 e1000_raise_mdi_clk(hw, &ctrl);
3224 ctrl = E1000_READ_REG(hw, CTRL);
3225 /* Check to see if we shifted in a "1". */
3226 if(ctrl & E1000_CTRL_MDIO) data |= 1;
3227 e1000_lower_mdi_clk(hw, &ctrl);
3230 e1000_raise_mdi_clk(hw, &ctrl);
3231 e1000_lower_mdi_clk(hw, &ctrl);
3237 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3239 uint32_t swfw_sync = 0;
3240 uint32_t swmask = mask;
3241 uint32_t fwmask = mask << 16;
3242 int32_t timeout = 200;
3244 DEBUGFUNC("e1000_swfw_sync_acquire");
3246 if (hw->swfwhw_semaphore_present)
3247 return e1000_get_software_flag(hw);
3249 if (!hw->swfw_sync_present)
3250 return e1000_get_hw_eeprom_semaphore(hw);
3253 if (e1000_get_hw_eeprom_semaphore(hw))
3254 return -E1000_ERR_SWFW_SYNC;
3256 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3257 if (!(swfw_sync & (fwmask | swmask))) {
3261 /* firmware currently using resource (fwmask) */
3262 /* or other software thread currently using resource (swmask) */
3263 e1000_put_hw_eeprom_semaphore(hw);
3269 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3270 return -E1000_ERR_SWFW_SYNC;
3273 swfw_sync |= swmask;
3274 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3276 e1000_put_hw_eeprom_semaphore(hw);
3277 return E1000_SUCCESS;
3281 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3284 uint32_t swmask = mask;
3286 DEBUGFUNC("e1000_swfw_sync_release");
3288 if (hw->swfwhw_semaphore_present) {
3289 e1000_release_software_flag(hw);
3293 if (!hw->swfw_sync_present) {
3294 e1000_put_hw_eeprom_semaphore(hw);
3298 /* if (e1000_get_hw_eeprom_semaphore(hw))
3299 * return -E1000_ERR_SWFW_SYNC; */
3300 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3303 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3304 swfw_sync &= ~swmask;
3305 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3307 e1000_put_hw_eeprom_semaphore(hw);
3310 /*****************************************************************************
3311 * Reads the value from a PHY register, if the value is on a specific non zero
3312 * page, sets the page first.
3313 * hw - Struct containing variables accessed by shared code
3314 * reg_addr - address of the PHY register to read
3315 ******************************************************************************/
3317 e1000_read_phy_reg(struct e1000_hw *hw,
3324 DEBUGFUNC("e1000_read_phy_reg");
3326 if ((hw->mac_type == e1000_80003es2lan) &&
3327 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3328 swfw = E1000_SWFW_PHY1_SM;
3330 swfw = E1000_SWFW_PHY0_SM;
3332 if (e1000_swfw_sync_acquire(hw, swfw))
3333 return -E1000_ERR_SWFW_SYNC;
3335 if ((hw->phy_type == e1000_phy_igp ||
3336 hw->phy_type == e1000_phy_igp_3 ||
3337 hw->phy_type == e1000_phy_igp_2) &&
3338 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3339 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3340 (uint16_t)reg_addr);
3342 e1000_swfw_sync_release(hw, swfw);
3345 } else if (hw->phy_type == e1000_phy_gg82563) {
3346 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3347 (hw->mac_type == e1000_80003es2lan)) {
3348 /* Select Configuration Page */
3349 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3350 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3351 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3353 /* Use Alternative Page Select register to access
3354 * registers 30 and 31
3356 ret_val = e1000_write_phy_reg_ex(hw,
3357 GG82563_PHY_PAGE_SELECT_ALT,
3358 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3362 e1000_swfw_sync_release(hw, swfw);
3368 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3371 e1000_swfw_sync_release(hw, swfw);
3376 e1000_read_phy_reg_ex(struct e1000_hw *hw,
3382 const uint32_t phy_addr = 1;
3384 DEBUGFUNC("e1000_read_phy_reg_ex");
3386 if(reg_addr > MAX_PHY_REG_ADDRESS) {
3387 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3388 return -E1000_ERR_PARAM;
3391 if(hw->mac_type > e1000_82543) {
3392 /* Set up Op-code, Phy Address, and register address in the MDI
3393 * Control register. The MAC will take care of interfacing with the
3394 * PHY to retrieve the desired data.
3396 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3397 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3398 (E1000_MDIC_OP_READ));
3400 E1000_WRITE_REG(hw, MDIC, mdic);
3402 /* Poll the ready bit to see if the MDI read completed */
3403 for(i = 0; i < 64; i++) {
3405 mdic = E1000_READ_REG(hw, MDIC);
3406 if(mdic & E1000_MDIC_READY) break;
3408 if(!(mdic & E1000_MDIC_READY)) {
3409 DEBUGOUT("MDI Read did not complete\n");
3410 return -E1000_ERR_PHY;
3412 if(mdic & E1000_MDIC_ERROR) {
3413 DEBUGOUT("MDI Error\n");
3414 return -E1000_ERR_PHY;
3416 *phy_data = (uint16_t) mdic;
3418 /* We must first send a preamble through the MDIO pin to signal the
3419 * beginning of an MII instruction. This is done by sending 32
3420 * consecutive "1" bits.
3422 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3424 /* Now combine the next few fields that are required for a read
3425 * operation. We use this method instead of calling the
3426 * e1000_shift_out_mdi_bits routine five different times. The format of
3427 * a MII read instruction consists of a shift out of 14 bits and is
3428 * defined as follows:
3429 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3430 * followed by a shift in of 18 bits. This first two bits shifted in
3431 * are TurnAround bits used to avoid contention on the MDIO pin when a
3432 * READ operation is performed. These two bits are thrown away
3433 * followed by a shift in of 16 bits which contains the desired data.
3435 mdic = ((reg_addr) | (phy_addr << 5) |
3436 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3438 e1000_shift_out_mdi_bits(hw, mdic, 14);
3440 /* Now that we've shifted out the read command to the MII, we need to
3441 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3444 *phy_data = e1000_shift_in_mdi_bits(hw);
3446 return E1000_SUCCESS;
3449 /******************************************************************************
3450 * Writes a value to a PHY register
3452 * hw - Struct containing variables accessed by shared code
3453 * reg_addr - address of the PHY register to write
3454 * data - data to write to the PHY
3455 ******************************************************************************/
3457 e1000_write_phy_reg(struct e1000_hw *hw,
3464 DEBUGFUNC("e1000_write_phy_reg");
3466 if ((hw->mac_type == e1000_80003es2lan) &&
3467 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3468 swfw = E1000_SWFW_PHY1_SM;
3470 swfw = E1000_SWFW_PHY0_SM;
3472 if (e1000_swfw_sync_acquire(hw, swfw))
3473 return -E1000_ERR_SWFW_SYNC;
3475 if ((hw->phy_type == e1000_phy_igp ||
3476 hw->phy_type == e1000_phy_igp_3 ||
3477 hw->phy_type == e1000_phy_igp_2) &&
3478 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3479 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3480 (uint16_t)reg_addr);
3482 e1000_swfw_sync_release(hw, swfw);
3485 } else if (hw->phy_type == e1000_phy_gg82563) {
3486 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3487 (hw->mac_type == e1000_80003es2lan)) {
3488 /* Select Configuration Page */
3489 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3490 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3491 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3493 /* Use Alternative Page Select register to access
3494 * registers 30 and 31
3496 ret_val = e1000_write_phy_reg_ex(hw,
3497 GG82563_PHY_PAGE_SELECT_ALT,
3498 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3502 e1000_swfw_sync_release(hw, swfw);
3508 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3511 e1000_swfw_sync_release(hw, swfw);
3516 e1000_write_phy_reg_ex(struct e1000_hw *hw,
3522 const uint32_t phy_addr = 1;
3524 DEBUGFUNC("e1000_write_phy_reg_ex");
3526 if(reg_addr > MAX_PHY_REG_ADDRESS) {
3527 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3528 return -E1000_ERR_PARAM;
3531 if(hw->mac_type > e1000_82543) {
3532 /* Set up Op-code, Phy Address, register address, and data intended
3533 * for the PHY register in the MDI Control register. The MAC will take
3534 * care of interfacing with the PHY to send the desired data.
3536 mdic = (((uint32_t) phy_data) |
3537 (reg_addr << E1000_MDIC_REG_SHIFT) |
3538 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3539 (E1000_MDIC_OP_WRITE));
3541 E1000_WRITE_REG(hw, MDIC, mdic);
3543 /* Poll the ready bit to see if the MDI read completed */
3544 for(i = 0; i < 640; i++) {
3546 mdic = E1000_READ_REG(hw, MDIC);
3547 if(mdic & E1000_MDIC_READY) break;
3549 if(!(mdic & E1000_MDIC_READY)) {
3550 DEBUGOUT("MDI Write did not complete\n");
3551 return -E1000_ERR_PHY;
3554 /* We'll need to use the SW defined pins to shift the write command
3555 * out to the PHY. We first send a preamble to the PHY to signal the
3556 * beginning of the MII instruction. This is done by sending 32
3557 * consecutive "1" bits.
3559 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3561 /* Now combine the remaining required fields that will indicate a
3562 * write operation. We use this method instead of calling the
3563 * e1000_shift_out_mdi_bits routine for each field in the command. The
3564 * format of a MII write instruction is as follows:
3565 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3567 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3568 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3570 mdic |= (uint32_t) phy_data;
3572 e1000_shift_out_mdi_bits(hw, mdic, 32);
3575 return E1000_SUCCESS;
3579 e1000_read_kmrn_reg(struct e1000_hw *hw,
3585 DEBUGFUNC("e1000_read_kmrn_reg");
3587 if ((hw->mac_type == e1000_80003es2lan) &&
3588 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3589 swfw = E1000_SWFW_PHY1_SM;
3591 swfw = E1000_SWFW_PHY0_SM;
3593 if (e1000_swfw_sync_acquire(hw, swfw))
3594 return -E1000_ERR_SWFW_SYNC;
3596 /* Write register address */
3597 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3598 E1000_KUMCTRLSTA_OFFSET) |
3599 E1000_KUMCTRLSTA_REN;
3600 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3603 /* Read the data returned */
3604 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3605 *data = (uint16_t)reg_val;
3607 e1000_swfw_sync_release(hw, swfw);
3608 return E1000_SUCCESS;
3612 e1000_write_kmrn_reg(struct e1000_hw *hw,
3618 DEBUGFUNC("e1000_write_kmrn_reg");
3620 if ((hw->mac_type == e1000_80003es2lan) &&
3621 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3622 swfw = E1000_SWFW_PHY1_SM;
3624 swfw = E1000_SWFW_PHY0_SM;
3626 if (e1000_swfw_sync_acquire(hw, swfw))
3627 return -E1000_ERR_SWFW_SYNC;
3629 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3630 E1000_KUMCTRLSTA_OFFSET) | data;
3631 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3634 e1000_swfw_sync_release(hw, swfw);
3635 return E1000_SUCCESS;
3638 /******************************************************************************
3639 * Returns the PHY to the power-on reset state
3641 * hw - Struct containing variables accessed by shared code
3642 ******************************************************************************/
3644 e1000_phy_hw_reset(struct e1000_hw *hw)
3646 uint32_t ctrl, ctrl_ext;
3651 DEBUGFUNC("e1000_phy_hw_reset");
3653 /* In the case of the phy reset being blocked, it's not an error, we
3654 * simply return success without performing the reset. */
3655 ret_val = e1000_check_phy_reset_block(hw);
3657 return E1000_SUCCESS;
3659 DEBUGOUT("Resetting Phy...\n");
3661 if(hw->mac_type > e1000_82543) {
3662 if ((hw->mac_type == e1000_80003es2lan) &&
3663 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3664 swfw = E1000_SWFW_PHY1_SM;
3666 swfw = E1000_SWFW_PHY0_SM;
3668 if (e1000_swfw_sync_acquire(hw, swfw)) {
3669 e1000_release_software_semaphore(hw);
3670 return -E1000_ERR_SWFW_SYNC;
3672 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3673 * bit. Then, take it out of reset.
3674 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3675 * and deassert. For e1000_82571 hardware and later, we instead delay
3676 * for 50us between and 10ms after the deassertion.
3678 ctrl = E1000_READ_REG(hw, CTRL);
3679 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3680 E1000_WRITE_FLUSH(hw);
3682 if (hw->mac_type < e1000_82571)
3687 E1000_WRITE_REG(hw, CTRL, ctrl);
3688 E1000_WRITE_FLUSH(hw);
3690 if (hw->mac_type >= e1000_82571)
3692 e1000_swfw_sync_release(hw, swfw);
3694 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3695 * bit to put the PHY into reset. Then, take it out of reset.
3697 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3698 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3699 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3700 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3701 E1000_WRITE_FLUSH(hw);
3703 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3704 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3705 E1000_WRITE_FLUSH(hw);
3709 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3710 /* Configure activity LED after PHY reset */
3711 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3712 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3713 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3714 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3717 /* Wait for FW to finish PHY configuration. */
3718 ret_val = e1000_get_phy_cfg_done(hw);
3719 e1000_release_software_semaphore(hw);
3721 if ((hw->mac_type == e1000_ich8lan) &&
3722 (hw->phy_type == e1000_phy_igp_3)) {
3723 ret_val = e1000_init_lcd_from_nvm(hw);
3730 /******************************************************************************
3733 * hw - Struct containing variables accessed by shared code
3735 * Sets bit 15 of the MII Control regiser
3736 ******************************************************************************/
3738 e1000_phy_reset(struct e1000_hw *hw)
3743 DEBUGFUNC("e1000_phy_reset");
3745 /* In the case of the phy reset being blocked, it's not an error, we
3746 * simply return success without performing the reset. */
3747 ret_val = e1000_check_phy_reset_block(hw);
3749 return E1000_SUCCESS;
3751 switch (hw->mac_type) {
3752 case e1000_82541_rev_2:
3756 ret_val = e1000_phy_hw_reset(hw);
3762 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3766 phy_data |= MII_CR_RESET;
3767 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3775 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3776 e1000_phy_init_script(hw);
3778 return E1000_SUCCESS;
3781 /******************************************************************************
3782 * Work-around for 82566 power-down: on D3 entry-
3783 * 1) disable gigabit link
3784 * 2) write VR power-down enable
3786 * if successful continue, else issue LCD reset and repeat
3788 * hw - struct containing variables accessed by shared code
3789 ******************************************************************************/
3791 e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3797 DEBUGFUNC("e1000_phy_powerdown_workaround");
3799 if (hw->phy_type != e1000_phy_igp_3)
3804 reg = E1000_READ_REG(hw, PHY_CTRL);
3805 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3806 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3808 /* Write VR power-down enable */
3809 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3810 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3811 IGP3_VR_CTRL_MODE_SHUT);
3813 /* Read it back and test */
3814 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3815 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3818 /* Issue PHY reset and repeat at most one more time */
3819 reg = E1000_READ_REG(hw, CTRL);
3820 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3828 /******************************************************************************
3829 * Work-around for 82566 Kumeran PCS lock loss:
3830 * On link status change (i.e. PCI reset, speed change) and link is up and
3832 * 0) if workaround is optionally disabled do nothing
3833 * 1) wait 1ms for Kumeran link to come up
3834 * 2) check Kumeran Diagnostic register PCS lock loss bit
3835 * 3) if not set the link is locked (all is good), otherwise...
3837 * 5) repeat up to 10 times
3838 * Note: this is only called for IGP3 copper when speed is 1gb.
3840 * hw - struct containing variables accessed by shared code
3841 ******************************************************************************/
3843 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3850 if (hw->kmrn_lock_loss_workaround_disabled)
3851 return E1000_SUCCESS;
3853 /* Make sure link is up before proceeding. If not just return.
3854 * Attempting this while link is negotiating fouls up link
3856 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3857 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3859 if (phy_data & MII_SR_LINK_STATUS) {
3860 for (cnt = 0; cnt < 10; cnt++) {
3861 /* read once to clear */
3862 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3865 /* and again to get new status */
3866 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3870 /* check for PCS lock */
3871 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3872 return E1000_SUCCESS;
3874 /* Issue PHY reset */
3875 e1000_phy_hw_reset(hw);
3878 /* Disable GigE link negotiation */
3879 reg = E1000_READ_REG(hw, PHY_CTRL);
3880 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3881 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3883 /* unable to acquire PCS lock */
3884 return E1000_ERR_PHY;
3887 return E1000_SUCCESS;
3890 /******************************************************************************
3891 * Probes the expected PHY address for known PHY IDs
3893 * hw - Struct containing variables accessed by shared code
3894 ******************************************************************************/
3896 e1000_detect_gig_phy(struct e1000_hw *hw)
3898 int32_t phy_init_status, ret_val;
3899 uint16_t phy_id_high, phy_id_low;
3900 boolean_t match = FALSE;
3902 DEBUGFUNC("e1000_detect_gig_phy");
3904 /* The 82571 firmware may still be configuring the PHY. In this
3905 * case, we cannot access the PHY until the configuration is done. So
3906 * we explicitly set the PHY values. */
3907 if (hw->mac_type == e1000_82571 ||
3908 hw->mac_type == e1000_82572) {
3909 hw->phy_id = IGP01E1000_I_PHY_ID;
3910 hw->phy_type = e1000_phy_igp_2;
3911 return E1000_SUCCESS;
3914 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
3915 * around that forces PHY page 0 to be set or the reads fail. The rest of
3916 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
3917 * So for ESB-2 we need to have this set so our reads won't fail. If the
3918 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
3919 * this out as well. */
3920 if (hw->mac_type == e1000_80003es2lan)
3921 hw->phy_type = e1000_phy_gg82563;
3923 /* Read the PHY ID Registers to identify which PHY is onboard. */
3924 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3928 hw->phy_id = (uint32_t) (phy_id_high << 16);
3930 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3934 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3935 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3937 switch(hw->mac_type) {
3939 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3942 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3946 case e1000_82545_rev_3:
3948 case e1000_82546_rev_3:
3949 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3952 case e1000_82541_rev_2:
3954 case e1000_82547_rev_2:
3955 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3958 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3960 case e1000_80003es2lan:
3961 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3964 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
3965 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
3966 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
3967 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
3970 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3971 return -E1000_ERR_CONFIG;
3973 phy_init_status = e1000_set_phy_type(hw);
3975 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3976 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3977 return E1000_SUCCESS;
3979 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3980 return -E1000_ERR_PHY;
3983 /******************************************************************************
3984 * Resets the PHY's DSP
3986 * hw - Struct containing variables accessed by shared code
3987 ******************************************************************************/
3989 e1000_phy_reset_dsp(struct e1000_hw *hw)
3992 DEBUGFUNC("e1000_phy_reset_dsp");
3995 if (hw->phy_type != e1000_phy_gg82563) {
3996 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3999 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4001 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4003 ret_val = E1000_SUCCESS;
4009 /******************************************************************************
4010 * Get PHY information from various PHY registers for igp PHY only.
4012 * hw - Struct containing variables accessed by shared code
4013 * phy_info - PHY information structure
4014 ******************************************************************************/
4016 e1000_phy_igp_get_info(struct e1000_hw *hw,
4017 struct e1000_phy_info *phy_info)
4020 uint16_t phy_data, polarity, min_length, max_length, average;
4022 DEBUGFUNC("e1000_phy_igp_get_info");
4024 /* The downshift status is checked only once, after link is established,
4025 * and it stored in the hw->speed_downgraded parameter. */
4026 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4028 /* IGP01E1000 does not need to support it. */
4029 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4031 /* IGP01E1000 always correct polarity reversal */
4032 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4034 /* Check polarity status */
4035 ret_val = e1000_check_polarity(hw, &polarity);
4039 phy_info->cable_polarity = polarity;
4041 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4045 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
4046 IGP01E1000_PSSR_MDIX_SHIFT;
4048 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4049 IGP01E1000_PSSR_SPEED_1000MBPS) {
4050 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4051 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4055 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4056 SR_1000T_LOCAL_RX_STATUS_SHIFT;
4057 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4058 SR_1000T_REMOTE_RX_STATUS_SHIFT;
4060 /* Get cable length */
4061 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4065 /* Translate to old method */
4066 average = (max_length + min_length) / 2;
4068 if(average <= e1000_igp_cable_length_50)
4069 phy_info->cable_length = e1000_cable_length_50;
4070 else if(average <= e1000_igp_cable_length_80)
4071 phy_info->cable_length = e1000_cable_length_50_80;
4072 else if(average <= e1000_igp_cable_length_110)
4073 phy_info->cable_length = e1000_cable_length_80_110;
4074 else if(average <= e1000_igp_cable_length_140)
4075 phy_info->cable_length = e1000_cable_length_110_140;
4077 phy_info->cable_length = e1000_cable_length_140;
4080 return E1000_SUCCESS;
4083 /******************************************************************************
4084 * Get PHY information from various PHY registers for ife PHY only.
4086 * hw - Struct containing variables accessed by shared code
4087 * phy_info - PHY information structure
4088 ******************************************************************************/
4090 e1000_phy_ife_get_info(struct e1000_hw *hw,
4091 struct e1000_phy_info *phy_info)
4094 uint16_t phy_data, polarity;
4096 DEBUGFUNC("e1000_phy_ife_get_info");
4098 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4099 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4101 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4104 phy_info->polarity_correction =
4105 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4106 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT;
4108 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4109 ret_val = e1000_check_polarity(hw, &polarity);
4113 /* Polarity is forced. */
4114 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >>
4115 IFE_PSC_FORCE_POLARITY_SHIFT;
4117 phy_info->cable_polarity = polarity;
4119 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4123 phy_info->mdix_mode =
4124 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4125 IFE_PMC_MDIX_MODE_SHIFT;
4127 return E1000_SUCCESS;
4130 /******************************************************************************
4131 * Get PHY information from various PHY registers fot m88 PHY only.
4133 * hw - Struct containing variables accessed by shared code
4134 * phy_info - PHY information structure
4135 ******************************************************************************/
4137 e1000_phy_m88_get_info(struct e1000_hw *hw,
4138 struct e1000_phy_info *phy_info)
4141 uint16_t phy_data, polarity;
4143 DEBUGFUNC("e1000_phy_m88_get_info");
4145 /* The downshift status is checked only once, after link is established,
4146 * and it stored in the hw->speed_downgraded parameter. */
4147 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4149 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4153 phy_info->extended_10bt_distance =
4154 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4155 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
4156 phy_info->polarity_correction =
4157 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4158 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
4160 /* Check polarity status */
4161 ret_val = e1000_check_polarity(hw, &polarity);
4164 phy_info->cable_polarity = polarity;
4166 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4170 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
4171 M88E1000_PSSR_MDIX_SHIFT;
4173 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4174 /* Cable Length Estimation and Local/Remote Receiver Information
4175 * are only valid at 1000 Mbps.
4177 if (hw->phy_type != e1000_phy_gg82563) {
4178 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4179 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4181 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4186 phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
4189 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4193 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4194 SR_1000T_LOCAL_RX_STATUS_SHIFT;
4196 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4197 SR_1000T_REMOTE_RX_STATUS_SHIFT;
4200 return E1000_SUCCESS;
4203 /******************************************************************************
4204 * Get PHY information from various PHY registers
4206 * hw - Struct containing variables accessed by shared code
4207 * phy_info - PHY information structure
4208 ******************************************************************************/
4210 e1000_phy_get_info(struct e1000_hw *hw,
4211 struct e1000_phy_info *phy_info)
4216 DEBUGFUNC("e1000_phy_get_info");
4218 phy_info->cable_length = e1000_cable_length_undefined;
4219 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4220 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4221 phy_info->downshift = e1000_downshift_undefined;
4222 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4223 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4224 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4225 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4227 if(hw->media_type != e1000_media_type_copper) {
4228 DEBUGOUT("PHY info is only valid for copper media\n");
4229 return -E1000_ERR_CONFIG;
4232 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4236 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4240 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4241 DEBUGOUT("PHY info is only valid if link is up\n");
4242 return -E1000_ERR_CONFIG;
4245 if (hw->phy_type == e1000_phy_igp ||
4246 hw->phy_type == e1000_phy_igp_3 ||
4247 hw->phy_type == e1000_phy_igp_2)
4248 return e1000_phy_igp_get_info(hw, phy_info);
4249 else if (hw->phy_type == e1000_phy_ife)
4250 return e1000_phy_ife_get_info(hw, phy_info);
4252 return e1000_phy_m88_get_info(hw, phy_info);
4256 e1000_validate_mdi_setting(struct e1000_hw *hw)
4258 DEBUGFUNC("e1000_validate_mdi_settings");
4260 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4261 DEBUGOUT("Invalid MDI setting detected\n");
4263 return -E1000_ERR_CONFIG;
4265 return E1000_SUCCESS;
4269 /******************************************************************************
4270 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4271 * is configured. Additionally, if this is ICH8, the flash controller GbE
4272 * registers must be mapped, or this will crash.
4274 * hw - Struct containing variables accessed by shared code
4275 *****************************************************************************/
4277 e1000_init_eeprom_params(struct e1000_hw *hw)
4279 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4280 uint32_t eecd = E1000_READ_REG(hw, EECD);
4281 int32_t ret_val = E1000_SUCCESS;
4282 uint16_t eeprom_size;
4284 DEBUGFUNC("e1000_init_eeprom_params");
4286 switch (hw->mac_type) {
4287 case e1000_82542_rev2_0:
4288 case e1000_82542_rev2_1:
4291 eeprom->type = e1000_eeprom_microwire;
4292 eeprom->word_size = 64;
4293 eeprom->opcode_bits = 3;
4294 eeprom->address_bits = 6;
4295 eeprom->delay_usec = 50;
4296 eeprom->use_eerd = FALSE;
4297 eeprom->use_eewr = FALSE;
4301 case e1000_82545_rev_3:
4303 case e1000_82546_rev_3:
4304 eeprom->type = e1000_eeprom_microwire;
4305 eeprom->opcode_bits = 3;
4306 eeprom->delay_usec = 50;
4307 if(eecd & E1000_EECD_SIZE) {
4308 eeprom->word_size = 256;
4309 eeprom->address_bits = 8;
4311 eeprom->word_size = 64;
4312 eeprom->address_bits = 6;
4314 eeprom->use_eerd = FALSE;
4315 eeprom->use_eewr = FALSE;
4318 case e1000_82541_rev_2:
4320 case e1000_82547_rev_2:
4321 if (eecd & E1000_EECD_TYPE) {
4322 eeprom->type = e1000_eeprom_spi;
4323 eeprom->opcode_bits = 8;
4324 eeprom->delay_usec = 1;
4325 if (eecd & E1000_EECD_ADDR_BITS) {
4326 eeprom->page_size = 32;
4327 eeprom->address_bits = 16;
4329 eeprom->page_size = 8;
4330 eeprom->address_bits = 8;
4333 eeprom->type = e1000_eeprom_microwire;
4334 eeprom->opcode_bits = 3;
4335 eeprom->delay_usec = 50;
4336 if (eecd & E1000_EECD_ADDR_BITS) {
4337 eeprom->word_size = 256;
4338 eeprom->address_bits = 8;
4340 eeprom->word_size = 64;
4341 eeprom->address_bits = 6;
4344 eeprom->use_eerd = FALSE;
4345 eeprom->use_eewr = FALSE;
4349 eeprom->type = e1000_eeprom_spi;
4350 eeprom->opcode_bits = 8;
4351 eeprom->delay_usec = 1;
4352 if (eecd & E1000_EECD_ADDR_BITS) {
4353 eeprom->page_size = 32;
4354 eeprom->address_bits = 16;
4356 eeprom->page_size = 8;
4357 eeprom->address_bits = 8;
4359 eeprom->use_eerd = FALSE;
4360 eeprom->use_eewr = FALSE;
4363 eeprom->type = e1000_eeprom_spi;
4364 eeprom->opcode_bits = 8;
4365 eeprom->delay_usec = 1;
4366 if (eecd & E1000_EECD_ADDR_BITS) {
4367 eeprom->page_size = 32;
4368 eeprom->address_bits = 16;
4370 eeprom->page_size = 8;
4371 eeprom->address_bits = 8;
4373 eeprom->use_eerd = TRUE;
4374 eeprom->use_eewr = TRUE;
4375 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4376 eeprom->type = e1000_eeprom_flash;
4377 eeprom->word_size = 2048;
4379 /* Ensure that the Autonomous FLASH update bit is cleared due to
4380 * Flash update issue on parts which use a FLASH for NVM. */
4381 eecd &= ~E1000_EECD_AUPDEN;
4382 E1000_WRITE_REG(hw, EECD, eecd);
4385 case e1000_80003es2lan:
4386 eeprom->type = e1000_eeprom_spi;
4387 eeprom->opcode_bits = 8;
4388 eeprom->delay_usec = 1;
4389 if (eecd & E1000_EECD_ADDR_BITS) {
4390 eeprom->page_size = 32;
4391 eeprom->address_bits = 16;
4393 eeprom->page_size = 8;
4394 eeprom->address_bits = 8;
4396 eeprom->use_eerd = TRUE;
4397 eeprom->use_eewr = FALSE;
4402 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4404 eeprom->type = e1000_eeprom_ich8;
4405 eeprom->use_eerd = FALSE;
4406 eeprom->use_eewr = FALSE;
4407 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4409 /* Zero the shadow RAM structure. But don't load it from NVM
4410 * so as to save time for driver init */
4411 if (hw->eeprom_shadow_ram != NULL) {
4412 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4413 hw->eeprom_shadow_ram[i].modified = FALSE;
4414 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4418 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4419 ICH8_FLASH_SECTOR_SIZE;
4421 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4422 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4423 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4424 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4432 if (eeprom->type == e1000_eeprom_spi) {
4433 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4434 * 32KB (incremented by powers of 2).
4436 if(hw->mac_type <= e1000_82547_rev_2) {
4437 /* Set to default value for initial eeprom read. */
4438 eeprom->word_size = 64;
4439 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4442 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4443 /* 256B eeprom size was not supported in earlier hardware, so we
4444 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4445 * is never the result used in the shifting logic below. */
4449 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4450 E1000_EECD_SIZE_EX_SHIFT);
4453 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4458 /******************************************************************************
4459 * Raises the EEPROM's clock input.
4461 * hw - Struct containing variables accessed by shared code
4462 * eecd - EECD's current value
4463 *****************************************************************************/
4465 e1000_raise_ee_clk(struct e1000_hw *hw,
4468 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4469 * wait <delay> microseconds.
4471 *eecd = *eecd | E1000_EECD_SK;
4472 E1000_WRITE_REG(hw, EECD, *eecd);
4473 E1000_WRITE_FLUSH(hw);
4474 udelay(hw->eeprom.delay_usec);
4477 /******************************************************************************
4478 * Lowers the EEPROM's clock input.
4480 * hw - Struct containing variables accessed by shared code
4481 * eecd - EECD's current value
4482 *****************************************************************************/
4484 e1000_lower_ee_clk(struct e1000_hw *hw,
4487 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4488 * wait 50 microseconds.
4490 *eecd = *eecd & ~E1000_EECD_SK;
4491 E1000_WRITE_REG(hw, EECD, *eecd);
4492 E1000_WRITE_FLUSH(hw);
4493 udelay(hw->eeprom.delay_usec);
4496 /******************************************************************************
4497 * Shift data bits out to the EEPROM.
4499 * hw - Struct containing variables accessed by shared code
4500 * data - data to send to the EEPROM
4501 * count - number of bits to shift out
4502 *****************************************************************************/
4504 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4508 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4512 /* We need to shift "count" bits out to the EEPROM. So, value in the
4513 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4514 * In order to do this, "data" must be broken down into bits.
4516 mask = 0x01 << (count - 1);
4517 eecd = E1000_READ_REG(hw, EECD);
4518 if (eeprom->type == e1000_eeprom_microwire) {
4519 eecd &= ~E1000_EECD_DO;
4520 } else if (eeprom->type == e1000_eeprom_spi) {
4521 eecd |= E1000_EECD_DO;
4524 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4525 * and then raising and then lowering the clock (the SK bit controls
4526 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4527 * by setting "DI" to "0" and then raising and then lowering the clock.
4529 eecd &= ~E1000_EECD_DI;
4532 eecd |= E1000_EECD_DI;
4534 E1000_WRITE_REG(hw, EECD, eecd);
4535 E1000_WRITE_FLUSH(hw);
4537 udelay(eeprom->delay_usec);
4539 e1000_raise_ee_clk(hw, &eecd);
4540 e1000_lower_ee_clk(hw, &eecd);
4546 /* We leave the "DI" bit set to "0" when we leave this routine. */
4547 eecd &= ~E1000_EECD_DI;
4548 E1000_WRITE_REG(hw, EECD, eecd);
4551 /******************************************************************************
4552 * Shift data bits in from the EEPROM
4554 * hw - Struct containing variables accessed by shared code
4555 *****************************************************************************/
4557 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4564 /* In order to read a register from the EEPROM, we need to shift 'count'
4565 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4566 * input to the EEPROM (setting the SK bit), and then reading the value of
4567 * the "DO" bit. During this "shifting in" process the "DI" bit should
4571 eecd = E1000_READ_REG(hw, EECD);
4573 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4576 for(i = 0; i < count; i++) {
4578 e1000_raise_ee_clk(hw, &eecd);
4580 eecd = E1000_READ_REG(hw, EECD);
4582 eecd &= ~(E1000_EECD_DI);
4583 if(eecd & E1000_EECD_DO)
4586 e1000_lower_ee_clk(hw, &eecd);
4592 /******************************************************************************
4593 * Prepares EEPROM for access
4595 * hw - Struct containing variables accessed by shared code
4597 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4598 * function should be called before issuing a command to the EEPROM.
4599 *****************************************************************************/
4601 e1000_acquire_eeprom(struct e1000_hw *hw)
4603 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4606 DEBUGFUNC("e1000_acquire_eeprom");
4608 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4609 return -E1000_ERR_SWFW_SYNC;
4610 eecd = E1000_READ_REG(hw, EECD);
4612 if (hw->mac_type != e1000_82573) {
4613 /* Request EEPROM Access */
4614 if(hw->mac_type > e1000_82544) {
4615 eecd |= E1000_EECD_REQ;
4616 E1000_WRITE_REG(hw, EECD, eecd);
4617 eecd = E1000_READ_REG(hw, EECD);
4618 while((!(eecd & E1000_EECD_GNT)) &&
4619 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4622 eecd = E1000_READ_REG(hw, EECD);
4624 if(!(eecd & E1000_EECD_GNT)) {
4625 eecd &= ~E1000_EECD_REQ;
4626 E1000_WRITE_REG(hw, EECD, eecd);
4627 DEBUGOUT("Could not acquire EEPROM grant\n");
4628 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4629 return -E1000_ERR_EEPROM;
4634 /* Setup EEPROM for Read/Write */
4636 if (eeprom->type == e1000_eeprom_microwire) {
4637 /* Clear SK and DI */
4638 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4639 E1000_WRITE_REG(hw, EECD, eecd);
4642 eecd |= E1000_EECD_CS;
4643 E1000_WRITE_REG(hw, EECD, eecd);
4644 } else if (eeprom->type == e1000_eeprom_spi) {
4645 /* Clear SK and CS */
4646 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4647 E1000_WRITE_REG(hw, EECD, eecd);
4651 return E1000_SUCCESS;
4654 /******************************************************************************
4655 * Returns EEPROM to a "standby" state
4657 * hw - Struct containing variables accessed by shared code
4658 *****************************************************************************/
4660 e1000_standby_eeprom(struct e1000_hw *hw)
4662 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4665 eecd = E1000_READ_REG(hw, EECD);
4667 if(eeprom->type == e1000_eeprom_microwire) {
4668 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4669 E1000_WRITE_REG(hw, EECD, eecd);
4670 E1000_WRITE_FLUSH(hw);
4671 udelay(eeprom->delay_usec);
4674 eecd |= E1000_EECD_SK;
4675 E1000_WRITE_REG(hw, EECD, eecd);
4676 E1000_WRITE_FLUSH(hw);
4677 udelay(eeprom->delay_usec);
4680 eecd |= E1000_EECD_CS;
4681 E1000_WRITE_REG(hw, EECD, eecd);
4682 E1000_WRITE_FLUSH(hw);
4683 udelay(eeprom->delay_usec);
4686 eecd &= ~E1000_EECD_SK;
4687 E1000_WRITE_REG(hw, EECD, eecd);
4688 E1000_WRITE_FLUSH(hw);
4689 udelay(eeprom->delay_usec);
4690 } else if(eeprom->type == e1000_eeprom_spi) {
4691 /* Toggle CS to flush commands */
4692 eecd |= E1000_EECD_CS;
4693 E1000_WRITE_REG(hw, EECD, eecd);
4694 E1000_WRITE_FLUSH(hw);
4695 udelay(eeprom->delay_usec);
4696 eecd &= ~E1000_EECD_CS;
4697 E1000_WRITE_REG(hw, EECD, eecd);
4698 E1000_WRITE_FLUSH(hw);
4699 udelay(eeprom->delay_usec);
4703 /******************************************************************************
4704 * Terminates a command by inverting the EEPROM's chip select pin
4706 * hw - Struct containing variables accessed by shared code
4707 *****************************************************************************/
4709 e1000_release_eeprom(struct e1000_hw *hw)
4713 DEBUGFUNC("e1000_release_eeprom");
4715 eecd = E1000_READ_REG(hw, EECD);
4717 if (hw->eeprom.type == e1000_eeprom_spi) {
4718 eecd |= E1000_EECD_CS; /* Pull CS high */
4719 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4721 E1000_WRITE_REG(hw, EECD, eecd);
4723 udelay(hw->eeprom.delay_usec);
4724 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
4725 /* cleanup eeprom */
4727 /* CS on Microwire is active-high */
4728 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4730 E1000_WRITE_REG(hw, EECD, eecd);
4732 /* Rising edge of clock */
4733 eecd |= E1000_EECD_SK;
4734 E1000_WRITE_REG(hw, EECD, eecd);
4735 E1000_WRITE_FLUSH(hw);
4736 udelay(hw->eeprom.delay_usec);
4738 /* Falling edge of clock */
4739 eecd &= ~E1000_EECD_SK;
4740 E1000_WRITE_REG(hw, EECD, eecd);
4741 E1000_WRITE_FLUSH(hw);
4742 udelay(hw->eeprom.delay_usec);
4745 /* Stop requesting EEPROM access */
4746 if(hw->mac_type > e1000_82544) {
4747 eecd &= ~E1000_EECD_REQ;
4748 E1000_WRITE_REG(hw, EECD, eecd);
4751 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4754 /******************************************************************************
4755 * Reads a 16 bit word from the EEPROM.
4757 * hw - Struct containing variables accessed by shared code
4758 *****************************************************************************/
4760 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4762 uint16_t retry_count = 0;
4763 uint8_t spi_stat_reg;
4765 DEBUGFUNC("e1000_spi_eeprom_ready");
4767 /* Read "Status Register" repeatedly until the LSB is cleared. The
4768 * EEPROM will signal that the command has been completed by clearing
4769 * bit 0 of the internal status register. If it's not cleared within
4770 * 5 milliseconds, then error out.
4774 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4775 hw->eeprom.opcode_bits);
4776 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4777 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4783 e1000_standby_eeprom(hw);
4784 } while(retry_count < EEPROM_MAX_RETRY_SPI);
4786 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4787 * only 0-5mSec on 5V devices)
4789 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
4790 DEBUGOUT("SPI EEPROM Status error\n");
4791 return -E1000_ERR_EEPROM;
4794 return E1000_SUCCESS;
4797 /******************************************************************************
4798 * Reads a 16 bit word from the EEPROM.
4800 * hw - Struct containing variables accessed by shared code
4801 * offset - offset of word in the EEPROM to read
4802 * data - word read from the EEPROM
4803 * words - number of words to read
4804 *****************************************************************************/
4806 e1000_read_eeprom(struct e1000_hw *hw,
4811 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4815 DEBUGFUNC("e1000_read_eeprom");
4817 /* A check for invalid values: offset too large, too many words, and not
4820 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4822 DEBUGOUT("\"words\" parameter out of bounds\n");
4823 return -E1000_ERR_EEPROM;
4826 /* FLASH reads without acquiring the semaphore are safe */
4827 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4828 hw->eeprom.use_eerd == FALSE) {
4829 switch (hw->mac_type) {
4830 case e1000_80003es2lan:
4833 /* Prepare the EEPROM for reading */
4834 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4835 return -E1000_ERR_EEPROM;
4840 if (eeprom->use_eerd == TRUE) {
4841 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
4842 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
4843 (hw->mac_type != e1000_82573))
4844 e1000_release_eeprom(hw);
4848 if (eeprom->type == e1000_eeprom_ich8)
4849 return e1000_read_eeprom_ich8(hw, offset, words, data);
4851 if (eeprom->type == e1000_eeprom_spi) {
4853 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4855 if(e1000_spi_eeprom_ready(hw)) {
4856 e1000_release_eeprom(hw);
4857 return -E1000_ERR_EEPROM;
4860 e1000_standby_eeprom(hw);
4862 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4863 if((eeprom->address_bits == 8) && (offset >= 128))
4864 read_opcode |= EEPROM_A8_OPCODE_SPI;
4866 /* Send the READ command (opcode + addr) */
4867 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4868 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
4870 /* Read the data. The address of the eeprom internally increments with
4871 * each byte (spi) being read, saving on the overhead of eeprom setup
4872 * and tear-down. The address counter will roll over if reading beyond
4873 * the size of the eeprom, thus allowing the entire memory to be read
4874 * starting from any offset. */
4875 for (i = 0; i < words; i++) {
4876 word_in = e1000_shift_in_ee_bits(hw, 16);
4877 data[i] = (word_in >> 8) | (word_in << 8);
4879 } else if(eeprom->type == e1000_eeprom_microwire) {
4880 for (i = 0; i < words; i++) {
4881 /* Send the READ command (opcode + addr) */
4882 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4883 eeprom->opcode_bits);
4884 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
4885 eeprom->address_bits);
4887 /* Read the data. For microwire, each word requires the overhead
4888 * of eeprom setup and tear-down. */
4889 data[i] = e1000_shift_in_ee_bits(hw, 16);
4890 e1000_standby_eeprom(hw);
4894 /* End this read operation */
4895 e1000_release_eeprom(hw);
4897 return E1000_SUCCESS;
4900 /******************************************************************************
4901 * Reads a 16 bit word from the EEPROM using the EERD register.
4903 * hw - Struct containing variables accessed by shared code
4904 * offset - offset of word in the EEPROM to read
4905 * data - word read from the EEPROM
4906 * words - number of words to read
4907 *****************************************************************************/
4909 e1000_read_eeprom_eerd(struct e1000_hw *hw,
4914 uint32_t i, eerd = 0;
4917 for (i = 0; i < words; i++) {
4918 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
4919 E1000_EEPROM_RW_REG_START;
4921 E1000_WRITE_REG(hw, EERD, eerd);
4922 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
4927 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
4934 /******************************************************************************
4935 * Writes a 16 bit word from the EEPROM using the EEWR register.
4937 * hw - Struct containing variables accessed by shared code
4938 * offset - offset of word in the EEPROM to read
4939 * data - word read from the EEPROM
4940 * words - number of words to read
4941 *****************************************************************************/
4943 e1000_write_eeprom_eewr(struct e1000_hw *hw,
4948 uint32_t register_value = 0;
4952 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4953 return -E1000_ERR_SWFW_SYNC;
4955 for (i = 0; i < words; i++) {
4956 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
4957 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
4958 E1000_EEPROM_RW_REG_START;
4960 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4965 E1000_WRITE_REG(hw, EEWR, register_value);
4967 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4974 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4978 /******************************************************************************
4979 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
4981 * hw - Struct containing variables accessed by shared code
4982 *****************************************************************************/
4984 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
4986 uint32_t attempts = 100000;
4987 uint32_t i, reg = 0;
4988 int32_t done = E1000_ERR_EEPROM;
4990 for(i = 0; i < attempts; i++) {
4991 if(eerd == E1000_EEPROM_POLL_READ)
4992 reg = E1000_READ_REG(hw, EERD);
4994 reg = E1000_READ_REG(hw, EEWR);
4996 if(reg & E1000_EEPROM_RW_REG_DONE) {
4997 done = E1000_SUCCESS;
5006 /***************************************************************************
5007 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5009 * hw - Struct containing variables accessed by shared code
5010 ****************************************************************************/
5012 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5016 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5018 if (hw->mac_type == e1000_ich8lan)
5021 if (hw->mac_type == e1000_82573) {
5022 eecd = E1000_READ_REG(hw, EECD);
5024 /* Isolate bits 15 & 16 */
5025 eecd = ((eecd >> 15) & 0x03);
5027 /* If both bits are set, device is Flash type */
5035 /******************************************************************************
5036 * Verifies that the EEPROM has a valid checksum
5038 * hw - Struct containing variables accessed by shared code
5040 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5041 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5043 *****************************************************************************/
5045 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5047 uint16_t checksum = 0;
5048 uint16_t i, eeprom_data;
5050 DEBUGFUNC("e1000_validate_eeprom_checksum");
5052 if ((hw->mac_type == e1000_82573) &&
5053 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5054 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5055 * 10h-12h. Checksum may need to be fixed. */
5056 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5057 if ((eeprom_data & 0x10) == 0) {
5058 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5059 * has already been fixed. If the checksum is still wrong and this
5060 * bit is a 1, we need to return bad checksum. Otherwise, we need
5061 * to set this bit to a 1 and update the checksum. */
5062 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5063 if ((eeprom_data & 0x8000) == 0) {
5064 eeprom_data |= 0x8000;
5065 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5066 e1000_update_eeprom_checksum(hw);
5071 if (hw->mac_type == e1000_ich8lan) {
5072 /* Drivers must allocate the shadow ram structure for the
5073 * EEPROM checksum to be updated. Otherwise, this bit as well
5074 * as the checksum must both be set correctly for this
5075 * validation to pass.
5077 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5078 if ((eeprom_data & 0x40) == 0) {
5079 eeprom_data |= 0x40;
5080 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5081 e1000_update_eeprom_checksum(hw);
5085 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5086 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5087 DEBUGOUT("EEPROM Read Error\n");
5088 return -E1000_ERR_EEPROM;
5090 checksum += eeprom_data;
5093 if(checksum == (uint16_t) EEPROM_SUM)
5094 return E1000_SUCCESS;
5096 DEBUGOUT("EEPROM Checksum Invalid\n");
5097 return -E1000_ERR_EEPROM;
5101 /******************************************************************************
5102 * Calculates the EEPROM checksum and writes it to the EEPROM
5104 * hw - Struct containing variables accessed by shared code
5106 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5107 * Writes the difference to word offset 63 of the EEPROM.
5108 *****************************************************************************/
5110 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5113 uint16_t checksum = 0;
5114 uint16_t i, eeprom_data;
5116 DEBUGFUNC("e1000_update_eeprom_checksum");
5118 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5119 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5120 DEBUGOUT("EEPROM Read Error\n");
5121 return -E1000_ERR_EEPROM;
5123 checksum += eeprom_data;
5125 checksum = (uint16_t) EEPROM_SUM - checksum;
5126 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5127 DEBUGOUT("EEPROM Write Error\n");
5128 return -E1000_ERR_EEPROM;
5129 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5130 e1000_commit_shadow_ram(hw);
5131 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5132 e1000_commit_shadow_ram(hw);
5133 /* Reload the EEPROM, or else modifications will not appear
5134 * until after next adapter reset. */
5135 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5136 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5137 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5140 return E1000_SUCCESS;
5143 /******************************************************************************
5144 * Parent function for writing words to the different EEPROM types.
5146 * hw - Struct containing variables accessed by shared code
5147 * offset - offset within the EEPROM to be written to
5148 * words - number of words to write
5149 * data - 16 bit word to be written to the EEPROM
5151 * If e1000_update_eeprom_checksum is not called after this function, the
5152 * EEPROM will most likely contain an invalid checksum.
5153 *****************************************************************************/
5155 e1000_write_eeprom(struct e1000_hw *hw,
5160 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5163 DEBUGFUNC("e1000_write_eeprom");
5165 /* A check for invalid values: offset too large, too many words, and not
5168 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5170 DEBUGOUT("\"words\" parameter out of bounds\n");
5171 return -E1000_ERR_EEPROM;
5174 /* 82573 writes only through eewr */
5175 if(eeprom->use_eewr == TRUE)
5176 return e1000_write_eeprom_eewr(hw, offset, words, data);
5178 if (eeprom->type == e1000_eeprom_ich8)
5179 return e1000_write_eeprom_ich8(hw, offset, words, data);
5181 /* Prepare the EEPROM for writing */
5182 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5183 return -E1000_ERR_EEPROM;
5185 if(eeprom->type == e1000_eeprom_microwire) {
5186 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5188 status = e1000_write_eeprom_spi(hw, offset, words, data);
5192 /* Done with writing */
5193 e1000_release_eeprom(hw);
5198 /******************************************************************************
5199 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5201 * hw - Struct containing variables accessed by shared code
5202 * offset - offset within the EEPROM to be written to
5203 * words - number of words to write
5204 * data - pointer to array of 8 bit words to be written to the EEPROM
5206 *****************************************************************************/
5208 e1000_write_eeprom_spi(struct e1000_hw *hw,
5213 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5216 DEBUGFUNC("e1000_write_eeprom_spi");
5218 while (widx < words) {
5219 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5221 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5223 e1000_standby_eeprom(hw);
5225 /* Send the WRITE ENABLE command (8 bit opcode ) */
5226 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5227 eeprom->opcode_bits);
5229 e1000_standby_eeprom(hw);
5231 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5232 if((eeprom->address_bits == 8) && (offset >= 128))
5233 write_opcode |= EEPROM_A8_OPCODE_SPI;
5235 /* Send the Write command (8-bit opcode + addr) */
5236 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5238 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5239 eeprom->address_bits);
5243 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5244 while (widx < words) {
5245 uint16_t word_out = data[widx];
5246 word_out = (word_out >> 8) | (word_out << 8);
5247 e1000_shift_out_ee_bits(hw, word_out, 16);
5250 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5251 * operation, while the smaller eeproms are capable of an 8-byte
5252 * PAGE WRITE operation. Break the inner loop to pass new address
5254 if((((offset + widx)*2) % eeprom->page_size) == 0) {
5255 e1000_standby_eeprom(hw);
5261 return E1000_SUCCESS;
5264 /******************************************************************************
5265 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5267 * hw - Struct containing variables accessed by shared code
5268 * offset - offset within the EEPROM to be written to
5269 * words - number of words to write
5270 * data - pointer to array of 16 bit words to be written to the EEPROM
5272 *****************************************************************************/
5274 e1000_write_eeprom_microwire(struct e1000_hw *hw,
5279 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5281 uint16_t words_written = 0;
5284 DEBUGFUNC("e1000_write_eeprom_microwire");
5286 /* Send the write enable command to the EEPROM (3-bit opcode plus
5287 * 6/8-bit dummy address beginning with 11). It's less work to include
5288 * the 11 of the dummy address as part of the opcode than it is to shift
5289 * it over the correct number of bits for the address. This puts the
5290 * EEPROM into write/erase mode.
5292 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5293 (uint16_t)(eeprom->opcode_bits + 2));
5295 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5297 /* Prepare the EEPROM */
5298 e1000_standby_eeprom(hw);
5300 while (words_written < words) {
5301 /* Send the Write command (3-bit opcode + addr) */
5302 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5303 eeprom->opcode_bits);
5305 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5306 eeprom->address_bits);
5309 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5311 /* Toggle the CS line. This in effect tells the EEPROM to execute
5312 * the previous command.
5314 e1000_standby_eeprom(hw);
5316 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5317 * signal that the command has been completed by raising the DO signal.
5318 * If DO does not go high in 10 milliseconds, then error out.
5320 for(i = 0; i < 200; i++) {
5321 eecd = E1000_READ_REG(hw, EECD);
5322 if(eecd & E1000_EECD_DO) break;
5326 DEBUGOUT("EEPROM Write did not complete\n");
5327 return -E1000_ERR_EEPROM;
5330 /* Recover from write */
5331 e1000_standby_eeprom(hw);
5336 /* Send the write disable command to the EEPROM (3-bit opcode plus
5337 * 6/8-bit dummy address beginning with 10). It's less work to include
5338 * the 10 of the dummy address as part of the opcode than it is to shift
5339 * it over the correct number of bits for the address. This takes the
5340 * EEPROM out of write/erase mode.
5342 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5343 (uint16_t)(eeprom->opcode_bits + 2));
5345 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5347 return E1000_SUCCESS;
5350 /******************************************************************************
5351 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5352 * in the eeprom cache and the non modified values in the currently active bank
5355 * hw - Struct containing variables accessed by shared code
5356 * offset - offset of word in the EEPROM to read
5357 * data - word read from the EEPROM
5358 * words - number of words to read
5359 *****************************************************************************/
5361 e1000_commit_shadow_ram(struct e1000_hw *hw)
5363 uint32_t attempts = 100000;
5367 int32_t error = E1000_SUCCESS;
5368 uint32_t old_bank_offset = 0;
5369 uint32_t new_bank_offset = 0;
5370 uint32_t sector_retries = 0;
5371 uint8_t low_byte = 0;
5372 uint8_t high_byte = 0;
5373 uint8_t temp_byte = 0;
5374 boolean_t sector_write_failed = FALSE;
5376 if (hw->mac_type == e1000_82573) {
5377 /* The flop register will be used to determine if flash type is STM */
5378 flop = E1000_READ_REG(hw, FLOP);
5379 for (i=0; i < attempts; i++) {
5380 eecd = E1000_READ_REG(hw, EECD);
5381 if ((eecd & E1000_EECD_FLUPD) == 0) {
5387 if (i == attempts) {
5388 return -E1000_ERR_EEPROM;
5391 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5392 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5393 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5396 /* Perform the flash update */
5397 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5399 for (i=0; i < attempts; i++) {
5400 eecd = E1000_READ_REG(hw, EECD);
5401 if ((eecd & E1000_EECD_FLUPD) == 0) {
5407 if (i == attempts) {
5408 return -E1000_ERR_EEPROM;
5412 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5413 /* We're writing to the opposite bank so if we're on bank 1,
5414 * write to bank 0 etc. We also need to erase the segment that
5415 * is going to be written */
5416 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5417 new_bank_offset = hw->flash_bank_size * 2;
5418 old_bank_offset = 0;
5419 e1000_erase_ich8_4k_segment(hw, 1);
5421 old_bank_offset = hw->flash_bank_size * 2;
5422 new_bank_offset = 0;
5423 e1000_erase_ich8_4k_segment(hw, 0);
5427 sector_write_failed = FALSE;
5428 /* Loop for every byte in the shadow RAM,
5429 * which is in units of words. */
5430 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5431 /* Determine whether to write the value stored
5432 * in the other NVM bank or a modified value stored
5433 * in the shadow RAM */
5434 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5435 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5436 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5439 error = e1000_verify_write_ich8_byte(hw,
5440 (i << 1) + new_bank_offset,
5442 if (error != E1000_SUCCESS)
5443 sector_write_failed = TRUE;
5445 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5446 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5450 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5453 error = e1000_verify_write_ich8_byte(hw,
5454 (i << 1) + new_bank_offset, low_byte);
5455 if (error != E1000_SUCCESS)
5456 sector_write_failed = TRUE;
5457 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5461 /* If the word is 0x13, then make sure the signature bits
5462 * (15:14) are 11b until the commit has completed.
5463 * This will allow us to write 10b which indicates the
5464 * signature is valid. We want to do this after the write
5465 * has completed so that we don't mark the segment valid
5466 * while the write is still in progress */
5467 if (i == E1000_ICH8_NVM_SIG_WORD)
5468 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5470 error = e1000_verify_write_ich8_byte(hw,
5471 (i << 1) + new_bank_offset + 1, high_byte);
5472 if (error != E1000_SUCCESS)
5473 sector_write_failed = TRUE;
5475 if (sector_write_failed == FALSE) {
5476 /* Clear the now not used entry in the cache */
5477 hw->eeprom_shadow_ram[i].modified = FALSE;
5478 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5482 /* Don't bother writing the segment valid bits if sector
5483 * programming failed. */
5484 if (sector_write_failed == FALSE) {
5485 /* Finally validate the new segment by setting bit 15:14
5486 * to 10b in word 0x13 , this can be done without an
5487 * erase as well since these bits are 11 to start with
5488 * and we need to change bit 14 to 0b */
5489 e1000_read_ich8_byte(hw,
5490 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5493 error = e1000_verify_write_ich8_byte(hw,
5494 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5496 if (error != E1000_SUCCESS)
5497 sector_write_failed = TRUE;
5499 /* And invalidate the previously valid segment by setting
5500 * its signature word (0x13) high_byte to 0b. This can be
5501 * done without an erase because flash erase sets all bits
5502 * to 1's. We can write 1's to 0's without an erase */
5503 error = e1000_verify_write_ich8_byte(hw,
5504 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5506 if (error != E1000_SUCCESS)
5507 sector_write_failed = TRUE;
5509 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5515 /******************************************************************************
5516 * Reads the adapter's part number from the EEPROM
5518 * hw - Struct containing variables accessed by shared code
5519 * part_num - Adapter's part number
5520 *****************************************************************************/
5522 e1000_read_part_num(struct e1000_hw *hw,
5525 uint16_t offset = EEPROM_PBA_BYTE_1;
5526 uint16_t eeprom_data;
5528 DEBUGFUNC("e1000_read_part_num");
5530 /* Get word 0 from EEPROM */
5531 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5532 DEBUGOUT("EEPROM Read Error\n");
5533 return -E1000_ERR_EEPROM;
5535 /* Save word 0 in upper half of part_num */
5536 *part_num = (uint32_t) (eeprom_data << 16);
5538 /* Get word 1 from EEPROM */
5539 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
5540 DEBUGOUT("EEPROM Read Error\n");
5541 return -E1000_ERR_EEPROM;
5543 /* Save word 1 in lower half of part_num */
5544 *part_num |= eeprom_data;
5546 return E1000_SUCCESS;
5549 /******************************************************************************
5550 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5551 * second function of dual function devices
5553 * hw - Struct containing variables accessed by shared code
5554 *****************************************************************************/
5556 e1000_read_mac_addr(struct e1000_hw * hw)
5559 uint16_t eeprom_data, i;
5561 DEBUGFUNC("e1000_read_mac_addr");
5563 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5565 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5566 DEBUGOUT("EEPROM Read Error\n");
5567 return -E1000_ERR_EEPROM;
5569 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5570 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5573 switch (hw->mac_type) {
5577 case e1000_82546_rev_3:
5579 case e1000_80003es2lan:
5580 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5581 hw->perm_mac_addr[5] ^= 0x01;
5585 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
5586 hw->mac_addr[i] = hw->perm_mac_addr[i];
5587 return E1000_SUCCESS;
5590 /******************************************************************************
5591 * Initializes receive address filters.
5593 * hw - Struct containing variables accessed by shared code
5595 * Places the MAC address in receive address register 0 and clears the rest
5596 * of the receive addresss registers. Clears the multicast table. Assumes
5597 * the receiver is in reset when the routine is called.
5598 *****************************************************************************/
5600 e1000_init_rx_addrs(struct e1000_hw *hw)
5605 DEBUGFUNC("e1000_init_rx_addrs");
5607 /* Setup the receive address. */
5608 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5610 e1000_rar_set(hw, hw->mac_addr, 0);
5612 rar_num = E1000_RAR_ENTRIES;
5614 /* Reserve a spot for the Locally Administered Address to work around
5615 * an 82571 issue in which a reset on one port will reload the MAC on
5616 * the other port. */
5617 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5619 if (hw->mac_type == e1000_ich8lan)
5620 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5622 /* Zero out the other 15 receive addresses. */
5623 DEBUGOUT("Clearing RAR[1-15]\n");
5624 for(i = 1; i < rar_num; i++) {
5625 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5626 E1000_WRITE_FLUSH(hw);
5627 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5628 E1000_WRITE_FLUSH(hw);
5632 /******************************************************************************
5633 * Updates the MAC's list of multicast addresses.
5635 * hw - Struct containing variables accessed by shared code
5636 * mc_addr_list - the list of new multicast addresses
5637 * mc_addr_count - number of addresses
5638 * pad - number of bytes between addresses in the list
5639 * rar_used_count - offset where to start adding mc addresses into the RAR's
5641 * The given list replaces any existing list. Clears the last 15 receive
5642 * address registers and the multicast table. Uses receive address registers
5643 * for the first 15 multicast addresses, and hashes the rest into the
5645 *****************************************************************************/
5647 e1000_mc_addr_list_update(struct e1000_hw *hw,
5648 uint8_t *mc_addr_list,
5649 uint32_t mc_addr_count,
5651 uint32_t rar_used_count)
5653 uint32_t hash_value;
5655 uint32_t num_rar_entry;
5656 uint32_t num_mta_entry;
5658 DEBUGFUNC("e1000_mc_addr_list_update");
5660 /* Set the new number of MC addresses that we are being requested to use. */
5661 hw->num_mc_addrs = mc_addr_count;
5663 /* Clear RAR[1-15] */
5664 DEBUGOUT(" Clearing RAR[1-15]\n");
5665 num_rar_entry = E1000_RAR_ENTRIES;
5666 if (hw->mac_type == e1000_ich8lan)
5667 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5668 /* Reserve a spot for the Locally Administered Address to work around
5669 * an 82571 issue in which a reset on one port will reload the MAC on
5670 * the other port. */
5671 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5674 for(i = rar_used_count; i < num_rar_entry; i++) {
5675 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5676 E1000_WRITE_FLUSH(hw);
5677 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5678 E1000_WRITE_FLUSH(hw);
5682 DEBUGOUT(" Clearing MTA\n");
5683 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5684 if (hw->mac_type == e1000_ich8lan)
5685 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5686 for(i = 0; i < num_mta_entry; i++) {
5687 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5688 E1000_WRITE_FLUSH(hw);
5691 /* Add the new addresses */
5692 for(i = 0; i < mc_addr_count; i++) {
5693 DEBUGOUT(" Adding the multicast addresses:\n");
5694 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5695 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
5696 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
5697 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
5698 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
5699 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
5700 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
5702 hash_value = e1000_hash_mc_addr(hw,
5704 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
5706 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
5708 /* Place this multicast address in the RAR if there is room, *
5709 * else put it in the MTA
5711 if (rar_used_count < num_rar_entry) {
5713 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
5717 e1000_mta_set(hw, hash_value);
5720 DEBUGOUT("MC Update Complete\n");
5723 /******************************************************************************
5724 * Hashes an address to determine its location in the multicast table
5726 * hw - Struct containing variables accessed by shared code
5727 * mc_addr - the multicast address to hash
5728 *****************************************************************************/
5730 e1000_hash_mc_addr(struct e1000_hw *hw,
5733 uint32_t hash_value = 0;
5735 /* The portion of the address that is used for the hash table is
5736 * determined by the mc_filter_type setting.
5738 switch (hw->mc_filter_type) {
5739 /* [0] [1] [2] [3] [4] [5]
5744 if (hw->mac_type == e1000_ich8lan) {
5745 /* [47:38] i.e. 0x158 for above example address */
5746 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5748 /* [47:36] i.e. 0x563 for above example address */
5749 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5753 if (hw->mac_type == e1000_ich8lan) {
5754 /* [46:37] i.e. 0x2B1 for above example address */
5755 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5757 /* [46:35] i.e. 0xAC6 for above example address */
5758 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5762 if (hw->mac_type == e1000_ich8lan) {
5763 /*[45:36] i.e. 0x163 for above example address */
5764 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5766 /* [45:34] i.e. 0x5D8 for above example address */
5767 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5771 if (hw->mac_type == e1000_ich8lan) {
5772 /* [43:34] i.e. 0x18D for above example address */
5773 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5775 /* [43:32] i.e. 0x634 for above example address */
5776 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5781 hash_value &= 0xFFF;
5782 if (hw->mac_type == e1000_ich8lan)
5783 hash_value &= 0x3FF;
5788 /******************************************************************************
5789 * Sets the bit in the multicast table corresponding to the hash value.
5791 * hw - Struct containing variables accessed by shared code
5792 * hash_value - Multicast address hash value
5793 *****************************************************************************/
5795 e1000_mta_set(struct e1000_hw *hw,
5796 uint32_t hash_value)
5798 uint32_t hash_bit, hash_reg;
5802 /* The MTA is a register array of 128 32-bit registers.
5803 * It is treated like an array of 4096 bits. We want to set
5804 * bit BitArray[hash_value]. So we figure out what register
5805 * the bit is in, read it, OR in the new bit, then write
5806 * back the new value. The register is determined by the
5807 * upper 7 bits of the hash value and the bit within that
5808 * register are determined by the lower 5 bits of the value.
5810 hash_reg = (hash_value >> 5) & 0x7F;
5811 if (hw->mac_type == e1000_ich8lan)
5813 hash_bit = hash_value & 0x1F;
5815 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5817 mta |= (1 << hash_bit);
5819 /* If we are on an 82544 and we are trying to write an odd offset
5820 * in the MTA, save off the previous entry before writing and
5821 * restore the old value after writing.
5823 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5824 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5825 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5826 E1000_WRITE_FLUSH(hw);
5827 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5828 E1000_WRITE_FLUSH(hw);
5830 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5831 E1000_WRITE_FLUSH(hw);
5835 /******************************************************************************
5836 * Puts an ethernet address into a receive address register.
5838 * hw - Struct containing variables accessed by shared code
5839 * addr - Address to put into receive address register
5840 * index - Receive address register to write
5841 *****************************************************************************/
5843 e1000_rar_set(struct e1000_hw *hw,
5847 uint32_t rar_low, rar_high;
5849 /* HW expects these in little endian so we reverse the byte order
5850 * from network order (big endian) to little endian
5852 rar_low = ((uint32_t) addr[0] |
5853 ((uint32_t) addr[1] << 8) |
5854 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5855 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5857 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5861 * If there are any Rx frames queued up or otherwise present in the HW
5862 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5863 * hang. To work around this issue, we have to disable receives and
5864 * flush out all Rx frames before we enable RSS. To do so, we modify we
5865 * redirect all Rx traffic to manageability and then reset the HW.
5866 * This flushes away Rx frames, and (since the redirections to
5867 * manageability persists across resets) keeps new ones from coming in
5868 * while we work. Then, we clear the Address Valid AV bit for all MAC
5869 * addresses and undo the re-direction to manageability.
5870 * Now, frames are coming in again, but the MAC won't accept them, so
5871 * far so good. We now proceed to initialize RSS (if necessary) and
5872 * configure the Rx unit. Last, we re-enable the AV bits and continue
5875 switch (hw->mac_type) {
5878 case e1000_80003es2lan:
5879 if (hw->leave_av_bit_off == TRUE)
5882 /* Indicate to hardware the Address is Valid. */
5883 rar_high |= E1000_RAH_AV;
5887 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5888 E1000_WRITE_FLUSH(hw);
5889 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5890 E1000_WRITE_FLUSH(hw);
5893 /******************************************************************************
5894 * Writes a value to the specified offset in the VLAN filter table.
5896 * hw - Struct containing variables accessed by shared code
5897 * offset - Offset in VLAN filer table to write
5898 * value - Value to write into VLAN filter table
5899 *****************************************************************************/
5901 e1000_write_vfta(struct e1000_hw *hw,
5907 if (hw->mac_type == e1000_ich8lan)
5910 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5911 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5912 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5913 E1000_WRITE_FLUSH(hw);
5914 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5915 E1000_WRITE_FLUSH(hw);
5917 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5918 E1000_WRITE_FLUSH(hw);
5922 /******************************************************************************
5923 * Clears the VLAN filer table
5925 * hw - Struct containing variables accessed by shared code
5926 *****************************************************************************/
5928 e1000_clear_vfta(struct e1000_hw *hw)
5931 uint32_t vfta_value = 0;
5932 uint32_t vfta_offset = 0;
5933 uint32_t vfta_bit_in_reg = 0;
5935 if (hw->mac_type == e1000_ich8lan)
5938 if (hw->mac_type == e1000_82573) {
5939 if (hw->mng_cookie.vlan_id != 0) {
5940 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5941 * ID. The following operations determine which 32b entry
5942 * (i.e. offset) into the array we want to set the VLAN ID
5943 * (i.e. bit) of the manageability unit. */
5944 vfta_offset = (hw->mng_cookie.vlan_id >>
5945 E1000_VFTA_ENTRY_SHIFT) &
5946 E1000_VFTA_ENTRY_MASK;
5947 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5948 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5951 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5952 /* If the offset we want to clear is the same offset of the
5953 * manageability VLAN ID, then clear all bits except that of the
5954 * manageability unit */
5955 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5956 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5957 E1000_WRITE_FLUSH(hw);
5962 e1000_id_led_init(struct e1000_hw * hw)
5965 const uint32_t ledctl_mask = 0x000000FF;
5966 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5967 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5968 uint16_t eeprom_data, i, temp;
5969 const uint16_t led_mask = 0x0F;
5971 DEBUGFUNC("e1000_id_led_init");
5973 if(hw->mac_type < e1000_82540) {
5975 return E1000_SUCCESS;
5978 ledctl = E1000_READ_REG(hw, LEDCTL);
5979 hw->ledctl_default = ledctl;
5980 hw->ledctl_mode1 = hw->ledctl_default;
5981 hw->ledctl_mode2 = hw->ledctl_default;
5983 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
5984 DEBUGOUT("EEPROM Read Error\n");
5985 return -E1000_ERR_EEPROM;
5988 if ((hw->mac_type == e1000_82573) &&
5989 (eeprom_data == ID_LED_RESERVED_82573))
5990 eeprom_data = ID_LED_DEFAULT_82573;
5991 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
5992 (eeprom_data == ID_LED_RESERVED_FFFF)) {
5993 if (hw->mac_type == e1000_ich8lan)
5994 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
5996 eeprom_data = ID_LED_DEFAULT;
5998 for (i = 0; i < 4; i++) {
5999 temp = (eeprom_data >> (i << 2)) & led_mask;
6001 case ID_LED_ON1_DEF2:
6002 case ID_LED_ON1_ON2:
6003 case ID_LED_ON1_OFF2:
6004 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6005 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6007 case ID_LED_OFF1_DEF2:
6008 case ID_LED_OFF1_ON2:
6009 case ID_LED_OFF1_OFF2:
6010 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6011 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6018 case ID_LED_DEF1_ON2:
6019 case ID_LED_ON1_ON2:
6020 case ID_LED_OFF1_ON2:
6021 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6022 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6024 case ID_LED_DEF1_OFF2:
6025 case ID_LED_ON1_OFF2:
6026 case ID_LED_OFF1_OFF2:
6027 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6028 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6035 return E1000_SUCCESS;
6038 /******************************************************************************
6039 * Prepares SW controlable LED for use and saves the current state of the LED.
6041 * hw - Struct containing variables accessed by shared code
6042 *****************************************************************************/
6044 e1000_setup_led(struct e1000_hw *hw)
6047 int32_t ret_val = E1000_SUCCESS;
6049 DEBUGFUNC("e1000_setup_led");
6051 switch(hw->mac_type) {
6052 case e1000_82542_rev2_0:
6053 case e1000_82542_rev2_1:
6056 /* No setup necessary */
6060 case e1000_82541_rev_2:
6061 case e1000_82547_rev_2:
6062 /* Turn off PHY Smart Power Down (if enabled) */
6063 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6064 &hw->phy_spd_default);
6067 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6068 (uint16_t)(hw->phy_spd_default &
6069 ~IGP01E1000_GMII_SPD));
6074 if(hw->media_type == e1000_media_type_fiber) {
6075 ledctl = E1000_READ_REG(hw, LEDCTL);
6076 /* Save current LEDCTL settings */
6077 hw->ledctl_default = ledctl;
6079 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6080 E1000_LEDCTL_LED0_BLINK |
6081 E1000_LEDCTL_LED0_MODE_MASK);
6082 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6083 E1000_LEDCTL_LED0_MODE_SHIFT);
6084 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6085 } else if(hw->media_type == e1000_media_type_copper)
6086 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6090 return E1000_SUCCESS;
6093 /******************************************************************************
6094 * Used on 82571 and later Si that has LED blink bits.
6095 * Callers must use their own timer and should have already called
6096 * e1000_id_led_init()
6097 * Call e1000_cleanup led() to stop blinking
6099 * hw - Struct containing variables accessed by shared code
6100 *****************************************************************************/
6102 e1000_blink_led_start(struct e1000_hw *hw)
6105 uint32_t ledctl_blink = 0;
6107 DEBUGFUNC("e1000_id_led_blink_on");
6109 if (hw->mac_type < e1000_82571) {
6111 return E1000_SUCCESS;
6113 if (hw->media_type == e1000_media_type_fiber) {
6114 /* always blink LED0 for PCI-E fiber */
6115 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6116 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6118 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6119 ledctl_blink = hw->ledctl_mode2;
6120 for (i=0; i < 4; i++)
6121 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6122 E1000_LEDCTL_MODE_LED_ON)
6123 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6126 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6128 return E1000_SUCCESS;
6131 /******************************************************************************
6132 * Restores the saved state of the SW controlable LED.
6134 * hw - Struct containing variables accessed by shared code
6135 *****************************************************************************/
6137 e1000_cleanup_led(struct e1000_hw *hw)
6139 int32_t ret_val = E1000_SUCCESS;
6141 DEBUGFUNC("e1000_cleanup_led");
6143 switch(hw->mac_type) {
6144 case e1000_82542_rev2_0:
6145 case e1000_82542_rev2_1:
6148 /* No cleanup necessary */
6152 case e1000_82541_rev_2:
6153 case e1000_82547_rev_2:
6154 /* Turn on PHY Smart Power Down (if previously enabled) */
6155 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6156 hw->phy_spd_default);
6161 if (hw->phy_type == e1000_phy_ife) {
6162 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6165 /* Restore LEDCTL settings */
6166 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6170 return E1000_SUCCESS;
6173 /******************************************************************************
6174 * Turns on the software controllable LED
6176 * hw - Struct containing variables accessed by shared code
6177 *****************************************************************************/
6179 e1000_led_on(struct e1000_hw *hw)
6181 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6183 DEBUGFUNC("e1000_led_on");
6185 switch(hw->mac_type) {
6186 case e1000_82542_rev2_0:
6187 case e1000_82542_rev2_1:
6189 /* Set SW Defineable Pin 0 to turn on the LED */
6190 ctrl |= E1000_CTRL_SWDPIN0;
6191 ctrl |= E1000_CTRL_SWDPIO0;
6194 if(hw->media_type == e1000_media_type_fiber) {
6195 /* Set SW Defineable Pin 0 to turn on the LED */
6196 ctrl |= E1000_CTRL_SWDPIN0;
6197 ctrl |= E1000_CTRL_SWDPIO0;
6199 /* Clear SW Defineable Pin 0 to turn on the LED */
6200 ctrl &= ~E1000_CTRL_SWDPIN0;
6201 ctrl |= E1000_CTRL_SWDPIO0;
6205 if(hw->media_type == e1000_media_type_fiber) {
6206 /* Clear SW Defineable Pin 0 to turn on the LED */
6207 ctrl &= ~E1000_CTRL_SWDPIN0;
6208 ctrl |= E1000_CTRL_SWDPIO0;
6209 } else if (hw->phy_type == e1000_phy_ife) {
6210 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6211 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6212 } else if (hw->media_type == e1000_media_type_copper) {
6213 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6214 return E1000_SUCCESS;
6219 E1000_WRITE_REG(hw, CTRL, ctrl);
6221 return E1000_SUCCESS;
6224 /******************************************************************************
6225 * Turns off the software controllable LED
6227 * hw - Struct containing variables accessed by shared code
6228 *****************************************************************************/
6230 e1000_led_off(struct e1000_hw *hw)
6232 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6234 DEBUGFUNC("e1000_led_off");
6236 switch(hw->mac_type) {
6237 case e1000_82542_rev2_0:
6238 case e1000_82542_rev2_1:
6240 /* Clear SW Defineable Pin 0 to turn off the LED */
6241 ctrl &= ~E1000_CTRL_SWDPIN0;
6242 ctrl |= E1000_CTRL_SWDPIO0;
6245 if(hw->media_type == e1000_media_type_fiber) {
6246 /* Clear SW Defineable Pin 0 to turn off the LED */
6247 ctrl &= ~E1000_CTRL_SWDPIN0;
6248 ctrl |= E1000_CTRL_SWDPIO0;
6250 /* Set SW Defineable Pin 0 to turn off the LED */
6251 ctrl |= E1000_CTRL_SWDPIN0;
6252 ctrl |= E1000_CTRL_SWDPIO0;
6256 if(hw->media_type == e1000_media_type_fiber) {
6257 /* Set SW Defineable Pin 0 to turn off the LED */
6258 ctrl |= E1000_CTRL_SWDPIN0;
6259 ctrl |= E1000_CTRL_SWDPIO0;
6260 } else if (hw->phy_type == e1000_phy_ife) {
6261 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6262 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6263 } else if (hw->media_type == e1000_media_type_copper) {
6264 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6265 return E1000_SUCCESS;
6270 E1000_WRITE_REG(hw, CTRL, ctrl);
6272 return E1000_SUCCESS;
6275 /******************************************************************************
6276 * Clears all hardware statistics counters.
6278 * hw - Struct containing variables accessed by shared code
6279 *****************************************************************************/
6281 e1000_clear_hw_cntrs(struct e1000_hw *hw)
6283 volatile uint32_t temp;
6285 temp = E1000_READ_REG(hw, CRCERRS);
6286 temp = E1000_READ_REG(hw, SYMERRS);
6287 temp = E1000_READ_REG(hw, MPC);
6288 temp = E1000_READ_REG(hw, SCC);
6289 temp = E1000_READ_REG(hw, ECOL);
6290 temp = E1000_READ_REG(hw, MCC);
6291 temp = E1000_READ_REG(hw, LATECOL);
6292 temp = E1000_READ_REG(hw, COLC);
6293 temp = E1000_READ_REG(hw, DC);
6294 temp = E1000_READ_REG(hw, SEC);
6295 temp = E1000_READ_REG(hw, RLEC);
6296 temp = E1000_READ_REG(hw, XONRXC);
6297 temp = E1000_READ_REG(hw, XONTXC);
6298 temp = E1000_READ_REG(hw, XOFFRXC);
6299 temp = E1000_READ_REG(hw, XOFFTXC);
6300 temp = E1000_READ_REG(hw, FCRUC);
6302 if (hw->mac_type != e1000_ich8lan) {
6303 temp = E1000_READ_REG(hw, PRC64);
6304 temp = E1000_READ_REG(hw, PRC127);
6305 temp = E1000_READ_REG(hw, PRC255);
6306 temp = E1000_READ_REG(hw, PRC511);
6307 temp = E1000_READ_REG(hw, PRC1023);
6308 temp = E1000_READ_REG(hw, PRC1522);
6311 temp = E1000_READ_REG(hw, GPRC);
6312 temp = E1000_READ_REG(hw, BPRC);
6313 temp = E1000_READ_REG(hw, MPRC);
6314 temp = E1000_READ_REG(hw, GPTC);
6315 temp = E1000_READ_REG(hw, GORCL);
6316 temp = E1000_READ_REG(hw, GORCH);
6317 temp = E1000_READ_REG(hw, GOTCL);
6318 temp = E1000_READ_REG(hw, GOTCH);
6319 temp = E1000_READ_REG(hw, RNBC);
6320 temp = E1000_READ_REG(hw, RUC);
6321 temp = E1000_READ_REG(hw, RFC);
6322 temp = E1000_READ_REG(hw, ROC);
6323 temp = E1000_READ_REG(hw, RJC);
6324 temp = E1000_READ_REG(hw, TORL);
6325 temp = E1000_READ_REG(hw, TORH);
6326 temp = E1000_READ_REG(hw, TOTL);
6327 temp = E1000_READ_REG(hw, TOTH);
6328 temp = E1000_READ_REG(hw, TPR);
6329 temp = E1000_READ_REG(hw, TPT);
6331 if (hw->mac_type != e1000_ich8lan) {
6332 temp = E1000_READ_REG(hw, PTC64);
6333 temp = E1000_READ_REG(hw, PTC127);
6334 temp = E1000_READ_REG(hw, PTC255);
6335 temp = E1000_READ_REG(hw, PTC511);
6336 temp = E1000_READ_REG(hw, PTC1023);
6337 temp = E1000_READ_REG(hw, PTC1522);
6340 temp = E1000_READ_REG(hw, MPTC);
6341 temp = E1000_READ_REG(hw, BPTC);
6343 if(hw->mac_type < e1000_82543) return;
6345 temp = E1000_READ_REG(hw, ALGNERRC);
6346 temp = E1000_READ_REG(hw, RXERRC);
6347 temp = E1000_READ_REG(hw, TNCRS);
6348 temp = E1000_READ_REG(hw, CEXTERR);
6349 temp = E1000_READ_REG(hw, TSCTC);
6350 temp = E1000_READ_REG(hw, TSCTFC);
6352 if(hw->mac_type <= e1000_82544) return;
6354 temp = E1000_READ_REG(hw, MGTPRC);
6355 temp = E1000_READ_REG(hw, MGTPDC);
6356 temp = E1000_READ_REG(hw, MGTPTC);
6358 if(hw->mac_type <= e1000_82547_rev_2) return;
6360 temp = E1000_READ_REG(hw, IAC);
6361 temp = E1000_READ_REG(hw, ICRXOC);
6363 if (hw->mac_type == e1000_ich8lan) return;
6365 temp = E1000_READ_REG(hw, ICRXPTC);
6366 temp = E1000_READ_REG(hw, ICRXATC);
6367 temp = E1000_READ_REG(hw, ICTXPTC);
6368 temp = E1000_READ_REG(hw, ICTXATC);
6369 temp = E1000_READ_REG(hw, ICTXQEC);
6370 temp = E1000_READ_REG(hw, ICTXQMTC);
6371 temp = E1000_READ_REG(hw, ICRXDMTC);
6374 /******************************************************************************
6375 * Resets Adaptive IFS to its default state.
6377 * hw - Struct containing variables accessed by shared code
6379 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6380 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6381 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6382 * before calling this function.
6383 *****************************************************************************/
6385 e1000_reset_adaptive(struct e1000_hw *hw)
6387 DEBUGFUNC("e1000_reset_adaptive");
6389 if(hw->adaptive_ifs) {
6390 if(!hw->ifs_params_forced) {
6391 hw->current_ifs_val = 0;
6392 hw->ifs_min_val = IFS_MIN;
6393 hw->ifs_max_val = IFS_MAX;
6394 hw->ifs_step_size = IFS_STEP;
6395 hw->ifs_ratio = IFS_RATIO;
6397 hw->in_ifs_mode = FALSE;
6398 E1000_WRITE_REG(hw, AIT, 0);
6400 DEBUGOUT("Not in Adaptive IFS mode!\n");
6404 /******************************************************************************
6405 * Called during the callback/watchdog routine to update IFS value based on
6406 * the ratio of transmits to collisions.
6408 * hw - Struct containing variables accessed by shared code
6409 * tx_packets - Number of transmits since last callback
6410 * total_collisions - Number of collisions since last callback
6411 *****************************************************************************/
6413 e1000_update_adaptive(struct e1000_hw *hw)
6415 DEBUGFUNC("e1000_update_adaptive");
6417 if(hw->adaptive_ifs) {
6418 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6419 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
6420 hw->in_ifs_mode = TRUE;
6421 if(hw->current_ifs_val < hw->ifs_max_val) {
6422 if(hw->current_ifs_val == 0)
6423 hw->current_ifs_val = hw->ifs_min_val;
6425 hw->current_ifs_val += hw->ifs_step_size;
6426 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6430 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6431 hw->current_ifs_val = 0;
6432 hw->in_ifs_mode = FALSE;
6433 E1000_WRITE_REG(hw, AIT, 0);
6437 DEBUGOUT("Not in Adaptive IFS mode!\n");
6441 /******************************************************************************
6442 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6444 * hw - Struct containing variables accessed by shared code
6445 * frame_len - The length of the frame in question
6446 * mac_addr - The Ethernet destination address of the frame in question
6447 *****************************************************************************/
6449 e1000_tbi_adjust_stats(struct e1000_hw *hw,
6450 struct e1000_hw_stats *stats,
6456 /* First adjust the frame length. */
6458 /* We need to adjust the statistics counters, since the hardware
6459 * counters overcount this packet as a CRC error and undercount
6460 * the packet as a good packet
6462 /* This packet should not be counted as a CRC error. */
6464 /* This packet does count as a Good Packet Received. */
6467 /* Adjust the Good Octets received counters */
6468 carry_bit = 0x80000000 & stats->gorcl;
6469 stats->gorcl += frame_len;
6470 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6471 * Received Count) was one before the addition,
6472 * AND it is zero after, then we lost the carry out,
6473 * need to add one to Gorch (Good Octets Received Count High).
6474 * This could be simplified if all environments supported
6477 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
6479 /* Is this a broadcast or multicast? Check broadcast first,
6480 * since the test for a multicast frame will test positive on
6481 * a broadcast frame.
6483 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6484 /* Broadcast packet */
6486 else if(*mac_addr & 0x01)
6487 /* Multicast packet */
6490 if(frame_len == hw->max_frame_size) {
6491 /* In this case, the hardware has overcounted the number of
6498 /* Adjust the bin counters when the extra byte put the frame in the
6499 * wrong bin. Remember that the frame_len was adjusted above.
6501 if(frame_len == 64) {
6504 } else if(frame_len == 127) {
6507 } else if(frame_len == 255) {
6510 } else if(frame_len == 511) {
6513 } else if(frame_len == 1023) {
6516 } else if(frame_len == 1522) {
6521 /******************************************************************************
6522 * Gets the current PCI bus type, speed, and width of the hardware
6524 * hw - Struct containing variables accessed by shared code
6525 *****************************************************************************/
6527 e1000_get_bus_info(struct e1000_hw *hw)
6531 switch (hw->mac_type) {
6532 case e1000_82542_rev2_0:
6533 case e1000_82542_rev2_1:
6534 hw->bus_type = e1000_bus_type_unknown;
6535 hw->bus_speed = e1000_bus_speed_unknown;
6536 hw->bus_width = e1000_bus_width_unknown;
6540 hw->bus_type = e1000_bus_type_pci_express;
6541 hw->bus_speed = e1000_bus_speed_2500;
6542 hw->bus_width = e1000_bus_width_pciex_1;
6546 case e1000_80003es2lan:
6547 hw->bus_type = e1000_bus_type_pci_express;
6548 hw->bus_speed = e1000_bus_speed_2500;
6549 hw->bus_width = e1000_bus_width_pciex_4;
6552 status = E1000_READ_REG(hw, STATUS);
6553 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6554 e1000_bus_type_pcix : e1000_bus_type_pci;
6556 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6557 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6558 e1000_bus_speed_66 : e1000_bus_speed_120;
6559 } else if(hw->bus_type == e1000_bus_type_pci) {
6560 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6561 e1000_bus_speed_66 : e1000_bus_speed_33;
6563 switch (status & E1000_STATUS_PCIX_SPEED) {
6564 case E1000_STATUS_PCIX_SPEED_66:
6565 hw->bus_speed = e1000_bus_speed_66;
6567 case E1000_STATUS_PCIX_SPEED_100:
6568 hw->bus_speed = e1000_bus_speed_100;
6570 case E1000_STATUS_PCIX_SPEED_133:
6571 hw->bus_speed = e1000_bus_speed_133;
6574 hw->bus_speed = e1000_bus_speed_reserved;
6578 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6579 e1000_bus_width_64 : e1000_bus_width_32;
6583 /******************************************************************************
6584 * Reads a value from one of the devices registers using port I/O (as opposed
6585 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6587 * hw - Struct containing variables accessed by shared code
6588 * offset - offset to read from
6589 *****************************************************************************/
6591 e1000_read_reg_io(struct e1000_hw *hw,
6594 unsigned long io_addr = hw->io_base;
6595 unsigned long io_data = hw->io_base + 4;
6597 e1000_io_write(hw, io_addr, offset);
6598 return e1000_io_read(hw, io_data);
6601 /******************************************************************************
6602 * Writes a value to one of the devices registers using port I/O (as opposed to
6603 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6605 * hw - Struct containing variables accessed by shared code
6606 * offset - offset to write to
6607 * value - value to write
6608 *****************************************************************************/
6610 e1000_write_reg_io(struct e1000_hw *hw,
6614 unsigned long io_addr = hw->io_base;
6615 unsigned long io_data = hw->io_base + 4;
6617 e1000_io_write(hw, io_addr, offset);
6618 e1000_io_write(hw, io_data, value);
6622 /******************************************************************************
6623 * Estimates the cable length.
6625 * hw - Struct containing variables accessed by shared code
6626 * min_length - The estimated minimum length
6627 * max_length - The estimated maximum length
6629 * returns: - E1000_ERR_XXX
6632 * This function always returns a ranged length (minimum & maximum).
6633 * So for M88 phy's, this function interprets the one value returned from the
6634 * register to the minimum and maximum range.
6635 * For IGP phy's, the function calculates the range by the AGC registers.
6636 *****************************************************************************/
6638 e1000_get_cable_length(struct e1000_hw *hw,
6639 uint16_t *min_length,
6640 uint16_t *max_length)
6643 uint16_t agc_value = 0;
6644 uint16_t i, phy_data;
6645 uint16_t cable_length;
6647 DEBUGFUNC("e1000_get_cable_length");
6649 *min_length = *max_length = 0;
6651 /* Use old method for Phy older than IGP */
6652 if(hw->phy_type == e1000_phy_m88) {
6654 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6658 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6659 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6661 /* Convert the enum value to ranged values */
6662 switch (cable_length) {
6663 case e1000_cable_length_50:
6665 *max_length = e1000_igp_cable_length_50;
6667 case e1000_cable_length_50_80:
6668 *min_length = e1000_igp_cable_length_50;
6669 *max_length = e1000_igp_cable_length_80;
6671 case e1000_cable_length_80_110:
6672 *min_length = e1000_igp_cable_length_80;
6673 *max_length = e1000_igp_cable_length_110;
6675 case e1000_cable_length_110_140:
6676 *min_length = e1000_igp_cable_length_110;
6677 *max_length = e1000_igp_cable_length_140;
6679 case e1000_cable_length_140:
6680 *min_length = e1000_igp_cable_length_140;
6681 *max_length = e1000_igp_cable_length_170;
6684 return -E1000_ERR_PHY;
6687 } else if (hw->phy_type == e1000_phy_gg82563) {
6688 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6692 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6694 switch (cable_length) {
6695 case e1000_gg_cable_length_60:
6697 *max_length = e1000_igp_cable_length_60;
6699 case e1000_gg_cable_length_60_115:
6700 *min_length = e1000_igp_cable_length_60;
6701 *max_length = e1000_igp_cable_length_115;
6703 case e1000_gg_cable_length_115_150:
6704 *min_length = e1000_igp_cable_length_115;
6705 *max_length = e1000_igp_cable_length_150;
6707 case e1000_gg_cable_length_150:
6708 *min_length = e1000_igp_cable_length_150;
6709 *max_length = e1000_igp_cable_length_180;
6712 return -E1000_ERR_PHY;
6715 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6716 uint16_t cur_agc_value;
6717 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6718 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6719 {IGP01E1000_PHY_AGC_A,
6720 IGP01E1000_PHY_AGC_B,
6721 IGP01E1000_PHY_AGC_C,
6722 IGP01E1000_PHY_AGC_D};
6723 /* Read the AGC registers for all channels */
6724 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6726 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6730 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6732 /* Value bound check. */
6733 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6734 (cur_agc_value == 0))
6735 return -E1000_ERR_PHY;
6737 agc_value += cur_agc_value;
6739 /* Update minimal AGC value. */
6740 if (min_agc_value > cur_agc_value)
6741 min_agc_value = cur_agc_value;
6744 /* Remove the minimal AGC result for length < 50m */
6745 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6746 agc_value -= min_agc_value;
6748 /* Get the average length of the remaining 3 channels */
6749 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6751 /* Get the average length of all the 4 channels. */
6752 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6755 /* Set the range of the calculated length. */
6756 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6757 IGP01E1000_AGC_RANGE) > 0) ?
6758 (e1000_igp_cable_length_table[agc_value] -
6759 IGP01E1000_AGC_RANGE) : 0;
6760 *max_length = e1000_igp_cable_length_table[agc_value] +
6761 IGP01E1000_AGC_RANGE;
6762 } else if (hw->phy_type == e1000_phy_igp_2 ||
6763 hw->phy_type == e1000_phy_igp_3) {
6764 uint16_t cur_agc_index, max_agc_index = 0;
6765 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6766 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6767 {IGP02E1000_PHY_AGC_A,
6768 IGP02E1000_PHY_AGC_B,
6769 IGP02E1000_PHY_AGC_C,
6770 IGP02E1000_PHY_AGC_D};
6771 /* Read the AGC registers for all channels */
6772 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6773 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6777 /* Getting bits 15:9, which represent the combination of course and
6778 * fine gain values. The result is a number that can be put into
6779 * the lookup table to obtain the approximate cable length. */
6780 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6781 IGP02E1000_AGC_LENGTH_MASK;
6783 /* Array index bound check. */
6784 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6785 (cur_agc_index == 0))
6786 return -E1000_ERR_PHY;
6788 /* Remove min & max AGC values from calculation. */
6789 if (e1000_igp_2_cable_length_table[min_agc_index] >
6790 e1000_igp_2_cable_length_table[cur_agc_index])
6791 min_agc_index = cur_agc_index;
6792 if (e1000_igp_2_cable_length_table[max_agc_index] <
6793 e1000_igp_2_cable_length_table[cur_agc_index])
6794 max_agc_index = cur_agc_index;
6796 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6799 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6800 e1000_igp_2_cable_length_table[max_agc_index]);
6801 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6803 /* Calculate cable length with the error range of +/- 10 meters. */
6804 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6805 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6806 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6809 return E1000_SUCCESS;
6812 /******************************************************************************
6813 * Check the cable polarity
6815 * hw - Struct containing variables accessed by shared code
6816 * polarity - output parameter : 0 - Polarity is not reversed
6817 * 1 - Polarity is reversed.
6819 * returns: - E1000_ERR_XXX
6822 * For phy's older then IGP, this function simply reads the polarity bit in the
6823 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6824 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6825 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6826 * IGP01E1000_PHY_PCS_INIT_REG.
6827 *****************************************************************************/
6829 e1000_check_polarity(struct e1000_hw *hw,
6835 DEBUGFUNC("e1000_check_polarity");
6837 if ((hw->phy_type == e1000_phy_m88) ||
6838 (hw->phy_type == e1000_phy_gg82563)) {
6839 /* return the Polarity bit in the Status register. */
6840 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6844 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6845 M88E1000_PSSR_REV_POLARITY_SHIFT;
6846 } else if (hw->phy_type == e1000_phy_igp ||
6847 hw->phy_type == e1000_phy_igp_3 ||
6848 hw->phy_type == e1000_phy_igp_2) {
6849 /* Read the Status register to check the speed */
6850 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6855 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6856 * find the polarity status */
6857 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6858 IGP01E1000_PSSR_SPEED_1000MBPS) {
6860 /* Read the GIG initialization PCS register (0x00B4) */
6861 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6866 /* Check the polarity bits */
6867 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
6869 /* For 10 Mbps, read the polarity bit in the status register. (for
6870 * 100 Mbps this bit is always 0) */
6871 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6873 } else if (hw->phy_type == e1000_phy_ife) {
6874 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6878 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >>
6879 IFE_PESC_POLARITY_REVERSED_SHIFT;
6881 return E1000_SUCCESS;
6884 /******************************************************************************
6885 * Check if Downshift occured
6887 * hw - Struct containing variables accessed by shared code
6888 * downshift - output parameter : 0 - No Downshift ocured.
6889 * 1 - Downshift ocured.
6891 * returns: - E1000_ERR_XXX
6894 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6895 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6896 * Link Health register. In IGP this bit is latched high, so the driver must
6897 * read it immediately after link is established.
6898 *****************************************************************************/
6900 e1000_check_downshift(struct e1000_hw *hw)
6905 DEBUGFUNC("e1000_check_downshift");
6907 if (hw->phy_type == e1000_phy_igp ||
6908 hw->phy_type == e1000_phy_igp_3 ||
6909 hw->phy_type == e1000_phy_igp_2) {
6910 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6915 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6916 } else if ((hw->phy_type == e1000_phy_m88) ||
6917 (hw->phy_type == e1000_phy_gg82563)) {
6918 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6923 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6924 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6925 } else if (hw->phy_type == e1000_phy_ife) {
6926 /* e1000_phy_ife supports 10/100 speed only */
6927 hw->speed_downgraded = FALSE;
6930 return E1000_SUCCESS;
6933 /*****************************************************************************
6935 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6936 * gigabit link is achieved to improve link quality.
6938 * hw: Struct containing variables accessed by shared code
6940 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6941 * E1000_SUCCESS at any other case.
6943 ****************************************************************************/
6946 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6950 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6951 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6952 {IGP01E1000_PHY_AGC_PARAM_A,
6953 IGP01E1000_PHY_AGC_PARAM_B,
6954 IGP01E1000_PHY_AGC_PARAM_C,
6955 IGP01E1000_PHY_AGC_PARAM_D};
6956 uint16_t min_length, max_length;
6958 DEBUGFUNC("e1000_config_dsp_after_link_change");
6960 if(hw->phy_type != e1000_phy_igp)
6961 return E1000_SUCCESS;
6964 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6966 DEBUGOUT("Error getting link speed and duplex\n");
6970 if(speed == SPEED_1000) {
6972 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6976 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6977 min_length >= e1000_igp_cable_length_50) {
6979 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6980 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6985 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6987 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
6992 hw->dsp_config_state = e1000_dsp_config_activated;
6995 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
6996 (min_length < e1000_igp_cable_length_50)) {
6998 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
6999 uint32_t idle_errs = 0;
7001 /* clear previous idle error counts */
7002 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7007 for(i = 0; i < ffe_idle_err_timeout; i++) {
7009 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7014 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7015 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7016 hw->ffe_config_state = e1000_ffe_config_active;
7018 ret_val = e1000_write_phy_reg(hw,
7019 IGP01E1000_PHY_DSP_FFE,
7020 IGP01E1000_PHY_DSP_FFE_CM_CP);
7027 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7032 if(hw->dsp_config_state == e1000_dsp_config_activated) {
7033 /* Save off the current value of register 0x2F5B to be restored at
7034 * the end of the routines. */
7035 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7040 /* Disable the PHY transmitter */
7041 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7048 ret_val = e1000_write_phy_reg(hw, 0x0000,
7049 IGP01E1000_IEEE_FORCE_GIGA);
7052 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7053 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7057 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7058 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7060 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7065 ret_val = e1000_write_phy_reg(hw, 0x0000,
7066 IGP01E1000_IEEE_RESTART_AUTONEG);
7072 /* Now enable the transmitter */
7073 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7078 hw->dsp_config_state = e1000_dsp_config_enabled;
7081 if(hw->ffe_config_state == e1000_ffe_config_active) {
7082 /* Save off the current value of register 0x2F5B to be restored at
7083 * the end of the routines. */
7084 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7089 /* Disable the PHY transmitter */
7090 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7097 ret_val = e1000_write_phy_reg(hw, 0x0000,
7098 IGP01E1000_IEEE_FORCE_GIGA);
7101 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7102 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7106 ret_val = e1000_write_phy_reg(hw, 0x0000,
7107 IGP01E1000_IEEE_RESTART_AUTONEG);
7113 /* Now enable the transmitter */
7114 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7119 hw->ffe_config_state = e1000_ffe_config_enabled;
7122 return E1000_SUCCESS;
7125 /*****************************************************************************
7126 * Set PHY to class A mode
7127 * Assumes the following operations will follow to enable the new class mode.
7128 * 1. Do a PHY soft reset
7129 * 2. Restart auto-negotiation or force link.
7131 * hw - Struct containing variables accessed by shared code
7132 ****************************************************************************/
7134 e1000_set_phy_mode(struct e1000_hw *hw)
7137 uint16_t eeprom_data;
7139 DEBUGFUNC("e1000_set_phy_mode");
7141 if((hw->mac_type == e1000_82545_rev_3) &&
7142 (hw->media_type == e1000_media_type_copper)) {
7143 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7148 if((eeprom_data != EEPROM_RESERVED_WORD) &&
7149 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7150 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7153 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7157 hw->phy_reset_disable = FALSE;
7161 return E1000_SUCCESS;
7164 /*****************************************************************************
7166 * This function sets the lplu state according to the active flag. When
7167 * activating lplu this function also disables smart speed and vise versa.
7168 * lplu will not be activated unless the device autonegotiation advertisment
7169 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7170 * hw: Struct containing variables accessed by shared code
7171 * active - true to enable lplu false to disable lplu.
7173 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7174 * E1000_SUCCESS at any other case.
7176 ****************************************************************************/
7179 e1000_set_d3_lplu_state(struct e1000_hw *hw,
7182 uint32_t phy_ctrl = 0;
7185 DEBUGFUNC("e1000_set_d3_lplu_state");
7187 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7188 && hw->phy_type != e1000_phy_igp_3)
7189 return E1000_SUCCESS;
7191 /* During driver activity LPLU should not be used or it will attain link
7192 * from the lowest speeds starting from 10Mbps. The capability is used for
7193 * Dx transitions and states */
7194 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7195 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7198 } else if (hw->mac_type == e1000_ich8lan) {
7199 /* MAC writes into PHY register based on the state transition
7200 * and start auto-negotiation. SW driver can overwrite the settings
7201 * in CSR PHY power control E1000_PHY_CTRL register. */
7202 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7204 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7210 if(hw->mac_type == e1000_82541_rev_2 ||
7211 hw->mac_type == e1000_82547_rev_2) {
7212 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7213 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7217 if (hw->mac_type == e1000_ich8lan) {
7218 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7219 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7221 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7222 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7229 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7230 * Dx states where the power conservation is most important. During
7231 * driver activity we should enable SmartSpeed, so performance is
7233 if (hw->smart_speed == e1000_smart_speed_on) {
7234 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7239 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7240 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7244 } else if (hw->smart_speed == e1000_smart_speed_off) {
7245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7250 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7251 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7257 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7258 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7259 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7261 if(hw->mac_type == e1000_82541_rev_2 ||
7262 hw->mac_type == e1000_82547_rev_2) {
7263 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7264 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7268 if (hw->mac_type == e1000_ich8lan) {
7269 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7270 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7272 phy_data |= IGP02E1000_PM_D3_LPLU;
7273 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7280 /* When LPLU is enabled we should disable SmartSpeed */
7281 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7285 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7286 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7291 return E1000_SUCCESS;
7294 /*****************************************************************************
7296 * This function sets the lplu d0 state according to the active flag. When
7297 * activating lplu this function also disables smart speed and vise versa.
7298 * lplu will not be activated unless the device autonegotiation advertisment
7299 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7300 * hw: Struct containing variables accessed by shared code
7301 * active - true to enable lplu false to disable lplu.
7303 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7304 * E1000_SUCCESS at any other case.
7306 ****************************************************************************/
7309 e1000_set_d0_lplu_state(struct e1000_hw *hw,
7312 uint32_t phy_ctrl = 0;
7315 DEBUGFUNC("e1000_set_d0_lplu_state");
7317 if(hw->mac_type <= e1000_82547_rev_2)
7318 return E1000_SUCCESS;
7320 if (hw->mac_type == e1000_ich8lan) {
7321 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7323 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7329 if (hw->mac_type == e1000_ich8lan) {
7330 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7331 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7333 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7334 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7339 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7340 * Dx states where the power conservation is most important. During
7341 * driver activity we should enable SmartSpeed, so performance is
7343 if (hw->smart_speed == e1000_smart_speed_on) {
7344 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7349 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7350 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7354 } else if (hw->smart_speed == e1000_smart_speed_off) {
7355 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7360 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7361 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7370 if (hw->mac_type == e1000_ich8lan) {
7371 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7372 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7374 phy_data |= IGP02E1000_PM_D0_LPLU;
7375 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7380 /* When LPLU is enabled we should disable SmartSpeed */
7381 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7385 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7386 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7391 return E1000_SUCCESS;
7394 /******************************************************************************
7395 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7397 * hw - Struct containing variables accessed by shared code
7398 *****************************************************************************/
7400 e1000_set_vco_speed(struct e1000_hw *hw)
7403 uint16_t default_page = 0;
7406 DEBUGFUNC("e1000_set_vco_speed");
7408 switch(hw->mac_type) {
7409 case e1000_82545_rev_3:
7410 case e1000_82546_rev_3:
7413 return E1000_SUCCESS;
7416 /* Set PHY register 30, page 5, bit 8 to 0 */
7418 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7422 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7426 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7430 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7431 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7435 /* Set PHY register 30, page 4, bit 11 to 1 */
7437 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7441 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7445 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7446 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7450 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7454 return E1000_SUCCESS;
7458 /*****************************************************************************
7459 * This function reads the cookie from ARC ram.
7461 * returns: - E1000_SUCCESS .
7462 ****************************************************************************/
7464 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7467 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7468 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7470 length = (length >> 2);
7471 offset = (offset >> 2);
7473 for (i = 0; i < length; i++) {
7474 *((uint32_t *) buffer + i) =
7475 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7477 return E1000_SUCCESS;
7481 /*****************************************************************************
7482 * This function checks whether the HOST IF is enabled for command operaton
7483 * and also checks whether the previous command is completed.
7484 * It busy waits in case of previous command is not completed.
7486 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7488 * - E1000_SUCCESS for success.
7489 ****************************************************************************/
7491 e1000_mng_enable_host_if(struct e1000_hw * hw)
7496 /* Check that the host interface is enabled. */
7497 hicr = E1000_READ_REG(hw, HICR);
7498 if ((hicr & E1000_HICR_EN) == 0) {
7499 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7500 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7502 /* check the previous command is completed */
7503 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7504 hicr = E1000_READ_REG(hw, HICR);
7505 if (!(hicr & E1000_HICR_C))
7510 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7511 DEBUGOUT("Previous command timeout failed .\n");
7512 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7514 return E1000_SUCCESS;
7517 /*****************************************************************************
7518 * This function writes the buffer content at the offset given on the host if.
7519 * It also does alignment considerations to do the writes in most efficient way.
7520 * Also fills up the sum of the buffer in *buffer parameter.
7522 * returns - E1000_SUCCESS for success.
7523 ****************************************************************************/
7525 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7526 uint16_t length, uint16_t offset, uint8_t *sum)
7529 uint8_t *bufptr = buffer;
7531 uint16_t remaining, i, j, prev_bytes;
7533 /* sum = only sum of the data and it is not checksum */
7535 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7536 return -E1000_ERR_PARAM;
7539 tmp = (uint8_t *)&data;
7540 prev_bytes = offset & 0x3;
7545 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7546 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7547 *(tmp + j) = *bufptr++;
7550 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7551 length -= j - prev_bytes;
7555 remaining = length & 0x3;
7556 length -= remaining;
7558 /* Calculate length in DWORDs */
7561 /* The device driver writes the relevant command block into the
7563 for (i = 0; i < length; i++) {
7564 for (j = 0; j < sizeof(uint32_t); j++) {
7565 *(tmp + j) = *bufptr++;
7569 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7572 for (j = 0; j < sizeof(uint32_t); j++) {
7574 *(tmp + j) = *bufptr++;
7580 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7583 return E1000_SUCCESS;
7587 /*****************************************************************************
7588 * This function writes the command header after does the checksum calculation.
7590 * returns - E1000_SUCCESS for success.
7591 ****************************************************************************/
7593 e1000_mng_write_cmd_header(struct e1000_hw * hw,
7594 struct e1000_host_mng_command_header * hdr)
7600 /* Write the whole command header structure which includes sum of
7603 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7605 sum = hdr->checksum;
7608 buffer = (uint8_t *) hdr;
7613 hdr->checksum = 0 - sum;
7616 /* The device driver writes the relevant command block into the ram area. */
7617 for (i = 0; i < length; i++) {
7618 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7619 E1000_WRITE_FLUSH(hw);
7622 return E1000_SUCCESS;
7626 /*****************************************************************************
7627 * This function indicates to ARC that a new command is pending which completes
7628 * one write operation by the driver.
7630 * returns - E1000_SUCCESS for success.
7631 ****************************************************************************/
7633 e1000_mng_write_commit(
7634 struct e1000_hw * hw)
7638 hicr = E1000_READ_REG(hw, HICR);
7639 /* Setting this bit tells the ARC that a new command is pending. */
7640 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7642 return E1000_SUCCESS;
7646 /*****************************************************************************
7647 * This function checks the mode of the firmware.
7649 * returns - TRUE when the mode is IAMT or FALSE.
7650 ****************************************************************************/
7652 e1000_check_mng_mode(struct e1000_hw *hw)
7656 fwsm = E1000_READ_REG(hw, FWSM);
7658 if (hw->mac_type == e1000_ich8lan) {
7659 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7660 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7662 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7663 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7670 /*****************************************************************************
7671 * This function writes the dhcp info .
7672 ****************************************************************************/
7674 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7678 struct e1000_host_mng_command_header hdr;
7680 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7681 hdr.command_length = length;
7686 ret_val = e1000_mng_enable_host_if(hw);
7687 if (ret_val == E1000_SUCCESS) {
7688 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7690 if (ret_val == E1000_SUCCESS) {
7691 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7692 if (ret_val == E1000_SUCCESS)
7693 ret_val = e1000_mng_write_commit(hw);
7700 /*****************************************************************************
7701 * This function calculates the checksum.
7703 * returns - checksum of buffer contents.
7704 ****************************************************************************/
7706 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7714 for (i=0; i < length; i++)
7717 return (uint8_t) (0 - sum);
7720 /*****************************************************************************
7721 * This function checks whether tx pkt filtering needs to be enabled or not.
7723 * returns - TRUE for packet filtering or FALSE.
7724 ****************************************************************************/
7726 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7728 /* called in init as well as watchdog timer functions */
7730 int32_t ret_val, checksum;
7731 boolean_t tx_filter = FALSE;
7732 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7733 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7735 if (e1000_check_mng_mode(hw)) {
7736 ret_val = e1000_mng_enable_host_if(hw);
7737 if (ret_val == E1000_SUCCESS) {
7738 ret_val = e1000_host_if_read_cookie(hw, buffer);
7739 if (ret_val == E1000_SUCCESS) {
7740 checksum = hdr->checksum;
7742 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7743 checksum == e1000_calculate_mng_checksum((char *)buffer,
7744 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7746 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7755 hw->tx_pkt_filtering = tx_filter;
7759 /******************************************************************************
7760 * Verifies the hardware needs to allow ARPs to be processed by the host
7762 * hw - Struct containing variables accessed by shared code
7764 * returns: - TRUE/FALSE
7766 *****************************************************************************/
7768 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7771 uint32_t fwsm, factps;
7773 if (hw->asf_firmware_present) {
7774 manc = E1000_READ_REG(hw, MANC);
7776 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7777 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7779 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7780 fwsm = E1000_READ_REG(hw, FWSM);
7781 factps = E1000_READ_REG(hw, FACTPS);
7783 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7784 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7785 (factps & E1000_FACTPS_MNGCG))
7788 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7795 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7798 uint16_t mii_status_reg;
7801 /* Polarity reversal workaround for forced 10F/10H links. */
7803 /* Disable the transmitter on the PHY */
7805 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7808 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7812 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7816 /* This loop will early-out if the NO link condition has been met. */
7817 for(i = PHY_FORCE_TIME; i > 0; i--) {
7818 /* Read the MII Status Register and wait for Link Status bit
7822 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7826 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7830 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7831 msec_delay_irq(100);
7834 /* Recommended delay time after link has been lost */
7835 msec_delay_irq(1000);
7837 /* Now we will re-enable th transmitter on the PHY */
7839 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7843 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7847 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7851 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7855 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7859 /* This loop will early-out if the link condition has been met. */
7860 for(i = PHY_FORCE_TIME; i > 0; i--) {
7861 /* Read the MII Status Register and wait for Link Status bit
7865 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7869 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7873 if(mii_status_reg & MII_SR_LINK_STATUS) break;
7874 msec_delay_irq(100);
7876 return E1000_SUCCESS;
7879 /***************************************************************************
7881 * Disables PCI-Express master access.
7883 * hw: Struct containing variables accessed by shared code
7887 ***************************************************************************/
7889 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7893 DEBUGFUNC("e1000_set_pci_express_master_disable");
7895 if (hw->bus_type != e1000_bus_type_pci_express)
7898 ctrl = E1000_READ_REG(hw, CTRL);
7899 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7900 E1000_WRITE_REG(hw, CTRL, ctrl);
7903 /***************************************************************************
7905 * Enables PCI-Express master access.
7907 * hw: Struct containing variables accessed by shared code
7911 ***************************************************************************/
7913 e1000_enable_pciex_master(struct e1000_hw *hw)
7917 DEBUGFUNC("e1000_enable_pciex_master");
7919 if (hw->bus_type != e1000_bus_type_pci_express)
7922 ctrl = E1000_READ_REG(hw, CTRL);
7923 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7924 E1000_WRITE_REG(hw, CTRL, ctrl);
7927 /*******************************************************************************
7929 * Disables PCI-Express master access and verifies there are no pending requests
7931 * hw: Struct containing variables accessed by shared code
7933 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7934 * caused the master requests to be disabled.
7935 * E1000_SUCCESS master requests disabled.
7937 ******************************************************************************/
7939 e1000_disable_pciex_master(struct e1000_hw *hw)
7941 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7943 DEBUGFUNC("e1000_disable_pciex_master");
7945 if (hw->bus_type != e1000_bus_type_pci_express)
7946 return E1000_SUCCESS;
7948 e1000_set_pci_express_master_disable(hw);
7951 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7959 DEBUGOUT("Master requests are pending.\n");
7960 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7963 return E1000_SUCCESS;
7966 /*******************************************************************************
7968 * Check for EEPROM Auto Read bit done.
7970 * hw: Struct containing variables accessed by shared code
7972 * returns: - E1000_ERR_RESET if fail to reset MAC
7973 * E1000_SUCCESS at any other case.
7975 ******************************************************************************/
7977 e1000_get_auto_rd_done(struct e1000_hw *hw)
7979 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7981 DEBUGFUNC("e1000_get_auto_rd_done");
7983 switch (hw->mac_type) {
7990 case e1000_80003es2lan:
7993 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8000 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8001 return -E1000_ERR_RESET;
8006 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8007 * Need to wait for PHY configuration completion before accessing NVM
8009 if (hw->mac_type == e1000_82573)
8012 return E1000_SUCCESS;
8015 /***************************************************************************
8016 * Checks if the PHY configuration is done
8018 * hw: Struct containing variables accessed by shared code
8020 * returns: - E1000_ERR_RESET if fail to reset MAC
8021 * E1000_SUCCESS at any other case.
8023 ***************************************************************************/
8025 e1000_get_phy_cfg_done(struct e1000_hw *hw)
8027 int32_t timeout = PHY_CFG_TIMEOUT;
8028 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8030 DEBUGFUNC("e1000_get_phy_cfg_done");
8032 switch (hw->mac_type) {
8036 case e1000_80003es2lan:
8037 /* Separate *_CFG_DONE_* bit for each port */
8038 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8039 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8044 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8052 DEBUGOUT("MNG configuration cycle has not completed.\n");
8053 return -E1000_ERR_RESET;
8058 return E1000_SUCCESS;
8061 /***************************************************************************
8063 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8064 * adapter or Eeprom access.
8066 * hw: Struct containing variables accessed by shared code
8068 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8069 * E1000_SUCCESS at any other case.
8071 ***************************************************************************/
8073 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8078 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8080 if(!hw->eeprom_semaphore_present)
8081 return E1000_SUCCESS;
8083 if (hw->mac_type == e1000_80003es2lan) {
8084 /* Get the SW semaphore. */
8085 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8086 return -E1000_ERR_EEPROM;
8089 /* Get the FW semaphore. */
8090 timeout = hw->eeprom.word_size + 1;
8092 swsm = E1000_READ_REG(hw, SWSM);
8093 swsm |= E1000_SWSM_SWESMBI;
8094 E1000_WRITE_REG(hw, SWSM, swsm);
8095 /* if we managed to set the bit we got the semaphore. */
8096 swsm = E1000_READ_REG(hw, SWSM);
8097 if(swsm & E1000_SWSM_SWESMBI)
8105 /* Release semaphores */
8106 e1000_put_hw_eeprom_semaphore(hw);
8107 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8108 return -E1000_ERR_EEPROM;
8111 return E1000_SUCCESS;
8114 /***************************************************************************
8115 * This function clears HW semaphore bits.
8117 * hw: Struct containing variables accessed by shared code
8121 ***************************************************************************/
8123 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8127 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8129 if(!hw->eeprom_semaphore_present)
8132 swsm = E1000_READ_REG(hw, SWSM);
8133 if (hw->mac_type == e1000_80003es2lan) {
8134 /* Release both semaphores. */
8135 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8137 swsm &= ~(E1000_SWSM_SWESMBI);
8138 E1000_WRITE_REG(hw, SWSM, swsm);
8141 /***************************************************************************
8143 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8145 * hw: Struct containing variables accessed by shared code
8147 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8148 * E1000_SUCCESS at any other case.
8150 ***************************************************************************/
8152 e1000_get_software_semaphore(struct e1000_hw *hw)
8154 int32_t timeout = hw->eeprom.word_size + 1;
8157 DEBUGFUNC("e1000_get_software_semaphore");
8159 if (hw->mac_type != e1000_80003es2lan)
8160 return E1000_SUCCESS;
8163 swsm = E1000_READ_REG(hw, SWSM);
8164 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8165 if(!(swsm & E1000_SWSM_SMBI))
8172 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8173 return -E1000_ERR_RESET;
8176 return E1000_SUCCESS;
8179 /***************************************************************************
8181 * Release semaphore bit (SMBI).
8183 * hw: Struct containing variables accessed by shared code
8185 ***************************************************************************/
8187 e1000_release_software_semaphore(struct e1000_hw *hw)
8191 DEBUGFUNC("e1000_release_software_semaphore");
8193 if (hw->mac_type != e1000_80003es2lan)
8196 swsm = E1000_READ_REG(hw, SWSM);
8197 /* Release the SW semaphores.*/
8198 swsm &= ~E1000_SWSM_SMBI;
8199 E1000_WRITE_REG(hw, SWSM, swsm);
8202 /******************************************************************************
8203 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8204 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8205 * the caller to figure out how to deal with it.
8207 * hw - Struct containing variables accessed by shared code
8209 * returns: - E1000_BLK_PHY_RESET
8212 *****************************************************************************/
8214 e1000_check_phy_reset_block(struct e1000_hw *hw)
8219 if (hw->mac_type == e1000_ich8lan) {
8220 fwsm = E1000_READ_REG(hw, FWSM);
8221 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8222 : E1000_BLK_PHY_RESET;
8225 if (hw->mac_type > e1000_82547_rev_2)
8226 manc = E1000_READ_REG(hw, MANC);
8227 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8228 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8232 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8236 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8237 * may not be provided a DMA clock when no manageability features are
8238 * enabled. We do not want to perform any reads/writes to these registers
8239 * if this is the case. We read FWSM to determine the manageability mode.
8241 switch (hw->mac_type) {
8245 case e1000_80003es2lan:
8246 fwsm = E1000_READ_REG(hw, FWSM);
8247 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
8259 /******************************************************************************
8260 * Configure PCI-Ex no-snoop
8262 * hw - Struct containing variables accessed by shared code.
8263 * no_snoop - Bitmap of no-snoop events.
8265 * returns: E1000_SUCCESS
8267 *****************************************************************************/
8269 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8271 uint32_t gcr_reg = 0;
8273 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8275 if (hw->bus_type == e1000_bus_type_unknown)
8276 e1000_get_bus_info(hw);
8278 if (hw->bus_type != e1000_bus_type_pci_express)
8279 return E1000_SUCCESS;
8282 gcr_reg = E1000_READ_REG(hw, GCR);
8283 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8284 gcr_reg |= no_snoop;
8285 E1000_WRITE_REG(hw, GCR, gcr_reg);
8287 if (hw->mac_type == e1000_ich8lan) {
8290 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8292 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8293 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8294 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8297 return E1000_SUCCESS;
8300 /***************************************************************************
8302 * Get software semaphore FLAG bit (SWFLAG).
8303 * SWFLAG is used to synchronize the access to all shared resource between
8306 * hw: Struct containing variables accessed by shared code
8308 ***************************************************************************/
8310 e1000_get_software_flag(struct e1000_hw *hw)
8312 int32_t timeout = PHY_CFG_TIMEOUT;
8313 uint32_t extcnf_ctrl;
8315 DEBUGFUNC("e1000_get_software_flag");
8317 if (hw->mac_type == e1000_ich8lan) {
8319 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8320 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8321 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8323 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8324 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8331 DEBUGOUT("FW or HW locks the resource too long.\n");
8332 return -E1000_ERR_CONFIG;
8336 return E1000_SUCCESS;
8339 /***************************************************************************
8341 * Release software semaphore FLAG bit (SWFLAG).
8342 * SWFLAG is used to synchronize the access to all shared resource between
8345 * hw: Struct containing variables accessed by shared code
8347 ***************************************************************************/
8349 e1000_release_software_flag(struct e1000_hw *hw)
8351 uint32_t extcnf_ctrl;
8353 DEBUGFUNC("e1000_release_software_flag");
8355 if (hw->mac_type == e1000_ich8lan) {
8356 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8357 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8358 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8364 /***************************************************************************
8366 * Disable dynamic power down mode in ife PHY.
8367 * It can be used to workaround band-gap problem.
8369 * hw: Struct containing variables accessed by shared code
8371 ***************************************************************************/
8373 e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
8376 int32_t ret_val = E1000_SUCCESS;
8378 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
8380 if (hw->phy_type == e1000_phy_ife) {
8381 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8385 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8386 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8392 /***************************************************************************
8394 * Enable dynamic power down mode in ife PHY.
8395 * It can be used to workaround band-gap problem.
8397 * hw: Struct containing variables accessed by shared code
8399 ***************************************************************************/
8401 e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
8404 int32_t ret_val = E1000_SUCCESS;
8406 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
8408 if (hw->phy_type == e1000_phy_ife) {
8409 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8413 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8414 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8420 /******************************************************************************
8421 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8424 * hw - Struct containing variables accessed by shared code
8425 * offset - offset of word in the EEPROM to read
8426 * data - word read from the EEPROM
8427 * words - number of words to read
8428 *****************************************************************************/
8430 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8433 int32_t error = E1000_SUCCESS;
8434 uint32_t flash_bank = 0;
8435 uint32_t act_offset = 0;
8436 uint32_t bank_offset = 0;
8440 /* We need to know which is the valid flash bank. In the event
8441 * that we didn't allocate eeprom_shadow_ram, we may not be
8442 * managing flash_bank. So it cannot be trusted and needs
8443 * to be updated with each read.
8445 /* Value of bit 22 corresponds to the flash bank we're on. */
8446 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8448 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8449 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8451 error = e1000_get_software_flag(hw);
8452 if (error != E1000_SUCCESS)
8455 for (i = 0; i < words; i++) {
8456 if (hw->eeprom_shadow_ram != NULL &&
8457 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8458 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8460 /* The NVM part needs a byte offset, hence * 2 */
8461 act_offset = bank_offset + ((offset + i) * 2);
8462 error = e1000_read_ich8_word(hw, act_offset, &word);
8463 if (error != E1000_SUCCESS)
8469 e1000_release_software_flag(hw);
8474 /******************************************************************************
8475 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8476 * register. Actually, writes are written to the shadow ram cache in the hw
8477 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8478 * the NVM, which occurs when the NVM checksum is updated.
8480 * hw - Struct containing variables accessed by shared code
8481 * offset - offset of word in the EEPROM to write
8482 * words - number of words to write
8483 * data - words to write to the EEPROM
8484 *****************************************************************************/
8486 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8490 int32_t error = E1000_SUCCESS;
8492 error = e1000_get_software_flag(hw);
8493 if (error != E1000_SUCCESS)
8496 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8497 * allocated. Subsequent reads to the modified words are read from
8498 * this cached structure as well. Writes will only go into this
8499 * cached structure unless it's followed by a call to
8500 * e1000_update_eeprom_checksum() where it will commit the changes
8501 * and clear the "modified" field.
8503 if (hw->eeprom_shadow_ram != NULL) {
8504 for (i = 0; i < words; i++) {
8505 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8506 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8507 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8509 error = -E1000_ERR_EEPROM;
8514 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8515 * as they don't perform any NVM writes. An attempt in doing so
8516 * will result in this error.
8518 error = -E1000_ERR_EEPROM;
8521 e1000_release_software_flag(hw);
8526 /******************************************************************************
8527 * This function does initial flash setup so that a new read/write/erase cycle
8530 * hw - The pointer to the hw structure
8531 ****************************************************************************/
8533 e1000_ich8_cycle_init(struct e1000_hw *hw)
8535 union ich8_hws_flash_status hsfsts;
8536 int32_t error = E1000_ERR_EEPROM;
8539 DEBUGFUNC("e1000_ich8_cycle_init");
8541 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8543 /* May be check the Flash Des Valid bit in Hw status */
8544 if (hsfsts.hsf_status.fldesvalid == 0) {
8545 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8549 /* Clear FCERR in Hw status by writing 1 */
8550 /* Clear DAEL in Hw status by writing a 1 */
8551 hsfsts.hsf_status.flcerr = 1;
8552 hsfsts.hsf_status.dael = 1;
8554 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8556 /* Either we should have a hardware SPI cycle in progress bit to check
8557 * against, in order to start a new cycle or FDONE bit should be changed
8558 * in the hardware so that it is 1 after harware reset, which can then be
8559 * used as an indication whether a cycle is in progress or has been
8560 * completed .. we should also have some software semaphore mechanism to
8561 * guard FDONE or the cycle in progress bit so that two threads access to
8562 * those bits can be sequentiallized or a way so that 2 threads dont
8563 * start the cycle at the same time */
8565 if (hsfsts.hsf_status.flcinprog == 0) {
8566 /* There is no cycle running at present, so we can start a cycle */
8567 /* Begin by setting Flash Cycle Done. */
8568 hsfsts.hsf_status.flcdone = 1;
8569 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8570 error = E1000_SUCCESS;
8572 /* otherwise poll for sometime so the current cycle has a chance
8573 * to end before giving up. */
8574 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8575 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8576 if (hsfsts.hsf_status.flcinprog == 0) {
8577 error = E1000_SUCCESS;
8582 if (error == E1000_SUCCESS) {
8583 /* Successful in waiting for previous cycle to timeout,
8584 * now set the Flash Cycle Done. */
8585 hsfsts.hsf_status.flcdone = 1;
8586 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8588 DEBUGOUT("Flash controller busy, cannot get access");
8594 /******************************************************************************
8595 * This function starts a flash cycle and waits for its completion
8597 * hw - The pointer to the hw structure
8598 ****************************************************************************/
8600 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8602 union ich8_hws_flash_ctrl hsflctl;
8603 union ich8_hws_flash_status hsfsts;
8604 int32_t error = E1000_ERR_EEPROM;
8607 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8608 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8609 hsflctl.hsf_ctrl.flcgo = 1;
8610 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8612 /* wait till FDONE bit is set to 1 */
8614 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8615 if (hsfsts.hsf_status.flcdone == 1)
8619 } while (i < timeout);
8620 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8621 error = E1000_SUCCESS;
8626 /******************************************************************************
8627 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8629 * hw - The pointer to the hw structure
8630 * index - The index of the byte or word to read.
8631 * size - Size of data to read, 1=byte 2=word
8632 * data - Pointer to the word to store the value read.
8633 *****************************************************************************/
8635 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8636 uint32_t size, uint16_t* data)
8638 union ich8_hws_flash_status hsfsts;
8639 union ich8_hws_flash_ctrl hsflctl;
8640 uint32_t flash_linear_address;
8641 uint32_t flash_data = 0;
8642 int32_t error = -E1000_ERR_EEPROM;
8645 DEBUGFUNC("e1000_read_ich8_data");
8647 if (size < 1 || size > 2 || data == 0x0 ||
8648 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8651 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8652 hw->flash_base_addr;
8657 error = e1000_ich8_cycle_init(hw);
8658 if (error != E1000_SUCCESS)
8661 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8662 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8663 hsflctl.hsf_ctrl.fldbcount = size - 1;
8664 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8665 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8667 /* Write the last 24 bits of index into Flash Linear address field in
8669 /* TODO: TBD maybe check the index against the size of flash */
8671 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8673 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8675 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8676 * sequence a few more times, else read in (shift in) the Flash Data0,
8677 * the order is least significant byte first msb to lsb */
8678 if (error == E1000_SUCCESS) {
8679 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8681 *data = (uint8_t)(flash_data & 0x000000FF);
8682 } else if (size == 2) {
8683 *data = (uint16_t)(flash_data & 0x0000FFFF);
8687 /* If we've gotten here, then things are probably completely hosed,
8688 * but if the error condition is detected, it won't hurt to give
8689 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8691 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8692 if (hsfsts.hsf_status.flcerr == 1) {
8693 /* Repeat for some time before giving up. */
8695 } else if (hsfsts.hsf_status.flcdone == 0) {
8696 DEBUGOUT("Timeout error - flash cycle did not complete.");
8700 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8705 /******************************************************************************
8706 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8708 * hw - The pointer to the hw structure
8709 * index - The index of the byte/word to read.
8710 * size - Size of data to read, 1=byte 2=word
8711 * data - The byte(s) to write to the NVM.
8712 *****************************************************************************/
8714 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8717 union ich8_hws_flash_status hsfsts;
8718 union ich8_hws_flash_ctrl hsflctl;
8719 uint32_t flash_linear_address;
8720 uint32_t flash_data = 0;
8721 int32_t error = -E1000_ERR_EEPROM;
8724 DEBUGFUNC("e1000_write_ich8_data");
8726 if (size < 1 || size > 2 || data > size * 0xff ||
8727 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8730 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8731 hw->flash_base_addr;
8736 error = e1000_ich8_cycle_init(hw);
8737 if (error != E1000_SUCCESS)
8740 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8741 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8742 hsflctl.hsf_ctrl.fldbcount = size -1;
8743 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8744 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8746 /* Write the last 24 bits of index into Flash Linear address field in
8748 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8751 flash_data = (uint32_t)data & 0x00FF;
8753 flash_data = (uint32_t)data;
8755 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8757 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8758 * sequence a few more times else done */
8759 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8760 if (error == E1000_SUCCESS) {
8763 /* If we're here, then things are most likely completely hosed,
8764 * but if the error condition is detected, it won't hurt to give
8765 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8767 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8768 if (hsfsts.hsf_status.flcerr == 1) {
8769 /* Repeat for some time before giving up. */
8771 } else if (hsfsts.hsf_status.flcdone == 0) {
8772 DEBUGOUT("Timeout error - flash cycle did not complete.");
8776 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8781 /******************************************************************************
8782 * Reads a single byte from the NVM using the ICH8 flash access registers.
8784 * hw - pointer to e1000_hw structure
8785 * index - The index of the byte to read.
8786 * data - Pointer to a byte to store the value read.
8787 *****************************************************************************/
8789 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8791 int32_t status = E1000_SUCCESS;
8794 status = e1000_read_ich8_data(hw, index, 1, &word);
8795 if (status == E1000_SUCCESS) {
8796 *data = (uint8_t)word;
8802 /******************************************************************************
8803 * Writes a single byte to the NVM using the ICH8 flash access registers.
8804 * Performs verification by reading back the value and then going through
8805 * a retry algorithm before giving up.
8807 * hw - pointer to e1000_hw structure
8808 * index - The index of the byte to write.
8809 * byte - The byte to write to the NVM.
8810 *****************************************************************************/
8812 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8814 int32_t error = E1000_SUCCESS;
8815 int32_t program_retries;
8818 e1000_write_ich8_byte(hw, index, byte);
8821 for (program_retries = 0; program_retries < 100; program_retries++) {
8822 e1000_read_ich8_byte(hw, index, &temp_byte);
8823 if (temp_byte == byte)
8826 e1000_write_ich8_byte(hw, index, byte);
8829 if (program_retries == 100)
8830 error = E1000_ERR_EEPROM;
8835 /******************************************************************************
8836 * Writes a single byte to the NVM using the ICH8 flash access registers.
8838 * hw - pointer to e1000_hw structure
8839 * index - The index of the byte to read.
8840 * data - The byte to write to the NVM.
8841 *****************************************************************************/
8843 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8845 int32_t status = E1000_SUCCESS;
8846 uint16_t word = (uint16_t)data;
8848 status = e1000_write_ich8_data(hw, index, 1, word);
8853 /******************************************************************************
8854 * Reads a word from the NVM using the ICH8 flash access registers.
8856 * hw - pointer to e1000_hw structure
8857 * index - The starting byte index of the word to read.
8858 * data - Pointer to a word to store the value read.
8859 *****************************************************************************/
8861 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8863 int32_t status = E1000_SUCCESS;
8864 status = e1000_read_ich8_data(hw, index, 2, data);
8868 /******************************************************************************
8869 * Writes a word to the NVM using the ICH8 flash access registers.
8871 * hw - pointer to e1000_hw structure
8872 * index - The starting byte index of the word to read.
8873 * data - The word to write to the NVM.
8874 *****************************************************************************/
8876 e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8878 int32_t status = E1000_SUCCESS;
8879 status = e1000_write_ich8_data(hw, index, 2, data);
8883 /******************************************************************************
8884 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8885 * segment N is 4096 * N + flash_reg_addr.
8887 * hw - pointer to e1000_hw structure
8888 * segment - 0 for first segment, 1 for second segment, etc.
8889 *****************************************************************************/
8891 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8893 union ich8_hws_flash_status hsfsts;
8894 union ich8_hws_flash_ctrl hsflctl;
8895 uint32_t flash_linear_address;
8897 int32_t error = E1000_ERR_EEPROM;
8898 int32_t iteration, seg_size;
8899 int32_t sector_size;
8901 int32_t error_flag = 0;
8903 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8905 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8906 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8907 * consecutive sectors. The start index for the nth Hw sector can be
8908 * calculated as = segment * 4096 + n * 256
8909 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8910 * The start index for the nth Hw sector can be calculated
8911 * as = segment * 4096
8912 * 10: Error condition
8913 * 11: The Hw sector size is much bigger than the size asked to
8914 * erase...error condition */
8915 if (hsfsts.hsf_status.berasesz == 0x0) {
8916 /* Hw sector size 256 */
8917 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8918 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8919 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8920 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8922 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8923 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8929 for (j = 0; j < iteration ; j++) {
8933 error = e1000_ich8_cycle_init(hw);
8934 if (error != E1000_SUCCESS) {
8939 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8941 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8942 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8943 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8945 /* Write the last 24 bits of an index within the block into Flash
8946 * Linear address field in Flash Address. This probably needs to
8947 * be calculated here based off the on-chip segment size and the
8948 * software segment size assumed (4K) */
8950 flash_linear_address = segment * sector_size + j * seg_size;
8951 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8952 flash_linear_address += hw->flash_base_addr;
8954 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8956 error = e1000_ich8_flash_cycle(hw, 1000000);
8957 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8958 * sequence a few more times else Done */
8959 if (error == E1000_SUCCESS) {
8962 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8963 if (hsfsts.hsf_status.flcerr == 1) {
8964 /* repeat for some time before giving up */
8966 } else if (hsfsts.hsf_status.flcdone == 0) {
8971 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8972 if (error_flag == 1)
8975 if (error_flag != 1)
8976 error = E1000_SUCCESS;
8980 /******************************************************************************
8982 * Reverse duplex setting without breaking the link.
8984 * hw: Struct containing variables accessed by shared code
8986 *****************************************************************************/
8988 e1000_duplex_reversal(struct e1000_hw *hw)
8993 if (hw->phy_type != e1000_phy_igp_3)
8994 return E1000_SUCCESS;
8996 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
9000 phy_data ^= MII_CR_FULL_DUPLEX;
9002 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
9006 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
9010 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
9011 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
9017 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9018 uint32_t cnf_base_addr, uint32_t cnf_size)
9020 uint32_t ret_val = E1000_SUCCESS;
9021 uint16_t word_addr, reg_data, reg_addr;
9024 /* cnf_base_addr is in DWORD */
9025 word_addr = (uint16_t)(cnf_base_addr << 1);
9027 /* cnf_size is returned in size of dwords */
9028 for (i = 0; i < cnf_size; i++) {
9029 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data);
9033 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr);
9037 ret_val = e1000_get_software_flag(hw);
9038 if (ret_val != E1000_SUCCESS)
9041 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9043 e1000_release_software_flag(hw);
9051 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9053 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9055 if (hw->phy_type != e1000_phy_igp_3)
9056 return E1000_SUCCESS;
9058 /* Check if SW needs configure the PHY */
9059 reg_data = E1000_READ_REG(hw, FEXTNVM);
9060 if (!(reg_data & FEXTNVM_SW_CONFIG))
9061 return E1000_SUCCESS;
9063 /* Wait for basic configuration completes before proceeding*/
9066 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9069 } while ((!reg_data) && (loop < 50));
9071 /* Clear the Init Done bit for the next init event */
9072 reg_data = E1000_READ_REG(hw, STATUS);
9073 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9074 E1000_WRITE_REG(hw, STATUS, reg_data);
9076 /* Make sure HW does not configure LCD from PHY extended configuration
9077 before SW configuration */
9078 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9079 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9080 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9081 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9084 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9085 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9086 /* cnf_base_addr is in DWORD */
9087 cnf_base_addr >>= 16;
9089 /* Configure LCD from extended configuration region. */
9090 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9097 return E1000_SUCCESS;