git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/apic/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/pci.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39 #ifdef CONFIG_ACPI
  40 #include <acpi/acpi_bus.h>
  41 #endif
  42 #include <linux/bootmem.h>
  43 #include <linux/dmar.h>
  44 #include <linux/hpet.h>
  45
  46 #include <asm/idle.h>
  47 #include <asm/io.h>
  48 #include <asm/smp.h>
  49 #include <asm/cpu.h>
  50 #include <asm/desc.h>
  51 #include <asm/proto.h>
  52 #include <asm/acpi.h>
  53 #include <asm/dma.h>
  54 #include <asm/timer.h>
  55 #include <asm/i8259.h>
  56 #include <asm/nmi.h>
  57 #include <asm/msidef.h>
  58 #include <asm/hypertransport.h>
  59 #include <asm/setup.h>
  60 #include <asm/irq_remapping.h>
  61 #include <asm/hpet.h>
  62 #include <asm/uv/uv_hub.h>
  63 #include <asm/uv/uv_irq.h>
  64
  65 #include <asm/apic.h>
  66
  67 #define __apicdebuginit(type) static type __init
  68
  69 /*
  70  *      Is the SiS APIC rmw bug present ?
  71  *      -1 = don't know, 0 = no, 1 = yes
  72  */
  73 int sis_apic_bug = -1;
  74
  75 static DEFINE_SPINLOCK(ioapic_lock);
  76 static DEFINE_SPINLOCK(vector_lock);
  77
  78 /*
  79  * # of IRQ routing registers
  80  */
  81 int nr_ioapic_registers[MAX_IO_APICS];
  82
  83 /* I/O APIC entries */
  84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  85 int nr_ioapics;
  86
  87 /* MP IRQ source entries */
  88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  89
  90 /* # of MP IRQ source entries */
  91 int mp_irq_entries;
  92
  93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  94 int mp_bus_id_to_type[MAX_MP_BUSSES];
  95 #endif
  96
  97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  98
  99 int skip_ioapic_setup;
 100
 101 void arch_disable_smp_support(void)
 102 {
 103 #ifdef CONFIG_PCI
 104         noioapicquirk = 1;
 105         noioapicreroute = -1;
 106 #endif
 107         skip_ioapic_setup = 1;
 108 }
 109
 110 static int __init parse_noapic(char *str)
 111 {
 112         /* disable IO-APIC */
 113         arch_disable_smp_support();
 114         return 0;
 115 }
 116 early_param("noapic", parse_noapic);
 117
 118 struct irq_pin_list;
 119
 120 /*
 121  * This is performance-critical, we want to do it O(1)
 122  *
 123  * the indexing order of this array favors 1:1 mappings
 124  * between pins and IRQs.
 125  */
 126
 127 struct irq_pin_list {
 128         int apic, pin;
 129         struct irq_pin_list *next;
 130 };
 131
 132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
 133 {
 134         struct irq_pin_list *pin;
 135         int node;
 136
 137         node = cpu_to_node(cpu);
 138
 139         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 140
 141         return pin;
 142 }
 143
 144 struct irq_cfg {
 145         struct irq_pin_list *irq_2_pin;
 146         cpumask_var_t domain;
 147         cpumask_var_t old_domain;
 148         unsigned move_cleanup_count;
 149         u8 vector;
 150         u8 move_in_progress : 1;
 151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 152         u8 move_desc_pending : 1;
 153 #endif
 154 };
 155
 156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 157 #ifdef CONFIG_SPARSE_IRQ
 158 static struct irq_cfg irq_cfgx[] = {
 159 #else
 160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
 161 #endif
 162         [0]  = { .vector = IRQ0_VECTOR,  },
 163         [1]  = { .vector = IRQ1_VECTOR,  },
 164         [2]  = { .vector = IRQ2_VECTOR,  },
 165         [3]  = { .vector = IRQ3_VECTOR,  },
 166         [4]  = { .vector = IRQ4_VECTOR,  },
 167         [5]  = { .vector = IRQ5_VECTOR,  },
 168         [6]  = { .vector = IRQ6_VECTOR,  },
 169         [7]  = { .vector = IRQ7_VECTOR,  },
 170         [8]  = { .vector = IRQ8_VECTOR,  },
 171         [9]  = { .vector = IRQ9_VECTOR,  },
 172         [10] = { .vector = IRQ10_VECTOR, },
 173         [11] = { .vector = IRQ11_VECTOR, },
 174         [12] = { .vector = IRQ12_VECTOR, },
 175         [13] = { .vector = IRQ13_VECTOR, },
 176         [14] = { .vector = IRQ14_VECTOR, },
 177         [15] = { .vector = IRQ15_VECTOR, },
 178 };
 179
 180 int __init arch_early_irq_init(void)
 181 {
 182         struct irq_cfg *cfg;
 183         struct irq_desc *desc;
 184         int count;
 185         int i;
 186
 187         cfg = irq_cfgx;
 188         count = ARRAY_SIZE(irq_cfgx);
 189
 190         for (i = 0; i < count; i++) {
 191                 desc = irq_to_desc(i);
 192                 desc->chip_data = &cfg[i];
 193                 alloc_bootmem_cpumask_var(&cfg[i].domain);
 194                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
 195                 if (i < NR_IRQS_LEGACY)
 196                         cpumask_setall(cfg[i].domain);
 197         }
 198
 199         return 0;
 200 }
 201
 202 #ifdef CONFIG_SPARSE_IRQ
 203 static struct irq_cfg *irq_cfg(unsigned int irq)
 204 {
 205         struct irq_cfg *cfg = NULL;
 206         struct irq_desc *desc;
 207
 208         desc = irq_to_desc(irq);
 209         if (desc)
 210                 cfg = desc->chip_data;
 211
 212         return cfg;
 213 }
 214
 215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
 216 {
 217         struct irq_cfg *cfg;
 218         int node;
 219
 220         node = cpu_to_node(cpu);
 221
 222         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
 223         if (cfg) {
 224                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
 225                         kfree(cfg);
 226                         cfg = NULL;
 227                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
 228                                                           GFP_ATOMIC, node)) {
 229                         free_cpumask_var(cfg->domain);
 230                         kfree(cfg);
 231                         cfg = NULL;
 232                 } else {
 233                         cpumask_clear(cfg->domain);
 234                         cpumask_clear(cfg->old_domain);
 235                 }
 236         }
 237
 238         return cfg;
 239 }
 240
 241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
 242 {
 243         struct irq_cfg *cfg;
 244
 245         cfg = desc->chip_data;
 246         if (!cfg) {
 247                 desc->chip_data = get_one_free_irq_cfg(cpu);
 248                 if (!desc->chip_data) {
 249                         printk(KERN_ERR "can not alloc irq_cfg\n");
 250                         BUG_ON(1);
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 258
 259 static void
 260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
 261 {
 262         struct irq_pin_list *old_entry, *head, *tail, *entry;
 263
 264         cfg->irq_2_pin = NULL;
 265         old_entry = old_cfg->irq_2_pin;
 266         if (!old_entry)
 267                 return;
 268
 269         entry = get_one_free_irq_2_pin(cpu);
 270         if (!entry)
 271                 return;
 272
 273         entry->apic     = old_entry->apic;
 274         entry->pin      = old_entry->pin;
 275         head            = entry;
 276         tail            = entry;
 277         old_entry       = old_entry->next;
 278         while (old_entry) {
 279                 entry = get_one_free_irq_2_pin(cpu);
 280                 if (!entry) {
 281                         entry = head;
 282                         while (entry) {
 283                                 head = entry->next;
 284                                 kfree(entry);
 285                                 entry = head;
 286                         }
 287                         /* still use the old one */
 288                         return;
 289                 }
 290                 entry->apic     = old_entry->apic;
 291                 entry->pin      = old_entry->pin;
 292                 tail->next      = entry;
 293                 tail            = entry;
 294                 old_entry       = old_entry->next;
 295         }
 296
 297         tail->next = NULL;
 298         cfg->irq_2_pin = head;
 299 }
 300
 301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 302 {
 303         struct irq_pin_list *entry, *next;
 304
 305         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
 306                 return;
 307
 308         entry = old_cfg->irq_2_pin;
 309
 310         while (entry) {
 311                 next = entry->next;
 312                 kfree(entry);
 313                 entry = next;
 314         }
 315         old_cfg->irq_2_pin = NULL;
 316 }
 317
 318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
 319                                  struct irq_desc *desc, int cpu)
 320 {
 321         struct irq_cfg *cfg;
 322         struct irq_cfg *old_cfg;
 323
 324         cfg = get_one_free_irq_cfg(cpu);
 325
 326         if (!cfg)
 327                 return;
 328
 329         desc->chip_data = cfg;
 330
 331         old_cfg = old_desc->chip_data;
 332
 333         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 334
 335         init_copy_irq_2_pin(old_cfg, cfg, cpu);
 336 }
 337
 338 static void free_irq_cfg(struct irq_cfg *old_cfg)
 339 {
 340         kfree(old_cfg);
 341 }
 342
 343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
 344 {
 345         struct irq_cfg *old_cfg, *cfg;
 346
 347         old_cfg = old_desc->chip_data;
 348         cfg = desc->chip_data;
 349
 350         if (old_cfg == cfg)
 351                 return;
 352
 353         if (old_cfg) {
 354                 free_irq_2_pin(old_cfg, cfg);
 355                 free_irq_cfg(old_cfg);
 356                 old_desc->chip_data = NULL;
 357         }
 358 }
 359
 360 static void
 361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 362 {
 363         struct irq_cfg *cfg = desc->chip_data;
 364
 365         if (!cfg->move_in_progress) {
 366                 /* it means that domain is not changed */
 367                 if (!cpumask_intersects(desc->affinity, mask))
 368                         cfg->move_desc_pending = 1;
 369         }
 370 }
 371 #endif
 372
 373 #else
 374 static struct irq_cfg *irq_cfg(unsigned int irq)
 375 {
 376         return irq < nr_irqs ? irq_cfgx + irq : NULL;
 377 }
 378
 379 #endif
 380
 381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
 382 static inline void
 383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 384 {
 385 }
 386 #endif
 387
 388 struct io_apic {
 389         unsigned int index;
 390         unsigned int unused[3];
 391         unsigned int data;
 392         unsigned int unused2[11];
 393         unsigned int eoi;
 394 };
 395
 396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 397 {
 398         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 399                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 400 }
 401
 402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
 403 {
 404         struct io_apic __iomem *io_apic = io_apic_base(apic);
 405         writel(vector, &io_apic->eoi);
 406 }
 407
 408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 409 {
 410         struct io_apic __iomem *io_apic = io_apic_base(apic);
 411         writel(reg, &io_apic->index);
 412         return readl(&io_apic->data);
 413 }
 414
 415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 416 {
 417         struct io_apic __iomem *io_apic = io_apic_base(apic);
 418         writel(reg, &io_apic->index);
 419         writel(value, &io_apic->data);
 420 }
 421
 422 /*
 423  * Re-write a value: to be used for read-modify-write
 424  * cycles where the read already set up the index register.
 425  *
 426  * Older SiS APIC requires we rewrite the index register
 427  */
 428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 429 {
 430         struct io_apic __iomem *io_apic = io_apic_base(apic);
 431
 432         if (sis_apic_bug)
 433                 writel(reg, &io_apic->index);
 434         writel(value, &io_apic->data);
 435 }
 436
 437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
 438 {
 439         struct irq_pin_list *entry;
 440         unsigned long flags;
 441
 442         spin_lock_irqsave(&ioapic_lock, flags);
 443         entry = cfg->irq_2_pin;
 444         for (;;) {
 445                 unsigned int reg;
 446                 int pin;
 447
 448                 if (!entry)
 449                         break;
 450                 pin = entry->pin;
 451                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 452                 /* Is the remote IRR bit set? */
 453                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
 454                         spin_unlock_irqrestore(&ioapic_lock, flags);
 455                         return true;
 456                 }
 457                 if (!entry->next)
 458                         break;
 459                 entry = entry->next;
 460         }
 461         spin_unlock_irqrestore(&ioapic_lock, flags);
 462
 463         return false;
 464 }
 465
 466 union entry_union {
 467         struct { u32 w1, w2; };
 468         struct IO_APIC_route_entry entry;
 469 };
 470
 471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 472 {
 473         union entry_union eu;
 474         unsigned long flags;
 475         spin_lock_irqsave(&ioapic_lock, flags);
 476         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 477         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 478         spin_unlock_irqrestore(&ioapic_lock, flags);
 479         return eu.entry;
 480 }
 481
 482 /*
 483  * When we write a new IO APIC routing entry, we need to write the high
 484  * word first! If the mask bit in the low word is clear, we will enable
 485  * the interrupt, and we need to make sure the entry is fully populated
 486  * before that happens.
 487  */
 488 static void
 489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 490 {
 491         union entry_union eu;
 492         eu.entry = e;
 493         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 494         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 495 }
 496
 497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 498 {
 499         unsigned long flags;
 500         spin_lock_irqsave(&ioapic_lock, flags);
 501         __ioapic_write_entry(apic, pin, e);
 502         spin_unlock_irqrestore(&ioapic_lock, flags);
 503 }
 504
 505 /*
 506  * When we mask an IO APIC routing entry, we need to write the low
 507  * word first, in order to set the mask bit before we change the
 508  * high bits!
 509  */
 510 static void ioapic_mask_entry(int apic, int pin)
 511 {
 512         unsigned long flags;
 513         union entry_union eu = { .entry.mask = 1 };
 514
 515         spin_lock_irqsave(&ioapic_lock, flags);
 516         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 517         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 518         spin_unlock_irqrestore(&ioapic_lock, flags);
 519 }
 520
 521 #ifdef CONFIG_SMP
 522 static void send_cleanup_vector(struct irq_cfg *cfg)
 523 {
 524         cpumask_var_t cleanup_mask;
 525
 526         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
 527                 unsigned int i;
 528                 cfg->move_cleanup_count = 0;
 529                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 530                         cfg->move_cleanup_count++;
 531                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 532                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
 533         } else {
 534                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
 535                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
 536                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
 537                 free_cpumask_var(cleanup_mask);
 538         }
 539         cfg->move_in_progress = 0;
 540 }
 541
 542 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
 543 {
 544         int apic, pin;
 545         struct irq_pin_list *entry;
 546         u8 vector = cfg->vector;
 547
 548         entry = cfg->irq_2_pin;
 549         for (;;) {
 550                 unsigned int reg;
 551
 552                 if (!entry)
 553                         break;
 554
 555                 apic = entry->apic;
 556                 pin = entry->pin;
 557                 /*
 558                  * With interrupt-remapping, destination information comes
 559                  * from interrupt-remapping table entry.
 560                  */
 561                 if (!irq_remapped(irq))
 562                         io_apic_write(apic, 0x11 + pin*2, dest);
 563                 reg = io_apic_read(apic, 0x10 + pin*2);
 564                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
 565                 reg |= vector;
 566                 io_apic_modify(apic, 0x10 + pin*2, reg);
 567                 if (!entry->next)
 568                         break;
 569                 entry = entry->next;
 570         }
 571 }
 572
 573 static int
 574 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
 575
 576 /*
 577  * Either sets desc->affinity to a valid value, and returns
 578  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
 579  * leaves desc->affinity untouched.
 580  */
 581 static unsigned int
 582 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
 583 {
 584         struct irq_cfg *cfg;
 585         unsigned int irq;
 586
 587         if (!cpumask_intersects(mask, cpu_online_mask))
 588                 return BAD_APICID;
 589
 590         irq = desc->irq;
 591         cfg = desc->chip_data;
 592         if (assign_irq_vector(irq, cfg, mask))
 593                 return BAD_APICID;
 594
 595         /* check that before desc->addinity get updated */
 596         set_extra_move_desc(desc, mask);
 597
 598         cpumask_copy(desc->affinity, mask);
 599
 600         return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
 601 }
 602
 603 static void
 604 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 605 {
 606         struct irq_cfg *cfg;
 607         unsigned long flags;
 608         unsigned int dest;
 609         unsigned int irq;
 610
 611         irq = desc->irq;
 612         cfg = desc->chip_data;
 613
 614         spin_lock_irqsave(&ioapic_lock, flags);
 615         dest = set_desc_affinity(desc, mask);
 616         if (dest != BAD_APICID) {
 617                 /* Only the high 8 bits are valid. */
 618                 dest = SET_APIC_LOGICAL_ID(dest);
 619                 __target_IO_APIC_irq(irq, dest, cfg);
 620         }
 621         spin_unlock_irqrestore(&ioapic_lock, flags);
 622 }
 623
 624 static void
 625 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
 626 {
 627         struct irq_desc *desc;
 628
 629         desc = irq_to_desc(irq);
 630
 631         set_ioapic_affinity_irq_desc(desc, mask);
 632 }
 633 #endif /* CONFIG_SMP */
 634
 635 /*
 636  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 637  * shared ISA-space IRQs, so we have to support them. We are super
 638  * fast in the common case, and fast for shared ISA-space IRQs.
 639  */
 640 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 641 {
 642         struct irq_pin_list *entry;
 643
 644         entry = cfg->irq_2_pin;
 645         if (!entry) {
 646                 entry = get_one_free_irq_2_pin(cpu);
 647                 if (!entry) {
 648                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
 649                                         apic, pin);
 650                         return;
 651                 }
 652                 cfg->irq_2_pin = entry;
 653                 entry->apic = apic;
 654                 entry->pin = pin;
 655                 return;
 656         }
 657
 658         while (entry->next) {
 659                 /* not again, please */
 660                 if (entry->apic == apic && entry->pin == pin)
 661                         return;
 662
 663                 entry = entry->next;
 664         }
 665
 666         entry->next = get_one_free_irq_2_pin(cpu);
 667         entry = entry->next;
 668         entry->apic = apic;
 669         entry->pin = pin;
 670 }
 671
 672 /*
 673  * Reroute an IRQ to a different pin.
 674  */
 675 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 676                                       int oldapic, int oldpin,
 677                                       int newapic, int newpin)
 678 {
 679         struct irq_pin_list *entry = cfg->irq_2_pin;
 680         int replaced = 0;
 681
 682         while (entry) {
 683                 if (entry->apic == oldapic && entry->pin == oldpin) {
 684                         entry->apic = newapic;
 685                         entry->pin = newpin;
 686                         replaced = 1;
 687                         /* every one is different, right? */
 688                         break;
 689                 }
 690                 entry = entry->next;
 691         }
 692
 693         /* why? call replace before add? */
 694         if (!replaced)
 695                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
 696 }
 697
 698 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
 699                                 int mask_and, int mask_or,
 700                                 void (*final)(struct irq_pin_list *entry))
 701 {
 702         int pin;
 703         struct irq_pin_list *entry;
 704
 705         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
 706                 unsigned int reg;
 707                 pin = entry->pin;
 708                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
 709                 reg &= mask_and;
 710                 reg |= mask_or;
 711                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
 712                 if (final)
 713                         final(entry);
 714         }
 715 }
 716
 717 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
 718 {
 719         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 720 }
 721
 722 #ifdef CONFIG_X86_64
 723 static void io_apic_sync(struct irq_pin_list *entry)
 724 {
 725         /*
 726          * Synchronize the IO-APIC and the CPU by doing
 727          * a dummy read from the IO-APIC
 728          */
 729         struct io_apic __iomem *io_apic;
 730         io_apic = io_apic_base(entry->apic);
 731         readl(&io_apic->data);
 732 }
 733
 734 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 735 {
 736         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 737 }
 738 #else /* CONFIG_X86_32 */
 739 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 740 {
 741         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
 742 }
 743
 744 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 745 {
 746         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
 747                         IO_APIC_REDIR_MASKED, NULL);
 748 }
 749
 750 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
 751 {
 752         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
 753                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 754 }
 755 #endif /* CONFIG_X86_32 */
 756
 757 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 758 {
 759         struct irq_cfg *cfg = desc->chip_data;
 760         unsigned long flags;
 761
 762         BUG_ON(!cfg);
 763
 764         spin_lock_irqsave(&ioapic_lock, flags);
 765         __mask_IO_APIC_irq(cfg);
 766         spin_unlock_irqrestore(&ioapic_lock, flags);
 767 }
 768
 769 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
 770 {
 771         struct irq_cfg *cfg = desc->chip_data;
 772         unsigned long flags;
 773
 774         spin_lock_irqsave(&ioapic_lock, flags);
 775         __unmask_IO_APIC_irq(cfg);
 776         spin_unlock_irqrestore(&ioapic_lock, flags);
 777 }
 778
 779 static void mask_IO_APIC_irq(unsigned int irq)
 780 {
 781         struct irq_desc *desc = irq_to_desc(irq);
 782
 783         mask_IO_APIC_irq_desc(desc);
 784 }
 785 static void unmask_IO_APIC_irq(unsigned int irq)
 786 {
 787         struct irq_desc *desc = irq_to_desc(irq);
 788
 789         unmask_IO_APIC_irq_desc(desc);
 790 }
 791
 792 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 793 {
 794         struct IO_APIC_route_entry entry;
 795
 796         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 797         entry = ioapic_read_entry(apic, pin);
 798         if (entry.delivery_mode == dest_SMI)
 799                 return;
 800         /*
 801          * Disable it in the IO-APIC irq-routing table:
 802          */
 803         ioapic_mask_entry(apic, pin);
 804 }
 805
 806 static void clear_IO_APIC (void)
 807 {
 808         int apic, pin;
 809
 810         for (apic = 0; apic < nr_ioapics; apic++)
 811                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 812                         clear_IO_APIC_pin(apic, pin);
 813 }
 814
 815 #ifdef CONFIG_X86_32
 816 /*
 817  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 818  * specific CPU-side IRQs.
 819  */
 820
 821 #define MAX_PIRQS 8
 822 static int pirq_entries[MAX_PIRQS] = {
 823         [0 ... MAX_PIRQS - 1] = -1
 824 };
 825
 826 static int __init ioapic_pirq_setup(char *str)
 827 {
 828         int i, max;
 829         int ints[MAX_PIRQS+1];
 830
 831         get_options(str, ARRAY_SIZE(ints), ints);
 832
 833         apic_printk(APIC_VERBOSE, KERN_INFO
 834                         "PIRQ redirection, working around broken MP-BIOS.\n");
 835         max = MAX_PIRQS;
 836         if (ints[0] < MAX_PIRQS)
 837                 max = ints[0];
 838
 839         for (i = 0; i < max; i++) {
 840                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 841                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 842                 /*
 843                  * PIRQs are mapped upside down, usually.
 844                  */
 845                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 846         }
 847         return 1;
 848 }
 849
 850 __setup("pirq=", ioapic_pirq_setup);
 851 #endif /* CONFIG_X86_32 */
 852
 853 #ifdef CONFIG_INTR_REMAP
 854 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
 855 {
 856         int apic;
 857         struct IO_APIC_route_entry **ioapic_entries;
 858
 859         ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
 860                                 GFP_ATOMIC);
 861         if (!ioapic_entries)
 862                 return 0;
 863
 864         for (apic = 0; apic < nr_ioapics; apic++) {
 865                 ioapic_entries[apic] =
 866                         kzalloc(sizeof(struct IO_APIC_route_entry) *
 867                                 nr_ioapic_registers[apic], GFP_ATOMIC);
 868                 if (!ioapic_entries[apic])
 869                         goto nomem;
 870         }
 871
 872         return ioapic_entries;
 873
 874 nomem:
 875         while (--apic >= 0)
 876                 kfree(ioapic_entries[apic]);
 877         kfree(ioapic_entries);
 878
 879         return 0;
 880 }
 881
 882 /*
 883  * Saves all the IO-APIC RTE's
 884  */
 885 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
 886 {
 887         int apic, pin;
 888
 889         if (!ioapic_entries)
 890                 return -ENOMEM;
 891
 892         for (apic = 0; apic < nr_ioapics; apic++) {
 893                 if (!ioapic_entries[apic])
 894                         return -ENOMEM;
 895
 896                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 897                         ioapic_entries[apic][pin] =
 898                                 ioapic_read_entry(apic, pin);
 899         }
 900
 901         return 0;
 902 }
 903
 904 /*
 905  * Mask all IO APIC entries.
 906  */
 907 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
 908 {
 909         int apic, pin;
 910
 911         if (!ioapic_entries)
 912                 return;
 913
 914         for (apic = 0; apic < nr_ioapics; apic++) {
 915                 if (!ioapic_entries[apic])
 916                         break;
 917
 918                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 919                         struct IO_APIC_route_entry entry;
 920
 921                         entry = ioapic_entries[apic][pin];
 922                         if (!entry.mask) {
 923                                 entry.mask = 1;
 924                                 ioapic_write_entry(apic, pin, entry);
 925                         }
 926                 }
 927         }
 928 }
 929
 930 /*
 931  * Restore IO APIC entries which was saved in ioapic_entries.
 932  */
 933 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
 934 {
 935         int apic, pin;
 936
 937         if (!ioapic_entries)
 938                 return -ENOMEM;
 939
 940         for (apic = 0; apic < nr_ioapics; apic++) {
 941                 if (!ioapic_entries[apic])
 942                         return -ENOMEM;
 943
 944                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 945                         ioapic_write_entry(apic, pin,
 946                                         ioapic_entries[apic][pin]);
 947         }
 948         return 0;
 949 }
 950
 951 void reinit_intr_remapped_IO_APIC(int intr_remapping,
 952         struct IO_APIC_route_entry **ioapic_entries)
 953
 954 {
 955         /*
 956          * for now plain restore of previous settings.
 957          * TBD: In the case of OS enabling interrupt-remapping,
 958          * IO-APIC RTE's need to be setup to point to interrupt-remapping
 959          * table entries. for now, do a plain restore, and wait for
 960          * the setup_IO_APIC_irqs() to do proper initialization.
 961          */
 962         restore_IO_APIC_setup(ioapic_entries);
 963 }
 964
 965 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
 966 {
 967         int apic;
 968
 969         for (apic = 0; apic < nr_ioapics; apic++)
 970                 kfree(ioapic_entries[apic]);
 971
 972         kfree(ioapic_entries);
 973 }
 974 #endif
 975
 976 /*
 977  * Find the IRQ entry number of a certain pin.
 978  */
 979 static int find_irq_entry(int apic, int pin, int type)
 980 {
 981         int i;
 982
 983         for (i = 0; i < mp_irq_entries; i++)
 984                 if (mp_irqs[i].irqtype == type &&
 985                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
 986                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 987                     mp_irqs[i].dstirq == pin)
 988                         return i;
 989
 990         return -1;
 991 }
 992
 993 /*
 994  * Find the pin to which IRQ[irq] (ISA) is connected
 995  */
 996 static int __init find_isa_irq_pin(int irq, int type)
 997 {
 998         int i;
 999
1000         for (i = 0; i < mp_irq_entries; i++) {
1001                 int lbus = mp_irqs[i].srcbus;
1002
1003                 if (test_bit(lbus, mp_bus_not_pci) &&
1004                     (mp_irqs[i].irqtype == type) &&
1005                     (mp_irqs[i].srcbusirq == irq))
1006
1007                         return mp_irqs[i].dstirq;
1008         }
1009         return -1;
1010 }
1011
1012 static int __init find_isa_irq_apic(int irq, int type)
1013 {
1014         int i;
1015
1016         for (i = 0; i < mp_irq_entries; i++) {
1017                 int lbus = mp_irqs[i].srcbus;
1018
1019                 if (test_bit(lbus, mp_bus_not_pci) &&
1020                     (mp_irqs[i].irqtype == type) &&
1021                     (mp_irqs[i].srcbusirq == irq))
1022                         break;
1023         }
1024         if (i < mp_irq_entries) {
1025                 int apic;
1026                 for(apic = 0; apic < nr_ioapics; apic++) {
1027                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
1028                                 return apic;
1029                 }
1030         }
1031
1032         return -1;
1033 }
1034
1035 /*
1036  * Find a specific PCI IRQ entry.
1037  * Not an __init, possibly needed by modules
1038  */
1039 static int pin_2_irq(int idx, int apic, int pin);
1040
1041 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1042 {
1043         int apic, i, best_guess = -1;
1044
1045         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1046                 bus, slot, pin);
1047         if (test_bit(bus, mp_bus_not_pci)) {
1048                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1049                 return -1;
1050         }
1051         for (i = 0; i < mp_irq_entries; i++) {
1052                 int lbus = mp_irqs[i].srcbus;
1053
1054                 for (apic = 0; apic < nr_ioapics; apic++)
1055                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1056                             mp_irqs[i].dstapic == MP_APIC_ALL)
1057                                 break;
1058
1059                 if (!test_bit(lbus, mp_bus_not_pci) &&
1060                     !mp_irqs[i].irqtype &&
1061                     (bus == lbus) &&
1062                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1063                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1064
1065                         if (!(apic || IO_APIC_IRQ(irq)))
1066                                 continue;
1067
1068                         if (pin == (mp_irqs[i].srcbusirq & 3))
1069                                 return irq;
1070                         /*
1071                          * Use the first all-but-pin matching entry as a
1072                          * best-guess fuzzy result for broken mptables.
1073                          */
1074                         if (best_guess < 0)
1075                                 best_guess = irq;
1076                 }
1077         }
1078         return best_guess;
1079 }
1080
1081 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1082
1083 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1084 /*
1085  * EISA Edge/Level control register, ELCR
1086  */
1087 static int EISA_ELCR(unsigned int irq)
1088 {
1089         if (irq < NR_IRQS_LEGACY) {
1090                 unsigned int port = 0x4d0 + (irq >> 3);
1091                 return (inb(port) >> (irq & 7)) & 1;
1092         }
1093         apic_printk(APIC_VERBOSE, KERN_INFO
1094                         "Broken MPtable reports ISA irq %d\n", irq);
1095         return 0;
1096 }
1097
1098 #endif
1099
1100 /* ISA interrupts are always polarity zero edge triggered,
1101  * when listed as conforming in the MP table. */
1102
1103 #define default_ISA_trigger(idx)        (0)
1104 #define default_ISA_polarity(idx)       (0)
1105
1106 /* EISA interrupts are always polarity zero and can be edge or level
1107  * trigger depending on the ELCR value.  If an interrupt is listed as
1108  * EISA conforming in the MP table, that means its trigger type must
1109  * be read in from the ELCR */
1110
1111 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1112 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1113
1114 /* PCI interrupts are always polarity one level triggered,
1115  * when listed as conforming in the MP table. */
1116
1117 #define default_PCI_trigger(idx)        (1)
1118 #define default_PCI_polarity(idx)       (1)
1119
1120 /* MCA interrupts are always polarity zero level triggered,
1121  * when listed as conforming in the MP table. */
1122
1123 #define default_MCA_trigger(idx)        (1)
1124 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1125
1126 static int MPBIOS_polarity(int idx)
1127 {
1128         int bus = mp_irqs[idx].srcbus;
1129         int polarity;
1130
1131         /*
1132          * Determine IRQ line polarity (high active or low active):
1133          */
1134         switch (mp_irqs[idx].irqflag & 3)
1135         {
1136                 case 0: /* conforms, ie. bus-type dependent polarity */
1137                         if (test_bit(bus, mp_bus_not_pci))
1138                                 polarity = default_ISA_polarity(idx);
1139                         else
1140                                 polarity = default_PCI_polarity(idx);
1141                         break;
1142                 case 1: /* high active */
1143                 {
1144                         polarity = 0;
1145                         break;
1146                 }
1147                 case 2: /* reserved */
1148                 {
1149                         printk(KERN_WARNING "broken BIOS!!\n");
1150                         polarity = 1;
1151                         break;
1152                 }
1153                 case 3: /* low active */
1154                 {
1155                         polarity = 1;
1156                         break;
1157                 }
1158                 default: /* invalid */
1159                 {
1160                         printk(KERN_WARNING "broken BIOS!!\n");
1161                         polarity = 1;
1162                         break;
1163                 }
1164         }
1165         return polarity;
1166 }
1167
1168 static int MPBIOS_trigger(int idx)
1169 {
1170         int bus = mp_irqs[idx].srcbus;
1171         int trigger;
1172
1173         /*
1174          * Determine IRQ trigger mode (edge or level sensitive):
1175          */
1176         switch ((mp_irqs[idx].irqflag>>2) & 3)
1177         {
1178                 case 0: /* conforms, ie. bus-type dependent */
1179                         if (test_bit(bus, mp_bus_not_pci))
1180                                 trigger = default_ISA_trigger(idx);
1181                         else
1182                                 trigger = default_PCI_trigger(idx);
1183 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1184                         switch (mp_bus_id_to_type[bus]) {
1185                                 case MP_BUS_ISA: /* ISA pin */
1186                                 {
1187                                         /* set before the switch */
1188                                         break;
1189                                 }
1190                                 case MP_BUS_EISA: /* EISA pin */
1191                                 {
1192                                         trigger = default_EISA_trigger(idx);
1193                                         break;
1194                                 }
1195                                 case MP_BUS_PCI: /* PCI pin */
1196                                 {
1197                                         /* set before the switch */
1198                                         break;
1199                                 }
1200                                 case MP_BUS_MCA: /* MCA pin */
1201                                 {
1202                                         trigger = default_MCA_trigger(idx);
1203                                         break;
1204                                 }
1205                                 default:
1206                                 {
1207                                         printk(KERN_WARNING "broken BIOS!!\n");
1208                                         trigger = 1;
1209                                         break;
1210                                 }
1211                         }
1212 #endif
1213                         break;
1214                 case 1: /* edge */
1215                 {
1216                         trigger = 0;
1217                         break;
1218                 }
1219                 case 2: /* reserved */
1220                 {
1221                         printk(KERN_WARNING "broken BIOS!!\n");
1222                         trigger = 1;
1223                         break;
1224                 }
1225                 case 3: /* level */
1226                 {
1227                         trigger = 1;
1228                         break;
1229                 }
1230                 default: /* invalid */
1231                 {
1232                         printk(KERN_WARNING "broken BIOS!!\n");
1233                         trigger = 0;
1234                         break;
1235                 }
1236         }
1237         return trigger;
1238 }
1239
1240 static inline int irq_polarity(int idx)
1241 {
1242         return MPBIOS_polarity(idx);
1243 }
1244
1245 static inline int irq_trigger(int idx)
1246 {
1247         return MPBIOS_trigger(idx);
1248 }
1249
1250 int (*ioapic_renumber_irq)(int ioapic, int irq);
1251 static int pin_2_irq(int idx, int apic, int pin)
1252 {
1253         int irq, i;
1254         int bus = mp_irqs[idx].srcbus;
1255
1256         /*
1257          * Debugging check, we are in big trouble if this message pops up!
1258          */
1259         if (mp_irqs[idx].dstirq != pin)
1260                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1261
1262         if (test_bit(bus, mp_bus_not_pci)) {
1263                 irq = mp_irqs[idx].srcbusirq;
1264         } else {
1265                 /*
1266                  * PCI IRQs are mapped in order
1267                  */
1268                 i = irq = 0;
1269                 while (i < apic)
1270                         irq += nr_ioapic_registers[i++];
1271                 irq += pin;
1272                 /*
1273                  * For MPS mode, so far only needed by ES7000 platform
1274                  */
1275                 if (ioapic_renumber_irq)
1276                         irq = ioapic_renumber_irq(apic, irq);
1277         }
1278
1279 #ifdef CONFIG_X86_32
1280         /*
1281          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1282          */
1283         if ((pin >= 16) && (pin <= 23)) {
1284                 if (pirq_entries[pin-16] != -1) {
1285                         if (!pirq_entries[pin-16]) {
1286                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1287                                                 "disabling PIRQ%d\n", pin-16);
1288                         } else {
1289                                 irq = pirq_entries[pin-16];
1290                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1291                                                 "using PIRQ%d -> IRQ %d\n",
1292                                                 pin-16, irq);
1293                         }
1294                 }
1295         }
1296 #endif
1297
1298         return irq;
1299 }
1300
1301 void lock_vector_lock(void)
1302 {
1303         /* Used to the online set of cpus does not change
1304          * during assign_irq_vector.
1305          */
1306         spin_lock(&vector_lock);
1307 }
1308
1309 void unlock_vector_lock(void)
1310 {
1311         spin_unlock(&vector_lock);
1312 }
1313
1314 static int
1315 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1316 {
1317         /*
1318          * NOTE! The local APIC isn't very good at handling
1319          * multiple interrupts at the same interrupt level.
1320          * As the interrupt level is determined by taking the
1321          * vector number and shifting that right by 4, we
1322          * want to spread these out a bit so that they don't
1323          * all fall in the same interrupt level.
1324          *
1325          * Also, we've got to be careful not to trash gate
1326          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1327          */
1328         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1329         unsigned int old_vector;
1330         int cpu, err;
1331         cpumask_var_t tmp_mask;
1332
1333         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1334                 return -EBUSY;
1335
1336         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1337                 return -ENOMEM;
1338
1339         old_vector = cfg->vector;
1340         if (old_vector) {
1341                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1342                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1343                 if (!cpumask_empty(tmp_mask)) {
1344                         free_cpumask_var(tmp_mask);
1345                         return 0;
1346                 }
1347         }
1348
1349         /* Only try and allocate irqs on cpus that are present */
1350         err = -ENOSPC;
1351         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1352                 int new_cpu;
1353                 int vector, offset;
1354
1355                 apic->vector_allocation_domain(cpu, tmp_mask);
1356
1357                 vector = current_vector;
1358                 offset = current_offset;
1359 next:
1360                 vector += 8;
1361                 if (vector >= first_system_vector) {
1362                         /* If out of vectors on large boxen, must share them. */
1363                         offset = (offset + 1) % 8;
1364                         vector = FIRST_DEVICE_VECTOR + offset;
1365                 }
1366                 if (unlikely(current_vector == vector))
1367                         continue;
1368
1369                 if (test_bit(vector, used_vectors))
1370                         goto next;
1371
1372                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1373                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1374                                 goto next;
1375                 /* Found one! */
1376                 current_vector = vector;
1377                 current_offset = offset;
1378                 if (old_vector) {
1379                         cfg->move_in_progress = 1;
1380                         cpumask_copy(cfg->old_domain, cfg->domain);
1381                 }
1382                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1383                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1384                 cfg->vector = vector;
1385                 cpumask_copy(cfg->domain, tmp_mask);
1386                 err = 0;
1387                 break;
1388         }
1389         free_cpumask_var(tmp_mask);
1390         return err;
1391 }
1392
1393 static int
1394 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1395 {
1396         int err;
1397         unsigned long flags;
1398
1399         spin_lock_irqsave(&vector_lock, flags);
1400         err = __assign_irq_vector(irq, cfg, mask);
1401         spin_unlock_irqrestore(&vector_lock, flags);
1402         return err;
1403 }
1404
1405 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1406 {
1407         int cpu, vector;
1408
1409         BUG_ON(!cfg->vector);
1410
1411         vector = cfg->vector;
1412         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1413                 per_cpu(vector_irq, cpu)[vector] = -1;
1414
1415         cfg->vector = 0;
1416         cpumask_clear(cfg->domain);
1417
1418         if (likely(!cfg->move_in_progress))
1419                 return;
1420         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1421                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1422                                                                 vector++) {
1423                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1424                                 continue;
1425                         per_cpu(vector_irq, cpu)[vector] = -1;
1426                         break;
1427                 }
1428         }
1429         cfg->move_in_progress = 0;
1430 }
1431
1432 void __setup_vector_irq(int cpu)
1433 {
1434         /* Initialize vector_irq on a new cpu */
1435         /* This function must be called with vector_lock held */
1436         int irq, vector;
1437         struct irq_cfg *cfg;
1438         struct irq_desc *desc;
1439
1440         /* Mark the inuse vectors */
1441         for_each_irq_desc(irq, desc) {
1442                 cfg = desc->chip_data;
1443                 if (!cpumask_test_cpu(cpu, cfg->domain))
1444                         continue;
1445                 vector = cfg->vector;
1446                 per_cpu(vector_irq, cpu)[vector] = irq;
1447         }
1448         /* Mark the free vectors */
1449         for (vector = 0; vector < NR_VECTORS; ++vector) {
1450                 irq = per_cpu(vector_irq, cpu)[vector];
1451                 if (irq < 0)
1452                         continue;
1453
1454                 cfg = irq_cfg(irq);
1455                 if (!cpumask_test_cpu(cpu, cfg->domain))
1456                         per_cpu(vector_irq, cpu)[vector] = -1;
1457         }
1458 }
1459
1460 static struct irq_chip ioapic_chip;
1461 static struct irq_chip ir_ioapic_chip;
1462
1463 #define IOAPIC_AUTO     -1
1464 #define IOAPIC_EDGE     0
1465 #define IOAPIC_LEVEL    1
1466
1467 #ifdef CONFIG_X86_32
1468 static inline int IO_APIC_irq_trigger(int irq)
1469 {
1470         int apic, idx, pin;
1471
1472         for (apic = 0; apic < nr_ioapics; apic++) {
1473                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1474                         idx = find_irq_entry(apic, pin, mp_INT);
1475                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1476                                 return irq_trigger(idx);
1477                 }
1478         }
1479         /*
1480          * nonexistent IRQs are edge default
1481          */
1482         return 0;
1483 }
1484 #else
1485 static inline int IO_APIC_irq_trigger(int irq)
1486 {
1487         return 1;
1488 }
1489 #endif
1490
1491 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1492 {
1493
1494         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1495             trigger == IOAPIC_LEVEL)
1496                 desc->status |= IRQ_LEVEL;
1497         else
1498                 desc->status &= ~IRQ_LEVEL;
1499
1500         if (irq_remapped(irq)) {
1501                 desc->status |= IRQ_MOVE_PCNTXT;
1502                 if (trigger)
1503                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1504                                                       handle_fasteoi_irq,
1505                                                      "fasteoi");
1506                 else
1507                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1508                                                       handle_edge_irq, "edge");
1509                 return;
1510         }
1511
1512         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1513             trigger == IOAPIC_LEVEL)
1514                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1515                                               handle_fasteoi_irq,
1516                                               "fasteoi");
1517         else
1518                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1519                                               handle_edge_irq, "edge");
1520 }
1521
1522 int setup_ioapic_entry(int apic_id, int irq,
1523                        struct IO_APIC_route_entry *entry,
1524                        unsigned int destination, int trigger,
1525                        int polarity, int vector, int pin)
1526 {
1527         /*
1528          * add it to the IO-APIC irq-routing table:
1529          */
1530         memset(entry,0,sizeof(*entry));
1531
1532         if (intr_remapping_enabled) {
1533                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1534                 struct irte irte;
1535                 struct IR_IO_APIC_route_entry *ir_entry =
1536                         (struct IR_IO_APIC_route_entry *) entry;
1537                 int index;
1538
1539                 if (!iommu)
1540                         panic("No mapping iommu for ioapic %d\n", apic_id);
1541
1542                 index = alloc_irte(iommu, irq, 1);
1543                 if (index < 0)
1544                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1545
1546                 memset(&irte, 0, sizeof(irte));
1547
1548                 irte.present = 1;
1549                 irte.dst_mode = apic->irq_dest_mode;
1550                 /*
1551                  * Trigger mode in the IRTE will always be edge, and the
1552                  * actual level or edge trigger will be setup in the IO-APIC
1553                  * RTE. This will help simplify level triggered irq migration.
1554                  * For more details, see the comments above explainig IO-APIC
1555                  * irq migration in the presence of interrupt-remapping.
1556                  */
1557                 irte.trigger_mode = 0;
1558                 irte.dlvry_mode = apic->irq_delivery_mode;
1559                 irte.vector = vector;
1560                 irte.dest_id = IRTE_DEST(destination);
1561
1562                 modify_irte(irq, &irte);
1563
1564                 ir_entry->index2 = (index >> 15) & 0x1;
1565                 ir_entry->zero = 0;
1566                 ir_entry->format = 1;
1567                 ir_entry->index = (index & 0x7fff);
1568                 /*
1569                  * IO-APIC RTE will be configured with virtual vector.
1570                  * irq handler will do the explicit EOI to the io-apic.
1571                  */
1572                 ir_entry->vector = pin;
1573         } else {
1574                 entry->delivery_mode = apic->irq_delivery_mode;
1575                 entry->dest_mode = apic->irq_dest_mode;
1576                 entry->dest = destination;
1577                 entry->vector = vector;
1578         }
1579
1580         entry->mask = 0;                                /* enable IRQ */
1581         entry->trigger = trigger;
1582         entry->polarity = polarity;
1583
1584         /* Mask level triggered irqs.
1585          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1586          */
1587         if (trigger)
1588                 entry->mask = 1;
1589         return 0;
1590 }
1591
1592 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1593                               int trigger, int polarity)
1594 {
1595         struct irq_cfg *cfg;
1596         struct IO_APIC_route_entry entry;
1597         unsigned int dest;
1598
1599         if (!IO_APIC_IRQ(irq))
1600                 return;
1601
1602         cfg = desc->chip_data;
1603
1604         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1605                 return;
1606
1607         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1608
1609         apic_printk(APIC_VERBOSE,KERN_DEBUG
1610                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1611                     "IRQ %d Mode:%i Active:%i)\n",
1612                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1613                     irq, trigger, polarity);
1614
1615
1616         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1617                                dest, trigger, polarity, cfg->vector, pin)) {
1618                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1619                        mp_ioapics[apic_id].apicid, pin);
1620                 __clear_irq_vector(irq, cfg);
1621                 return;
1622         }
1623
1624         ioapic_register_intr(irq, desc, trigger);
1625         if (irq < NR_IRQS_LEGACY)
1626                 disable_8259A_irq(irq);
1627
1628         ioapic_write_entry(apic_id, pin, entry);
1629 }
1630
1631 static void __init setup_IO_APIC_irqs(void)
1632 {
1633         int apic_id, pin, idx, irq;
1634         int notcon = 0;
1635         struct irq_desc *desc;
1636         struct irq_cfg *cfg;
1637         int cpu = boot_cpu_id;
1638
1639         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1640
1641         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1642                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1643
1644                         idx = find_irq_entry(apic_id, pin, mp_INT);
1645                         if (idx == -1) {
1646                                 if (!notcon) {
1647                                         notcon = 1;
1648                                         apic_printk(APIC_VERBOSE,
1649                                                 KERN_DEBUG " %d-%d",
1650                                                 mp_ioapics[apic_id].apicid, pin);
1651                                 } else
1652                                         apic_printk(APIC_VERBOSE, " %d-%d",
1653                                                 mp_ioapics[apic_id].apicid, pin);
1654                                 continue;
1655                         }
1656                         if (notcon) {
1657                                 apic_printk(APIC_VERBOSE,
1658                                         " (apicid-pin) not connected\n");
1659                                 notcon = 0;
1660                         }
1661
1662                         irq = pin_2_irq(idx, apic_id, pin);
1663
1664                         /*
1665                          * Skip the timer IRQ if there's a quirk handler
1666                          * installed and if it returns 1:
1667                          */
1668                         if (apic->multi_timer_check &&
1669                                         apic->multi_timer_check(apic_id, irq))
1670                                 continue;
1671
1672                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1673                         if (!desc) {
1674                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1675                                 continue;
1676                         }
1677                         cfg = desc->chip_data;
1678                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1679
1680                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1681                                         irq_trigger(idx), irq_polarity(idx));
1682                 }
1683         }
1684
1685         if (notcon)
1686                 apic_printk(APIC_VERBOSE,
1687                         " (apicid-pin) not connected\n");
1688 }
1689
1690 /*
1691  * Set up the timer pin, possibly with the 8259A-master behind.
1692  */
1693 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1694                                         int vector)
1695 {
1696         struct IO_APIC_route_entry entry;
1697
1698         if (intr_remapping_enabled)
1699                 return;
1700
1701         memset(&entry, 0, sizeof(entry));
1702
1703         /*
1704          * We use logical delivery to get the timer IRQ
1705          * to the first CPU.
1706          */
1707         entry.dest_mode = apic->irq_dest_mode;
1708         entry.mask = 0;                 /* don't mask IRQ for edge */
1709         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1710         entry.delivery_mode = apic->irq_delivery_mode;
1711         entry.polarity = 0;
1712         entry.trigger = 0;
1713         entry.vector = vector;
1714
1715         /*
1716          * The timer IRQ doesn't have to know that behind the
1717          * scene we may have a 8259A-master in AEOI mode ...
1718          */
1719         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1720
1721         /*
1722          * Add it to the IO-APIC irq-routing table:
1723          */
1724         ioapic_write_entry(apic_id, pin, entry);
1725 }
1726
1727
1728 __apicdebuginit(void) print_IO_APIC(void)
1729 {
1730         int apic, i;
1731         union IO_APIC_reg_00 reg_00;
1732         union IO_APIC_reg_01 reg_01;
1733         union IO_APIC_reg_02 reg_02;
1734         union IO_APIC_reg_03 reg_03;
1735         unsigned long flags;
1736         struct irq_cfg *cfg;
1737         struct irq_desc *desc;
1738         unsigned int irq;
1739
1740         if (apic_verbosity == APIC_QUIET)
1741                 return;
1742
1743         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1744         for (i = 0; i < nr_ioapics; i++)
1745                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1746                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1747
1748         /*
1749          * We are a bit conservative about what we expect.  We have to
1750          * know about every hardware change ASAP.
1751          */
1752         printk(KERN_INFO "testing the IO APIC.......................\n");
1753
1754         for (apic = 0; apic < nr_ioapics; apic++) {
1755
1756         spin_lock_irqsave(&ioapic_lock, flags);
1757         reg_00.raw = io_apic_read(apic, 0);
1758         reg_01.raw = io_apic_read(apic, 1);
1759         if (reg_01.bits.version >= 0x10)
1760                 reg_02.raw = io_apic_read(apic, 2);
1761         if (reg_01.bits.version >= 0x20)
1762                 reg_03.raw = io_apic_read(apic, 3);
1763         spin_unlock_irqrestore(&ioapic_lock, flags);
1764
1765         printk("\n");
1766         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1767         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1768         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1769         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1770         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1771
1772         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1773         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1774
1775         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1776         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1777
1778         /*
1779          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1780          * but the value of reg_02 is read as the previous read register
1781          * value, so ignore it if reg_02 == reg_01.
1782          */
1783         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1784                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1785                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1786         }
1787
1788         /*
1789          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1790          * or reg_03, but the value of reg_0[23] is read as the previous read
1791          * register value, so ignore it if reg_03 == reg_0[12].
1792          */
1793         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1794             reg_03.raw != reg_01.raw) {
1795                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1796                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1797         }
1798
1799         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1800
1801         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1802                           " Stat Dmod Deli Vect:   \n");
1803
1804         for (i = 0; i <= reg_01.bits.entries; i++) {
1805                 struct IO_APIC_route_entry entry;
1806
1807                 entry = ioapic_read_entry(apic, i);
1808
1809                 printk(KERN_DEBUG " %02x %03X ",
1810                         i,
1811                         entry.dest
1812                 );
1813
1814                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1815                         entry.mask,
1816                         entry.trigger,
1817                         entry.irr,
1818                         entry.polarity,
1819                         entry.delivery_status,
1820                         entry.dest_mode,
1821                         entry.delivery_mode,
1822                         entry.vector
1823                 );
1824         }
1825         }
1826         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1827         for_each_irq_desc(irq, desc) {
1828                 struct irq_pin_list *entry;
1829
1830                 cfg = desc->chip_data;
1831                 entry = cfg->irq_2_pin;
1832                 if (!entry)
1833                         continue;
1834                 printk(KERN_DEBUG "IRQ%d ", irq);
1835                 for (;;) {
1836                         printk("-> %d:%d", entry->apic, entry->pin);
1837                         if (!entry->next)
1838                                 break;
1839                         entry = entry->next;
1840                 }
1841                 printk("\n");
1842         }
1843
1844         printk(KERN_INFO ".................................... done.\n");
1845
1846         return;
1847 }
1848
1849 __apicdebuginit(void) print_APIC_bitfield(int base)
1850 {
1851         unsigned int v;
1852         int i, j;
1853
1854         if (apic_verbosity == APIC_QUIET)
1855                 return;
1856
1857         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1858         for (i = 0; i < 8; i++) {
1859                 v = apic_read(base + i*0x10);
1860                 for (j = 0; j < 32; j++) {
1861                         if (v & (1<<j))
1862                                 printk("1");
1863                         else
1864                                 printk("0");
1865                 }
1866                 printk("\n");
1867         }
1868 }
1869
1870 __apicdebuginit(void) print_local_APIC(void *dummy)
1871 {
1872         unsigned int v, ver, maxlvt;
1873         u64 icr;
1874
1875         if (apic_verbosity == APIC_QUIET)
1876                 return;
1877
1878         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1879                 smp_processor_id(), hard_smp_processor_id());
1880         v = apic_read(APIC_ID);
1881         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1882         v = apic_read(APIC_LVR);
1883         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1884         ver = GET_APIC_VERSION(v);
1885         maxlvt = lapic_get_maxlvt();
1886
1887         v = apic_read(APIC_TASKPRI);
1888         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1889
1890         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1891                 if (!APIC_XAPIC(ver)) {
1892                         v = apic_read(APIC_ARBPRI);
1893                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1894                                v & APIC_ARBPRI_MASK);
1895                 }
1896                 v = apic_read(APIC_PROCPRI);
1897                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1898         }
1899
1900         /*
1901          * Remote read supported only in the 82489DX and local APIC for
1902          * Pentium processors.
1903          */
1904         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1905                 v = apic_read(APIC_RRR);
1906                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1907         }
1908
1909         v = apic_read(APIC_LDR);
1910         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1911         if (!x2apic_enabled()) {
1912                 v = apic_read(APIC_DFR);
1913                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1914         }
1915         v = apic_read(APIC_SPIV);
1916         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1917
1918         printk(KERN_DEBUG "... APIC ISR field:\n");
1919         print_APIC_bitfield(APIC_ISR);
1920         printk(KERN_DEBUG "... APIC TMR field:\n");
1921         print_APIC_bitfield(APIC_TMR);
1922         printk(KERN_DEBUG "... APIC IRR field:\n");
1923         print_APIC_bitfield(APIC_IRR);
1924
1925         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1926                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1927                         apic_write(APIC_ESR, 0);
1928
1929                 v = apic_read(APIC_ESR);
1930                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1931         }
1932
1933         icr = apic_icr_read();
1934         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1935         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1936
1937         v = apic_read(APIC_LVTT);
1938         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1939
1940         if (maxlvt > 3) {                       /* PC is LVT#4. */
1941                 v = apic_read(APIC_LVTPC);
1942                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1943         }
1944         v = apic_read(APIC_LVT0);
1945         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1946         v = apic_read(APIC_LVT1);
1947         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1948
1949         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1950                 v = apic_read(APIC_LVTERR);
1951                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1952         }
1953
1954         v = apic_read(APIC_TMICT);
1955         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1956         v = apic_read(APIC_TMCCT);
1957         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1958         v = apic_read(APIC_TDCR);
1959         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1960         printk("\n");
1961 }
1962
1963 __apicdebuginit(void) print_all_local_APICs(void)
1964 {
1965         int cpu;
1966
1967         preempt_disable();
1968         for_each_online_cpu(cpu)
1969                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1970         preempt_enable();
1971 }
1972
1973 __apicdebuginit(void) print_PIC(void)
1974 {
1975         unsigned int v;
1976         unsigned long flags;
1977
1978         if (apic_verbosity == APIC_QUIET)
1979                 return;
1980
1981         printk(KERN_DEBUG "\nprinting PIC contents\n");
1982
1983         spin_lock_irqsave(&i8259A_lock, flags);
1984
1985         v = inb(0xa1) << 8 | inb(0x21);
1986         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1987
1988         v = inb(0xa0) << 8 | inb(0x20);
1989         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1990
1991         outb(0x0b,0xa0);
1992         outb(0x0b,0x20);
1993         v = inb(0xa0) << 8 | inb(0x20);
1994         outb(0x0a,0xa0);
1995         outb(0x0a,0x20);
1996
1997         spin_unlock_irqrestore(&i8259A_lock, flags);
1998
1999         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
2000
2001         v = inb(0x4d1) << 8 | inb(0x4d0);
2002         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
2003 }
2004
2005 __apicdebuginit(int) print_all_ICs(void)
2006 {
2007         print_PIC();
2008         print_all_local_APICs();
2009         print_IO_APIC();
2010
2011         return 0;
2012 }
2013
2014 fs_initcall(print_all_ICs);
2015
2016
2017 /* Where if anywhere is the i8259 connect in external int mode */
2018 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
2019
2020 void __init enable_IO_APIC(void)
2021 {
2022         union IO_APIC_reg_01 reg_01;
2023         int i8259_apic, i8259_pin;
2024         int apic;
2025         unsigned long flags;
2026
2027         /*
2028          * The number of IO-APIC IRQ registers (== #pins):
2029          */
2030         for (apic = 0; apic < nr_ioapics; apic++) {
2031                 spin_lock_irqsave(&ioapic_lock, flags);
2032                 reg_01.raw = io_apic_read(apic, 1);
2033                 spin_unlock_irqrestore(&ioapic_lock, flags);
2034                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2035         }
2036         for(apic = 0; apic < nr_ioapics; apic++) {
2037                 int pin;
2038                 /* See if any of the pins is in ExtINT mode */
2039                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2040                         struct IO_APIC_route_entry entry;
2041                         entry = ioapic_read_entry(apic, pin);
2042
2043                         /* If the interrupt line is enabled and in ExtInt mode
2044                          * I have found the pin where the i8259 is connected.
2045                          */
2046                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2047                                 ioapic_i8259.apic = apic;
2048                                 ioapic_i8259.pin  = pin;
2049                                 goto found_i8259;
2050                         }
2051                 }
2052         }
2053  found_i8259:
2054         /* Look to see what if the MP table has reported the ExtINT */
2055         /* If we could not find the appropriate pin by looking at the ioapic
2056          * the i8259 probably is not connected the ioapic but give the
2057          * mptable a chance anyway.
2058          */
2059         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2060         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2061         /* Trust the MP table if nothing is setup in the hardware */
2062         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2063                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2064                 ioapic_i8259.pin  = i8259_pin;
2065                 ioapic_i8259.apic = i8259_apic;
2066         }
2067         /* Complain if the MP table and the hardware disagree */
2068         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2069                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2070         {
2071                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2072         }
2073
2074         /*
2075          * Do not trust the IO-APIC being empty at bootup
2076          */
2077         clear_IO_APIC();
2078 }
2079
2080 /*
2081  * Not an __init, needed by the reboot code
2082  */
2083 void disable_IO_APIC(void)
2084 {
2085         /*
2086          * Clear the IO-APIC before rebooting:
2087          */
2088         clear_IO_APIC();
2089
2090         /*
2091          * If the i8259 is routed through an IOAPIC
2092          * Put that IOAPIC in virtual wire mode
2093          * so legacy interrupts can be delivered.
2094          *
2095          * With interrupt-remapping, for now we will use virtual wire A mode,
2096          * as virtual wire B is little complex (need to configure both
2097          * IOAPIC RTE aswell as interrupt-remapping table entry).
2098          * As this gets called during crash dump, keep this simple for now.
2099          */
2100         if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2101                 struct IO_APIC_route_entry entry;
2102
2103                 memset(&entry, 0, sizeof(entry));
2104                 entry.mask            = 0; /* Enabled */
2105                 entry.trigger         = 0; /* Edge */
2106                 entry.irr             = 0;
2107                 entry.polarity        = 0; /* High */
2108                 entry.delivery_status = 0;
2109                 entry.dest_mode       = 0; /* Physical */
2110                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2111                 entry.vector          = 0;
2112                 entry.dest            = read_apic_id();
2113
2114                 /*
2115                  * Add it to the IO-APIC irq-routing table:
2116                  */
2117                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2118         }
2119
2120         /*
2121          * Use virtual wire A mode when interrupt remapping is enabled.
2122          */
2123         disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2124 }
2125
2126 #ifdef CONFIG_X86_32
2127 /*
2128  * function to set the IO-APIC physical IDs based on the
2129  * values stored in the MPC table.
2130  *
2131  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2132  */
2133
2134 static void __init setup_ioapic_ids_from_mpc(void)
2135 {
2136         union IO_APIC_reg_00 reg_00;
2137         physid_mask_t phys_id_present_map;
2138         int apic_id;
2139         int i;
2140         unsigned char old_id;
2141         unsigned long flags;
2142
2143         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2144                 return;
2145
2146         /*
2147          * Don't check I/O APIC IDs for xAPIC systems.  They have
2148          * no meaning without the serial APIC bus.
2149          */
2150         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2151                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2152                 return;
2153         /*
2154          * This is broken; anything with a real cpu count has to
2155          * circumvent this idiocy regardless.
2156          */
2157         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2158
2159         /*
2160          * Set the IOAPIC ID to the value stored in the MPC table.
2161          */
2162         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2163
2164                 /* Read the register 0 value */
2165                 spin_lock_irqsave(&ioapic_lock, flags);
2166                 reg_00.raw = io_apic_read(apic_id, 0);
2167                 spin_unlock_irqrestore(&ioapic_lock, flags);
2168
2169                 old_id = mp_ioapics[apic_id].apicid;
2170
2171                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2172                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2173                                 apic_id, mp_ioapics[apic_id].apicid);
2174                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2175                                 reg_00.bits.ID);
2176                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2177                 }
2178
2179                 /*
2180                  * Sanity check, is the ID really free? Every APIC in a
2181                  * system must have a unique ID or we get lots of nice
2182                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2183                  */
2184                 if (apic->check_apicid_used(phys_id_present_map,
2185                                         mp_ioapics[apic_id].apicid)) {
2186                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2187                                 apic_id, mp_ioapics[apic_id].apicid);
2188                         for (i = 0; i < get_physical_broadcast(); i++)
2189                                 if (!physid_isset(i, phys_id_present_map))
2190                                         break;
2191                         if (i >= get_physical_broadcast())
2192                                 panic("Max APIC ID exceeded!\n");
2193                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2194                                 i);
2195                         physid_set(i, phys_id_present_map);
2196                         mp_ioapics[apic_id].apicid = i;
2197                 } else {
2198                         physid_mask_t tmp;
2199                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2200                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2201                                         "phys_id_present_map\n",
2202                                         mp_ioapics[apic_id].apicid);
2203                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2204                 }
2205
2206
2207                 /*
2208                  * We need to adjust the IRQ routing table
2209                  * if the ID changed.
2210                  */
2211                 if (old_id != mp_ioapics[apic_id].apicid)
2212                         for (i = 0; i < mp_irq_entries; i++)
2213                                 if (mp_irqs[i].dstapic == old_id)
2214                                         mp_irqs[i].dstapic
2215                                                 = mp_ioapics[apic_id].apicid;
2216
2217                 /*
2218                  * Read the right value from the MPC table and
2219                  * write it into the ID register.
2220                  */
2221                 apic_printk(APIC_VERBOSE, KERN_INFO
2222                         "...changing IO-APIC physical APIC ID to %d ...",
2223                         mp_ioapics[apic_id].apicid);
2224
2225                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2226                 spin_lock_irqsave(&ioapic_lock, flags);
2227                 io_apic_write(apic_id, 0, reg_00.raw);
2228                 spin_unlock_irqrestore(&ioapic_lock, flags);
2229
2230                 /*
2231                  * Sanity check
2232                  */
2233                 spin_lock_irqsave(&ioapic_lock, flags);
2234                 reg_00.raw = io_apic_read(apic_id, 0);
2235                 spin_unlock_irqrestore(&ioapic_lock, flags);
2236                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2237                         printk("could not set ID!\n");
2238                 else
2239                         apic_printk(APIC_VERBOSE, " ok.\n");
2240         }
2241 }
2242 #endif
2243
2244 int no_timer_check __initdata;
2245
2246 static int __init notimercheck(char *s)
2247 {
2248         no_timer_check = 1;
2249         return 1;
2250 }
2251 __setup("no_timer_check", notimercheck);
2252
2253 /*
2254  * There is a nasty bug in some older SMP boards, their mptable lies
2255  * about the timer IRQ. We do the following to work around the situation:
2256  *
2257  *      - timer IRQ defaults to IO-APIC IRQ
2258  *      - if this function detects that timer IRQs are defunct, then we fall
2259  *        back to ISA timer IRQs
2260  */
2261 static int __init timer_irq_works(void)
2262 {
2263         unsigned long t1 = jiffies;
2264         unsigned long flags;
2265
2266         if (no_timer_check)
2267                 return 1;
2268
2269         local_save_flags(flags);
2270         local_irq_enable();
2271         /* Let ten ticks pass... */
2272         mdelay((10 * 1000) / HZ);
2273         local_irq_restore(flags);
2274
2275         /*
2276          * Expect a few ticks at least, to be sure some possible
2277          * glue logic does not lock up after one or two first
2278          * ticks in a non-ExtINT mode.  Also the local APIC
2279          * might have cached one ExtINT interrupt.  Finally, at
2280          * least one tick may be lost due to delays.
2281          */
2282
2283         /* jiffies wrap? */
2284         if (time_after(jiffies, t1 + 4))
2285                 return 1;
2286         return 0;
2287 }
2288
2289 /*
2290  * In the SMP+IOAPIC case it might happen that there are an unspecified
2291  * number of pending IRQ events unhandled. These cases are very rare,
2292  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2293  * better to do it this way as thus we do not have to be aware of
2294  * 'pending' interrupts in the IRQ path, except at this point.
2295  */
2296 /*
2297  * Edge triggered needs to resend any interrupt
2298  * that was delayed but this is now handled in the device
2299  * independent code.
2300  */
2301
2302 /*
2303  * Starting up a edge-triggered IO-APIC interrupt is
2304  * nasty - we need to make sure that we get the edge.
2305  * If it is already asserted for some reason, we need
2306  * return 1 to indicate that is was pending.
2307  *
2308  * This is not complete - we should be able to fake
2309  * an edge even if it isn't on the 8259A...
2310  */
2311
2312 static unsigned int startup_ioapic_irq(unsigned int irq)
2313 {
2314         int was_pending = 0;
2315         unsigned long flags;
2316         struct irq_cfg *cfg;
2317
2318         spin_lock_irqsave(&ioapic_lock, flags);
2319         if (irq < NR_IRQS_LEGACY) {
2320                 disable_8259A_irq(irq);
2321                 if (i8259A_irq_pending(irq))
2322                         was_pending = 1;
2323         }
2324         cfg = irq_cfg(irq);
2325         __unmask_IO_APIC_irq(cfg);
2326         spin_unlock_irqrestore(&ioapic_lock, flags);
2327
2328         return was_pending;
2329 }
2330
2331 #ifdef CONFIG_X86_64
2332 static int ioapic_retrigger_irq(unsigned int irq)
2333 {
2334
2335         struct irq_cfg *cfg = irq_cfg(irq);
2336         unsigned long flags;
2337
2338         spin_lock_irqsave(&vector_lock, flags);
2339         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2340         spin_unlock_irqrestore(&vector_lock, flags);
2341
2342         return 1;
2343 }
2344 #else
2345 static int ioapic_retrigger_irq(unsigned int irq)
2346 {
2347         apic->send_IPI_self(irq_cfg(irq)->vector);
2348
2349         return 1;
2350 }
2351 #endif
2352
2353 /*
2354  * Level and edge triggered IO-APIC interrupts need different handling,
2355  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2356  * handled with the level-triggered descriptor, but that one has slightly
2357  * more overhead. Level-triggered interrupts cannot be handled with the
2358  * edge-triggered handler, without risking IRQ storms and other ugly
2359  * races.
2360  */
2361
2362 #ifdef CONFIG_SMP
2363
2364 #ifdef CONFIG_INTR_REMAP
2365
2366 /*
2367  * Migrate the IO-APIC irq in the presence of intr-remapping.
2368  *
2369  * For both level and edge triggered, irq migration is a simple atomic
2370  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2371  *
2372  * For level triggered, we eliminate the io-apic RTE modification (with the
2373  * updated vector information), by using a virtual vector (io-apic pin number).
2374  * Real vector that is used for interrupting cpu will be coming from
2375  * the interrupt-remapping table entry.
2376  */
2377 static void
2378 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2379 {
2380         struct irq_cfg *cfg;
2381         struct irte irte;
2382         unsigned int dest;
2383         unsigned int irq;
2384
2385         if (!cpumask_intersects(mask, cpu_online_mask))
2386                 return;
2387
2388         irq = desc->irq;
2389         if (get_irte(irq, &irte))
2390                 return;
2391
2392         cfg = desc->chip_data;
2393         if (assign_irq_vector(irq, cfg, mask))
2394                 return;
2395
2396         set_extra_move_desc(desc, mask);
2397
2398         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2399
2400         irte.vector = cfg->vector;
2401         irte.dest_id = IRTE_DEST(dest);
2402
2403         /*
2404          * Modified the IRTE and flushes the Interrupt entry cache.
2405          */
2406         modify_irte(irq, &irte);
2407
2408         if (cfg->move_in_progress)
2409                 send_cleanup_vector(cfg);
2410
2411         cpumask_copy(desc->affinity, mask);
2412 }
2413
2414 /*
2415  * Migrates the IRQ destination in the process context.
2416  */
2417 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2418                                             const struct cpumask *mask)
2419 {
2420         migrate_ioapic_irq_desc(desc, mask);
2421 }
2422 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2423                                        const struct cpumask *mask)
2424 {
2425         struct irq_desc *desc = irq_to_desc(irq);
2426
2427         set_ir_ioapic_affinity_irq_desc(desc, mask);
2428 }
2429 #else
2430 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2431                                                    const struct cpumask *mask)
2432 {
2433 }
2434 #endif
2435
2436 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2437 {
2438         unsigned vector, me;
2439
2440         ack_APIC_irq();
2441         exit_idle();
2442         irq_enter();
2443
2444         me = smp_processor_id();
2445         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2446                 unsigned int irq;
2447                 unsigned int irr;
2448                 struct irq_desc *desc;
2449                 struct irq_cfg *cfg;
2450                 irq = __get_cpu_var(vector_irq)[vector];
2451
2452                 if (irq == -1)
2453                         continue;
2454
2455                 desc = irq_to_desc(irq);
2456                 if (!desc)
2457                         continue;
2458
2459                 cfg = irq_cfg(irq);
2460                 spin_lock(&desc->lock);
2461                 if (!cfg->move_cleanup_count)
2462                         goto unlock;
2463
2464                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2465                         goto unlock;
2466
2467                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2468                 /*
2469                  * Check if the vector that needs to be cleanedup is
2470                  * registered at the cpu's IRR. If so, then this is not
2471                  * the best time to clean it up. Lets clean it up in the
2472                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2473                  * to myself.
2474                  */
2475                 if (irr  & (1 << (vector % 32))) {
2476                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2477                         goto unlock;
2478                 }
2479                 __get_cpu_var(vector_irq)[vector] = -1;
2480                 cfg->move_cleanup_count--;
2481 unlock:
2482                 spin_unlock(&desc->lock);
2483         }
2484
2485         irq_exit();
2486 }
2487
2488 static void irq_complete_move(struct irq_desc **descp)
2489 {
2490         struct irq_desc *desc = *descp;
2491         struct irq_cfg *cfg = desc->chip_data;
2492         unsigned vector, me;
2493
2494         if (likely(!cfg->move_in_progress)) {
2495 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2496                 if (likely(!cfg->move_desc_pending))
2497                         return;
2498
2499                 /* domain has not changed, but affinity did */
2500                 me = smp_processor_id();
2501                 if (cpumask_test_cpu(me, desc->affinity)) {
2502                         *descp = desc = move_irq_desc(desc, me);
2503                         /* get the new one */
2504                         cfg = desc->chip_data;
2505                         cfg->move_desc_pending = 0;
2506                 }
2507 #endif
2508                 return;
2509         }
2510
2511         vector = ~get_irq_regs()->orig_ax;
2512         me = smp_processor_id();
2513
2514         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2515 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2516                 *descp = desc = move_irq_desc(desc, me);
2517                 /* get the new one */
2518                 cfg = desc->chip_data;
2519 #endif
2520                 send_cleanup_vector(cfg);
2521         }
2522 }
2523 #else
2524 static inline void irq_complete_move(struct irq_desc **descp) {}
2525 #endif
2526
2527 #ifdef CONFIG_X86_X2APIC
2528 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2529 {
2530         int apic, pin;
2531         struct irq_pin_list *entry;
2532
2533         entry = cfg->irq_2_pin;
2534         for (;;) {
2535
2536                 if (!entry)
2537                         break;
2538
2539                 apic = entry->apic;
2540                 pin = entry->pin;
2541                 io_apic_eoi(apic, pin);
2542                 entry = entry->next;
2543         }
2544 }
2545
2546 static void
2547 eoi_ioapic_irq(struct irq_desc *desc)
2548 {
2549         struct irq_cfg *cfg;
2550         unsigned long flags;
2551         unsigned int irq;
2552
2553         irq = desc->irq;
2554         cfg = desc->chip_data;
2555
2556         spin_lock_irqsave(&ioapic_lock, flags);
2557         __eoi_ioapic_irq(irq, cfg);
2558         spin_unlock_irqrestore(&ioapic_lock, flags);
2559 }
2560
2561 static void ack_x2apic_level(unsigned int irq)
2562 {
2563         struct irq_desc *desc = irq_to_desc(irq);
2564         ack_x2APIC_irq();
2565         eoi_ioapic_irq(desc);
2566 }
2567
2568 static void ack_x2apic_edge(unsigned int irq)
2569 {
2570         ack_x2APIC_irq();
2571 }
2572 #endif
2573
2574 static void ack_apic_edge(unsigned int irq)
2575 {
2576         struct irq_desc *desc = irq_to_desc(irq);
2577
2578         irq_complete_move(&desc);
2579         move_native_irq(irq);
2580         ack_APIC_irq();
2581 }
2582
2583 atomic_t irq_mis_count;
2584
2585 static void ack_apic_level(unsigned int irq)
2586 {
2587         struct irq_desc *desc = irq_to_desc(irq);
2588
2589 #ifdef CONFIG_X86_32
2590         unsigned long v;
2591         int i;
2592 #endif
2593         struct irq_cfg *cfg;
2594         int do_unmask_irq = 0;
2595
2596         irq_complete_move(&desc);
2597 #ifdef CONFIG_GENERIC_PENDING_IRQ
2598         /* If we are moving the irq we need to mask it */
2599         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2600                 do_unmask_irq = 1;
2601                 mask_IO_APIC_irq_desc(desc);
2602         }
2603 #endif
2604
2605 #ifdef CONFIG_X86_32
2606         /*
2607         * It appears there is an erratum which affects at least version 0x11
2608         * of I/O APIC (that's the 82093AA and cores integrated into various
2609         * chipsets).  Under certain conditions a level-triggered interrupt is
2610         * erroneously delivered as edge-triggered one but the respective IRR
2611         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2612         * message but it will never arrive and further interrupts are blocked
2613         * from the source.  The exact reason is so far unknown, but the
2614         * phenomenon was observed when two consecutive interrupt requests
2615         * from a given source get delivered to the same CPU and the source is
2616         * temporarily disabled in between.
2617         *
2618         * A workaround is to simulate an EOI message manually.  We achieve it
2619         * by setting the trigger mode to edge and then to level when the edge
2620         * trigger mode gets detected in the TMR of a local APIC for a
2621         * level-triggered interrupt.  We mask the source for the time of the
2622         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2623         * The idea is from Manfred Spraul.  --macro
2624         */
2625         cfg = desc->chip_data;
2626         i = cfg->vector;
2627
2628         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2629 #endif
2630
2631         /*
2632          * We must acknowledge the irq before we move it or the acknowledge will
2633          * not propagate properly.
2634          */
2635         ack_APIC_irq();
2636
2637         /* Now we can move and renable the irq */
2638         if (unlikely(do_unmask_irq)) {
2639                 /* Only migrate the irq if the ack has been received.
2640                  *
2641                  * On rare occasions the broadcast level triggered ack gets
2642                  * delayed going to ioapics, and if we reprogram the
2643                  * vector while Remote IRR is still set the irq will never
2644                  * fire again.
2645                  *
2646                  * To prevent this scenario we read the Remote IRR bit
2647                  * of the ioapic.  This has two effects.
2648                  * - On any sane system the read of the ioapic will
2649                  *   flush writes (and acks) going to the ioapic from
2650                  *   this cpu.
2651                  * - We get to see if the ACK has actually been delivered.
2652                  *
2653                  * Based on failed experiments of reprogramming the
2654                  * ioapic entry from outside of irq context starting
2655                  * with masking the ioapic entry and then polling until
2656                  * Remote IRR was clear before reprogramming the
2657                  * ioapic I don't trust the Remote IRR bit to be
2658                  * completey accurate.
2659                  *
2660                  * However there appears to be no other way to plug
2661                  * this race, so if the Remote IRR bit is not
2662                  * accurate and is causing problems then it is a hardware bug
2663                  * and you can go talk to the chipset vendor about it.
2664                  */
2665                 cfg = desc->chip_data;
2666                 if (!io_apic_level_ack_pending(cfg))
2667                         move_masked_irq(irq);
2668                 unmask_IO_APIC_irq_desc(desc);
2669         }
2670
2671 #ifdef CONFIG_X86_32
2672         if (!(v & (1 << (i & 0x1f)))) {
2673                 atomic_inc(&irq_mis_count);
2674                 spin_lock(&ioapic_lock);
2675                 __mask_and_edge_IO_APIC_irq(cfg);
2676                 __unmask_and_level_IO_APIC_irq(cfg);
2677                 spin_unlock(&ioapic_lock);
2678         }
2679 #endif
2680 }
2681
2682 #ifdef CONFIG_INTR_REMAP
2683 static void ir_ack_apic_edge(unsigned int irq)
2684 {
2685 #ifdef CONFIG_X86_X2APIC
2686        if (x2apic_enabled())
2687                return ack_x2apic_edge(irq);
2688 #endif
2689        return ack_apic_edge(irq);
2690 }
2691
2692 static void ir_ack_apic_level(unsigned int irq)
2693 {
2694 #ifdef CONFIG_X86_X2APIC
2695        if (x2apic_enabled())
2696                return ack_x2apic_level(irq);
2697 #endif
2698        return ack_apic_level(irq);
2699 }
2700 #endif /* CONFIG_INTR_REMAP */
2701
2702 static struct irq_chip ioapic_chip __read_mostly = {
2703         .name           = "IO-APIC",
2704         .startup        = startup_ioapic_irq,
2705         .mask           = mask_IO_APIC_irq,
2706         .unmask         = unmask_IO_APIC_irq,
2707         .ack            = ack_apic_edge,
2708         .eoi            = ack_apic_level,
2709 #ifdef CONFIG_SMP
2710         .set_affinity   = set_ioapic_affinity_irq,
2711 #endif
2712         .retrigger      = ioapic_retrigger_irq,
2713 };
2714
2715 static struct irq_chip ir_ioapic_chip __read_mostly = {
2716         .name           = "IR-IO-APIC",
2717         .startup        = startup_ioapic_irq,
2718         .mask           = mask_IO_APIC_irq,
2719         .unmask         = unmask_IO_APIC_irq,
2720 #ifdef CONFIG_INTR_REMAP
2721         .ack            = ir_ack_apic_edge,
2722         .eoi            = ir_ack_apic_level,
2723 #ifdef CONFIG_SMP
2724         .set_affinity   = set_ir_ioapic_affinity_irq,
2725 #endif
2726 #endif
2727         .retrigger      = ioapic_retrigger_irq,
2728 };
2729
2730 static inline void init_IO_APIC_traps(void)
2731 {
2732         int irq;
2733         struct irq_desc *desc;
2734         struct irq_cfg *cfg;
2735
2736         /*
2737          * NOTE! The local APIC isn't very good at handling
2738          * multiple interrupts at the same interrupt level.
2739          * As the interrupt level is determined by taking the
2740          * vector number and shifting that right by 4, we
2741          * want to spread these out a bit so that they don't
2742          * all fall in the same interrupt level.
2743          *
2744          * Also, we've got to be careful not to trash gate
2745          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2746          */
2747         for_each_irq_desc(irq, desc) {
2748                 cfg = desc->chip_data;
2749                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2750                         /*
2751                          * Hmm.. We don't have an entry for this,
2752                          * so default to an old-fashioned 8259
2753                          * interrupt if we can..
2754                          */
2755                         if (irq < NR_IRQS_LEGACY)
2756                                 make_8259A_irq(irq);
2757                         else
2758                                 /* Strange. Oh, well.. */
2759                                 desc->chip = &no_irq_chip;
2760                 }
2761         }
2762 }
2763
2764 /*
2765  * The local APIC irq-chip implementation:
2766  */
2767
2768 static void mask_lapic_irq(unsigned int irq)
2769 {
2770         unsigned long v;
2771
2772         v = apic_read(APIC_LVT0);
2773         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2774 }
2775
2776 static void unmask_lapic_irq(unsigned int irq)
2777 {
2778         unsigned long v;
2779
2780         v = apic_read(APIC_LVT0);
2781         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2782 }
2783
2784 static void ack_lapic_irq(unsigned int irq)
2785 {
2786         ack_APIC_irq();
2787 }
2788
2789 static struct irq_chip lapic_chip __read_mostly = {
2790         .name           = "local-APIC",
2791         .mask           = mask_lapic_irq,
2792         .unmask         = unmask_lapic_irq,
2793         .ack            = ack_lapic_irq,
2794 };
2795
2796 static void lapic_register_intr(int irq, struct irq_desc *desc)
2797 {
2798         desc->status &= ~IRQ_LEVEL;
2799         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2800                                       "edge");
2801 }
2802
2803 static void __init setup_nmi(void)
2804 {
2805         /*
2806          * Dirty trick to enable the NMI watchdog ...
2807          * We put the 8259A master into AEOI mode and
2808          * unmask on all local APICs LVT0 as NMI.
2809          *
2810          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2811          * is from Maciej W. Rozycki - so we do not have to EOI from
2812          * the NMI handler or the timer interrupt.
2813          */
2814         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2815
2816         enable_NMI_through_LVT0();
2817
2818         apic_printk(APIC_VERBOSE, " done.\n");
2819 }
2820
2821 /*
2822  * This looks a bit hackish but it's about the only one way of sending
2823  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2824  * not support the ExtINT mode, unfortunately.  We need to send these
2825  * cycles as some i82489DX-based boards have glue logic that keeps the
2826  * 8259A interrupt line asserted until INTA.  --macro
2827  */
2828 static inline void __init unlock_ExtINT_logic(void)
2829 {
2830         int apic, pin, i;
2831         struct IO_APIC_route_entry entry0, entry1;
2832         unsigned char save_control, save_freq_select;
2833
2834         pin  = find_isa_irq_pin(8, mp_INT);
2835         if (pin == -1) {
2836                 WARN_ON_ONCE(1);
2837                 return;
2838         }
2839         apic = find_isa_irq_apic(8, mp_INT);
2840         if (apic == -1) {
2841                 WARN_ON_ONCE(1);
2842                 return;
2843         }
2844
2845         entry0 = ioapic_read_entry(apic, pin);
2846         clear_IO_APIC_pin(apic, pin);
2847
2848         memset(&entry1, 0, sizeof(entry1));
2849
2850         entry1.dest_mode = 0;                   /* physical delivery */
2851         entry1.mask = 0;                        /* unmask IRQ now */
2852         entry1.dest = hard_smp_processor_id();
2853         entry1.delivery_mode = dest_ExtINT;
2854         entry1.polarity = entry0.polarity;
2855         entry1.trigger = 0;
2856         entry1.vector = 0;
2857
2858         ioapic_write_entry(apic, pin, entry1);
2859
2860         save_control = CMOS_READ(RTC_CONTROL);
2861         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2862         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2863                    RTC_FREQ_SELECT);
2864         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2865
2866         i = 100;
2867         while (i-- > 0) {
2868                 mdelay(10);
2869                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2870                         i -= 10;
2871         }
2872
2873         CMOS_WRITE(save_control, RTC_CONTROL);
2874         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2875         clear_IO_APIC_pin(apic, pin);
2876
2877         ioapic_write_entry(apic, pin, entry0);
2878 }
2879
2880 static int disable_timer_pin_1 __initdata;
2881 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2882 static int __init disable_timer_pin_setup(char *arg)
2883 {
2884         disable_timer_pin_1 = 1;
2885         return 0;
2886 }
2887 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2888
2889 int timer_through_8259 __initdata;
2890
2891 /*
2892  * This code may look a bit paranoid, but it's supposed to cooperate with
2893  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2894  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2895  * fanatically on his truly buggy board.
2896  *
2897  * FIXME: really need to revamp this for all platforms.
2898  */
2899 static inline void __init check_timer(void)
2900 {
2901         struct irq_desc *desc = irq_to_desc(0);
2902         struct irq_cfg *cfg = desc->chip_data;
2903         int cpu = boot_cpu_id;
2904         int apic1, pin1, apic2, pin2;
2905         unsigned long flags;
2906         int no_pin1 = 0;
2907
2908         local_irq_save(flags);
2909
2910         /*
2911          * get/set the timer IRQ vector:
2912          */
2913         disable_8259A_irq(0);
2914         assign_irq_vector(0, cfg, apic->target_cpus());
2915
2916         /*
2917          * As IRQ0 is to be enabled in the 8259A, the virtual
2918          * wire has to be disabled in the local APIC.  Also
2919          * timer interrupts need to be acknowledged manually in
2920          * the 8259A for the i82489DX when using the NMI
2921          * watchdog as that APIC treats NMIs as level-triggered.
2922          * The AEOI mode will finish them in the 8259A
2923          * automatically.
2924          */
2925         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2926         init_8259A(1);
2927 #ifdef CONFIG_X86_32
2928         {
2929                 unsigned int ver;
2930
2931                 ver = apic_read(APIC_LVR);
2932                 ver = GET_APIC_VERSION(ver);
2933                 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2934         }
2935 #endif
2936
2937         pin1  = find_isa_irq_pin(0, mp_INT);
2938         apic1 = find_isa_irq_apic(0, mp_INT);
2939         pin2  = ioapic_i8259.pin;
2940         apic2 = ioapic_i8259.apic;
2941
2942         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2943                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2944                     cfg->vector, apic1, pin1, apic2, pin2);
2945
2946         /*
2947          * Some BIOS writers are clueless and report the ExtINTA
2948          * I/O APIC input from the cascaded 8259A as the timer
2949          * interrupt input.  So just in case, if only one pin
2950          * was found above, try it both directly and through the
2951          * 8259A.
2952          */
2953         if (pin1 == -1) {
2954                 if (intr_remapping_enabled)
2955                         panic("BIOS bug: timer not connected to IO-APIC");
2956                 pin1 = pin2;
2957                 apic1 = apic2;
2958                 no_pin1 = 1;
2959         } else if (pin2 == -1) {
2960                 pin2 = pin1;
2961                 apic2 = apic1;
2962         }
2963
2964         if (pin1 != -1) {
2965                 /*
2966                  * Ok, does IRQ0 through the IOAPIC work?
2967                  */
2968                 if (no_pin1) {
2969                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2970                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2971                 } else {
2972                         /* for edge trigger, setup_IO_APIC_irq already
2973                          * leave it unmasked.
2974                          * so only need to unmask if it is level-trigger
2975                          * do we really have level trigger timer?
2976                          */
2977                         int idx;
2978                         idx = find_irq_entry(apic1, pin1, mp_INT);
2979                         if (idx != -1 && irq_trigger(idx))
2980                                 unmask_IO_APIC_irq_desc(desc);
2981                 }
2982                 if (timer_irq_works()) {
2983                         if (nmi_watchdog == NMI_IO_APIC) {
2984                                 setup_nmi();
2985                                 enable_8259A_irq(0);
2986                         }
2987                         if (disable_timer_pin_1 > 0)
2988                                 clear_IO_APIC_pin(0, pin1);
2989                         goto out;
2990                 }
2991                 if (intr_remapping_enabled)
2992                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2993                 local_irq_disable();
2994                 clear_IO_APIC_pin(apic1, pin1);
2995                 if (!no_pin1)
2996                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2997                                     "8254 timer not connected to IO-APIC\n");
2998
2999                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3000                             "(IRQ0) through the 8259A ...\n");
3001                 apic_printk(APIC_QUIET, KERN_INFO
3002                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
3003                 /*
3004                  * legacy devices should be connected to IO APIC #0
3005                  */
3006                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
3007                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3008                 enable_8259A_irq(0);
3009                 if (timer_irq_works()) {
3010                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3011                         timer_through_8259 = 1;
3012                         if (nmi_watchdog == NMI_IO_APIC) {
3013                                 disable_8259A_irq(0);
3014                                 setup_nmi();
3015                                 enable_8259A_irq(0);
3016                         }
3017                         goto out;
3018                 }
3019                 /*
3020                  * Cleanup, just in case ...
3021                  */
3022                 local_irq_disable();
3023                 disable_8259A_irq(0);
3024                 clear_IO_APIC_pin(apic2, pin2);
3025                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3026         }
3027
3028         if (nmi_watchdog == NMI_IO_APIC) {
3029                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3030                             "through the IO-APIC - disabling NMI Watchdog!\n");
3031                 nmi_watchdog = NMI_NONE;
3032         }
3033 #ifdef CONFIG_X86_32
3034         timer_ack = 0;
3035 #endif
3036
3037         apic_printk(APIC_QUIET, KERN_INFO
3038                     "...trying to set up timer as Virtual Wire IRQ...\n");
3039
3040         lapic_register_intr(0, desc);
3041         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
3042         enable_8259A_irq(0);
3043
3044         if (timer_irq_works()) {
3045                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3046                 goto out;
3047         }
3048         local_irq_disable();
3049         disable_8259A_irq(0);
3050         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3051         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3052
3053         apic_printk(APIC_QUIET, KERN_INFO
3054                     "...trying to set up timer as ExtINT IRQ...\n");
3055
3056         init_8259A(0);
3057         make_8259A_irq(0);
3058         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3059
3060         unlock_ExtINT_logic();
3061
3062         if (timer_irq_works()) {
3063                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3064                 goto out;
3065         }
3066         local_irq_disable();
3067         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3068         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3069                 "report.  Then try booting with the 'noapic' option.\n");
3070 out:
3071         local_irq_restore(flags);
3072 }
3073
3074 /*
3075  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3076  * to devices.  However there may be an I/O APIC pin available for
3077  * this interrupt regardless.  The pin may be left unconnected, but
3078  * typically it will be reused as an ExtINT cascade interrupt for
3079  * the master 8259A.  In the MPS case such a pin will normally be
3080  * reported as an ExtINT interrupt in the MP table.  With ACPI
3081  * there is no provision for ExtINT interrupts, and in the absence
3082  * of an override it would be treated as an ordinary ISA I/O APIC
3083  * interrupt, that is edge-triggered and unmasked by default.  We
3084  * used to do this, but it caused problems on some systems because
3085  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3086  * the same ExtINT cascade interrupt to drive the local APIC of the
3087  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3088  * the I/O APIC in all cases now.  No actual device should request
3089  * it anyway.  --macro
3090  */
3091 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3092
3093 void __init setup_IO_APIC(void)
3094 {
3095
3096         /*
3097          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3098          */
3099
3100         io_apic_irqs = ~PIC_IRQS;
3101
3102         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3103         /*
3104          * Set up IO-APIC IRQ routing.
3105          */
3106 #ifdef CONFIG_X86_32
3107         if (!acpi_ioapic)
3108                 setup_ioapic_ids_from_mpc();
3109 #endif
3110         sync_Arb_IDs();
3111         setup_IO_APIC_irqs();
3112         init_IO_APIC_traps();
3113         check_timer();
3114 }
3115
3116 /*
3117  *      Called after all the initialization is done. If we didnt find any
3118  *      APIC bugs then we can allow the modify fast path
3119  */
3120
3121 static int __init io_apic_bug_finalize(void)
3122 {
3123         if (sis_apic_bug == -1)
3124                 sis_apic_bug = 0;
3125         return 0;
3126 }
3127
3128 late_initcall(io_apic_bug_finalize);
3129
3130 struct sysfs_ioapic_data {
3131         struct sys_device dev;
3132         struct IO_APIC_route_entry entry[0];
3133 };
3134 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3135
3136 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3137 {
3138         struct IO_APIC_route_entry *entry;
3139         struct sysfs_ioapic_data *data;
3140         int i;
3141
3142         data = container_of(dev, struct sysfs_ioapic_data, dev);
3143         entry = data->entry;
3144         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3145                 *entry = ioapic_read_entry(dev->id, i);
3146
3147         return 0;
3148 }
3149
3150 static int ioapic_resume(struct sys_device *dev)
3151 {
3152         struct IO_APIC_route_entry *entry;
3153         struct sysfs_ioapic_data *data;
3154         unsigned long flags;
3155         union IO_APIC_reg_00 reg_00;
3156         int i;
3157
3158         data = container_of(dev, struct sysfs_ioapic_data, dev);
3159         entry = data->entry;
3160
3161         spin_lock_irqsave(&ioapic_lock, flags);
3162         reg_00.raw = io_apic_read(dev->id, 0);
3163         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3164                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3165                 io_apic_write(dev->id, 0, reg_00.raw);
3166         }
3167         spin_unlock_irqrestore(&ioapic_lock, flags);
3168         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3169                 ioapic_write_entry(dev->id, i, entry[i]);
3170
3171         return 0;
3172 }
3173
3174 static struct sysdev_class ioapic_sysdev_class = {
3175         .name = "ioapic",
3176         .suspend = ioapic_suspend,
3177         .resume = ioapic_resume,
3178 };
3179
3180 static int __init ioapic_init_sysfs(void)
3181 {
3182         struct sys_device * dev;
3183         int i, size, error;
3184
3185         error = sysdev_class_register(&ioapic_sysdev_class);
3186         if (error)
3187                 return error;
3188
3189         for (i = 0; i < nr_ioapics; i++ ) {
3190                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3191                         * sizeof(struct IO_APIC_route_entry);
3192                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3193                 if (!mp_ioapic_data[i]) {
3194                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3195                         continue;
3196                 }
3197                 dev = &mp_ioapic_data[i]->dev;
3198                 dev->id = i;
3199                 dev->cls = &ioapic_sysdev_class;
3200                 error = sysdev_register(dev);
3201                 if (error) {
3202                         kfree(mp_ioapic_data[i]);
3203                         mp_ioapic_data[i] = NULL;
3204                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3205                         continue;
3206                 }
3207         }
3208
3209         return 0;
3210 }
3211
3212 device_initcall(ioapic_init_sysfs);
3213
3214 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3215 /*
3216  * Dynamic irq allocate and deallocation
3217  */
3218 unsigned int create_irq_nr(unsigned int irq_want)
3219 {
3220         /* Allocate an unused irq */
3221         unsigned int irq;
3222         unsigned int new;
3223         unsigned long flags;
3224         struct irq_cfg *cfg_new = NULL;
3225         int cpu = boot_cpu_id;
3226         struct irq_desc *desc_new = NULL;
3227
3228         irq = 0;
3229         if (irq_want < nr_irqs_gsi)
3230                 irq_want = nr_irqs_gsi;
3231
3232         spin_lock_irqsave(&vector_lock, flags);
3233         for (new = irq_want; new < nr_irqs; new++) {
3234                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3235                 if (!desc_new) {
3236                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3237                         continue;
3238                 }
3239                 cfg_new = desc_new->chip_data;
3240
3241                 if (cfg_new->vector != 0)
3242                         continue;
3243                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3244                         irq = new;
3245                 break;
3246         }
3247         spin_unlock_irqrestore(&vector_lock, flags);
3248
3249         if (irq > 0) {
3250                 dynamic_irq_init(irq);
3251                 /* restore it, in case dynamic_irq_init clear it */
3252                 if (desc_new)
3253                         desc_new->chip_data = cfg_new;
3254         }
3255         return irq;
3256 }
3257
3258 int create_irq(void)
3259 {
3260         unsigned int irq_want;
3261         int irq;
3262
3263         irq_want = nr_irqs_gsi;
3264         irq = create_irq_nr(irq_want);
3265
3266         if (irq == 0)
3267                 irq = -1;
3268
3269         return irq;
3270 }
3271
3272 void destroy_irq(unsigned int irq)
3273 {
3274         unsigned long flags;
3275         struct irq_cfg *cfg;
3276         struct irq_desc *desc;
3277
3278         /* store it, in case dynamic_irq_cleanup clear it */
3279         desc = irq_to_desc(irq);
3280         cfg = desc->chip_data;
3281         dynamic_irq_cleanup(irq);
3282         /* connect back irq_cfg */
3283         if (desc)
3284                 desc->chip_data = cfg;
3285
3286         free_irte(irq);
3287         spin_lock_irqsave(&vector_lock, flags);
3288         __clear_irq_vector(irq, cfg);
3289         spin_unlock_irqrestore(&vector_lock, flags);
3290 }
3291
3292 /*
3293  * MSI message composition
3294  */
3295 #ifdef CONFIG_PCI_MSI
3296 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3297 {
3298         struct irq_cfg *cfg;
3299         int err;
3300         unsigned dest;
3301
3302         if (disable_apic)
3303                 return -ENXIO;
3304
3305         cfg = irq_cfg(irq);
3306         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3307         if (err)
3308                 return err;
3309
3310         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3311
3312         if (irq_remapped(irq)) {
3313                 struct irte irte;
3314                 int ir_index;
3315                 u16 sub_handle;
3316
3317                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3318                 BUG_ON(ir_index == -1);
3319
3320                 memset (&irte, 0, sizeof(irte));
3321
3322                 irte.present = 1;
3323                 irte.dst_mode = apic->irq_dest_mode;
3324                 irte.trigger_mode = 0; /* edge */
3325                 irte.dlvry_mode = apic->irq_delivery_mode;
3326                 irte.vector = cfg->vector;
3327                 irte.dest_id = IRTE_DEST(dest);
3328
3329                 modify_irte(irq, &irte);
3330
3331                 msg->address_hi = MSI_ADDR_BASE_HI;
3332                 msg->data = sub_handle;
3333                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3334                                   MSI_ADDR_IR_SHV |
3335                                   MSI_ADDR_IR_INDEX1(ir_index) |
3336                                   MSI_ADDR_IR_INDEX2(ir_index);
3337         } else {
3338                 if (x2apic_enabled())
3339                         msg->address_hi = MSI_ADDR_BASE_HI |
3340                                           MSI_ADDR_EXT_DEST_ID(dest);
3341                 else
3342                         msg->address_hi = MSI_ADDR_BASE_HI;
3343
3344                 msg->address_lo =
3345                         MSI_ADDR_BASE_LO |
3346                         ((apic->irq_dest_mode == 0) ?
3347                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3348                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3349                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3350                                 MSI_ADDR_REDIRECTION_CPU:
3351                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3352                         MSI_ADDR_DEST_ID(dest);
3353
3354                 msg->data =
3355                         MSI_DATA_TRIGGER_EDGE |
3356                         MSI_DATA_LEVEL_ASSERT |
3357                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3358                                 MSI_DATA_DELIVERY_FIXED:
3359                                 MSI_DATA_DELIVERY_LOWPRI) |
3360                         MSI_DATA_VECTOR(cfg->vector);
3361         }
3362         return err;
3363 }
3364
3365 #ifdef CONFIG_SMP
3366 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3367 {
3368         struct irq_desc *desc = irq_to_desc(irq);
3369         struct irq_cfg *cfg;
3370         struct msi_msg msg;
3371         unsigned int dest;
3372
3373         dest = set_desc_affinity(desc, mask);
3374         if (dest == BAD_APICID)
3375                 return;
3376
3377         cfg = desc->chip_data;
3378
3379         read_msi_msg_desc(desc, &msg);
3380
3381         msg.data &= ~MSI_DATA_VECTOR_MASK;
3382         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3383         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3384         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3385
3386         write_msi_msg_desc(desc, &msg);
3387 }
3388 #ifdef CONFIG_INTR_REMAP
3389 /*
3390  * Migrate the MSI irq to another cpumask. This migration is
3391  * done in the process context using interrupt-remapping hardware.
3392  */
3393 static void
3394 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3395 {
3396         struct irq_desc *desc = irq_to_desc(irq);
3397         struct irq_cfg *cfg = desc->chip_data;
3398         unsigned int dest;
3399         struct irte irte;
3400
3401         if (get_irte(irq, &irte))
3402                 return;
3403
3404         dest = set_desc_affinity(desc, mask);
3405         if (dest == BAD_APICID)
3406                 return;
3407
3408         irte.vector = cfg->vector;
3409         irte.dest_id = IRTE_DEST(dest);
3410
3411         /*
3412          * atomically update the IRTE with the new destination and vector.
3413          */
3414         modify_irte(irq, &irte);
3415
3416         /*
3417          * After this point, all the interrupts will start arriving
3418          * at the new destination. So, time to cleanup the previous
3419          * vector allocation.
3420          */
3421         if (cfg->move_in_progress)
3422                 send_cleanup_vector(cfg);
3423 }
3424
3425 #endif
3426 #endif /* CONFIG_SMP */
3427
3428 /*
3429  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3430  * which implement the MSI or MSI-X Capability Structure.
3431  */
3432 static struct irq_chip msi_chip = {
3433         .name           = "PCI-MSI",
3434         .unmask         = unmask_msi_irq,
3435         .mask           = mask_msi_irq,
3436         .ack            = ack_apic_edge,
3437 #ifdef CONFIG_SMP
3438         .set_affinity   = set_msi_irq_affinity,
3439 #endif
3440         .retrigger      = ioapic_retrigger_irq,
3441 };
3442
3443 static struct irq_chip msi_ir_chip = {
3444         .name           = "IR-PCI-MSI",
3445         .unmask         = unmask_msi_irq,
3446         .mask           = mask_msi_irq,
3447 #ifdef CONFIG_INTR_REMAP
3448         .ack            = ir_ack_apic_edge,
3449 #ifdef CONFIG_SMP
3450         .set_affinity   = ir_set_msi_irq_affinity,
3451 #endif
3452 #endif
3453         .retrigger      = ioapic_retrigger_irq,
3454 };
3455
3456 /*
3457  * Map the PCI dev to the corresponding remapping hardware unit
3458  * and allocate 'nvec' consecutive interrupt-remapping table entries
3459  * in it.
3460  */
3461 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3462 {
3463         struct intel_iommu *iommu;
3464         int index;
3465
3466         iommu = map_dev_to_ir(dev);
3467         if (!iommu) {
3468                 printk(KERN_ERR
3469                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3470                 return -ENOENT;
3471         }
3472
3473         index = alloc_irte(iommu, irq, nvec);
3474         if (index < 0) {
3475                 printk(KERN_ERR
3476                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3477                        pci_name(dev));
3478                 return -ENOSPC;
3479         }
3480         return index;
3481 }
3482
3483 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3484 {
3485         int ret;
3486         struct msi_msg msg;
3487
3488         ret = msi_compose_msg(dev, irq, &msg);
3489         if (ret < 0)
3490                 return ret;
3491
3492         set_irq_msi(irq, msidesc);
3493         write_msi_msg(irq, &msg);
3494
3495         if (irq_remapped(irq)) {
3496                 struct irq_desc *desc = irq_to_desc(irq);
3497                 /*
3498                  * irq migration in process context
3499                  */
3500                 desc->status |= IRQ_MOVE_PCNTXT;
3501                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3502         } else
3503                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3504
3505         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3506
3507         return 0;
3508 }
3509
3510 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3511 {
3512         unsigned int irq;
3513         int ret, sub_handle;
3514         struct msi_desc *msidesc;
3515         unsigned int irq_want;
3516         struct intel_iommu *iommu = NULL;
3517         int index = 0;
3518
3519         /* x86 doesn't support multiple MSI yet */
3520         if (type == PCI_CAP_ID_MSI && nvec > 1)
3521                 return 1;
3522
3523         irq_want = nr_irqs_gsi;
3524         sub_handle = 0;
3525         list_for_each_entry(msidesc, &dev->msi_list, list) {
3526                 irq = create_irq_nr(irq_want);
3527                 if (irq == 0)
3528                         return -1;
3529                 irq_want = irq + 1;
3530                 if (!intr_remapping_enabled)
3531                         goto no_ir;
3532
3533                 if (!sub_handle) {
3534                         /*
3535                          * allocate the consecutive block of IRTE's
3536                          * for 'nvec'
3537                          */
3538                         index = msi_alloc_irte(dev, irq, nvec);
3539                         if (index < 0) {
3540                                 ret = index;
3541                                 goto error;
3542                         }
3543                 } else {
3544                         iommu = map_dev_to_ir(dev);
3545                         if (!iommu) {
3546                                 ret = -ENOENT;
3547                                 goto error;
3548                         }
3549                         /*
3550                          * setup the mapping between the irq and the IRTE
3551                          * base index, the sub_handle pointing to the
3552                          * appropriate interrupt remap table entry.
3553                          */
3554                         set_irte_irq(irq, iommu, index, sub_handle);
3555                 }
3556 no_ir:
3557                 ret = setup_msi_irq(dev, msidesc, irq);
3558                 if (ret < 0)
3559                         goto error;
3560                 sub_handle++;
3561         }
3562         return 0;
3563
3564 error:
3565         destroy_irq(irq);
3566         return ret;
3567 }
3568
3569 void arch_teardown_msi_irq(unsigned int irq)
3570 {
3571         destroy_irq(irq);
3572 }
3573
3574 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3575 #ifdef CONFIG_SMP
3576 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3577 {
3578         struct irq_desc *desc = irq_to_desc(irq);
3579         struct irq_cfg *cfg;
3580         struct msi_msg msg;
3581         unsigned int dest;
3582
3583         dest = set_desc_affinity(desc, mask);
3584         if (dest == BAD_APICID)
3585                 return;
3586
3587         cfg = desc->chip_data;
3588
3589         dmar_msi_read(irq, &msg);
3590
3591         msg.data &= ~MSI_DATA_VECTOR_MASK;
3592         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3593         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3594         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3595
3596         dmar_msi_write(irq, &msg);
3597 }
3598
3599 #endif /* CONFIG_SMP */
3600
3601 struct irq_chip dmar_msi_type = {
3602         .name = "DMAR_MSI",
3603         .unmask = dmar_msi_unmask,
3604         .mask = dmar_msi_mask,
3605         .ack = ack_apic_edge,
3606 #ifdef CONFIG_SMP
3607         .set_affinity = dmar_msi_set_affinity,
3608 #endif
3609         .retrigger = ioapic_retrigger_irq,
3610 };
3611
3612 int arch_setup_dmar_msi(unsigned int irq)
3613 {
3614         int ret;
3615         struct msi_msg msg;
3616
3617         ret = msi_compose_msg(NULL, irq, &msg);
3618         if (ret < 0)
3619                 return ret;
3620         dmar_msi_write(irq, &msg);
3621         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3622                 "edge");
3623         return 0;
3624 }
3625 #endif
3626
3627 #ifdef CONFIG_HPET_TIMER
3628
3629 #ifdef CONFIG_SMP
3630 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3631 {
3632         struct irq_desc *desc = irq_to_desc(irq);
3633         struct irq_cfg *cfg;
3634         struct msi_msg msg;
3635         unsigned int dest;
3636
3637         dest = set_desc_affinity(desc, mask);
3638         if (dest == BAD_APICID)
3639                 return;
3640
3641         cfg = desc->chip_data;
3642
3643         hpet_msi_read(irq, &msg);
3644
3645         msg.data &= ~MSI_DATA_VECTOR_MASK;
3646         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3647         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3648         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3649
3650         hpet_msi_write(irq, &msg);
3651 }
3652
3653 #endif /* CONFIG_SMP */
3654
3655 static struct irq_chip hpet_msi_type = {
3656         .name = "HPET_MSI",
3657         .unmask = hpet_msi_unmask,
3658         .mask = hpet_msi_mask,
3659         .ack = ack_apic_edge,
3660 #ifdef CONFIG_SMP
3661         .set_affinity = hpet_msi_set_affinity,
3662 #endif
3663         .retrigger = ioapic_retrigger_irq,
3664 };
3665
3666 int arch_setup_hpet_msi(unsigned int irq)
3667 {
3668         int ret;
3669         struct msi_msg msg;
3670
3671         ret = msi_compose_msg(NULL, irq, &msg);
3672         if (ret < 0)
3673                 return ret;
3674
3675         hpet_msi_write(irq, &msg);
3676         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3677                 "edge");
3678
3679         return 0;
3680 }
3681 #endif
3682
3683 #endif /* CONFIG_PCI_MSI */
3684 /*
3685  * Hypertransport interrupt support
3686  */
3687 #ifdef CONFIG_HT_IRQ
3688
3689 #ifdef CONFIG_SMP
3690
3691 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3692 {
3693         struct ht_irq_msg msg;
3694         fetch_ht_irq_msg(irq, &msg);
3695
3696         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3697         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3698
3699         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3700         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3701
3702         write_ht_irq_msg(irq, &msg);
3703 }
3704
3705 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3706 {
3707         struct irq_desc *desc = irq_to_desc(irq);
3708         struct irq_cfg *cfg;
3709         unsigned int dest;
3710
3711         dest = set_desc_affinity(desc, mask);
3712         if (dest == BAD_APICID)
3713                 return;
3714
3715         cfg = desc->chip_data;
3716
3717         target_ht_irq(irq, dest, cfg->vector);
3718 }
3719
3720 #endif
3721
3722 static struct irq_chip ht_irq_chip = {
3723         .name           = "PCI-HT",
3724         .mask           = mask_ht_irq,
3725         .unmask         = unmask_ht_irq,
3726         .ack            = ack_apic_edge,
3727 #ifdef CONFIG_SMP
3728         .set_affinity   = set_ht_irq_affinity,
3729 #endif
3730         .retrigger      = ioapic_retrigger_irq,
3731 };
3732
3733 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3734 {
3735         struct irq_cfg *cfg;
3736         int err;
3737
3738         if (disable_apic)
3739                 return -ENXIO;
3740
3741         cfg = irq_cfg(irq);
3742         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3743         if (!err) {
3744                 struct ht_irq_msg msg;
3745                 unsigned dest;
3746
3747                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3748                                                     apic->target_cpus());
3749
3750                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3751
3752                 msg.address_lo =
3753                         HT_IRQ_LOW_BASE |
3754                         HT_IRQ_LOW_DEST_ID(dest) |
3755                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3756                         ((apic->irq_dest_mode == 0) ?
3757                                 HT_IRQ_LOW_DM_PHYSICAL :
3758                                 HT_IRQ_LOW_DM_LOGICAL) |
3759                         HT_IRQ_LOW_RQEOI_EDGE |
3760                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3761                                 HT_IRQ_LOW_MT_FIXED :
3762                                 HT_IRQ_LOW_MT_ARBITRATED) |
3763                         HT_IRQ_LOW_IRQ_MASKED;
3764
3765                 write_ht_irq_msg(irq, &msg);
3766
3767                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3768                                               handle_edge_irq, "edge");
3769
3770                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3771         }
3772         return err;
3773 }
3774 #endif /* CONFIG_HT_IRQ */
3775
3776 #ifdef CONFIG_X86_UV
3777 /*
3778  * Re-target the irq to the specified CPU and enable the specified MMR located
3779  * on the specified blade to allow the sending of MSIs to the specified CPU.
3780  */
3781 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3782                        unsigned long mmr_offset)
3783 {
3784         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3785         struct irq_cfg *cfg;
3786         int mmr_pnode;
3787         unsigned long mmr_value;
3788         struct uv_IO_APIC_route_entry *entry;
3789         unsigned long flags;
3790         int err;
3791
3792         cfg = irq_cfg(irq);
3793
3794         err = assign_irq_vector(irq, cfg, eligible_cpu);
3795         if (err != 0)
3796                 return err;
3797
3798         spin_lock_irqsave(&vector_lock, flags);
3799         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3800                                       irq_name);
3801         spin_unlock_irqrestore(&vector_lock, flags);
3802
3803         mmr_value = 0;
3804         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3805         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3806
3807         entry->vector = cfg->vector;
3808         entry->delivery_mode = apic->irq_delivery_mode;
3809         entry->dest_mode = apic->irq_dest_mode;
3810         entry->polarity = 0;
3811         entry->trigger = 0;
3812         entry->mask = 0;
3813         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3814
3815         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3816         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3817
3818         return irq;
3819 }
3820
3821 /*
3822  * Disable the specified MMR located on the specified blade so that MSIs are
3823  * longer allowed to be sent.
3824  */
3825 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3826 {
3827         unsigned long mmr_value;
3828         struct uv_IO_APIC_route_entry *entry;
3829         int mmr_pnode;
3830
3831         mmr_value = 0;
3832         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3833         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3834
3835         entry->mask = 1;
3836
3837         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3838         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3839 }
3840 #endif /* CONFIG_X86_64 */
3841
3842 int __init io_apic_get_redir_entries (int ioapic)
3843 {
3844         union IO_APIC_reg_01    reg_01;
3845         unsigned long flags;
3846
3847         spin_lock_irqsave(&ioapic_lock, flags);
3848         reg_01.raw = io_apic_read(ioapic, 1);
3849         spin_unlock_irqrestore(&ioapic_lock, flags);
3850
3851         return reg_01.bits.entries;
3852 }
3853
3854 void __init probe_nr_irqs_gsi(void)
3855 {
3856         int nr = 0;
3857
3858         nr = acpi_probe_gsi();
3859         if (nr > nr_irqs_gsi) {
3860                 nr_irqs_gsi = nr;
3861         } else {
3862                 /* for acpi=off or acpi is not compiled in */
3863                 int idx;
3864
3865                 nr = 0;
3866                 for (idx = 0; idx < nr_ioapics; idx++)
3867                         nr += io_apic_get_redir_entries(idx) + 1;
3868
3869                 if (nr > nr_irqs_gsi)
3870                         nr_irqs_gsi = nr;
3871         }
3872
3873         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3874 }
3875
3876 #ifdef CONFIG_SPARSE_IRQ
3877 int __init arch_probe_nr_irqs(void)
3878 {
3879         int nr;
3880
3881         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3882                 nr_irqs = NR_VECTORS * nr_cpu_ids;
3883
3884         nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3885 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3886         /*
3887          * for MSI and HT dyn irq
3888          */
3889         nr += nr_irqs_gsi * 16;
3890 #endif
3891         if (nr < nr_irqs)
3892                 nr_irqs = nr;
3893
3894         return 0;
3895 }
3896 #endif
3897
3898 /* --------------------------------------------------------------------------
3899                           ACPI-based IOAPIC Configuration
3900    -------------------------------------------------------------------------- */
3901
3902 #ifdef CONFIG_ACPI
3903
3904 #ifdef CONFIG_X86_32
3905 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3906 {
3907         union IO_APIC_reg_00 reg_00;
3908         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3909         physid_mask_t tmp;
3910         unsigned long flags;
3911         int i = 0;
3912
3913         /*
3914          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3915          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3916          * supports up to 16 on one shared APIC bus.
3917          *
3918          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3919          *      advantage of new APIC bus architecture.
3920          */
3921
3922         if (physids_empty(apic_id_map))
3923                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3924
3925         spin_lock_irqsave(&ioapic_lock, flags);
3926         reg_00.raw = io_apic_read(ioapic, 0);
3927         spin_unlock_irqrestore(&ioapic_lock, flags);
3928
3929         if (apic_id >= get_physical_broadcast()) {
3930                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3931                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3932                 apic_id = reg_00.bits.ID;
3933         }
3934
3935         /*
3936          * Every APIC in a system must have a unique ID or we get lots of nice
3937          * 'stuck on smp_invalidate_needed IPI wait' messages.
3938          */
3939         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3940
3941                 for (i = 0; i < get_physical_broadcast(); i++) {
3942                         if (!apic->check_apicid_used(apic_id_map, i))
3943                                 break;
3944                 }
3945
3946                 if (i == get_physical_broadcast())
3947                         panic("Max apic_id exceeded!\n");
3948
3949                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3950                         "trying %d\n", ioapic, apic_id, i);
3951
3952                 apic_id = i;
3953         }
3954
3955         tmp = apic->apicid_to_cpu_present(apic_id);
3956         physids_or(apic_id_map, apic_id_map, tmp);
3957
3958         if (reg_00.bits.ID != apic_id) {
3959                 reg_00.bits.ID = apic_id;
3960
3961                 spin_lock_irqsave(&ioapic_lock, flags);
3962                 io_apic_write(ioapic, 0, reg_00.raw);
3963                 reg_00.raw = io_apic_read(ioapic, 0);
3964                 spin_unlock_irqrestore(&ioapic_lock, flags);
3965
3966                 /* Sanity check */
3967                 if (reg_00.bits.ID != apic_id) {
3968                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3969                         return -1;
3970                 }
3971         }
3972
3973         apic_printk(APIC_VERBOSE, KERN_INFO
3974                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3975
3976         return apic_id;
3977 }
3978
3979 int __init io_apic_get_version(int ioapic)
3980 {
3981         union IO_APIC_reg_01    reg_01;
3982         unsigned long flags;
3983
3984         spin_lock_irqsave(&ioapic_lock, flags);
3985         reg_01.raw = io_apic_read(ioapic, 1);
3986         spin_unlock_irqrestore(&ioapic_lock, flags);
3987
3988         return reg_01.bits.version;
3989 }
3990 #endif
3991
3992 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3993 {
3994         struct irq_desc *desc;
3995         struct irq_cfg *cfg;
3996         int cpu = boot_cpu_id;
3997
3998         if (!IO_APIC_IRQ(irq)) {
3999                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
4000                         ioapic);
4001                 return -EINVAL;
4002         }
4003
4004         desc = irq_to_desc_alloc_cpu(irq, cpu);
4005         if (!desc) {
4006                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
4007                 return 0;
4008         }
4009
4010         /*
4011          * IRQs < 16 are already in the irq_2_pin[] map
4012          */
4013         if (irq >= NR_IRQS_LEGACY) {
4014                 cfg = desc->chip_data;
4015                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
4016         }
4017
4018         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
4019
4020         return 0;
4021 }
4022
4023
4024 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4025 {
4026         int i;
4027
4028         if (skip_ioapic_setup)
4029                 return -1;
4030
4031         for (i = 0; i < mp_irq_entries; i++)
4032                 if (mp_irqs[i].irqtype == mp_INT &&
4033                     mp_irqs[i].srcbusirq == bus_irq)
4034                         break;
4035         if (i >= mp_irq_entries)
4036                 return -1;
4037
4038         *trigger = irq_trigger(i);
4039         *polarity = irq_polarity(i);
4040         return 0;
4041 }
4042
4043 #endif /* CONFIG_ACPI */
4044
4045 /*
4046  * This function currently is only a helper for the i386 smp boot process where
4047  * we need to reprogram the ioredtbls to cater for the cpus which have come online
4048  * so mask in all cases should simply be apic->target_cpus()
4049  */
4050 #ifdef CONFIG_SMP
4051 void __init setup_ioapic_dest(void)
4052 {
4053         int pin, ioapic, irq, irq_entry;
4054         struct irq_desc *desc;
4055         struct irq_cfg *cfg;
4056         const struct cpumask *mask;
4057
4058         if (skip_ioapic_setup == 1)
4059                 return;
4060
4061         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4062                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4063                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4064                         if (irq_entry == -1)
4065                                 continue;
4066                         irq = pin_2_irq(irq_entry, ioapic, pin);
4067
4068                         /* setup_IO_APIC_irqs could fail to get vector for some device
4069                          * when you have too many devices, because at that time only boot
4070                          * cpu is online.
4071                          */
4072                         desc = irq_to_desc(irq);
4073                         cfg = desc->chip_data;
4074                         if (!cfg->vector) {
4075                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4076                                                   irq_trigger(irq_entry),
4077                                                   irq_polarity(irq_entry));
4078                                 continue;
4079
4080                         }
4081
4082                         /*
4083                          * Honour affinities which have been set in early boot
4084                          */
4085                         if (desc->status &
4086                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4087                                 mask = desc->affinity;
4088                         else
4089                                 mask = apic->target_cpus();
4090
4091                         if (intr_remapping_enabled)
4092                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4093                         else
4094                                 set_ioapic_affinity_irq_desc(desc, mask);
4095                 }
4096
4097         }
4098 }
4099 #endif
4100
4101 #define IOAPIC_RESOURCE_NAME_SIZE 11
4102
4103 static struct resource *ioapic_resources;
4104
4105 static struct resource * __init ioapic_setup_resources(void)
4106 {
4107         unsigned long n;
4108         struct resource *res;
4109         char *mem;
4110         int i;
4111
4112         if (nr_ioapics <= 0)
4113                 return NULL;
4114
4115         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4116         n *= nr_ioapics;
4117
4118         mem = alloc_bootmem(n);
4119         res = (void *)mem;
4120
4121         if (mem != NULL) {
4122                 mem += sizeof(struct resource) * nr_ioapics;
4123
4124                 for (i = 0; i < nr_ioapics; i++) {
4125                         res[i].name = mem;
4126                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4127                         sprintf(mem,  "IOAPIC %u", i);
4128                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4129                 }
4130         }
4131
4132         ioapic_resources = res;
4133
4134         return res;
4135 }
4136
4137 void __init ioapic_init_mappings(void)
4138 {
4139         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4140         struct resource *ioapic_res;
4141         int i;
4142
4143         ioapic_res = ioapic_setup_resources();
4144         for (i = 0; i < nr_ioapics; i++) {
4145                 if (smp_found_config) {
4146                         ioapic_phys = mp_ioapics[i].apicaddr;
4147 #ifdef CONFIG_X86_32
4148                         if (!ioapic_phys) {
4149                                 printk(KERN_ERR
4150                                        "WARNING: bogus zero IO-APIC "
4151                                        "address found in MPTABLE, "
4152                                        "disabling IO/APIC support!\n");
4153                                 smp_found_config = 0;
4154                                 skip_ioapic_setup = 1;
4155                                 goto fake_ioapic_page;
4156                         }
4157 #endif
4158                 } else {
4159 #ifdef CONFIG_X86_32
4160 fake_ioapic_page:
4161 #endif
4162                         ioapic_phys = (unsigned long)
4163                                 alloc_bootmem_pages(PAGE_SIZE);
4164                         ioapic_phys = __pa(ioapic_phys);
4165                 }
4166                 set_fixmap_nocache(idx, ioapic_phys);
4167                 apic_printk(APIC_VERBOSE,
4168                             "mapped IOAPIC to %08lx (%08lx)\n",
4169                             __fix_to_virt(idx), ioapic_phys);
4170                 idx++;
4171
4172                 if (ioapic_res != NULL) {
4173                         ioapic_res->start = ioapic_phys;
4174                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4175                         ioapic_res++;
4176                 }
4177         }
4178 }
4179
4180 static int __init ioapic_insert_resources(void)
4181 {
4182         int i;
4183         struct resource *r = ioapic_resources;
4184
4185         if (!r) {
4186                 if (nr_ioapics > 0) {
4187                         printk(KERN_ERR
4188                                 "IO APIC resources couldn't be allocated.\n");
4189                         return -1;
4190                 }
4191                 return 0;
4192         }
4193
4194         for (i = 0; i < nr_ioapics; i++) {
4195                 insert_resource(&iomem_resource, r);
4196                 r++;
4197         }
4198
4199         return 0;
4200 }
4201
4202 /* Insert the IO APIC resources after PCI initialization has occured to handle
4203  * IO APICS that are mapped in on a BAR in PCI space. */
4204 late_initcall(ioapic_insert_resources);