2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/string.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/slab.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/skbuff.h>
27 #include <linux/spinlock.h>
29 #include <linux/module.h>
30 #include <linux/mii.h>
31 #include <linux/ethtool.h>
32 #include <linux/phy.h>
36 #include <asm/uaccess.h>
38 #define MII_M1011_IEVENT 0x13
39 #define MII_M1011_IEVENT_CLEAR 0x0000
41 #define MII_M1011_IMASK 0x12
42 #define MII_M1011_IMASK_INIT 0x6400
43 #define MII_M1011_IMASK_CLEAR 0x0000
45 #define MII_M1011_PHY_SCR 0x10
46 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
48 #define MII_M1145_PHY_EXT_CR 0x14
49 #define MII_M1145_RGMII_RX_DELAY 0x0080
50 #define MII_M1145_RGMII_TX_DELAY 0x0002
52 #define M1145_DEV_FLAGS_RESISTANCE 0x00000001
54 #define MII_M1111_PHY_LED_CONTROL 0x18
55 #define MII_M1111_PHY_LED_DIRECT 0x4100
56 #define MII_M1111_PHY_LED_COMBINE 0x411c
57 #define MII_M1111_PHY_EXT_CR 0x14
58 #define MII_M1111_RX_DELAY 0x80
59 #define MII_M1111_TX_DELAY 0x2
60 #define MII_M1111_PHY_EXT_SR 0x1b
61 #define MII_M1111_HWCFG_MODE_MASK 0xf
62 #define MII_M1111_HWCFG_MODE_RGMII 0xb
64 MODULE_DESCRIPTION("Marvell PHY driver");
65 MODULE_AUTHOR("Andy Fleming");
66 MODULE_LICENSE("GPL");
68 static int marvell_ack_interrupt(struct phy_device *phydev)
72 /* Clear the interrupts by reading the reg */
73 err = phy_read(phydev, MII_M1011_IEVENT);
81 static int marvell_config_intr(struct phy_device *phydev)
85 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
86 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
88 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
93 static int marvell_config_aneg(struct phy_device *phydev)
97 /* The Marvell PHY has an errata which requires
98 * that certain registers get written in order
99 * to restart autonegotiation */
100 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
105 err = phy_write(phydev, 0x1d, 0x1f);
109 err = phy_write(phydev, 0x1e, 0x200c);
113 err = phy_write(phydev, 0x1d, 0x5);
117 err = phy_write(phydev, 0x1e, 0);
121 err = phy_write(phydev, 0x1e, 0x100);
125 err = phy_write(phydev, MII_M1011_PHY_SCR,
126 MII_M1011_PHY_SCR_AUTO_CROSS);
130 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
131 MII_M1111_PHY_LED_DIRECT);
135 err = genphy_config_aneg(phydev);
140 static int m88e1111_config_init(struct phy_device *phydev)
144 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
145 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
148 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
149 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
153 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
155 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
160 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
164 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
165 temp |= MII_M1111_HWCFG_MODE_RGMII;
167 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
172 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
179 static int m88e1145_config_init(struct phy_device *phydev)
183 /* Take care of errata E0 & E1 */
184 err = phy_write(phydev, 0x1d, 0x001b);
188 err = phy_write(phydev, 0x1e, 0x418f);
192 err = phy_write(phydev, 0x1d, 0x0016);
196 err = phy_write(phydev, 0x1e, 0xa2da);
200 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
201 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
205 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
207 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
211 if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
212 err = phy_write(phydev, 0x1d, 0x0012);
216 temp = phy_read(phydev, 0x1e);
221 temp |= 2 << 9; /* 36 ohm */
222 temp |= 2 << 6; /* 39 ohm */
224 err = phy_write(phydev, 0x1e, temp);
228 err = phy_write(phydev, 0x1d, 0x3);
232 err = phy_write(phydev, 0x1e, 0x8000);
241 static struct phy_driver m88e1101_driver = {
242 .phy_id = 0x01410c60,
243 .phy_id_mask = 0xfffffff0,
244 .name = "Marvell 88E1101",
245 .features = PHY_GBIT_FEATURES,
246 .flags = PHY_HAS_INTERRUPT,
247 .config_aneg = &marvell_config_aneg,
248 .read_status = &genphy_read_status,
249 .ack_interrupt = &marvell_ack_interrupt,
250 .config_intr = &marvell_config_intr,
251 .driver = {.owner = THIS_MODULE,},
254 static struct phy_driver m88e1111_driver = {
255 .phy_id = 0x01410cc0,
256 .phy_id_mask = 0xfffffff0,
257 .name = "Marvell 88E1111",
258 .features = PHY_GBIT_FEATURES,
259 .flags = PHY_HAS_INTERRUPT,
260 .config_aneg = &marvell_config_aneg,
261 .read_status = &genphy_read_status,
262 .ack_interrupt = &marvell_ack_interrupt,
263 .config_intr = &marvell_config_intr,
264 .config_init = &m88e1111_config_init,
265 .driver = {.owner = THIS_MODULE,},
268 static struct phy_driver m88e1145_driver = {
269 .phy_id = 0x01410cd0,
270 .phy_id_mask = 0xfffffff0,
271 .name = "Marvell 88E1145",
272 .features = PHY_GBIT_FEATURES,
273 .flags = PHY_HAS_INTERRUPT,
274 .config_init = &m88e1145_config_init,
275 .config_aneg = &marvell_config_aneg,
276 .read_status = &genphy_read_status,
277 .ack_interrupt = &marvell_ack_interrupt,
278 .config_intr = &marvell_config_intr,
279 .driver = {.owner = THIS_MODULE,},
282 static int __init marvell_init(void)
286 ret = phy_driver_register(&m88e1101_driver);
290 ret = phy_driver_register(&m88e1111_driver);
294 ret = phy_driver_register(&m88e1145_driver);
301 phy_driver_unregister(&m88e1111_driver);
303 phy_driver_unregister(&m88e1101_driver);
307 static void __exit marvell_exit(void)
309 phy_driver_unregister(&m88e1101_driver);
310 phy_driver_unregister(&m88e1111_driver);
311 phy_driver_unregister(&m88e1145_driver);
314 module_init(marvell_init);
315 module_exit(marvell_exit);