1 /*****************************************************************************
5 * $Date: 2005/06/21 22:49:43 $ *
7 * part of the Chelsio 10Gb Ethernet Driver. *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * http://www.chelsio.com *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
26 * Maintainers: maintainers@chelsio.com *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
37 ****************************************************************************/
39 #ifndef _CXGB_ELMER0_H_
40 #define _CXGB_ELMER0_H_
44 ELMER0_XC2S300E_6FT256_C,
45 ELMER0_XC2S100E_6TQ144_C
48 /* ELMER0 registers */
49 #define A_ELMER0_VERSION 0x100000
50 #define A_ELMER0_PHY_CFG 0x100004
51 #define A_ELMER0_INT_ENABLE 0x100008
52 #define A_ELMER0_INT_CAUSE 0x10000c
53 #define A_ELMER0_GPI_CFG 0x100010
54 #define A_ELMER0_GPI_STAT 0x100014
55 #define A_ELMER0_GPO 0x100018
56 #define A_ELMER0_PORT0_MI1_CFG 0x400000
58 #define S_MI1_MDI_ENABLE 0
59 #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE)
60 #define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U)
62 #define S_MI1_MDI_INVERT 1
63 #define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT)
64 #define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U)
66 #define S_MI1_PREAMBLE_ENABLE 2
67 #define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE)
68 #define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U)
72 #define V_MI1_SOF(x) ((x) << S_MI1_SOF)
73 #define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF)
75 #define S_MI1_CLK_DIV 5
76 #define M_MI1_CLK_DIV 0xff
77 #define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV)
78 #define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV)
80 #define A_ELMER0_PORT0_MI1_ADDR 0x400004
82 #define S_MI1_REG_ADDR 0
83 #define M_MI1_REG_ADDR 0x1f
84 #define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR)
85 #define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR)
87 #define S_MI1_PHY_ADDR 5
88 #define M_MI1_PHY_ADDR 0x1f
89 #define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR)
90 #define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR)
92 #define A_ELMER0_PORT0_MI1_DATA 0x400008
95 #define M_MI1_DATA 0xffff
96 #define V_MI1_DATA(x) ((x) << S_MI1_DATA)
97 #define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA)
99 #define A_ELMER0_PORT0_MI1_OP 0x40000c
103 #define V_MI1_OP(x) ((x) << S_MI1_OP)
104 #define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP)
106 #define S_MI1_ADDR_AUTOINC 2
107 #define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC)
108 #define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U)
110 #define S_MI1_OP_BUSY 31
111 #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY)
112 #define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U)
114 #define A_ELMER0_PORT1_MI1_CFG 0x500000
115 #define A_ELMER0_PORT1_MI1_ADDR 0x500004
116 #define A_ELMER0_PORT1_MI1_DATA 0x500008
117 #define A_ELMER0_PORT1_MI1_OP 0x50000c
118 #define A_ELMER0_PORT2_MI1_CFG 0x600000
119 #define A_ELMER0_PORT2_MI1_ADDR 0x600004
120 #define A_ELMER0_PORT2_MI1_DATA 0x600008
121 #define A_ELMER0_PORT2_MI1_OP 0x60000c
122 #define A_ELMER0_PORT3_MI1_CFG 0x700000
123 #define A_ELMER0_PORT3_MI1_ADDR 0x700004
124 #define A_ELMER0_PORT3_MI1_DATA 0x700008
125 #define A_ELMER0_PORT3_MI1_OP 0x70000c
127 /* Simple bit definition for GPI and GP0 registers. */
128 #define ELMER0_GP_BIT0 0x0001
129 #define ELMER0_GP_BIT1 0x0002
130 #define ELMER0_GP_BIT2 0x0004
131 #define ELMER0_GP_BIT3 0x0008
132 #define ELMER0_GP_BIT4 0x0010
133 #define ELMER0_GP_BIT5 0x0020
134 #define ELMER0_GP_BIT6 0x0040
135 #define ELMER0_GP_BIT7 0x0080
136 #define ELMER0_GP_BIT8 0x0100
137 #define ELMER0_GP_BIT9 0x0200
138 #define ELMER0_GP_BIT10 0x0400
139 #define ELMER0_GP_BIT11 0x0800
140 #define ELMER0_GP_BIT12 0x1000
141 #define ELMER0_GP_BIT13 0x2000
142 #define ELMER0_GP_BIT14 0x4000
143 #define ELMER0_GP_BIT15 0x8000
144 #define ELMER0_GP_BIT16 0x10000
145 #define ELMER0_GP_BIT17 0x20000
146 #define ELMER0_GP_BIT18 0x40000
147 #define ELMER0_GP_BIT19 0x80000
149 #define MI1_OP_DIRECT_WRITE 1
150 #define MI1_OP_DIRECT_READ 2
152 #define MI1_OP_INDIRECT_ADDRESS 0
153 #define MI1_OP_INDIRECT_WRITE 1
154 #define MI1_OP_INDIRECT_READ_INC 2
155 #define MI1_OP_INDIRECT_READ 3
157 #endif /* _CXGB_ELMER0_H_ */