git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20
  21 #define ATH_PCI_VERSION "0.1"
  22
  23 static char *dev_info = "ath9k";
  24
  25 MODULE_AUTHOR("Atheros Communications");
  26 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  27 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  28 MODULE_LICENSE("Dual BSD/GPL");
  29
  30 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  31         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  32         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  33         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  34         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  36         { 0 }
  37 };
  38
  39 static void ath_detach(struct ath_softc *sc);
  40
  41 /* return bus cachesize in 4B word units */
  42
  43 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  44 {
  45         u8 u8tmp;
  46
  47         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  48         *csz = (int)u8tmp;
  49
  50         /*
  51          * This check was put in to avoid "unplesant" consequences if
  52          * the bootrom has not fully initialized all PCI devices.
  53          * Sometimes the cache line size register is not set
  54          */
  55
  56         if (*csz == 0)
  57                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  58 }
  59
  60 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
  61 {
  62         sc->sc_curmode = mode;
  63         /*
  64          * All protection frames are transmited at 2Mb/s for
  65          * 11g, otherwise at 1Mb/s.
  66          * XXX select protection rate index from rate table.
  67          */
  68         sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
  69 }
  70
  71 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
  72 {
  73         if (chan->chanmode == CHANNEL_A)
  74                 return ATH9K_MODE_11A;
  75         else if (chan->chanmode == CHANNEL_G)
  76                 return ATH9K_MODE_11G;
  77         else if (chan->chanmode == CHANNEL_B)
  78                 return ATH9K_MODE_11B;
  79         else if (chan->chanmode == CHANNEL_A_HT20)
  80                 return ATH9K_MODE_11NA_HT20;
  81         else if (chan->chanmode == CHANNEL_G_HT20)
  82                 return ATH9K_MODE_11NG_HT20;
  83         else if (chan->chanmode == CHANNEL_A_HT40PLUS)
  84                 return ATH9K_MODE_11NA_HT40PLUS;
  85         else if (chan->chanmode == CHANNEL_A_HT40MINUS)
  86                 return ATH9K_MODE_11NA_HT40MINUS;
  87         else if (chan->chanmode == CHANNEL_G_HT40PLUS)
  88                 return ATH9K_MODE_11NG_HT40PLUS;
  89         else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  90                 return ATH9K_MODE_11NG_HT40MINUS;
  91
  92         WARN_ON(1); /* should not get here */
  93
  94         return ATH9K_MODE_11B;
  95 }
  96
  97 static void ath_update_txpow(struct ath_softc *sc)
  98 {
  99         struct ath_hal *ah = sc->sc_ah;
 100         u32 txpow;
 101
 102         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 103                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 104                 /* read back in case value is clamped */
 105                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 106                 sc->sc_curtxpow = txpow;
 107         }
 108 }
 109
 110 static u8 parse_mpdudensity(u8 mpdudensity)
 111 {
 112         /*
 113          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 114          *   0 for no restriction
 115          *   1 for 1/4 us
 116          *   2 for 1/2 us
 117          *   3 for 1 us
 118          *   4 for 2 us
 119          *   5 for 4 us
 120          *   6 for 8 us
 121          *   7 for 16 us
 122          */
 123         switch (mpdudensity) {
 124         case 0:
 125                 return 0;
 126         case 1:
 127         case 2:
 128         case 3:
 129                 /* Our lower layer calculations limit our precision to
 130                    1 microsecond */
 131                 return 1;
 132         case 4:
 133                 return 2;
 134         case 5:
 135                 return 4;
 136         case 6:
 137                 return 8;
 138         case 7:
 139                 return 16;
 140         default:
 141                 return 0;
 142         }
 143 }
 144
 145 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 146 {
 147         struct ath_rate_table *rate_table = NULL;
 148         struct ieee80211_supported_band *sband;
 149         struct ieee80211_rate *rate;
 150         int i, maxrates;
 151
 152         switch (band) {
 153         case IEEE80211_BAND_2GHZ:
 154                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 155                 break;
 156         case IEEE80211_BAND_5GHZ:
 157                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 158                 break;
 159         default:
 160                 break;
 161         }
 162
 163         if (rate_table == NULL)
 164                 return;
 165
 166         sband = &sc->sbands[band];
 167         rate = sc->rates[band];
 168
 169         if (rate_table->rate_cnt > ATH_RATE_MAX)
 170                 maxrates = ATH_RATE_MAX;
 171         else
 172                 maxrates = rate_table->rate_cnt;
 173
 174         for (i = 0; i < maxrates; i++) {
 175                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 176                 rate[i].hw_value = rate_table->info[i].ratecode;
 177                 sband->n_bitrates++;
 178                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Rate: %2dMbps, ratecode: %2d\n",
 179                         __func__, rate[i].bitrate / 10, rate[i].hw_value);
 180         }
 181 }
 182
 183 static int ath_setup_channels(struct ath_softc *sc)
 184 {
 185         struct ath_hal *ah = sc->sc_ah;
 186         int nchan, i, a = 0, b = 0;
 187         u8 regclassids[ATH_REGCLASSIDS_MAX];
 188         u32 nregclass = 0;
 189         struct ieee80211_supported_band *band_2ghz;
 190         struct ieee80211_supported_band *band_5ghz;
 191         struct ieee80211_channel *chan_2ghz;
 192         struct ieee80211_channel *chan_5ghz;
 193         struct ath9k_channel *c;
 194
 195         /* Fill in ah->ah_channels */
 196         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 197                                       regclassids, ATH_REGCLASSIDS_MAX,
 198                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 199                 u32 rd = ah->ah_currentRD;
 200                 DPRINTF(sc, ATH_DBG_FATAL,
 201                         "%s: unable to collect channel list; "
 202                         "regdomain likely %u country code %u\n",
 203                         __func__, rd, CTRY_DEFAULT);
 204                 return -EINVAL;
 205         }
 206
 207         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 208         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 209         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 210         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 211
 212         for (i = 0; i < nchan; i++) {
 213                 c = &ah->ah_channels[i];
 214                 if (IS_CHAN_2GHZ(c)) {
 215                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 216                         chan_2ghz[a].center_freq = c->channel;
 217                         chan_2ghz[a].max_power = c->maxTxPower;
 218
 219                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 220                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 221                         if (c->channelFlags & CHANNEL_PASSIVE)
 222                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 223
 224                         band_2ghz->n_channels = ++a;
 225
 226                         DPRINTF(sc, ATH_DBG_CONFIG, "%s: 2MHz channel: %d, "
 227                                 "channelFlags: 0x%x\n",
 228                                 __func__, c->channel, c->channelFlags);
 229                 } else if (IS_CHAN_5GHZ(c)) {
 230                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 231                         chan_5ghz[b].center_freq = c->channel;
 232                         chan_5ghz[b].max_power = c->maxTxPower;
 233
 234                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 235                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 236                         if (c->channelFlags & CHANNEL_PASSIVE)
 237                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 238
 239                         band_5ghz->n_channels = ++b;
 240
 241                         DPRINTF(sc, ATH_DBG_CONFIG, "%s: 5MHz channel: %d, "
 242                                 "channelFlags: 0x%x\n",
 243                                 __func__, c->channel, c->channelFlags);
 244                 }
 245         }
 246
 247         return 0;
 248 }
 249
 250 /*
 251  * Set/change channels.  If the channel is really being changed, it's done
 252  * by reseting the chip.  To accomplish this we must first cleanup any pending
 253  * DMA, then restart stuff.
 254 */
 255 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 256 {
 257         struct ath_hal *ah = sc->sc_ah;
 258         bool fastcc = true, stopped;
 259
 260         if (sc->sc_flags & SC_OP_INVALID)
 261                 return -EIO;
 262
 263         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 264             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 265             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 266             (sc->sc_flags & SC_OP_FULL_RESET)) {
 267                 int status;
 268                 /*
 269                  * This is only performed if the channel settings have
 270                  * actually changed.
 271                  *
 272                  * To switch channels clear any pending DMA operations;
 273                  * wait long enough for the RX fifo to drain, reset the
 274                  * hardware at the new frequency, and then re-enable
 275                  * the relevant bits of the h/w.
 276                  */
 277                 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
 278                 ath_draintxq(sc, false);        /* clear pending tx frames */
 279                 stopped = ath_stoprecv(sc);     /* turn off frame recv */
 280
 281                 /* XXX: do not flush receive queue here. We don't want
 282                  * to flush data frames already in queue because of
 283                  * changing channel. */
 284
 285                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 286                         fastcc = false;
 287
 288                 DPRINTF(sc, ATH_DBG_CONFIG,
 289                         "%s: (%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
 290                         __func__,
 291                         sc->sc_ah->ah_curchan->channel,
 292                         hchan->channel, hchan->channelFlags, sc->tx_chan_width);
 293
 294                 spin_lock_bh(&sc->sc_resetlock);
 295                 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
 296                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 297                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 298                         DPRINTF(sc, ATH_DBG_FATAL,
 299                                 "%s: unable to reset channel %u (%uMhz) "
 300                                 "flags 0x%x hal status %u\n", __func__,
 301                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 302                                                   hchan->channelFlags),
 303                                 hchan->channel, hchan->channelFlags, status);
 304                         spin_unlock_bh(&sc->sc_resetlock);
 305                         return -EIO;
 306                 }
 307                 spin_unlock_bh(&sc->sc_resetlock);
 308
 309                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 310                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 311
 312                 if (ath_startrecv(sc) != 0) {
 313                         DPRINTF(sc, ATH_DBG_FATAL,
 314                                 "%s: unable to restart recv logic\n", __func__);
 315                         return -EIO;
 316                 }
 317
 318                 ath_setcurmode(sc, ath_chan2mode(hchan));
 319                 ath_update_txpow(sc);
 320                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 321         }
 322         return 0;
 323 }
 324
 325 /*
 326  *  This routine performs the periodic noise floor calibration function
 327  *  that is used to adjust and optimize the chip performance.  This
 328  *  takes environmental changes (location, temperature) into account.
 329  *  When the task is complete, it reschedules itself depending on the
 330  *  appropriate interval that was calculated.
 331  */
 332 static void ath_ani_calibrate(unsigned long data)
 333 {
 334         struct ath_softc *sc;
 335         struct ath_hal *ah;
 336         bool longcal = false;
 337         bool shortcal = false;
 338         bool aniflag = false;
 339         unsigned int timestamp = jiffies_to_msecs(jiffies);
 340         u32 cal_interval;
 341
 342         sc = (struct ath_softc *)data;
 343         ah = sc->sc_ah;
 344
 345         /*
 346         * don't calibrate when we're scanning.
 347         * we are most likely not on our home channel.
 348         */
 349         if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)
 350                 return;
 351
 352         /* Long calibration runs independently of short calibration. */
 353         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 354                 longcal = true;
 355                 DPRINTF(sc, ATH_DBG_ANI, "%s: longcal @%lu\n",
 356                         __func__, jiffies);
 357                 sc->sc_ani.sc_longcal_timer = timestamp;
 358         }
 359
 360         /* Short calibration applies only while sc_caldone is false */
 361         if (!sc->sc_ani.sc_caldone) {
 362                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 363                     ATH_SHORT_CALINTERVAL) {
 364                         shortcal = true;
 365                         DPRINTF(sc, ATH_DBG_ANI, "%s: shortcal @%lu\n",
 366                                __func__, jiffies);
 367                         sc->sc_ani.sc_shortcal_timer = timestamp;
 368                         sc->sc_ani.sc_resetcal_timer = timestamp;
 369                 }
 370         } else {
 371                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 372                     ATH_RESTART_CALINTERVAL) {
 373                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 374                                                 &sc->sc_ani.sc_caldone);
 375                         if (sc->sc_ani.sc_caldone)
 376                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 377                 }
 378         }
 379
 380         /* Verify whether we must check ANI */
 381         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 382            ATH_ANI_POLLINTERVAL) {
 383                 aniflag = true;
 384                 sc->sc_ani.sc_checkani_timer = timestamp;
 385         }
 386
 387         /* Skip all processing if there's nothing to do. */
 388         if (longcal || shortcal || aniflag) {
 389                 /* Call ANI routine if necessary */
 390                 if (aniflag)
 391                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 392                                              ah->ah_curchan);
 393
 394                 /* Perform calibration if necessary */
 395                 if (longcal || shortcal) {
 396                         bool iscaldone = false;
 397
 398                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 399                                                sc->sc_rx_chainmask, longcal,
 400                                                &iscaldone)) {
 401                                 if (longcal)
 402                                         sc->sc_ani.sc_noise_floor =
 403                                                 ath9k_hw_getchan_noise(ah,
 404                                                                ah->ah_curchan);
 405
 406                                 DPRINTF(sc, ATH_DBG_ANI,
 407                                         "%s: calibrate chan %u/%x nf: %d\n",
 408                                          __func__,
 409                                         ah->ah_curchan->channel,
 410                                         ah->ah_curchan->channelFlags,
 411                                         sc->sc_ani.sc_noise_floor);
 412                         } else {
 413                                 DPRINTF(sc, ATH_DBG_ANY,
 414                                         "%s: calibrate chan %u/%x failed\n",
 415                                          __func__,
 416                                         ah->ah_curchan->channel,
 417                                         ah->ah_curchan->channelFlags);
 418                         }
 419                         sc->sc_ani.sc_caldone = iscaldone;
 420                 }
 421         }
 422
 423         /*
 424         * Set timer interval based on previous results.
 425         * The interval must be the shortest necessary to satisfy ANI,
 426         * short calibration and long calibration.
 427         */
 428
 429         cal_interval = ATH_ANI_POLLINTERVAL;
 430         if (!sc->sc_ani.sc_caldone)
 431                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 432
 433         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 434 }
 435
 436 /*
 437  * Update tx/rx chainmask. For legacy association,
 438  * hard code chainmask to 1x1, for 11n association, use
 439  * the chainmask configuration.
 440  */
 441 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 442 {
 443         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 444         if (is_ht) {
 445                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 446                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 447         } else {
 448                 sc->sc_tx_chainmask = 1;
 449                 sc->sc_rx_chainmask = 1;
 450         }
 451
 452         DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
 453                 __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 454 }
 455
 456 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 457 {
 458         struct ath_node *an;
 459
 460         an = (struct ath_node *)sta->drv_priv;
 461
 462         if (sc->sc_flags & SC_OP_TXAGGR)
 463                 ath_tx_node_init(sc, an);
 464
 465         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 466                              sta->ht_cap.ampdu_factor);
 467         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 468 }
 469
 470 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 471 {
 472         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 473
 474         if (sc->sc_flags & SC_OP_TXAGGR)
 475                 ath_tx_node_cleanup(sc, an);
 476 }
 477
 478 static void ath9k_tasklet(unsigned long data)
 479 {
 480         struct ath_softc *sc = (struct ath_softc *)data;
 481         u32 status = sc->sc_intrstatus;
 482
 483         if (status & ATH9K_INT_FATAL) {
 484                 /* need a chip reset */
 485                 ath_reset(sc, false);
 486                 return;
 487         } else {
 488
 489                 if (status &
 490                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 491                         spin_lock_bh(&sc->sc_rxflushlock);
 492                         ath_rx_tasklet(sc, 0);
 493                         spin_unlock_bh(&sc->sc_rxflushlock);
 494                 }
 495                 /* XXX: optimize this */
 496                 if (status & ATH9K_INT_TX)
 497                         ath_tx_tasklet(sc);
 498         }
 499
 500         /* re-enable hardware interrupt */
 501         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 502 }
 503
 504 static irqreturn_t ath_isr(int irq, void *dev)
 505 {
 506         struct ath_softc *sc = dev;
 507         struct ath_hal *ah = sc->sc_ah;
 508         enum ath9k_int status;
 509         bool sched = false;
 510
 511         do {
 512                 if (sc->sc_flags & SC_OP_INVALID) {
 513                         /*
 514                          * The hardware is not ready/present, don't
 515                          * touch anything. Note this can happen early
 516                          * on if the IRQ is shared.
 517                          */
 518                         return IRQ_NONE;
 519                 }
 520                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 521                         return IRQ_NONE;
 522                 }
 523
 524                 /*
 525                  * Figure out the reason(s) for the interrupt.  Note
 526                  * that the hal returns a pseudo-ISR that may include
 527                  * bits we haven't explicitly enabled so we mask the
 528                  * value to insure we only process bits we requested.
 529                  */
 530                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 531
 532                 status &= sc->sc_imask; /* discard unasked-for bits */
 533
 534                 /*
 535                  * If there are no status bits set, then this interrupt was not
 536                  * for me (should have been caught above).
 537                  */
 538                 if (!status)
 539                         return IRQ_NONE;
 540
 541                 sc->sc_intrstatus = status;
 542
 543                 if (status & ATH9K_INT_FATAL) {
 544                         /* need a chip reset */
 545                         sched = true;
 546                 } else if (status & ATH9K_INT_RXORN) {
 547                         /* need a chip reset */
 548                         sched = true;
 549                 } else {
 550                         if (status & ATH9K_INT_SWBA) {
 551                                 /* schedule a tasklet for beacon handling */
 552                                 tasklet_schedule(&sc->bcon_tasklet);
 553                         }
 554                         if (status & ATH9K_INT_RXEOL) {
 555                                 /*
 556                                  * NB: the hardware should re-read the link when
 557                                  *     RXE bit is written, but it doesn't work
 558                                  *     at least on older hardware revs.
 559                                  */
 560                                 sched = true;
 561                         }
 562
 563                         if (status & ATH9K_INT_TXURN)
 564                                 /* bump tx trigger level */
 565                                 ath9k_hw_updatetxtriglevel(ah, true);
 566                         /* XXX: optimize this */
 567                         if (status & ATH9K_INT_RX)
 568                                 sched = true;
 569                         if (status & ATH9K_INT_TX)
 570                                 sched = true;
 571                         if (status & ATH9K_INT_BMISS)
 572                                 sched = true;
 573                         /* carrier sense timeout */
 574                         if (status & ATH9K_INT_CST)
 575                                 sched = true;
 576                         if (status & ATH9K_INT_MIB) {
 577                                 /*
 578                                  * Disable interrupts until we service the MIB
 579                                  * interrupt; otherwise it will continue to
 580                                  * fire.
 581                                  */
 582                                 ath9k_hw_set_interrupts(ah, 0);
 583                                 /*
 584                                  * Let the hal handle the event. We assume
 585                                  * it will clear whatever condition caused
 586                                  * the interrupt.
 587                                  */
 588                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 589                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 590                         }
 591                         if (status & ATH9K_INT_TIM_TIMER) {
 592                                 if (!(ah->ah_caps.hw_caps &
 593                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 594                                         /* Clear RxAbort bit so that we can
 595                                          * receive frames */
 596                                         ath9k_hw_setrxabort(ah, 0);
 597                                         sched = true;
 598                                 }
 599                         }
 600                 }
 601         } while (0);
 602
 603         if (sched) {
 604                 /* turn off every interrupt except SWBA */
 605                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 606                 tasklet_schedule(&sc->intr_tq);
 607         }
 608
 609         return IRQ_HANDLED;
 610 }
 611
 612 static int ath_get_channel(struct ath_softc *sc,
 613                            struct ieee80211_channel *chan)
 614 {
 615         int i;
 616
 617         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 618                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 619                         return i;
 620         }
 621
 622         return -1;
 623 }
 624
 625 static u32 ath_get_extchanmode(struct ath_softc *sc,
 626                                struct ieee80211_channel *chan,
 627                                struct ieee80211_bss_conf *bss_conf)
 628 {
 629         u32 chanmode = 0;
 630         u8 ext_chan_offset = bss_conf->ht.secondary_channel_offset;
 631         enum ath9k_ht_macmode tx_chan_width = (bss_conf->ht.width_40_ok) ?
 632                 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
 633
 634         switch (chan->band) {
 635         case IEEE80211_BAND_2GHZ:
 636                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
 637                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 638                         chanmode = CHANNEL_G_HT20;
 639                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
 640                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 641                         chanmode = CHANNEL_G_HT40PLUS;
 642                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
 643                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 644                         chanmode = CHANNEL_G_HT40MINUS;
 645                 break;
 646         case IEEE80211_BAND_5GHZ:
 647                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
 648                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 649                         chanmode = CHANNEL_A_HT20;
 650                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
 651                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 652                         chanmode = CHANNEL_A_HT40PLUS;
 653                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
 654                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 655                         chanmode = CHANNEL_A_HT40MINUS;
 656                 break;
 657         default:
 658                 break;
 659         }
 660
 661         return chanmode;
 662 }
 663
 664 static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
 665 {
 666         ath9k_hw_keyreset(sc->sc_ah, keyix);
 667         if (freeslot)
 668                 clear_bit(keyix, sc->sc_keymap);
 669 }
 670
 671 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 672                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 673 {
 674         bool status;
 675
 676         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 677                 keyix, hk, mac, false);
 678
 679         return status != false;
 680 }
 681
 682 static int ath_setkey_tkip(struct ath_softc *sc,
 683                            struct ieee80211_key_conf *key,
 684                            struct ath9k_keyval *hk,
 685                            const u8 *addr)
 686 {
 687         u8 *key_rxmic = NULL;
 688         u8 *key_txmic = NULL;
 689
 690         key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 691         key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 692
 693         if (addr == NULL) {
 694                 /* Group key installation */
 695                 memcpy(hk->kv_mic,  key_rxmic, sizeof(hk->kv_mic));
 696                 return ath_keyset(sc, key->keyidx, hk, addr);
 697         }
 698         if (!sc->sc_splitmic) {
 699                 /*
 700                  * data key goes at first index,
 701                  * the hal handles the MIC keys at index+64.
 702                  */
 703                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 704                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 705                 return ath_keyset(sc, key->keyidx, hk, addr);
 706         }
 707         /*
 708          * TX key goes at first index, RX key at +32.
 709          * The hal handles the MIC keys at index+64.
 710          */
 711         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 712         if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
 713                 /* Txmic entry failed. No need to proceed further */
 714                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 715                         "%s Setting TX MIC Key Failed\n", __func__);
 716                 return 0;
 717         }
 718
 719         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 720         /* XXX delete tx key on failure? */
 721         return ath_keyset(sc, key->keyidx+32, hk, addr);
 722 }
 723
 724 static int ath_key_config(struct ath_softc *sc,
 725                           const u8 *addr,
 726                           struct ieee80211_key_conf *key)
 727 {
 728         struct ieee80211_vif *vif;
 729         struct ath9k_keyval hk;
 730         const u8 *mac = NULL;
 731         int ret = 0;
 732         enum nl80211_iftype opmode;
 733
 734         memset(&hk, 0, sizeof(hk));
 735
 736         switch (key->alg) {
 737         case ALG_WEP:
 738                 hk.kv_type = ATH9K_CIPHER_WEP;
 739                 break;
 740         case ALG_TKIP:
 741                 hk.kv_type = ATH9K_CIPHER_TKIP;
 742                 break;
 743         case ALG_CCMP:
 744                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 745                 break;
 746         default:
 747                 return -EINVAL;
 748         }
 749
 750         hk.kv_len  = key->keylen;
 751         memcpy(hk.kv_val, key->key, key->keylen);
 752
 753         if (!sc->sc_vaps[0])
 754                 return -EIO;
 755
 756         vif = sc->sc_vaps[0];
 757         opmode = vif->type;
 758
 759         /*
 760          *  Strategy:
 761          *   For _M_STA mc tx, we will not setup a key at all since we never
 762          *   tx mc.
 763          *   _M_STA mc rx, we will use the keyID.
 764          *   for _M_IBSS mc tx, we will use the keyID, and no macaddr.
 765          *   for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
 766          *   peer node. BUT we will plumb a cleartext key so that we can do
 767          *   perSta default key table lookup in software.
 768          */
 769         if (is_broadcast_ether_addr(addr)) {
 770                 switch (opmode) {
 771                 case NL80211_IFTYPE_STATION:
 772                         /* default key:  could be group WPA key
 773                          * or could be static WEP key */
 774                         mac = NULL;
 775                         break;
 776                 case NL80211_IFTYPE_ADHOC:
 777                         break;
 778                 case NL80211_IFTYPE_AP:
 779                         break;
 780                 default:
 781                         ASSERT(0);
 782                         break;
 783                 }
 784         } else {
 785                 mac = addr;
 786         }
 787
 788         if (key->alg == ALG_TKIP)
 789                 ret = ath_setkey_tkip(sc, key, &hk, mac);
 790         else
 791                 ret = ath_keyset(sc, key->keyidx, &hk, mac);
 792
 793         if (!ret)
 794                 return -EIO;
 795
 796         return 0;
 797 }
 798
 799 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 800 {
 801         int freeslot;
 802
 803         freeslot = (key->keyidx >= 4) ? 1 : 0;
 804         ath_key_reset(sc, key->keyidx, freeslot);
 805 }
 806
 807 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 808 {
 809 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 810 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 811
 812         ht_info->ht_supported = true;
 813         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 814                        IEEE80211_HT_CAP_SM_PS |
 815                        IEEE80211_HT_CAP_SGI_40 |
 816                        IEEE80211_HT_CAP_DSSSCCK40;
 817
 818         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 819         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 820         /* set up supported mcs set */
 821         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 822         ht_info->mcs.rx_mask[0] = 0xff;
 823         ht_info->mcs.rx_mask[1] = 0xff;
 824         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 825 }
 826
 827 static void ath9k_ht_conf(struct ath_softc *sc,
 828                           struct ieee80211_bss_conf *bss_conf)
 829 {
 830         if (sc->hw->conf.ht.enabled) {
 831                 if (bss_conf->ht.width_40_ok)
 832                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
 833                 else
 834                         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
 835
 836                 ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width);
 837
 838                 DPRINTF(sc, ATH_DBG_CONFIG,
 839                         "%s: BSS Changed HT, chanwidth: %d\n",
 840                         __func__, sc->tx_chan_width);
 841         }
 842 }
 843
 844 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 845                                  struct ieee80211_vif *vif,
 846                                  struct ieee80211_bss_conf *bss_conf)
 847 {
 848         struct ieee80211_hw *hw = sc->hw;
 849         struct ieee80211_channel *curchan = hw->conf.channel;
 850         struct ath_vap *avp = (void *)vif->drv_priv;
 851         int pos;
 852
 853         if (bss_conf->assoc) {
 854                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
 855                         __func__,
 856                         bss_conf->aid);
 857
 858                 /* New association, store aid */
 859                 if (avp->av_opmode == ATH9K_M_STA) {
 860                         sc->sc_curaid = bss_conf->aid;
 861                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 862                                                sc->sc_curaid);
 863                 }
 864
 865                 /* Configure the beacon */
 866                 ath_beacon_config(sc, 0);
 867                 sc->sc_flags |= SC_OP_BEACONS;
 868
 869                 /* Reset rssi stats */
 870                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 871                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 872                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 873                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 874
 875                 /* Update chainmask */
 876                 ath_update_chainmask(sc, hw->conf.ht.enabled);
 877
 878                 DPRINTF(sc, ATH_DBG_CONFIG,
 879                         "%s: bssid %pM aid 0x%x\n",
 880                         __func__,
 881                         sc->sc_curbssid, sc->sc_curaid);
 882
 883                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
 884                         __func__,
 885                         curchan->center_freq);
 886
 887                 pos = ath_get_channel(sc, curchan);
 888                 if (pos == -1) {
 889                         DPRINTF(sc, ATH_DBG_FATAL,
 890                                 "%s: Invalid channel\n", __func__);
 891                         return;
 892                 }
 893
 894                 if (hw->conf.ht.enabled) {
 895                         sc->sc_ah->ah_channels[pos].chanmode =
 896                                 ath_get_extchanmode(sc, curchan, bss_conf);
 897
 898                         if (bss_conf->ht.width_40_ok)
 899                                 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
 900                         else
 901                                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
 902                 } else {
 903                         sc->sc_ah->ah_channels[pos].chanmode =
 904                                 (curchan->band == IEEE80211_BAND_2GHZ) ?
 905                                 CHANNEL_G : CHANNEL_A;
 906                 }
 907
 908                 /* set h/w channel */
 909                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
 910                         DPRINTF(sc, ATH_DBG_FATAL,
 911                                 "%s: Unable to set channel\n", __func__);
 912                 /* Start ANI */
 913                 mod_timer(&sc->sc_ani.timer,
 914                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 915
 916         } else {
 917                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info DISSOC\n", __func__);
 918                 sc->sc_curaid = 0;
 919         }
 920 }
 921
 922 /********************************/
 923 /*       LED functions          */
 924 /********************************/
 925
 926 static void ath_led_brightness(struct led_classdev *led_cdev,
 927                                enum led_brightness brightness)
 928 {
 929         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 930         struct ath_softc *sc = led->sc;
 931
 932         switch (brightness) {
 933         case LED_OFF:
 934                 if (led->led_type == ATH_LED_ASSOC ||
 935                     led->led_type == ATH_LED_RADIO)
 936                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 937                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 938                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 939                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 940                 break;
 941         case LED_FULL:
 942                 if (led->led_type == ATH_LED_ASSOC)
 943                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 944                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 945                 break;
 946         default:
 947                 break;
 948         }
 949 }
 950
 951 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 952                             char *trigger)
 953 {
 954         int ret;
 955
 956         led->sc = sc;
 957         led->led_cdev.name = led->name;
 958         led->led_cdev.default_trigger = trigger;
 959         led->led_cdev.brightness_set = ath_led_brightness;
 960
 961         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 962         if (ret)
 963                 DPRINTF(sc, ATH_DBG_FATAL,
 964                         "Failed to register led:%s", led->name);
 965         else
 966                 led->registered = 1;
 967         return ret;
 968 }
 969
 970 static void ath_unregister_led(struct ath_led *led)
 971 {
 972         if (led->registered) {
 973                 led_classdev_unregister(&led->led_cdev);
 974                 led->registered = 0;
 975         }
 976 }
 977
 978 static void ath_deinit_leds(struct ath_softc *sc)
 979 {
 980         ath_unregister_led(&sc->assoc_led);
 981         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 982         ath_unregister_led(&sc->tx_led);
 983         ath_unregister_led(&sc->rx_led);
 984         ath_unregister_led(&sc->radio_led);
 985         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 986 }
 987
 988 static void ath_init_leds(struct ath_softc *sc)
 989 {
 990         char *trigger;
 991         int ret;
 992
 993         /* Configure gpio 1 for output */
 994         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
 995                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 996         /* LED off, active low */
 997         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 998
 999         trigger = ieee80211_get_radio_led_name(sc->hw);
1000         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1001                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1002         ret = ath_register_led(sc, &sc->radio_led, trigger);
1003         sc->radio_led.led_type = ATH_LED_RADIO;
1004         if (ret)
1005                 goto fail;
1006
1007         trigger = ieee80211_get_assoc_led_name(sc->hw);
1008         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1009                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1010         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1011         sc->assoc_led.led_type = ATH_LED_ASSOC;
1012         if (ret)
1013                 goto fail;
1014
1015         trigger = ieee80211_get_tx_led_name(sc->hw);
1016         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1017                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1018         ret = ath_register_led(sc, &sc->tx_led, trigger);
1019         sc->tx_led.led_type = ATH_LED_TX;
1020         if (ret)
1021                 goto fail;
1022
1023         trigger = ieee80211_get_rx_led_name(sc->hw);
1024         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1025                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1026         ret = ath_register_led(sc, &sc->rx_led, trigger);
1027         sc->rx_led.led_type = ATH_LED_RX;
1028         if (ret)
1029                 goto fail;
1030
1031         return;
1032
1033 fail:
1034         ath_deinit_leds(sc);
1035 }
1036
1037 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1038
1039 /*******************/
1040 /*      Rfkill     */
1041 /*******************/
1042
1043 static void ath_radio_enable(struct ath_softc *sc)
1044 {
1045         struct ath_hal *ah = sc->sc_ah;
1046         int status;
1047
1048         spin_lock_bh(&sc->sc_resetlock);
1049         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1050                             sc->tx_chan_width,
1051                             sc->sc_tx_chainmask,
1052                             sc->sc_rx_chainmask,
1053                             sc->sc_ht_extprotspacing,
1054                             false, &status)) {
1055                 DPRINTF(sc, ATH_DBG_FATAL,
1056                         "%s: unable to reset channel %u (%uMhz) "
1057                         "flags 0x%x hal status %u\n", __func__,
1058                         ath9k_hw_mhz2ieee(ah,
1059                                           ah->ah_curchan->channel,
1060                                           ah->ah_curchan->channelFlags),
1061                         ah->ah_curchan->channel,
1062                         ah->ah_curchan->channelFlags, status);
1063         }
1064         spin_unlock_bh(&sc->sc_resetlock);
1065
1066         ath_update_txpow(sc);
1067         if (ath_startrecv(sc) != 0) {
1068                 DPRINTF(sc, ATH_DBG_FATAL,
1069                         "%s: unable to restart recv logic\n", __func__);
1070                 return;
1071         }
1072
1073         if (sc->sc_flags & SC_OP_BEACONS)
1074                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1075
1076         /* Re-Enable  interrupts */
1077         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1078
1079         /* Enable LED */
1080         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1081                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1082         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1083
1084         ieee80211_wake_queues(sc->hw);
1085 }
1086
1087 static void ath_radio_disable(struct ath_softc *sc)
1088 {
1089         struct ath_hal *ah = sc->sc_ah;
1090         int status;
1091
1092
1093         ieee80211_stop_queues(sc->hw);
1094
1095         /* Disable LED */
1096         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1097         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1098
1099         /* Disable interrupts */
1100         ath9k_hw_set_interrupts(ah, 0);
1101
1102         ath_draintxq(sc, false);        /* clear pending tx frames */
1103         ath_stoprecv(sc);               /* turn off frame recv */
1104         ath_flushrecv(sc);              /* flush recv queue */
1105
1106         spin_lock_bh(&sc->sc_resetlock);
1107         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1108                             sc->tx_chan_width,
1109                             sc->sc_tx_chainmask,
1110                             sc->sc_rx_chainmask,
1111                             sc->sc_ht_extprotspacing,
1112                             false, &status)) {
1113                 DPRINTF(sc, ATH_DBG_FATAL,
1114                         "%s: unable to reset channel %u (%uMhz) "
1115                         "flags 0x%x hal status %u\n", __func__,
1116                         ath9k_hw_mhz2ieee(ah,
1117                                 ah->ah_curchan->channel,
1118                                 ah->ah_curchan->channelFlags),
1119                         ah->ah_curchan->channel,
1120                         ah->ah_curchan->channelFlags, status);
1121         }
1122         spin_unlock_bh(&sc->sc_resetlock);
1123
1124         ath9k_hw_phy_disable(ah);
1125         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1126 }
1127
1128 static bool ath_is_rfkill_set(struct ath_softc *sc)
1129 {
1130         struct ath_hal *ah = sc->sc_ah;
1131
1132         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1133                                   ah->ah_rfkill_polarity;
1134 }
1135
1136 /* h/w rfkill poll function */
1137 static void ath_rfkill_poll(struct work_struct *work)
1138 {
1139         struct ath_softc *sc = container_of(work, struct ath_softc,
1140                                             rf_kill.rfkill_poll.work);
1141         bool radio_on;
1142
1143         if (sc->sc_flags & SC_OP_INVALID)
1144                 return;
1145
1146         radio_on = !ath_is_rfkill_set(sc);
1147
1148         /*
1149          * enable/disable radio only when there is a
1150          * state change in RF switch
1151          */
1152         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1153                 enum rfkill_state state;
1154
1155                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1156                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1157                                 : RFKILL_STATE_HARD_BLOCKED;
1158                 } else if (radio_on) {
1159                         ath_radio_enable(sc);
1160                         state = RFKILL_STATE_UNBLOCKED;
1161                 } else {
1162                         ath_radio_disable(sc);
1163                         state = RFKILL_STATE_HARD_BLOCKED;
1164                 }
1165
1166                 if (state == RFKILL_STATE_HARD_BLOCKED)
1167                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1168                 else
1169                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1170
1171                 rfkill_force_state(sc->rf_kill.rfkill, state);
1172         }
1173
1174         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1175                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1176 }
1177
1178 /* s/w rfkill handler */
1179 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1180 {
1181         struct ath_softc *sc = data;
1182
1183         switch (state) {
1184         case RFKILL_STATE_SOFT_BLOCKED:
1185                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1186                     SC_OP_RFKILL_SW_BLOCKED)))
1187                         ath_radio_disable(sc);
1188                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1189                 return 0;
1190         case RFKILL_STATE_UNBLOCKED:
1191                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1192                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1193                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1194                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1195                                         "radio as it is disabled by h/w \n");
1196                                 return -EPERM;
1197                         }
1198                         ath_radio_enable(sc);
1199                 }
1200                 return 0;
1201         default:
1202                 return -EINVAL;
1203         }
1204 }
1205
1206 /* Init s/w rfkill */
1207 static int ath_init_sw_rfkill(struct ath_softc *sc)
1208 {
1209         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1210                                              RFKILL_TYPE_WLAN);
1211         if (!sc->rf_kill.rfkill) {
1212                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1213                 return -ENOMEM;
1214         }
1215
1216         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1217                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1218         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1219         sc->rf_kill.rfkill->data = sc;
1220         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1221         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1222         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1223
1224         return 0;
1225 }
1226
1227 /* Deinitialize rfkill */
1228 static void ath_deinit_rfkill(struct ath_softc *sc)
1229 {
1230         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1231                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1232
1233         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1234                 rfkill_unregister(sc->rf_kill.rfkill);
1235                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1236                 sc->rf_kill.rfkill = NULL;
1237         }
1238 }
1239
1240 static int ath_start_rfkill_poll(struct ath_softc *sc)
1241 {
1242         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1243                 queue_delayed_work(sc->hw->workqueue,
1244                                    &sc->rf_kill.rfkill_poll, 0);
1245
1246         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1247                 if (rfkill_register(sc->rf_kill.rfkill)) {
1248                         DPRINTF(sc, ATH_DBG_FATAL,
1249                                 "Unable to register rfkill\n");
1250                         rfkill_free(sc->rf_kill.rfkill);
1251
1252                         /* Deinitialize the device */
1253                         ath_detach(sc);
1254                         if (sc->pdev->irq)
1255                                 free_irq(sc->pdev->irq, sc);
1256                         pci_iounmap(sc->pdev, sc->mem);
1257                         pci_release_region(sc->pdev, 0);
1258                         pci_disable_device(sc->pdev);
1259                         ieee80211_free_hw(sc->hw);
1260                         return -EIO;
1261                 } else {
1262                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1263                 }
1264         }
1265
1266         return 0;
1267 }
1268 #endif /* CONFIG_RFKILL */
1269
1270 static void ath_detach(struct ath_softc *sc)
1271 {
1272         struct ieee80211_hw *hw = sc->hw;
1273         int i = 0;
1274
1275         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
1276
1277 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1278         ath_deinit_rfkill(sc);
1279 #endif
1280         ath_deinit_leds(sc);
1281
1282         ieee80211_unregister_hw(hw);
1283
1284         ath_rate_control_unregister();
1285
1286         ath_rx_cleanup(sc);
1287         ath_tx_cleanup(sc);
1288
1289         tasklet_kill(&sc->intr_tq);
1290         tasklet_kill(&sc->bcon_tasklet);
1291
1292         if (!(sc->sc_flags & SC_OP_INVALID))
1293                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1294
1295         /* cleanup tx queues */
1296         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1297                 if (ATH_TXQ_SETUP(sc, i))
1298                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1299
1300         ath9k_hw_detach(sc->sc_ah);
1301 }
1302
1303 static int ath_init(u16 devid, struct ath_softc *sc)
1304 {
1305         struct ath_hal *ah = NULL;
1306         int status;
1307         int error = 0, i;
1308         int csz = 0;
1309
1310         /* XXX: hardware will not be ready until ath_open() being called */
1311         sc->sc_flags |= SC_OP_INVALID;
1312         sc->sc_debug = DBG_DEFAULT;
1313
1314         spin_lock_init(&sc->sc_resetlock);
1315         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1316         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1317                      (unsigned long)sc);
1318
1319         /*
1320          * Cache line size is used to size and align various
1321          * structures used to communicate with the hardware.
1322          */
1323         bus_read_cachesize(sc, &csz);
1324         /* XXX assert csz is non-zero */
1325         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1326
1327         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1328         if (ah == NULL) {
1329                 DPRINTF(sc, ATH_DBG_FATAL,
1330                         "%s: unable to attach hardware; HAL status %u\n",
1331                         __func__, status);
1332                 error = -ENXIO;
1333                 goto bad;
1334         }
1335         sc->sc_ah = ah;
1336
1337         /* Get the hardware key cache size. */
1338         sc->sc_keymax = ah->ah_caps.keycache_size;
1339         if (sc->sc_keymax > ATH_KEYMAX) {
1340                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1341                         "%s: Warning, using only %u entries in %u key cache\n",
1342                         __func__, ATH_KEYMAX, sc->sc_keymax);
1343                 sc->sc_keymax = ATH_KEYMAX;
1344         }
1345
1346         /*
1347          * Reset the key cache since some parts do not
1348          * reset the contents on initial power up.
1349          */
1350         for (i = 0; i < sc->sc_keymax; i++)
1351                 ath9k_hw_keyreset(ah, (u16) i);
1352         /*
1353          * Mark key cache slots associated with global keys
1354          * as in use.  If we knew TKIP was not to be used we
1355          * could leave the +32, +64, and +32+64 slots free.
1356          * XXX only for splitmic.
1357          */
1358         for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1359                 set_bit(i, sc->sc_keymap);
1360                 set_bit(i + 32, sc->sc_keymap);
1361                 set_bit(i + 64, sc->sc_keymap);
1362                 set_bit(i + 32 + 64, sc->sc_keymap);
1363         }
1364
1365         /* Collect the channel list using the default country code */
1366
1367         error = ath_setup_channels(sc);
1368         if (error)
1369                 goto bad;
1370
1371         /* default to MONITOR mode */
1372         sc->sc_ah->ah_opmode = ATH9K_M_MONITOR;
1373
1374         /* Setup rate tables */
1375
1376         ath_rate_attach(sc);
1377         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1378         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1379
1380         /*
1381          * Allocate hardware transmit queues: one queue for
1382          * beacon frames and one data queue for each QoS
1383          * priority.  Note that the hal handles reseting
1384          * these queues at the needed time.
1385          */
1386         sc->sc_bhalq = ath_beaconq_setup(ah);
1387         if (sc->sc_bhalq == -1) {
1388                 DPRINTF(sc, ATH_DBG_FATAL,
1389                         "%s: unable to setup a beacon xmit queue\n", __func__);
1390                 error = -EIO;
1391                 goto bad2;
1392         }
1393         sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1394         if (sc->sc_cabq == NULL) {
1395                 DPRINTF(sc, ATH_DBG_FATAL,
1396                         "%s: unable to setup CAB xmit queue\n", __func__);
1397                 error = -EIO;
1398                 goto bad2;
1399         }
1400
1401         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1402         ath_cabq_update(sc);
1403
1404         for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1405                 sc->sc_haltype2q[i] = -1;
1406
1407         /* Setup data queues */
1408         /* NB: ensure BK queue is the lowest priority h/w queue */
1409         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1410                 DPRINTF(sc, ATH_DBG_FATAL,
1411                         "%s: unable to setup xmit queue for BK traffic\n",
1412                         __func__);
1413                 error = -EIO;
1414                 goto bad2;
1415         }
1416
1417         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1418                 DPRINTF(sc, ATH_DBG_FATAL,
1419                         "%s: unable to setup xmit queue for BE traffic\n",
1420                         __func__);
1421                 error = -EIO;
1422                 goto bad2;
1423         }
1424         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1425                 DPRINTF(sc, ATH_DBG_FATAL,
1426                         "%s: unable to setup xmit queue for VI traffic\n",
1427                         __func__);
1428                 error = -EIO;
1429                 goto bad2;
1430         }
1431         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1432                 DPRINTF(sc, ATH_DBG_FATAL,
1433                         "%s: unable to setup xmit queue for VO traffic\n",
1434                         __func__);
1435                 error = -EIO;
1436                 goto bad2;
1437         }
1438
1439         /* Initializes the noise floor to a reasonable default value.
1440          * Later on this will be updated during ANI processing. */
1441
1442         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1443         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1444
1445         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1446                                    ATH9K_CIPHER_TKIP, NULL)) {
1447                 /*
1448                  * Whether we should enable h/w TKIP MIC.
1449                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1450                  * report WMM capable, so it's always safe to turn on
1451                  * TKIP MIC in this case.
1452                  */
1453                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1454                                        0, 1, NULL);
1455         }
1456
1457         /*
1458          * Check whether the separate key cache entries
1459          * are required to handle both tx+rx MIC keys.
1460          * With split mic keys the number of stations is limited
1461          * to 27 otherwise 59.
1462          */
1463         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1464                                    ATH9K_CIPHER_TKIP, NULL)
1465             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1466                                       ATH9K_CIPHER_MIC, NULL)
1467             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1468                                       0, NULL))
1469                 sc->sc_splitmic = 1;
1470
1471         /* turn on mcast key search if possible */
1472         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1473                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1474                                              1, NULL);
1475
1476         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1477         sc->sc_config.txpowlimit_override = 0;
1478
1479         /* 11n Capabilities */
1480         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1481                 sc->sc_flags |= SC_OP_TXAGGR;
1482                 sc->sc_flags |= SC_OP_RXAGGR;
1483         }
1484
1485         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1486         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1487
1488         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1489         sc->sc_defant = ath9k_hw_getdefantenna(ah);
1490
1491         ath9k_hw_getmac(ah, sc->sc_myaddr);
1492         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1493                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1494                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1495                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1496         }
1497
1498         sc->sc_slottime = ATH9K_SLOT_TIME_9;    /* default to short slot time */
1499
1500         /* initialize beacon slots */
1501         for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1502                 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1503
1504         /* save MISC configurations */
1505         sc->sc_config.swBeaconProcess = 1;
1506
1507 #ifdef CONFIG_SLOW_ANT_DIV
1508         /* range is 40 - 255, we use something in the middle */
1509         ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1510 #endif
1511
1512         /* setup channels and rates */
1513
1514         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1515                 sc->channels[IEEE80211_BAND_2GHZ];
1516         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1517                 sc->rates[IEEE80211_BAND_2GHZ];
1518         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1519
1520         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1521                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1522                         sc->channels[IEEE80211_BAND_5GHZ];
1523                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1524                         sc->rates[IEEE80211_BAND_5GHZ];
1525                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1526         }
1527
1528         return 0;
1529 bad2:
1530         /* cleanup tx queues */
1531         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1532                 if (ATH_TXQ_SETUP(sc, i))
1533                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1534 bad:
1535         if (ah)
1536                 ath9k_hw_detach(ah);
1537
1538         return error;
1539 }
1540
1541 static int ath_attach(u16 devid, struct ath_softc *sc)
1542 {
1543         struct ieee80211_hw *hw = sc->hw;
1544         int error = 0;
1545
1546         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
1547
1548         error = ath_init(devid, sc);
1549         if (error != 0)
1550                 return error;
1551
1552         /* get mac address from hardware and set in mac80211 */
1553
1554         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1555
1556         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1557                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1558                 IEEE80211_HW_SIGNAL_DBM |
1559                 IEEE80211_HW_AMPDU_AGGREGATION;
1560
1561         hw->wiphy->interface_modes =
1562                 BIT(NL80211_IFTYPE_AP) |
1563                 BIT(NL80211_IFTYPE_STATION) |
1564                 BIT(NL80211_IFTYPE_ADHOC);
1565
1566         hw->queues = 4;
1567         hw->max_rates = 4;
1568         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1569         hw->sta_data_size = sizeof(struct ath_node);
1570         hw->vif_data_size = sizeof(struct ath_vap);
1571
1572         /* Register rate control */
1573         hw->rate_control_algorithm = "ath9k_rate_control";
1574         error = ath_rate_control_register();
1575         if (error != 0) {
1576                 DPRINTF(sc, ATH_DBG_FATAL,
1577                         "%s: Unable to register rate control "
1578                         "algorithm:%d\n", __func__, error);
1579                 ath_rate_control_unregister();
1580                 goto bad;
1581         }
1582
1583         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1584                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1585                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1586                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1587         }
1588
1589         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1590         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1591                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1592                         &sc->sbands[IEEE80211_BAND_5GHZ];
1593
1594         /* initialize tx/rx engine */
1595         error = ath_tx_init(sc, ATH_TXBUF);
1596         if (error != 0)
1597                 goto detach;
1598
1599         error = ath_rx_init(sc, ATH_RXBUF);
1600         if (error != 0)
1601                 goto detach;
1602
1603 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1604         /* Initialze h/w Rfkill */
1605         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1606                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1607
1608         /* Initialize s/w rfkill */
1609         if (ath_init_sw_rfkill(sc))
1610                 goto detach;
1611 #endif
1612
1613         error = ieee80211_register_hw(hw);
1614         if (error != 0) {
1615                 ath_rate_control_unregister();
1616                 goto bad;
1617         }
1618
1619         /* Initialize LED control */
1620         ath_init_leds(sc);
1621
1622         return 0;
1623 detach:
1624         ath_detach(sc);
1625 bad:
1626         return error;
1627 }
1628
1629 int ath_reset(struct ath_softc *sc, bool retry_tx)
1630 {
1631         struct ath_hal *ah = sc->sc_ah;
1632         int status;
1633         int error = 0;
1634
1635         ath9k_hw_set_interrupts(ah, 0);
1636         ath_draintxq(sc, retry_tx);
1637         ath_stoprecv(sc);
1638         ath_flushrecv(sc);
1639
1640         spin_lock_bh(&sc->sc_resetlock);
1641         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1642                             sc->tx_chan_width,
1643                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1644                             sc->sc_ht_extprotspacing, false, &status)) {
1645                 DPRINTF(sc, ATH_DBG_FATAL,
1646                         "%s: unable to reset hardware; hal status %u\n",
1647                         __func__, status);
1648                 error = -EIO;
1649         }
1650         spin_unlock_bh(&sc->sc_resetlock);
1651
1652         if (ath_startrecv(sc) != 0)
1653                 DPRINTF(sc, ATH_DBG_FATAL,
1654                         "%s: unable to start recv logic\n", __func__);
1655
1656         /*
1657          * We may be doing a reset in response to a request
1658          * that changes the channel so update any state that
1659          * might change as a result.
1660          */
1661         ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1662
1663         ath_update_txpow(sc);
1664
1665         if (sc->sc_flags & SC_OP_BEACONS)
1666                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1667
1668         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1669
1670         if (retry_tx) {
1671                 int i;
1672                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1673                         if (ATH_TXQ_SETUP(sc, i)) {
1674                                 spin_lock_bh(&sc->sc_txq[i].axq_lock);
1675                                 ath_txq_schedule(sc, &sc->sc_txq[i]);
1676                                 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
1677                         }
1678                 }
1679         }
1680
1681         return error;
1682 }
1683
1684 /*
1685  *  This function will allocate both the DMA descriptor structure, and the
1686  *  buffers it contains.  These are used to contain the descriptors used
1687  *  by the system.
1688 */
1689 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1690                       struct list_head *head, const char *name,
1691                       int nbuf, int ndesc)
1692 {
1693 #define DS2PHYS(_dd, _ds)                                               \
1694         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1695 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1696 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1697
1698         struct ath_desc *ds;
1699         struct ath_buf *bf;
1700         int i, bsize, error;
1701
1702         DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
1703                 __func__, name, nbuf, ndesc);
1704
1705         /* ath_desc must be a multiple of DWORDs */
1706         if ((sizeof(struct ath_desc) % 4) != 0) {
1707                 DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
1708                         __func__);
1709                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1710                 error = -ENOMEM;
1711                 goto fail;
1712         }
1713
1714         dd->dd_name = name;
1715         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1716
1717         /*
1718          * Need additional DMA memory because we can't use
1719          * descriptors that cross the 4K page boundary. Assume
1720          * one skipped descriptor per 4K page.
1721          */
1722         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1723                 u32 ndesc_skipped =
1724                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1725                 u32 dma_len;
1726
1727                 while (ndesc_skipped) {
1728                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1729                         dd->dd_desc_len += dma_len;
1730
1731                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1732                 };
1733         }
1734
1735         /* allocate descriptors */
1736         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1737                               dd->dd_desc_len,
1738                               &dd->dd_desc_paddr);
1739         if (dd->dd_desc == NULL) {
1740                 error = -ENOMEM;
1741                 goto fail;
1742         }
1743         ds = dd->dd_desc;
1744         DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
1745                 __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
1746                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1747
1748         /* allocate buffers */
1749         bsize = sizeof(struct ath_buf) * nbuf;
1750         bf = kmalloc(bsize, GFP_KERNEL);
1751         if (bf == NULL) {
1752                 error = -ENOMEM;
1753                 goto fail2;
1754         }
1755         memset(bf, 0, bsize);
1756         dd->dd_bufptr = bf;
1757
1758         INIT_LIST_HEAD(head);
1759         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1760                 bf->bf_desc = ds;
1761                 bf->bf_daddr = DS2PHYS(dd, ds);
1762
1763                 if (!(sc->sc_ah->ah_caps.hw_caps &
1764                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1765                         /*
1766                          * Skip descriptor addresses which can cause 4KB
1767                          * boundary crossing (addr + length) with a 32 dword
1768                          * descriptor fetch.
1769                          */
1770                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1771                                 ASSERT((caddr_t) bf->bf_desc <
1772                                        ((caddr_t) dd->dd_desc +
1773                                         dd->dd_desc_len));
1774
1775                                 ds += ndesc;
1776                                 bf->bf_desc = ds;
1777                                 bf->bf_daddr = DS2PHYS(dd, ds);
1778                         }
1779                 }
1780                 list_add_tail(&bf->list, head);
1781         }
1782         return 0;
1783 fail2:
1784         pci_free_consistent(sc->pdev,
1785                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1786 fail:
1787         memset(dd, 0, sizeof(*dd));
1788         return error;
1789 #undef ATH_DESC_4KB_BOUND_CHECK
1790 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1791 #undef DS2PHYS
1792 }
1793
1794 void ath_descdma_cleanup(struct ath_softc *sc,
1795                          struct ath_descdma *dd,
1796                          struct list_head *head)
1797 {
1798         pci_free_consistent(sc->pdev,
1799                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1800
1801         INIT_LIST_HEAD(head);
1802         kfree(dd->dd_bufptr);
1803         memset(dd, 0, sizeof(*dd));
1804 }
1805
1806 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1807 {
1808         int qnum;
1809
1810         switch (queue) {
1811         case 0:
1812                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1813                 break;
1814         case 1:
1815                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1816                 break;
1817         case 2:
1818                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1819                 break;
1820         case 3:
1821                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1822                 break;
1823         default:
1824                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1825                 break;
1826         }
1827
1828         return qnum;
1829 }
1830
1831 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1832 {
1833         int qnum;
1834
1835         switch (queue) {
1836         case ATH9K_WME_AC_VO:
1837                 qnum = 0;
1838                 break;
1839         case ATH9K_WME_AC_VI:
1840                 qnum = 1;
1841                 break;
1842         case ATH9K_WME_AC_BE:
1843                 qnum = 2;
1844                 break;
1845         case ATH9K_WME_AC_BK:
1846                 qnum = 3;
1847                 break;
1848         default:
1849                 qnum = -1;
1850                 break;
1851         }
1852
1853         return qnum;
1854 }
1855
1856 /**********************/
1857 /* mac80211 callbacks */
1858 /**********************/
1859
1860 static int ath9k_start(struct ieee80211_hw *hw)
1861 {
1862         struct ath_softc *sc = hw->priv;
1863         struct ieee80211_channel *curchan = hw->conf.channel;
1864         struct ath9k_channel *init_channel;
1865         int error = 0, pos, status;
1866
1867         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
1868                 "initial channel: %d MHz\n", __func__, curchan->center_freq);
1869
1870         /* setup initial channel */
1871
1872         pos = ath_get_channel(sc, curchan);
1873         if (pos == -1) {
1874                 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
1875                 error = -EINVAL;
1876                 goto error;
1877         }
1878
1879         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1880         sc->sc_ah->ah_channels[pos].chanmode =
1881                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1882         init_channel = &sc->sc_ah->ah_channels[pos];
1883
1884         /* Reset SERDES registers */
1885         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1886
1887         /*
1888          * The basic interface to setting the hardware in a good
1889          * state is ``reset''.  On return the hardware is known to
1890          * be powered up and with interrupts disabled.  This must
1891          * be followed by initialization of the appropriate bits
1892          * and then setup of the interrupt mask.
1893          */
1894         spin_lock_bh(&sc->sc_resetlock);
1895         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1896                             sc->tx_chan_width,
1897                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1898                             sc->sc_ht_extprotspacing, false, &status)) {
1899                 DPRINTF(sc, ATH_DBG_FATAL,
1900                         "%s: unable to reset hardware; hal status %u "
1901                         "(freq %u flags 0x%x)\n", __func__, status,
1902                         init_channel->channel, init_channel->channelFlags);
1903                 error = -EIO;
1904                 spin_unlock_bh(&sc->sc_resetlock);
1905                 goto error;
1906         }
1907         spin_unlock_bh(&sc->sc_resetlock);
1908
1909         /*
1910          * This is needed only to setup initial state
1911          * but it's best done after a reset.
1912          */
1913         ath_update_txpow(sc);
1914
1915         /*
1916          * Setup the hardware after reset:
1917          * The receive engine is set going.
1918          * Frame transmit is handled entirely
1919          * in the frame output path; there's nothing to do
1920          * here except setup the interrupt mask.
1921          */
1922         if (ath_startrecv(sc) != 0) {
1923                 DPRINTF(sc, ATH_DBG_FATAL,
1924                         "%s: unable to start recv logic\n", __func__);
1925                 error = -EIO;
1926                 goto error;
1927         }
1928
1929         /* Setup our intr mask. */
1930         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1931                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1932                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1933
1934         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1935                 sc->sc_imask |= ATH9K_INT_GTT;
1936
1937         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1938                 sc->sc_imask |= ATH9K_INT_CST;
1939
1940         /*
1941          * Enable MIB interrupts when there are hardware phy counters.
1942          * Note we only do this (at the moment) for station mode.
1943          */
1944         if (ath9k_hw_phycounters(sc->sc_ah) &&
1945             ((sc->sc_ah->ah_opmode == ATH9K_M_STA) ||
1946              (sc->sc_ah->ah_opmode == ATH9K_M_IBSS)))
1947                 sc->sc_imask |= ATH9K_INT_MIB;
1948         /*
1949          * Some hardware processes the TIM IE and fires an
1950          * interrupt when the TIM bit is set.  For hardware
1951          * that does, if not overridden by configuration,
1952          * enable the TIM interrupt when operating as station.
1953          */
1954         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1955             (sc->sc_ah->ah_opmode == ATH9K_M_STA) &&
1956             !sc->sc_config.swBeaconProcess)
1957                 sc->sc_imask |= ATH9K_INT_TIM;
1958
1959         ath_setcurmode(sc, ath_chan2mode(init_channel));
1960
1961         sc->sc_flags &= ~SC_OP_INVALID;
1962
1963         /* Disable BMISS interrupt when we're not associated */
1964         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1965         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1966
1967         ieee80211_wake_queues(sc->hw);
1968
1969 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1970         error = ath_start_rfkill_poll(sc);
1971 #endif
1972
1973 error:
1974         return error;
1975 }
1976
1977 static int ath9k_tx(struct ieee80211_hw *hw,
1978                     struct sk_buff *skb)
1979 {
1980         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1981         struct ath_softc *sc = hw->priv;
1982         struct ath_tx_control txctl;
1983         int hdrlen, padsize;
1984
1985         memset(&txctl, 0, sizeof(struct ath_tx_control));
1986
1987         /*
1988          * As a temporary workaround, assign seq# here; this will likely need
1989          * to be cleaned up to work better with Beacon transmission and virtual
1990          * BSSes.
1991          */
1992         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1993                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1994                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1995                         sc->seq_no += 0x10;
1996                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1997                 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
1998         }
1999
2000         /* Add the padding after the header if this is not already done */
2001         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2002         if (hdrlen & 3) {
2003                 padsize = hdrlen % 4;
2004                 if (skb_headroom(skb) < padsize)
2005                         return -1;
2006                 skb_push(skb, padsize);
2007                 memmove(skb->data, skb->data + padsize, hdrlen);
2008         }
2009
2010         /* Check if a tx queue is available */
2011
2012         txctl.txq = ath_test_get_txq(sc, skb);
2013         if (!txctl.txq)
2014                 goto exit;
2015
2016         DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
2017                 __func__,
2018                 skb);
2019
2020         if (ath_tx_start(sc, skb, &txctl) != 0) {
2021                 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
2022                 goto exit;
2023         }
2024
2025         return 0;
2026 exit:
2027         dev_kfree_skb_any(skb);
2028         return 0;
2029 }
2030
2031 static void ath9k_stop(struct ieee80211_hw *hw)
2032 {
2033         struct ath_softc *sc = hw->priv;
2034
2035         if (sc->sc_flags & SC_OP_INVALID) {
2036                 DPRINTF(sc, ATH_DBG_ANY, "%s: Device not present\n", __func__);
2037                 return;
2038         }
2039
2040         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Cleaning up\n", __func__);
2041
2042         ieee80211_stop_queues(sc->hw);
2043
2044         /* make sure h/w will not generate any interrupt
2045          * before setting the invalid flag. */
2046         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2047
2048         if (!(sc->sc_flags & SC_OP_INVALID)) {
2049                 ath_draintxq(sc, false);
2050                 ath_stoprecv(sc);
2051                 ath9k_hw_phy_disable(sc->sc_ah);
2052         } else
2053                 sc->sc_rxlink = NULL;
2054
2055 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2056         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2057                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2058 #endif
2059         /* disable HAL and put h/w to sleep */
2060         ath9k_hw_disable(sc->sc_ah);
2061         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2062
2063         sc->sc_flags |= SC_OP_INVALID;
2064
2065         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
2066 }
2067
2068 static int ath9k_add_interface(struct ieee80211_hw *hw,
2069                                struct ieee80211_if_init_conf *conf)
2070 {
2071         struct ath_softc *sc = hw->priv;
2072         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2073         int ic_opmode = 0;
2074
2075         /* Support only vap for now */
2076
2077         if (sc->sc_nvaps)
2078                 return -ENOBUFS;
2079
2080         switch (conf->type) {
2081         case NL80211_IFTYPE_STATION:
2082                 ic_opmode = ATH9K_M_STA;
2083                 break;
2084         case NL80211_IFTYPE_ADHOC:
2085                 ic_opmode = ATH9K_M_IBSS;
2086                 break;
2087         case NL80211_IFTYPE_AP:
2088                 ic_opmode = ATH9K_M_HOSTAP;
2089                 break;
2090         default:
2091                 DPRINTF(sc, ATH_DBG_FATAL,
2092                         "%s: Interface type %d not yet supported\n",
2093                         __func__, conf->type);
2094                 return -EOPNOTSUPP;
2095         }
2096
2097         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
2098                 __func__,
2099                 ic_opmode);
2100
2101         /* Set the VAP opmode */
2102         avp->av_opmode = ic_opmode;
2103         avp->av_bslot = -1;
2104
2105         if (ic_opmode == ATH9K_M_HOSTAP)
2106                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2107
2108         sc->sc_vaps[0] = conf->vif;
2109         sc->sc_nvaps++;
2110
2111         /* Set the device opmode */
2112         sc->sc_ah->ah_opmode = ic_opmode;
2113
2114         if (conf->type == NL80211_IFTYPE_AP) {
2115                 /* TODO: is this a suitable place to start ANI for AP mode? */
2116                 /* Start ANI */
2117                 mod_timer(&sc->sc_ani.timer,
2118                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2119         }
2120
2121         return 0;
2122 }
2123
2124 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2125                                    struct ieee80211_if_init_conf *conf)
2126 {
2127         struct ath_softc *sc = hw->priv;
2128         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2129
2130         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
2131
2132 #ifdef CONFIG_SLOW_ANT_DIV
2133         ath_slow_ant_div_stop(&sc->sc_antdiv);
2134 #endif
2135         /* Stop ANI */
2136         del_timer_sync(&sc->sc_ani.timer);
2137
2138         /* Reclaim beacon resources */
2139         if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
2140             sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
2141                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2142                 ath_beacon_return(sc, avp);
2143         }
2144
2145         sc->sc_flags &= ~SC_OP_BEACONS;
2146
2147         sc->sc_vaps[0] = NULL;
2148         sc->sc_nvaps--;
2149 }
2150
2151 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2152 {
2153         struct ath_softc *sc = hw->priv;
2154         struct ieee80211_conf *conf = &hw->conf;
2155
2156         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2157                 struct ieee80211_channel *curchan = hw->conf.channel;
2158                 int pos;
2159
2160                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
2161                         __func__, curchan->center_freq);
2162
2163                 pos = ath_get_channel(sc, curchan);
2164                 if (pos == -1) {
2165                         DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
2166                         return -EINVAL;
2167                 }
2168
2169                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2170                 sc->sc_ah->ah_channels[pos].chanmode =
2171                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2172                         CHANNEL_G : CHANNEL_A;
2173
2174                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
2175                         DPRINTF(sc, ATH_DBG_FATAL,
2176                                 "%s: Unable to set channel\n", __func__);
2177         }
2178
2179         if (changed & IEEE80211_CONF_CHANGE_HT)
2180                 ath_update_chainmask(sc, conf->ht.enabled);
2181
2182         if (changed & IEEE80211_CONF_CHANGE_POWER)
2183                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2184
2185         return 0;
2186 }
2187
2188 static int ath9k_config_interface(struct ieee80211_hw *hw,
2189                                   struct ieee80211_vif *vif,
2190                                   struct ieee80211_if_conf *conf)
2191 {
2192         struct ath_softc *sc = hw->priv;
2193         struct ath_hal *ah = sc->sc_ah;
2194         struct ath_vap *avp = (void *)vif->drv_priv;
2195         u32 rfilt = 0;
2196         int error, i;
2197
2198         /* TODO: Need to decide which hw opmode to use for multi-interface
2199          * cases */
2200         if (vif->type == NL80211_IFTYPE_AP &&
2201             ah->ah_opmode != ATH9K_M_HOSTAP) {
2202                 ah->ah_opmode = ATH9K_M_HOSTAP;
2203                 ath9k_hw_setopmode(ah);
2204                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2205                 /* Request full reset to get hw opmode changed properly */
2206                 sc->sc_flags |= SC_OP_FULL_RESET;
2207         }
2208
2209         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2210             !is_zero_ether_addr(conf->bssid)) {
2211                 switch (vif->type) {
2212                 case NL80211_IFTYPE_STATION:
2213                 case NL80211_IFTYPE_ADHOC:
2214                         /* Set BSSID */
2215                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2216                         sc->sc_curaid = 0;
2217                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2218                                                sc->sc_curaid);
2219
2220                         /* Set aggregation protection mode parameters */
2221                         sc->sc_config.ath_aggr_prot = 0;
2222
2223                         DPRINTF(sc, ATH_DBG_CONFIG,
2224                                 "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
2225                                 __func__, rfilt,
2226                                 sc->sc_curbssid, sc->sc_curaid);
2227
2228                         /* need to reconfigure the beacon */
2229                         sc->sc_flags &= ~SC_OP_BEACONS ;
2230
2231                         break;
2232                 default:
2233                         break;
2234                 }
2235         }
2236
2237         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2238             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2239              (vif->type == NL80211_IFTYPE_AP))) {
2240                 /*
2241                  * Allocate and setup the beacon frame.
2242                  *
2243                  * Stop any previous beacon DMA.  This may be
2244                  * necessary, for example, when an ibss merge
2245                  * causes reconfiguration; we may be called
2246                  * with beacon transmission active.
2247                  */
2248                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2249
2250                 error = ath_beacon_alloc(sc, 0);
2251                 if (error != 0)
2252                         return error;
2253
2254                 ath_beacon_sync(sc, 0);
2255         }
2256
2257         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2258         if ((avp->av_opmode != ATH9K_M_STA)) {
2259                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2260                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2261                                 ath9k_hw_keysetmac(sc->sc_ah,
2262                                                    (u16)i,
2263                                                    sc->sc_curbssid);
2264         }
2265
2266         /* Only legacy IBSS for now */
2267         if (vif->type == NL80211_IFTYPE_ADHOC)
2268                 ath_update_chainmask(sc, 0);
2269
2270         return 0;
2271 }
2272
2273 #define SUPPORTED_FILTERS                       \
2274         (FIF_PROMISC_IN_BSS |                   \
2275         FIF_ALLMULTI |                          \
2276         FIF_CONTROL |                           \
2277         FIF_OTHER_BSS |                         \
2278         FIF_BCN_PRBRESP_PROMISC |               \
2279         FIF_FCSFAIL)
2280
2281 /* FIXME: sc->sc_full_reset ? */
2282 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2283                                    unsigned int changed_flags,
2284                                    unsigned int *total_flags,
2285                                    int mc_count,
2286                                    struct dev_mc_list *mclist)
2287 {
2288         struct ath_softc *sc = hw->priv;
2289         u32 rfilt;
2290
2291         changed_flags &= SUPPORTED_FILTERS;
2292         *total_flags &= SUPPORTED_FILTERS;
2293
2294         sc->rx_filter = *total_flags;
2295         rfilt = ath_calcrxfilter(sc);
2296         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2297
2298         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2299                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2300                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2301         }
2302
2303         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
2304                 __func__, sc->rx_filter);
2305 }
2306
2307 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2308                              struct ieee80211_vif *vif,
2309                              enum sta_notify_cmd cmd,
2310                              struct ieee80211_sta *sta)
2311 {
2312         struct ath_softc *sc = hw->priv;
2313
2314         switch (cmd) {
2315         case STA_NOTIFY_ADD:
2316                 ath_node_attach(sc, sta);
2317                 break;
2318         case STA_NOTIFY_REMOVE:
2319                 ath_node_detach(sc, sta);
2320                 break;
2321         default:
2322                 break;
2323         }
2324 }
2325
2326 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2327                          u16 queue,
2328                          const struct ieee80211_tx_queue_params *params)
2329 {
2330         struct ath_softc *sc = hw->priv;
2331         struct ath9k_tx_queue_info qi;
2332         int ret = 0, qnum;
2333
2334         if (queue >= WME_NUM_AC)
2335                 return 0;
2336
2337         qi.tqi_aifs = params->aifs;
2338         qi.tqi_cwmin = params->cw_min;
2339         qi.tqi_cwmax = params->cw_max;
2340         qi.tqi_burstTime = params->txop;
2341         qnum = ath_get_hal_qnum(queue, sc);
2342
2343         DPRINTF(sc, ATH_DBG_CONFIG,
2344                 "%s: Configure tx [queue/halq] [%d/%d],  "
2345                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2346                 __func__,
2347                 queue,
2348                 qnum,
2349                 params->aifs,
2350                 params->cw_min,
2351                 params->cw_max,
2352                 params->txop);
2353
2354         ret = ath_txq_update(sc, qnum, &qi);
2355         if (ret)
2356                 DPRINTF(sc, ATH_DBG_FATAL,
2357                         "%s: TXQ Update failed\n", __func__);
2358
2359         return ret;
2360 }
2361
2362 static int ath9k_set_key(struct ieee80211_hw *hw,
2363                          enum set_key_cmd cmd,
2364                          const u8 *local_addr,
2365                          const u8 *addr,
2366                          struct ieee80211_key_conf *key)
2367 {
2368         struct ath_softc *sc = hw->priv;
2369         int ret = 0;
2370
2371         DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
2372
2373         switch (cmd) {
2374         case SET_KEY:
2375                 ret = ath_key_config(sc, addr, key);
2376                 if (!ret) {
2377                         set_bit(key->keyidx, sc->sc_keymap);
2378                         key->hw_key_idx = key->keyidx;
2379                         /* push IV and Michael MIC generation to stack */
2380                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2381                         if (key->alg == ALG_TKIP)
2382                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2383                 }
2384                 break;
2385         case DISABLE_KEY:
2386                 ath_key_delete(sc, key);
2387                 clear_bit(key->keyidx, sc->sc_keymap);
2388                 break;
2389         default:
2390                 ret = -EINVAL;
2391         }
2392
2393         return ret;
2394 }
2395
2396 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2397                                    struct ieee80211_vif *vif,
2398                                    struct ieee80211_bss_conf *bss_conf,
2399                                    u32 changed)
2400 {
2401         struct ath_softc *sc = hw->priv;
2402
2403         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2404                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
2405                         __func__,
2406                         bss_conf->use_short_preamble);
2407                 if (bss_conf->use_short_preamble)
2408                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2409                 else
2410                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2411         }
2412
2413         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2414                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
2415                         __func__,
2416                         bss_conf->use_cts_prot);
2417                 if (bss_conf->use_cts_prot &&
2418                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2419                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2420                 else
2421                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2422         }
2423
2424         if (changed & BSS_CHANGED_HT)
2425                 ath9k_ht_conf(sc, bss_conf);
2426
2427         if (changed & BSS_CHANGED_ASSOC) {
2428                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
2429                         __func__,
2430                         bss_conf->assoc);
2431                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2432         }
2433 }
2434
2435 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2436 {
2437         u64 tsf;
2438         struct ath_softc *sc = hw->priv;
2439         struct ath_hal *ah = sc->sc_ah;
2440
2441         tsf = ath9k_hw_gettsf64(ah);
2442
2443         return tsf;
2444 }
2445
2446 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2447 {
2448         struct ath_softc *sc = hw->priv;
2449         struct ath_hal *ah = sc->sc_ah;
2450
2451         ath9k_hw_reset_tsf(ah);
2452 }
2453
2454 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2455                        enum ieee80211_ampdu_mlme_action action,
2456                        struct ieee80211_sta *sta,
2457                        u16 tid, u16 *ssn)
2458 {
2459         struct ath_softc *sc = hw->priv;
2460         int ret = 0;
2461
2462         switch (action) {
2463         case IEEE80211_AMPDU_RX_START:
2464                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2465                         ret = -ENOTSUPP;
2466                 break;
2467         case IEEE80211_AMPDU_RX_STOP:
2468                 break;
2469         case IEEE80211_AMPDU_TX_START:
2470                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2471                 if (ret < 0)
2472                         DPRINTF(sc, ATH_DBG_FATAL,
2473                                 "%s: Unable to start TX aggregation\n",
2474                                 __func__);
2475                 else
2476                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2477                 break;
2478         case IEEE80211_AMPDU_TX_STOP:
2479                 ret = ath_tx_aggr_stop(sc, sta, tid);
2480                 if (ret < 0)
2481                         DPRINTF(sc, ATH_DBG_FATAL,
2482                                 "%s: Unable to stop TX aggregation\n",
2483                                 __func__);
2484
2485                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2486                 break;
2487         case IEEE80211_AMPDU_TX_RESUME:
2488                 ath_tx_aggr_resume(sc, sta, tid);
2489                 break;
2490         default:
2491                 DPRINTF(sc, ATH_DBG_FATAL,
2492                         "%s: Unknown AMPDU action\n", __func__);
2493         }
2494
2495         return ret;
2496 }
2497
2498 static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
2499 {
2500         return -EOPNOTSUPP;
2501 }
2502
2503 static struct ieee80211_ops ath9k_ops = {
2504         .tx                 = ath9k_tx,
2505         .start              = ath9k_start,
2506         .stop               = ath9k_stop,
2507         .add_interface      = ath9k_add_interface,
2508         .remove_interface   = ath9k_remove_interface,
2509         .config             = ath9k_config,
2510         .config_interface   = ath9k_config_interface,
2511         .configure_filter   = ath9k_configure_filter,
2512         .sta_notify         = ath9k_sta_notify,
2513         .conf_tx            = ath9k_conf_tx,
2514         .bss_info_changed   = ath9k_bss_info_changed,
2515         .set_key            = ath9k_set_key,
2516         .get_tsf            = ath9k_get_tsf,
2517         .reset_tsf          = ath9k_reset_tsf,
2518         .ampdu_action       = ath9k_ampdu_action,
2519         .set_frag_threshold = ath9k_no_fragmentation,
2520 };
2521
2522 static struct {
2523         u32 version;
2524         const char * name;
2525 } ath_mac_bb_names[] = {
2526         { AR_SREV_VERSION_5416_PCI,     "5416" },
2527         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2528         { AR_SREV_VERSION_9100,         "9100" },
2529         { AR_SREV_VERSION_9160,         "9160" },
2530         { AR_SREV_VERSION_9280,         "9280" },
2531         { AR_SREV_VERSION_9285,         "9285" }
2532 };
2533
2534 static struct {
2535         u16 version;
2536         const char * name;
2537 } ath_rf_names[] = {
2538         { 0,                            "5133" },
2539         { AR_RAD5133_SREV_MAJOR,        "5133" },
2540         { AR_RAD5122_SREV_MAJOR,        "5122" },
2541         { AR_RAD2133_SREV_MAJOR,        "2133" },
2542         { AR_RAD2122_SREV_MAJOR,        "2122" }
2543 };
2544
2545 /*
2546  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2547  */
2548
2549 static const char *
2550 ath_mac_bb_name(u32 mac_bb_version)
2551 {
2552         int i;
2553
2554         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2555                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2556                         return ath_mac_bb_names[i].name;
2557                 }
2558         }
2559
2560         return "????";
2561 }
2562
2563 /*
2564  * Return the RF name. "????" is returned if the RF is unknown.
2565  */
2566
2567 static const char *
2568 ath_rf_name(u16 rf_version)
2569 {
2570         int i;
2571
2572         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2573                 if (ath_rf_names[i].version == rf_version) {
2574                         return ath_rf_names[i].name;
2575                 }
2576         }
2577
2578         return "????";
2579 }
2580
2581 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2582 {
2583         void __iomem *mem;
2584         struct ath_softc *sc;
2585         struct ieee80211_hw *hw;
2586         u8 csz;
2587         u32 val;
2588         int ret = 0;
2589         struct ath_hal *ah;
2590
2591         if (pci_enable_device(pdev))
2592                 return -EIO;
2593
2594         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2595
2596         if (ret) {
2597                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2598                 goto bad;
2599         }
2600
2601         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2602
2603         if (ret) {
2604                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2605                         "DMA enable faled\n");
2606                 goto bad;
2607         }
2608
2609         /*
2610          * Cache line size is used to size and align various
2611          * structures used to communicate with the hardware.
2612          */
2613         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2614         if (csz == 0) {
2615                 /*
2616                  * Linux 2.4.18 (at least) writes the cache line size
2617                  * register as a 16-bit wide register which is wrong.
2618                  * We must have this setup properly for rx buffer
2619                  * DMA to work so force a reasonable value here if it
2620                  * comes up zero.
2621                  */
2622                 csz = L1_CACHE_BYTES / sizeof(u32);
2623                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2624         }
2625         /*
2626          * The default setting of latency timer yields poor results,
2627          * set it to the value used by other systems. It may be worth
2628          * tweaking this setting more.
2629          */
2630         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2631
2632         pci_set_master(pdev);
2633
2634         /*
2635          * Disable the RETRY_TIMEOUT register (0x41) to keep
2636          * PCI Tx retries from interfering with C3 CPU state.
2637          */
2638         pci_read_config_dword(pdev, 0x40, &val);
2639         if ((val & 0x0000ff00) != 0)
2640                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2641
2642         ret = pci_request_region(pdev, 0, "ath9k");
2643         if (ret) {
2644                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2645                 ret = -ENODEV;
2646                 goto bad;
2647         }
2648
2649         mem = pci_iomap(pdev, 0, 0);
2650         if (!mem) {
2651                 printk(KERN_ERR "PCI memory map error\n") ;
2652                 ret = -EIO;
2653                 goto bad1;
2654         }
2655
2656         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2657         if (hw == NULL) {
2658                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2659                 goto bad2;
2660         }
2661
2662         SET_IEEE80211_DEV(hw, &pdev->dev);
2663         pci_set_drvdata(pdev, hw);
2664
2665         sc = hw->priv;
2666         sc->hw = hw;
2667         sc->pdev = pdev;
2668         sc->mem = mem;
2669
2670         if (ath_attach(id->device, sc) != 0) {
2671                 ret = -ENODEV;
2672                 goto bad3;
2673         }
2674
2675         /* setup interrupt service routine */
2676
2677         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2678                 printk(KERN_ERR "%s: request_irq failed\n",
2679                         wiphy_name(hw->wiphy));
2680                 ret = -EIO;
2681                 goto bad4;
2682         }
2683
2684         ah = sc->sc_ah;
2685         printk(KERN_INFO
2686                "%s: Atheros AR%s MAC/BB Rev:%x "
2687                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2688                wiphy_name(hw->wiphy),
2689                ath_mac_bb_name(ah->ah_macVersion),
2690                ah->ah_macRev,
2691                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2692                ah->ah_phyRev,
2693                (unsigned long)mem, pdev->irq);
2694
2695         return 0;
2696 bad4:
2697         ath_detach(sc);
2698 bad3:
2699         ieee80211_free_hw(hw);
2700 bad2:
2701         pci_iounmap(pdev, mem);
2702 bad1:
2703         pci_release_region(pdev, 0);
2704 bad:
2705         pci_disable_device(pdev);
2706         return ret;
2707 }
2708
2709 static void ath_pci_remove(struct pci_dev *pdev)
2710 {
2711         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2712         struct ath_softc *sc = hw->priv;
2713
2714         ath_detach(sc);
2715         if (pdev->irq)
2716                 free_irq(pdev->irq, sc);
2717         pci_iounmap(pdev, sc->mem);
2718         pci_release_region(pdev, 0);
2719         pci_disable_device(pdev);
2720         ieee80211_free_hw(hw);
2721 }
2722
2723 #ifdef CONFIG_PM
2724
2725 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2726 {
2727         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2728         struct ath_softc *sc = hw->priv;
2729
2730         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2731
2732 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2733         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2734                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2735 #endif
2736
2737         pci_save_state(pdev);
2738         pci_disable_device(pdev);
2739         pci_set_power_state(pdev, 3);
2740
2741         return 0;
2742 }
2743
2744 static int ath_pci_resume(struct pci_dev *pdev)
2745 {
2746         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2747         struct ath_softc *sc = hw->priv;
2748         u32 val;
2749         int err;
2750
2751         err = pci_enable_device(pdev);
2752         if (err)
2753                 return err;
2754         pci_restore_state(pdev);
2755         /*
2756          * Suspend/Resume resets the PCI configuration space, so we have to
2757          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2758          * PCI Tx retries from interfering with C3 CPU state
2759          */
2760         pci_read_config_dword(pdev, 0x40, &val);
2761         if ((val & 0x0000ff00) != 0)
2762                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2763
2764         /* Enable LED */
2765         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2766                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2767         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2768
2769 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2770         /*
2771          * check the h/w rfkill state on resume
2772          * and start the rfkill poll timer
2773          */
2774         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2775                 queue_delayed_work(sc->hw->workqueue,
2776                                    &sc->rf_kill.rfkill_poll, 0);
2777 #endif
2778
2779         return 0;
2780 }
2781
2782 #endif /* CONFIG_PM */
2783
2784 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2785
2786 static struct pci_driver ath_pci_driver = {
2787         .name       = "ath9k",
2788         .id_table   = ath_pci_id_table,
2789         .probe      = ath_pci_probe,
2790         .remove     = ath_pci_remove,
2791 #ifdef CONFIG_PM
2792         .suspend    = ath_pci_suspend,
2793         .resume     = ath_pci_resume,
2794 #endif /* CONFIG_PM */
2795 };
2796
2797 static int __init init_ath_pci(void)
2798 {
2799         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2800
2801         if (pci_register_driver(&ath_pci_driver) < 0) {
2802                 printk(KERN_ERR
2803                         "ath_pci: No devices found, driver not installed.\n");
2804                 pci_unregister_driver(&ath_pci_driver);
2805                 return -ENODEV;
2806         }
2807
2808         return 0;
2809 }
2810 module_init(init_ath_pci);
2811
2812 static void __exit exit_ath_pci(void)
2813 {
2814         pci_unregister_driver(&ath_pci_driver);
2815         printk(KERN_INFO "%s: driver unloaded\n", dev_info);
2816 }
2817 module_exit(exit_ath_pci);