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   1 /*
   2  * I/O SAPIC support.
   3  *
   4  * Copyright (C) 1999 Intel Corp.
   5  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   6  * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
   7  * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
   8  *      David Mosberger-Tang <davidm@hpl.hp.com>
   9  * Copyright (C) 1999 VA Linux Systems
  10  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  11  *
  12  * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O APIC code.
  13  *                              In particular, we now have separate handlers for edge
  14  *                              and level triggered interrupts.
  15  * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
  16  *                              PCI to vector mapping, shared PCI interrupts.
  17  * 00/10/27     D. Mosberger    Document things a bit more to make them more understandable.
  18  *                              Clean up much of the old IOSAPIC cruft.
  19  * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts and fixes for
  20  *                              ACPI S5(SoftOff) support.
  21  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
  22  * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt vectors in
  23  *                              iosapic_set_affinity(), initializations for
  24  *                              /proc/irq/#/smp_affinity
  25  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
  26  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
  27  * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
  28  *                              error
  29  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
  30  * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system interrupt, vector, etc.)
  31  * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's pci_irq code.
  32  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
  33  *                              Remove iosapic_address & gsi_base from external interfaces.
  34  *                              Rationalize __init/__devinit attributes.
  35  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
  36  *                              Updated to work with irq migration necessary for CPU Hotplug
  37  */
  38 /*
  39  * Here is what the interrupt logic between a PCI device and the kernel looks like:
  40  *
  41  * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD).  The
  42  *     device is uniquely identified by its bus--, and slot-number (the function
  43  *     number does not matter here because all functions share the same interrupt
  44  *     lines).
  45  *
  46  * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
  47  *     Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
  48  *     triggered and use the same polarity).  Each interrupt line has a unique Global
  49  *     System Interrupt (GSI) number which can be calculated as the sum of the controller's
  50  *     base GSI number and the IOSAPIC pin number to which the line connects.
  51  *
  52  * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
  53  *     into the IA-64 interrupt vector.  This interrupt vector is then sent to the CPU.
  54  *
  55  * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is used as
  56  *     architecture-independent interrupt handling mechanism in Linux.  As an
  57  *     IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
  58  *     mapping.  On smaller systems, we use one-to-one mapping between IA-64 vector and
  59  *     IRQ.  A platform can implement platform_irq_to_vector(irq) and
  60  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
  61  *     Please see also include/asm-ia64/hw_irq.h for those APIs.
  62  *
  63  * To sum up, there are three levels of mappings involved:
  64  *
  65  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  66  *
  67  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
  68  * Now we use "IRQ" only for Linux IRQ's.  ISA IRQ (isa_irq) is the only exception in this
  69  * source code.
  70  */
  71 #include <linux/config.h>
  72
  73 #include <linux/acpi.h>
  74 #include <linux/init.h>
  75 #include <linux/irq.h>
  76 #include <linux/kernel.h>
  77 #include <linux/list.h>
  78 #include <linux/pci.h>
  79 #include <linux/smp.h>
  80 #include <linux/smp_lock.h>
  81 #include <linux/string.h>
  82 #include <linux/bootmem.h>
  83
  84 #include <asm/delay.h>
  85 #include <asm/hw_irq.h>
  86 #include <asm/io.h>
  87 #include <asm/iosapic.h>
  88 #include <asm/machvec.h>
  89 #include <asm/processor.h>
  90 #include <asm/ptrace.h>
  91 #include <asm/system.h>
  92
  93
  94 #undef DEBUG_INTERRUPT_ROUTING
  95
  96 #ifdef DEBUG_INTERRUPT_ROUTING
  97 #define DBG(fmt...)     printk(fmt)
  98 #else
  99 #define DBG(fmt...)
 100 #endif
 101
 102 #define NR_PREALLOCATE_RTE_ENTRIES      (PAGE_SIZE / sizeof(struct iosapic_rte_info))
 103 #define RTE_PREALLOCATED        (1)
 104
 105 static DEFINE_SPINLOCK(iosapic_lock);
 106
 107 /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */
 108
 109 struct iosapic_rte_info {
 110         struct list_head rte_list;      /* node in list of RTEs sharing the same vector */
 111         char __iomem    *addr;          /* base address of IOSAPIC */
 112         unsigned int    gsi_base;       /* first GSI assigned to this IOSAPIC */
 113         char            rte_index;      /* IOSAPIC RTE index */
 114         int             refcnt;         /* reference counter */
 115         unsigned int    flags;          /* flags */
 116 } ____cacheline_aligned;
 117
 118 static struct iosapic_intr_info {
 119         struct list_head rtes;          /* RTEs using this vector (empty => not an IOSAPIC interrupt) */
 120         int             count;          /* # of RTEs that shares this vector */
 121         u32             low32;          /* current value of low word of Redirection table entry */
 122         unsigned int    dest;           /* destination CPU physical ID */
 123         unsigned char   dmode   : 3;    /* delivery mode (see iosapic.h) */
 124         unsigned char   polarity: 1;    /* interrupt polarity (see iosapic.h) */
 125         unsigned char   trigger : 1;    /* trigger mode (see iosapic.h) */
 126 } iosapic_intr_info[IA64_NUM_VECTORS];
 127
 128 static struct iosapic {
 129         char __iomem    *addr;          /* base address of IOSAPIC */
 130         unsigned int    gsi_base;       /* first GSI assigned to this IOSAPIC */
 131         unsigned short  num_rte;        /* number of RTE in this IOSAPIC */
 132 #ifdef CONFIG_NUMA
 133         unsigned short  node;           /* numa node association via pxm */
 134 #endif
 135 } iosapic_lists[NR_IOSAPICS];
 136
 137 static int num_iosapic;
 138
 139 static unsigned char pcat_compat __initdata;    /* 8259 compatibility flag */
 140
 141 static int iosapic_kmalloc_ok;
 142 static LIST_HEAD(free_rte_list);
 143
 144 /*
 145  * Find an IOSAPIC associated with a GSI
 146  */
 147 static inline int
 148 find_iosapic (unsigned int gsi)
 149 {
 150         int i;
 151
 152         for (i = 0; i < num_iosapic; i++) {
 153                 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte)
 154                         return i;
 155         }
 156
 157         return -1;
 158 }
 159
 160 static inline int
 161 _gsi_to_vector (unsigned int gsi)
 162 {
 163         struct iosapic_intr_info *info;
 164         struct iosapic_rte_info *rte;
 165
 166         for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info)
 167                 list_for_each_entry(rte, &info->rtes, rte_list)
 168                         if (rte->gsi_base + rte->rte_index == gsi)
 169                                 return info - iosapic_intr_info;
 170         return -1;
 171 }
 172
 173 /*
 174  * Translate GSI number to the corresponding IA-64 interrupt vector.  If no
 175  * entry exists, return -1.
 176  */
 177 inline int
 178 gsi_to_vector (unsigned int gsi)
 179 {
 180         return _gsi_to_vector(gsi);
 181 }
 182
 183 int
 184 gsi_to_irq (unsigned int gsi)
 185 {
 186         unsigned long flags;
 187         int irq;
 188         /*
 189          * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq
 190          * numbers...
 191          */
 192         spin_lock_irqsave(&iosapic_lock, flags);
 193         {
 194                 irq = _gsi_to_vector(gsi);
 195         }
 196         spin_unlock_irqrestore(&iosapic_lock, flags);
 197
 198         return irq;
 199 }
 200
 201 static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi, unsigned int vec)
 202 {
 203         struct iosapic_rte_info *rte;
 204
 205         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
 206                 if (rte->gsi_base + rte->rte_index == gsi)
 207                         return rte;
 208         return NULL;
 209 }
 210
 211 static void
 212 set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
 213 {
 214         unsigned long pol, trigger, dmode;
 215         u32 low32, high32;
 216         char __iomem *addr;
 217         int rte_index;
 218         char redir;
 219         struct iosapic_rte_info *rte;
 220
 221         DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
 222
 223         rte = gsi_vector_to_rte(gsi, vector);
 224         if (!rte)
 225                 return;         /* not an IOSAPIC interrupt */
 226
 227         rte_index = rte->rte_index;
 228         addr    = rte->addr;
 229         pol     = iosapic_intr_info[vector].polarity;
 230         trigger = iosapic_intr_info[vector].trigger;
 231         dmode   = iosapic_intr_info[vector].dmode;
 232
 233         redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
 234
 235 #ifdef CONFIG_SMP
 236         {
 237                 unsigned int irq;
 238
 239                 for (irq = 0; irq < NR_IRQS; ++irq)
 240                         if (irq_to_vector(irq) == vector) {
 241                                 set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
 242                                 break;
 243                         }
 244         }
 245 #endif
 246
 247         low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 248                  (trigger << IOSAPIC_TRIGGER_SHIFT) |
 249                  (dmode << IOSAPIC_DELIVERY_SHIFT) |
 250                  ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
 251                  vector);
 252
 253         /* dest contains both id and eid */
 254         high32 = (dest << IOSAPIC_DEST_SHIFT);
 255
 256         iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
 257         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 258         iosapic_intr_info[vector].low32 = low32;
 259         iosapic_intr_info[vector].dest = dest;
 260 }
 261
 262 static void
 263 nop (unsigned int vector)
 264 {
 265         /* do nothing... */
 266 }
 267
 268 static void
 269 mask_irq (unsigned int irq)
 270 {
 271         unsigned long flags;
 272         char __iomem *addr;
 273         u32 low32;
 274         int rte_index;
 275         ia64_vector vec = irq_to_vector(irq);
 276         struct iosapic_rte_info *rte;
 277
 278         if (list_empty(&iosapic_intr_info[vec].rtes))
 279                 return;                 /* not an IOSAPIC interrupt! */
 280
 281         spin_lock_irqsave(&iosapic_lock, flags);
 282         {
 283                 /* set only the mask bit */
 284                 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
 285                 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
 286                         addr = rte->addr;
 287                         rte_index = rte->rte_index;
 288                         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 289                 }
 290         }
 291         spin_unlock_irqrestore(&iosapic_lock, flags);
 292 }
 293
 294 static void
 295 unmask_irq (unsigned int irq)
 296 {
 297         unsigned long flags;
 298         char __iomem *addr;
 299         u32 low32;
 300         int rte_index;
 301         ia64_vector vec = irq_to_vector(irq);
 302         struct iosapic_rte_info *rte;
 303
 304         if (list_empty(&iosapic_intr_info[vec].rtes))
 305                 return;                 /* not an IOSAPIC interrupt! */
 306
 307         spin_lock_irqsave(&iosapic_lock, flags);
 308         {
 309                 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
 310                 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
 311                         addr = rte->addr;
 312                         rte_index = rte->rte_index;
 313                         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 314                 }
 315         }
 316         spin_unlock_irqrestore(&iosapic_lock, flags);
 317 }
 318
 319
 320 static void
 321 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
 322 {
 323 #ifdef CONFIG_SMP
 324         unsigned long flags;
 325         u32 high32, low32;
 326         int dest, rte_index;
 327         char __iomem *addr;
 328         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
 329         ia64_vector vec;
 330         struct iosapic_rte_info *rte;
 331
 332         irq &= (~IA64_IRQ_REDIRECTED);
 333         vec = irq_to_vector(irq);
 334
 335         if (cpus_empty(mask))
 336                 return;
 337
 338         dest = cpu_physical_id(first_cpu(mask));
 339
 340         if (list_empty(&iosapic_intr_info[vec].rtes))
 341                 return;                 /* not an IOSAPIC interrupt */
 342
 343         set_irq_affinity_info(irq, dest, redir);
 344
 345         /* dest contains both id and eid */
 346         high32 = dest << IOSAPIC_DEST_SHIFT;
 347
 348         spin_lock_irqsave(&iosapic_lock, flags);
 349         {
 350                 low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
 351
 352                 if (redir)
 353                         /* change delivery mode to lowest priority */
 354                         low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
 355                 else
 356                         /* change delivery mode to fixed */
 357                         low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 358
 359                 iosapic_intr_info[vec].low32 = low32;
 360                 iosapic_intr_info[vec].dest = dest;
 361                 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
 362                         addr = rte->addr;
 363                         rte_index = rte->rte_index;
 364                         iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
 365                         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 366                 }
 367         }
 368         spin_unlock_irqrestore(&iosapic_lock, flags);
 369 #endif
 370 }
 371
 372 /*
 373  * Handlers for level-triggered interrupts.
 374  */
 375
 376 static unsigned int
 377 iosapic_startup_level_irq (unsigned int irq)
 378 {
 379         unmask_irq(irq);
 380         return 0;
 381 }
 382
 383 static void
 384 iosapic_end_level_irq (unsigned int irq)
 385 {
 386         ia64_vector vec = irq_to_vector(irq);
 387         struct iosapic_rte_info *rte;
 388
 389         move_irq(irq);
 390         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
 391                 iosapic_eoi(rte->addr, vec);
 392 }
 393
 394 #define iosapic_shutdown_level_irq      mask_irq
 395 #define iosapic_enable_level_irq        unmask_irq
 396 #define iosapic_disable_level_irq       mask_irq
 397 #define iosapic_ack_level_irq           nop
 398
 399 struct hw_interrupt_type irq_type_iosapic_level = {
 400         .typename =     "IO-SAPIC-level",
 401         .startup =      iosapic_startup_level_irq,
 402         .shutdown =     iosapic_shutdown_level_irq,
 403         .enable =       iosapic_enable_level_irq,
 404         .disable =      iosapic_disable_level_irq,
 405         .ack =          iosapic_ack_level_irq,
 406         .end =          iosapic_end_level_irq,
 407         .set_affinity = iosapic_set_affinity
 408 };
 409
 410 /*
 411  * Handlers for edge-triggered interrupts.
 412  */
 413
 414 static unsigned int
 415 iosapic_startup_edge_irq (unsigned int irq)
 416 {
 417         unmask_irq(irq);
 418         /*
 419          * IOSAPIC simply drops interrupts pended while the
 420          * corresponding pin was masked, so we can't know if an
 421          * interrupt is pending already.  Let's hope not...
 422          */
 423         return 0;
 424 }
 425
 426 static void
 427 iosapic_ack_edge_irq (unsigned int irq)
 428 {
 429         irq_desc_t *idesc = irq_descp(irq);
 430
 431         move_irq(irq);
 432         /*
 433          * Once we have recorded IRQ_PENDING already, we can mask the
 434          * interrupt for real. This prevents IRQ storms from unhandled
 435          * devices.
 436          */
 437         if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED))
 438                 mask_irq(irq);
 439 }
 440
 441 #define iosapic_enable_edge_irq         unmask_irq
 442 #define iosapic_disable_edge_irq        nop
 443 #define iosapic_end_edge_irq            nop
 444
 445 struct hw_interrupt_type irq_type_iosapic_edge = {
 446         .typename =     "IO-SAPIC-edge",
 447         .startup =      iosapic_startup_edge_irq,
 448         .shutdown =     iosapic_disable_edge_irq,
 449         .enable =       iosapic_enable_edge_irq,
 450         .disable =      iosapic_disable_edge_irq,
 451         .ack =          iosapic_ack_edge_irq,
 452         .end =          iosapic_end_edge_irq,
 453         .set_affinity = iosapic_set_affinity
 454 };
 455
 456 unsigned int
 457 iosapic_version (char __iomem *addr)
 458 {
 459         /*
 460          * IOSAPIC Version Register return 32 bit structure like:
 461          * {
 462          *      unsigned int version   : 8;
 463          *      unsigned int reserved1 : 8;
 464          *      unsigned int max_redir : 8;
 465          *      unsigned int reserved2 : 8;
 466          * }
 467          */
 468         return iosapic_read(addr, IOSAPIC_VERSION);
 469 }
 470
 471 static int iosapic_find_sharable_vector (unsigned long trigger, unsigned long pol)
 472 {
 473         int i, vector = -1, min_count = -1;
 474         struct iosapic_intr_info *info;
 475
 476         /*
 477          * shared vectors for edge-triggered interrupts are not
 478          * supported yet
 479          */
 480         if (trigger == IOSAPIC_EDGE)
 481                 return -1;
 482
 483         for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) {
 484                 info = &iosapic_intr_info[i];
 485                 if (info->trigger == trigger && info->polarity == pol &&
 486                     (info->dmode == IOSAPIC_FIXED || info->dmode == IOSAPIC_LOWEST_PRIORITY)) {
 487                         if (min_count == -1 || info->count < min_count) {
 488                                 vector = i;
 489                                 min_count = info->count;
 490                         }
 491                 }
 492         }
 493         if (vector < 0)
 494                 panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 495
 496         return vector;
 497 }
 498
 499 /*
 500  * if the given vector is already owned by other,
 501  *  assign a new vector for the other and make the vector available
 502  */
 503 static void __init
 504 iosapic_reassign_vector (int vector)
 505 {
 506         int new_vector;
 507
 508         if (!list_empty(&iosapic_intr_info[vector].rtes)) {
 509                 new_vector = assign_irq_vector(AUTO_ASSIGN);
 510                 printk(KERN_INFO "Reassigning vector %d to %d\n", vector, new_vector);
 511                 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
 512                        sizeof(struct iosapic_intr_info));
 513                 INIT_LIST_HEAD(&iosapic_intr_info[new_vector].rtes);
 514                 list_move(iosapic_intr_info[vector].rtes.next, &iosapic_intr_info[new_vector].rtes);
 515                 memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
 516                 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
 517                 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
 518         }
 519 }
 520
 521 static struct iosapic_rte_info *iosapic_alloc_rte (void)
 522 {
 523         int i;
 524         struct iosapic_rte_info *rte;
 525         int preallocated = 0;
 526
 527         if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
 528                 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) * NR_PREALLOCATE_RTE_ENTRIES);
 529                 if (!rte)
 530                         return NULL;
 531                 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
 532                         list_add(&rte->rte_list, &free_rte_list);
 533         }
 534
 535         if (!list_empty(&free_rte_list)) {
 536                 rte = list_entry(free_rte_list.next, struct iosapic_rte_info, rte_list);
 537                 list_del(&rte->rte_list);
 538                 preallocated++;
 539         } else {
 540                 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
 541                 if (!rte)
 542                         return NULL;
 543         }
 544
 545         memset(rte, 0, sizeof(struct iosapic_rte_info));
 546         if (preallocated)
 547                 rte->flags |= RTE_PREALLOCATED;
 548
 549         return rte;
 550 }
 551
 552 static void iosapic_free_rte (struct iosapic_rte_info *rte)
 553 {
 554         if (rte->flags & RTE_PREALLOCATED)
 555                 list_add_tail(&rte->rte_list, &free_rte_list);
 556         else
 557                 kfree(rte);
 558 }
 559
 560 static inline int vector_is_shared (int vector)
 561 {
 562         return (iosapic_intr_info[vector].count > 1);
 563 }
 564
 565 static void
 566 register_intr (unsigned int gsi, int vector, unsigned char delivery,
 567                unsigned long polarity, unsigned long trigger)
 568 {
 569         irq_desc_t *idesc;
 570         struct hw_interrupt_type *irq_type;
 571         int rte_index;
 572         int index;
 573         unsigned long gsi_base;
 574         void __iomem *iosapic_address;
 575         struct iosapic_rte_info *rte;
 576
 577         index = find_iosapic(gsi);
 578         if (index < 0) {
 579                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", __FUNCTION__, gsi);
 580                 return;
 581         }
 582
 583         iosapic_address = iosapic_lists[index].addr;
 584         gsi_base = iosapic_lists[index].gsi_base;
 585
 586         rte = gsi_vector_to_rte(gsi, vector);
 587         if (!rte) {
 588                 rte = iosapic_alloc_rte();
 589                 if (!rte) {
 590                         printk(KERN_WARNING "%s: cannot allocate memory\n", __FUNCTION__);
 591                         return;
 592                 }
 593
 594                 rte_index = gsi - gsi_base;
 595                 rte->rte_index  = rte_index;
 596                 rte->addr       = iosapic_address;
 597                 rte->gsi_base   = gsi_base;
 598                 rte->refcnt++;
 599                 list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes);
 600                 iosapic_intr_info[vector].count++;
 601         }
 602         else if (vector_is_shared(vector)) {
 603                 struct iosapic_intr_info *info = &iosapic_intr_info[vector];
 604                 if (info->trigger != trigger || info->polarity != polarity) {
 605                         printk (KERN_WARNING "%s: cannot override the interrupt\n", __FUNCTION__);
 606                         return;
 607                 }
 608         }
 609
 610         iosapic_intr_info[vector].polarity = polarity;
 611         iosapic_intr_info[vector].dmode    = delivery;
 612         iosapic_intr_info[vector].trigger  = trigger;
 613
 614         if (trigger == IOSAPIC_EDGE)
 615                 irq_type = &irq_type_iosapic_edge;
 616         else
 617                 irq_type = &irq_type_iosapic_level;
 618
 619         idesc = irq_descp(vector);
 620         if (idesc->handler != irq_type) {
 621                 if (idesc->handler != &no_irq_type)
 622                         printk(KERN_WARNING "%s: changing vector %d from %s to %s\n",
 623                                __FUNCTION__, vector, idesc->handler->typename, irq_type->typename);
 624                 idesc->handler = irq_type;
 625         }
 626 }
 627
 628 static unsigned int
 629 get_target_cpu (unsigned int gsi, int vector)
 630 {
 631 #ifdef CONFIG_SMP
 632         static int cpu = -1;
 633
 634         /*
 635          * In case of vector shared by multiple RTEs, all RTEs that
 636          * share the vector need to use the same destination CPU.
 637          */
 638         if (!list_empty(&iosapic_intr_info[vector].rtes))
 639                 return iosapic_intr_info[vector].dest;
 640
 641         /*
 642          * If the platform supports redirection via XTP, let it
 643          * distribute interrupts.
 644          */
 645         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
 646                 return cpu_physical_id(smp_processor_id());
 647
 648         /*
 649          * Some interrupts (ACPI SCI, for instance) are registered
 650          * before the BSP is marked as online.
 651          */
 652         if (!cpu_online(smp_processor_id()))
 653                 return cpu_physical_id(smp_processor_id());
 654
 655 #ifdef CONFIG_NUMA
 656         {
 657                 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
 658                 cpumask_t cpu_mask;
 659
 660                 iosapic_index = find_iosapic(gsi);
 661                 if (iosapic_index < 0 ||
 662                     iosapic_lists[iosapic_index].node == MAX_NUMNODES)
 663                         goto skip_numa_setup;
 664
 665                 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
 666
 667                 for_each_cpu_mask(numa_cpu, cpu_mask) {
 668                         if (!cpu_online(numa_cpu))
 669                                 cpu_clear(numa_cpu, cpu_mask);
 670                 }
 671
 672                 num_cpus = cpus_weight(cpu_mask);
 673
 674                 if (!num_cpus)
 675                         goto skip_numa_setup;
 676
 677                 /* Use vector assigment to distribute across cpus in node */
 678                 cpu_index = vector % num_cpus;
 679
 680                 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
 681                         numa_cpu = next_cpu(numa_cpu, cpu_mask);
 682
 683                 if (numa_cpu != NR_CPUS)
 684                         return cpu_physical_id(numa_cpu);
 685         }
 686 skip_numa_setup:
 687 #endif
 688         /*
 689          * Otherwise, round-robin interrupt vectors across all the
 690          * processors.  (It'd be nice if we could be smarter in the
 691          * case of NUMA.)
 692          */
 693         do {
 694                 if (++cpu >= NR_CPUS)
 695                         cpu = 0;
 696         } while (!cpu_online(cpu));
 697
 698         return cpu_physical_id(cpu);
 699 #else
 700         return cpu_physical_id(smp_processor_id());
 701 #endif
 702 }
 703
 704 /*
 705  * ACPI can describe IOSAPIC interrupts via static tables and namespace
 706  * methods.  This provides an interface to register those interrupts and
 707  * program the IOSAPIC RTE.
 708  */
 709 int
 710 iosapic_register_intr (unsigned int gsi,
 711                        unsigned long polarity, unsigned long trigger)
 712 {
 713         int vector, mask = 1;
 714         unsigned int dest;
 715         unsigned long flags;
 716         struct iosapic_rte_info *rte;
 717         u32 low32;
 718 again:
 719         /*
 720          * If this GSI has already been registered (i.e., it's a
 721          * shared interrupt, or we lost a race to register it),
 722          * don't touch the RTE.
 723          */
 724         spin_lock_irqsave(&iosapic_lock, flags);
 725         {
 726                 vector = gsi_to_vector(gsi);
 727                 if (vector > 0) {
 728                         rte = gsi_vector_to_rte(gsi, vector);
 729                         rte->refcnt++;
 730                         spin_unlock_irqrestore(&iosapic_lock, flags);
 731                         return vector;
 732                 }
 733         }
 734         spin_unlock_irqrestore(&iosapic_lock, flags);
 735
 736         /* If vector is running out, we try to find a sharable vector */
 737         vector = assign_irq_vector_nopanic(AUTO_ASSIGN);
 738         if (vector < 0)
 739                 vector = iosapic_find_sharable_vector(trigger, polarity);
 740
 741         spin_lock_irqsave(&irq_descp(vector)->lock, flags);
 742         spin_lock(&iosapic_lock);
 743         {
 744                 if (gsi_to_vector(gsi) > 0) {
 745                         if (list_empty(&iosapic_intr_info[vector].rtes))
 746                                 free_irq_vector(vector);
 747                         spin_unlock(&iosapic_lock);
 748                         spin_unlock_irqrestore(&irq_descp(vector)->lock, flags);
 749                         goto again;
 750                 }
 751
 752                 dest = get_target_cpu(gsi, vector);
 753                 register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
 754                               polarity, trigger);
 755
 756                 /*
 757                  * If the vector is shared and already unmasked for
 758                  * other interrupt sources, don't mask it.
 759                  */
 760                 low32 = iosapic_intr_info[vector].low32;
 761                 if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK))
 762                         mask = 0;
 763                 set_rte(gsi, vector, dest, mask);
 764         }
 765         spin_unlock(&iosapic_lock);
 766         spin_unlock_irqrestore(&irq_descp(vector)->lock, flags);
 767
 768         printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
 769                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 770                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 771                cpu_logical_id(dest), dest, vector);
 772
 773         return vector;
 774 }
 775
 776 #ifdef CONFIG_ACPI_DEALLOCATE_IRQ
 777 void
 778 iosapic_unregister_intr (unsigned int gsi)
 779 {
 780         unsigned long flags;
 781         int irq, vector;
 782         irq_desc_t *idesc;
 783         u32 low32;
 784         unsigned long trigger, polarity;
 785         unsigned int dest;
 786         struct iosapic_rte_info *rte;
 787
 788         /*
 789          * If the irq associated with the gsi is not found,
 790          * iosapic_unregister_intr() is unbalanced. We need to check
 791          * this again after getting locks.
 792          */
 793         irq = gsi_to_irq(gsi);
 794         if (irq < 0) {
 795                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi);
 796                 WARN_ON(1);
 797                 return;
 798         }
 799         vector = irq_to_vector(irq);
 800
 801         idesc = irq_descp(irq);
 802         spin_lock_irqsave(&idesc->lock, flags);
 803         spin_lock(&iosapic_lock);
 804         {
 805                 if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
 806                         printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi);
 807                         WARN_ON(1);
 808                         goto out;
 809                 }
 810
 811                 if (--rte->refcnt > 0)
 812                         goto out;
 813
 814                 /* Mask the interrupt */
 815                 low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
 816                 iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), low32);
 817
 818                 /* Remove the rte entry from the list */
 819                 list_del(&rte->rte_list);
 820                 iosapic_intr_info[vector].count--;
 821                 iosapic_free_rte(rte);
 822
 823                 trigger  = iosapic_intr_info[vector].trigger;
 824                 polarity = iosapic_intr_info[vector].polarity;
 825                 dest     = iosapic_intr_info[vector].dest;
 826                 printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
 827                        gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 828                        (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 829                        cpu_logical_id(dest), dest, vector);
 830
 831                 if (list_empty(&iosapic_intr_info[vector].rtes)) {
 832                         /* Sanity check */
 833                         BUG_ON(iosapic_intr_info[vector].count);
 834
 835                         /* Clear the interrupt controller descriptor */
 836                         idesc->handler = &no_irq_type;
 837
 838                         /* Clear the interrupt information */
 839                         memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info));
 840                         iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
 841                         INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
 842
 843                         if (idesc->action) {
 844                                 printk(KERN_ERR "interrupt handlers still exist on IRQ %u\n", irq);
 845                                 WARN_ON(1);
 846                         }
 847
 848                         /* Free the interrupt vector */
 849                         free_irq_vector(vector);
 850                 }
 851         }
 852  out:
 853         spin_unlock(&iosapic_lock);
 854         spin_unlock_irqrestore(&idesc->lock, flags);
 855 }
 856 #endif /* CONFIG_ACPI_DEALLOCATE_IRQ */
 857
 858 /*
 859  * ACPI calls this when it finds an entry for a platform interrupt.
 860  * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
 861  */
 862 int __init
 863 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
 864                                 int iosapic_vector, u16 eid, u16 id,
 865                                 unsigned long polarity, unsigned long trigger)
 866 {
 867         static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
 868         unsigned char delivery;
 869         int vector, mask = 0;
 870         unsigned int dest = ((id << 8) | eid) & 0xffff;
 871
 872         switch (int_type) {
 873               case ACPI_INTERRUPT_PMI:
 874                 vector = iosapic_vector;
 875                 /*
 876                  * since PMI vector is alloc'd by FW(ACPI) not by kernel,
 877                  * we need to make sure the vector is available
 878                  */
 879                 iosapic_reassign_vector(vector);
 880                 delivery = IOSAPIC_PMI;
 881                 break;
 882               case ACPI_INTERRUPT_INIT:
 883                 vector = assign_irq_vector(AUTO_ASSIGN);
 884                 delivery = IOSAPIC_INIT;
 885                 break;
 886               case ACPI_INTERRUPT_CPEI:
 887                 vector = IA64_CPE_VECTOR;
 888                 delivery = IOSAPIC_LOWEST_PRIORITY;
 889                 mask = 1;
 890                 break;
 891               default:
 892                 printk(KERN_ERR "iosapic_register_platform_irq(): invalid int type 0x%x\n", int_type);
 893                 return -1;
 894         }
 895
 896         register_intr(gsi, vector, delivery, polarity, trigger);
 897
 898         printk(KERN_INFO "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
 899                int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
 900                int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 901                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 902                cpu_logical_id(dest), dest, vector);
 903
 904         set_rte(gsi, vector, dest, mask);
 905         return vector;
 906 }
 907
 908
 909 /*
 910  * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
 911  * Note that the gsi_base and IOSAPIC address must be set in iosapic_init().
 912  */
 913 void __init
 914 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
 915                           unsigned long polarity,
 916                           unsigned long trigger)
 917 {
 918         int vector;
 919         unsigned int dest = cpu_physical_id(smp_processor_id());
 920
 921         vector = isa_irq_to_vector(isa_irq);
 922
 923         register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
 924
 925         DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
 926             isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
 927             polarity == IOSAPIC_POL_HIGH ? "high" : "low",
 928             cpu_logical_id(dest), dest, vector);
 929
 930         set_rte(gsi, vector, dest, 1);
 931 }
 932
 933 void __init
 934 iosapic_system_init (int system_pcat_compat)
 935 {
 936         int vector;
 937
 938         for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) {
 939                 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
 940                 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);        /* mark as unused */
 941         }
 942
 943         pcat_compat = system_pcat_compat;
 944         if (pcat_compat) {
 945                 /*
 946                  * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
 947                  * enabled.
 948                  */
 949                 printk(KERN_INFO "%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__);
 950                 outb(0xff, 0xA1);
 951                 outb(0xff, 0x21);
 952         }
 953 }
 954
 955 void __init
 956 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
 957 {
 958         int num_rte;
 959         unsigned int isa_irq, ver;
 960         char __iomem *addr;
 961
 962         addr = ioremap(phys_addr, 0);
 963         ver = iosapic_version(addr);
 964
 965         /*
 966          * The MAX_REDIR register holds the highest input pin
 967          * number (starting from 0).
 968          * We add 1 so that we can use it for number of pins (= RTEs)
 969          */
 970         num_rte = ((ver >> 16) & 0xff) + 1;
 971
 972         iosapic_lists[num_iosapic].addr = addr;
 973         iosapic_lists[num_iosapic].gsi_base = gsi_base;
 974         iosapic_lists[num_iosapic].num_rte = num_rte;
 975 #ifdef CONFIG_NUMA
 976         iosapic_lists[num_iosapic].node = MAX_NUMNODES;
 977 #endif
 978         num_iosapic++;
 979
 980         if ((gsi_base == 0) && pcat_compat) {
 981                 /*
 982                  * Map the legacy ISA devices into the IOSAPIC data.  Some of these may
 983                  * get reprogrammed later on with data from the ACPI Interrupt Source
 984                  * Override table.
 985                  */
 986                 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
 987                         iosapic_override_isa_irq(isa_irq, isa_irq, IOSAPIC_POL_HIGH, IOSAPIC_EDGE);
 988         }
 989 }
 990
 991 #ifdef CONFIG_NUMA
 992 void __init
 993 map_iosapic_to_node(unsigned int gsi_base, int node)
 994 {
 995         int index;
 996
 997         index = find_iosapic(gsi_base);
 998         if (index < 0) {
 999                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1000                        __FUNCTION__, gsi_base);
1001                 return;
1002         }
1003         iosapic_lists[index].node = node;
1004         return;
1005 }
1006 #endif
1007
1008 static int __init iosapic_enable_kmalloc (void)
1009 {
1010         iosapic_kmalloc_ok = 1;
1011         return 0;
1012 }
1013 core_initcall (iosapic_enable_kmalloc);