git.oblomov.eu Git - linux-2.6/blob - drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  72         /* required last entry */
  73         {0, }
  74 };
  75
  76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  77
  78 void igb_reset(struct igb_adapter *);
  79 static int igb_setup_all_tx_resources(struct igb_adapter *);
  80 static int igb_setup_all_rx_resources(struct igb_adapter *);
  81 static void igb_free_all_tx_resources(struct igb_adapter *);
  82 static void igb_free_all_rx_resources(struct igb_adapter *);
  83 void igb_update_stats(struct igb_adapter *);
  84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  85 static void __devexit igb_remove(struct pci_dev *pdev);
  86 static int igb_sw_init(struct igb_adapter *);
  87 static int igb_open(struct net_device *);
  88 static int igb_close(struct net_device *);
  89 static void igb_configure_tx(struct igb_adapter *);
  90 static void igb_configure_rx(struct igb_adapter *);
  91 static void igb_setup_rctl(struct igb_adapter *);
  92 static void igb_clean_all_tx_rings(struct igb_adapter *);
  93 static void igb_clean_all_rx_rings(struct igb_adapter *);
  94 static void igb_clean_tx_ring(struct igb_ring *);
  95 static void igb_clean_rx_ring(struct igb_ring *);
  96 static void igb_set_multi(struct net_device *);
  97 static void igb_update_phy_info(unsigned long);
  98 static void igb_watchdog(unsigned long);
  99 static void igb_watchdog_task(struct work_struct *);
 100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
 101                                   struct igb_ring *);
 102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 103 static struct net_device_stats *igb_get_stats(struct net_device *);
 104 static int igb_change_mtu(struct net_device *, int);
 105 static int igb_set_mac(struct net_device *, void *);
 106 static irqreturn_t igb_intr(int irq, void *);
 107 static irqreturn_t igb_intr_msi(int irq, void *);
 108 static irqreturn_t igb_msix_other(int irq, void *);
 109 static irqreturn_t igb_msix_rx(int irq, void *);
 110 static irqreturn_t igb_msix_tx(int irq, void *);
 111 #ifdef CONFIG_IGB_DCA
 112 static void igb_update_rx_dca(struct igb_ring *);
 113 static void igb_update_tx_dca(struct igb_ring *);
 114 static void igb_setup_dca(struct igb_adapter *);
 115 #endif /* CONFIG_IGB_DCA */
 116 static bool igb_clean_tx_irq(struct igb_ring *);
 117 static int igb_poll(struct napi_struct *, int);
 118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 121 static void igb_tx_timeout(struct net_device *);
 122 static void igb_reset_task(struct work_struct *);
 123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 126 static void igb_restore_vlan(struct igb_adapter *);
 127 static void igb_ping_all_vfs(struct igb_adapter *);
 128 static void igb_msg_task(struct igb_adapter *);
 129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
 131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
 132 static void igb_vmm_control(struct igb_adapter *);
 133 static inline void igb_set_vmolr(struct e1000_hw *, int);
 134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
 135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 137
 138 #ifdef CONFIG_PM
 139 static int igb_suspend(struct pci_dev *, pm_message_t);
 140 static int igb_resume(struct pci_dev *);
 141 #endif
 142 static void igb_shutdown(struct pci_dev *);
 143 #ifdef CONFIG_IGB_DCA
 144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 145 static struct notifier_block dca_notifier = {
 146         .notifier_call  = igb_notify_dca,
 147         .next           = NULL,
 148         .priority       = 0
 149 };
 150 #endif
 151 #ifdef CONFIG_NET_POLL_CONTROLLER
 152 /* for netdump / net console */
 153 static void igb_netpoll(struct net_device *);
 154 #endif
 155 #ifdef CONFIG_PCI_IOV
 156 static unsigned int max_vfs = 0;
 157 module_param(max_vfs, uint, 0);
 158 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 159                  "per physical function");
 160 #endif /* CONFIG_PCI_IOV */
 161
 162 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 163                      pci_channel_state_t);
 164 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 165 static void igb_io_resume(struct pci_dev *);
 166
 167 static struct pci_error_handlers igb_err_handler = {
 168         .error_detected = igb_io_error_detected,
 169         .slot_reset = igb_io_slot_reset,
 170         .resume = igb_io_resume,
 171 };
 172
 173
 174 static struct pci_driver igb_driver = {
 175         .name     = igb_driver_name,
 176         .id_table = igb_pci_tbl,
 177         .probe    = igb_probe,
 178         .remove   = __devexit_p(igb_remove),
 179 #ifdef CONFIG_PM
 180         /* Power Managment Hooks */
 181         .suspend  = igb_suspend,
 182         .resume   = igb_resume,
 183 #endif
 184         .shutdown = igb_shutdown,
 185         .err_handler = &igb_err_handler
 186 };
 187
 188 static int global_quad_port_a; /* global quad port a indication */
 189
 190 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 191 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 192 MODULE_LICENSE("GPL");
 193 MODULE_VERSION(DRV_VERSION);
 194
 195 /**
 196  * Scale the NIC clock cycle by a large factor so that
 197  * relatively small clock corrections can be added or
 198  * substracted at each clock tick. The drawbacks of a
 199  * large factor are a) that the clock register overflows
 200  * more quickly (not such a big deal) and b) that the
 201  * increment per tick has to fit into 24 bits.
 202  *
 203  * Note that
 204  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 205  *             IGB_TSYNC_SCALE
 206  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 207  *
 208  * The base scale factor is intentionally a power of two
 209  * so that the division in %struct timecounter can be done with
 210  * a shift.
 211  */
 212 #define IGB_TSYNC_SHIFT (19)
 213 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 214
 215 /**
 216  * The duration of one clock cycle of the NIC.
 217  *
 218  * @todo This hard-coded value is part of the specification and might change
 219  * in future hardware revisions. Add revision check.
 220  */
 221 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 222
 223 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 224 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 225 #endif
 226
 227 /**
 228  * igb_read_clock - read raw cycle counter (to be used by time counter)
 229  */
 230 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 231 {
 232         struct igb_adapter *adapter =
 233                 container_of(tc, struct igb_adapter, cycles);
 234         struct e1000_hw *hw = &adapter->hw;
 235         u64 stamp;
 236
 237         stamp =  rd32(E1000_SYSTIML);
 238         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 239
 240         return stamp;
 241 }
 242
 243 #ifdef DEBUG
 244 /**
 245  * igb_get_hw_dev_name - return device name string
 246  * used by hardware layer to print debugging information
 247  **/
 248 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 249 {
 250         struct igb_adapter *adapter = hw->back;
 251         return adapter->netdev->name;
 252 }
 253
 254 /**
 255  * igb_get_time_str - format current NIC and system time as string
 256  */
 257 static char *igb_get_time_str(struct igb_adapter *adapter,
 258                               char buffer[160])
 259 {
 260         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 261         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 262         struct timespec sys;
 263         struct timespec delta;
 264         getnstimeofday(&sys);
 265
 266         delta = timespec_sub(nic, sys);
 267
 268         sprintf(buffer,
 269                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 270                 hw,
 271                 (long)nic.tv_sec, nic.tv_nsec,
 272                 (long)sys.tv_sec, sys.tv_nsec,
 273                 (long)delta.tv_sec, delta.tv_nsec);
 274
 275         return buffer;
 276 }
 277 #endif
 278
 279 /**
 280  * igb_desc_unused - calculate if we have unused descriptors
 281  **/
 282 static int igb_desc_unused(struct igb_ring *ring)
 283 {
 284         if (ring->next_to_clean > ring->next_to_use)
 285                 return ring->next_to_clean - ring->next_to_use - 1;
 286
 287         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 288 }
 289
 290 /**
 291  * igb_init_module - Driver Registration Routine
 292  *
 293  * igb_init_module is the first routine called when the driver is
 294  * loaded. All it does is register with the PCI subsystem.
 295  **/
 296 static int __init igb_init_module(void)
 297 {
 298         int ret;
 299         printk(KERN_INFO "%s - version %s\n",
 300                igb_driver_string, igb_driver_version);
 301
 302         printk(KERN_INFO "%s\n", igb_copyright);
 303
 304         global_quad_port_a = 0;
 305
 306 #ifdef CONFIG_IGB_DCA
 307         dca_register_notify(&dca_notifier);
 308 #endif
 309
 310         ret = pci_register_driver(&igb_driver);
 311         return ret;
 312 }
 313
 314 module_init(igb_init_module);
 315
 316 /**
 317  * igb_exit_module - Driver Exit Cleanup Routine
 318  *
 319  * igb_exit_module is called just before the driver is removed
 320  * from memory.
 321  **/
 322 static void __exit igb_exit_module(void)
 323 {
 324 #ifdef CONFIG_IGB_DCA
 325         dca_unregister_notify(&dca_notifier);
 326 #endif
 327         pci_unregister_driver(&igb_driver);
 328 }
 329
 330 module_exit(igb_exit_module);
 331
 332 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 333 /**
 334  * igb_cache_ring_register - Descriptor ring to register mapping
 335  * @adapter: board private structure to initialize
 336  *
 337  * Once we know the feature-set enabled for the device, we'll cache
 338  * the register offset the descriptor ring is assigned to.
 339  **/
 340 static void igb_cache_ring_register(struct igb_adapter *adapter)
 341 {
 342         int i;
 343         unsigned int rbase_offset = adapter->vfs_allocated_count;
 344
 345         switch (adapter->hw.mac.type) {
 346         case e1000_82576:
 347                 /* The queues are allocated for virtualization such that VF 0
 348                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 349                  * In order to avoid collision we start at the first free queue
 350                  * and continue consuming queues in the same sequence
 351                  */
 352                 for (i = 0; i < adapter->num_rx_queues; i++)
 353                         adapter->rx_ring[i].reg_idx = rbase_offset +
 354                                                       Q_IDX_82576(i);
 355                 for (i = 0; i < adapter->num_tx_queues; i++)
 356                         adapter->tx_ring[i].reg_idx = rbase_offset +
 357                                                       Q_IDX_82576(i);
 358                 break;
 359         case e1000_82575:
 360         default:
 361                 for (i = 0; i < adapter->num_rx_queues; i++)
 362                         adapter->rx_ring[i].reg_idx = i;
 363                 for (i = 0; i < adapter->num_tx_queues; i++)
 364                         adapter->tx_ring[i].reg_idx = i;
 365                 break;
 366         }
 367 }
 368
 369 /**
 370  * igb_alloc_queues - Allocate memory for all rings
 371  * @adapter: board private structure to initialize
 372  *
 373  * We allocate one ring per queue at run-time since we don't know the
 374  * number of queues at compile-time.
 375  **/
 376 static int igb_alloc_queues(struct igb_adapter *adapter)
 377 {
 378         int i;
 379
 380         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 381                                    sizeof(struct igb_ring), GFP_KERNEL);
 382         if (!adapter->tx_ring)
 383                 return -ENOMEM;
 384
 385         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 386                                    sizeof(struct igb_ring), GFP_KERNEL);
 387         if (!adapter->rx_ring) {
 388                 kfree(adapter->tx_ring);
 389                 return -ENOMEM;
 390         }
 391
 392         adapter->rx_ring->buddy = adapter->tx_ring;
 393
 394         for (i = 0; i < adapter->num_tx_queues; i++) {
 395                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 396                 ring->count = adapter->tx_ring_count;
 397                 ring->adapter = adapter;
 398                 ring->queue_index = i;
 399         }
 400         for (i = 0; i < adapter->num_rx_queues; i++) {
 401                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 402                 ring->count = adapter->rx_ring_count;
 403                 ring->adapter = adapter;
 404                 ring->queue_index = i;
 405                 ring->itr_register = E1000_ITR;
 406
 407                 /* set a default napi handler for each rx_ring */
 408                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 409         }
 410
 411         igb_cache_ring_register(adapter);
 412         return 0;
 413 }
 414
 415 static void igb_free_queues(struct igb_adapter *adapter)
 416 {
 417         int i;
 418
 419         for (i = 0; i < adapter->num_rx_queues; i++)
 420                 netif_napi_del(&adapter->rx_ring[i].napi);
 421
 422         adapter->num_rx_queues = 0;
 423         adapter->num_tx_queues = 0;
 424
 425         kfree(adapter->tx_ring);
 426         kfree(adapter->rx_ring);
 427 }
 428
 429 #define IGB_N0_QUEUE -1
 430 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 431                               int tx_queue, int msix_vector)
 432 {
 433         u32 msixbm = 0;
 434         struct e1000_hw *hw = &adapter->hw;
 435         u32 ivar, index;
 436
 437         switch (hw->mac.type) {
 438         case e1000_82575:
 439                 /* The 82575 assigns vectors using a bitmask, which matches the
 440                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 441                    or more queues to a vector, we write the appropriate bits
 442                    into the MSIXBM register for that vector. */
 443                 if (rx_queue > IGB_N0_QUEUE) {
 444                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 445                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 446                 }
 447                 if (tx_queue > IGB_N0_QUEUE) {
 448                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 449                         adapter->tx_ring[tx_queue].eims_value =
 450                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 451                 }
 452                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 453                 break;
 454         case e1000_82576:
 455                 /* 82576 uses a table-based method for assigning vectors.
 456                    Each queue has a single entry in the table to which we write
 457                    a vector number along with a "valid" bit.  Sadly, the layout
 458                    of the table is somewhat counterintuitive. */
 459                 if (rx_queue > IGB_N0_QUEUE) {
 460                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 461                         ivar = array_rd32(E1000_IVAR0, index);
 462                         if (rx_queue & 0x1) {
 463                                 /* vector goes into third byte of register */
 464                                 ivar = ivar & 0xFF00FFFF;
 465                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 466                         } else {
 467                                 /* vector goes into low byte of register */
 468                                 ivar = ivar & 0xFFFFFF00;
 469                                 ivar |= msix_vector | E1000_IVAR_VALID;
 470                         }
 471                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 472                         array_wr32(E1000_IVAR0, index, ivar);
 473                 }
 474                 if (tx_queue > IGB_N0_QUEUE) {
 475                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 476                         ivar = array_rd32(E1000_IVAR0, index);
 477                         if (tx_queue & 0x1) {
 478                                 /* vector goes into high byte of register */
 479                                 ivar = ivar & 0x00FFFFFF;
 480                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 481                         } else {
 482                                 /* vector goes into second byte of register */
 483                                 ivar = ivar & 0xFFFF00FF;
 484                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 485                         }
 486                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 487                         array_wr32(E1000_IVAR0, index, ivar);
 488                 }
 489                 break;
 490         default:
 491                 BUG();
 492                 break;
 493         }
 494 }
 495
 496 /**
 497  * igb_configure_msix - Configure MSI-X hardware
 498  *
 499  * igb_configure_msix sets up the hardware to properly
 500  * generate MSI-X interrupts.
 501  **/
 502 static void igb_configure_msix(struct igb_adapter *adapter)
 503 {
 504         u32 tmp;
 505         int i, vector = 0;
 506         struct e1000_hw *hw = &adapter->hw;
 507
 508         adapter->eims_enable_mask = 0;
 509         if (hw->mac.type == e1000_82576)
 510                 /* Turn on MSI-X capability first, or our settings
 511                  * won't stick.  And it will take days to debug. */
 512                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 513                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 514                                    E1000_GPIE_NSICR);
 515
 516         for (i = 0; i < adapter->num_tx_queues; i++) {
 517                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 518                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 519                 adapter->eims_enable_mask |= tx_ring->eims_value;
 520                 if (tx_ring->itr_val)
 521                         writel(tx_ring->itr_val,
 522                                hw->hw_addr + tx_ring->itr_register);
 523                 else
 524                         writel(1, hw->hw_addr + tx_ring->itr_register);
 525         }
 526
 527         for (i = 0; i < adapter->num_rx_queues; i++) {
 528                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 529                 rx_ring->buddy = NULL;
 530                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 531                 adapter->eims_enable_mask |= rx_ring->eims_value;
 532                 if (rx_ring->itr_val)
 533                         writel(rx_ring->itr_val,
 534                                hw->hw_addr + rx_ring->itr_register);
 535                 else
 536                         writel(1, hw->hw_addr + rx_ring->itr_register);
 537         }
 538
 539
 540         /* set vector for other causes, i.e. link changes */
 541         switch (hw->mac.type) {
 542         case e1000_82575:
 543                 array_wr32(E1000_MSIXBM(0), vector++,
 544                                       E1000_EIMS_OTHER);
 545
 546                 tmp = rd32(E1000_CTRL_EXT);
 547                 /* enable MSI-X PBA support*/
 548                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 549
 550                 /* Auto-Mask interrupts upon ICR read. */
 551                 tmp |= E1000_CTRL_EXT_EIAME;
 552                 tmp |= E1000_CTRL_EXT_IRCA;
 553
 554                 wr32(E1000_CTRL_EXT, tmp);
 555                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 556                 adapter->eims_other = E1000_EIMS_OTHER;
 557
 558                 break;
 559
 560         case e1000_82576:
 561                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 562                 wr32(E1000_IVAR_MISC, tmp);
 563
 564                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 565                 adapter->eims_other = 1 << (vector - 1);
 566                 break;
 567         default:
 568                 /* do nothing, since nothing else supports MSI-X */
 569                 break;
 570         } /* switch (hw->mac.type) */
 571         wrfl();
 572 }
 573
 574 /**
 575  * igb_request_msix - Initialize MSI-X interrupts
 576  *
 577  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 578  * kernel.
 579  **/
 580 static int igb_request_msix(struct igb_adapter *adapter)
 581 {
 582         struct net_device *netdev = adapter->netdev;
 583         int i, err = 0, vector = 0;
 584
 585         vector = 0;
 586
 587         for (i = 0; i < adapter->num_tx_queues; i++) {
 588                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 589                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 590                 err = request_irq(adapter->msix_entries[vector].vector,
 591                                   &igb_msix_tx, 0, ring->name,
 592                                   &(adapter->tx_ring[i]));
 593                 if (err)
 594                         goto out;
 595                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 596                 ring->itr_val = 976; /* ~4000 ints/sec */
 597                 vector++;
 598         }
 599         for (i = 0; i < adapter->num_rx_queues; i++) {
 600                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 601                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 602                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 603                 else
 604                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 605                 err = request_irq(adapter->msix_entries[vector].vector,
 606                                   &igb_msix_rx, 0, ring->name,
 607                                   &(adapter->rx_ring[i]));
 608                 if (err)
 609                         goto out;
 610                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 611                 ring->itr_val = adapter->itr;
 612                 vector++;
 613         }
 614
 615         err = request_irq(adapter->msix_entries[vector].vector,
 616                           &igb_msix_other, 0, netdev->name, netdev);
 617         if (err)
 618                 goto out;
 619
 620         igb_configure_msix(adapter);
 621         return 0;
 622 out:
 623         return err;
 624 }
 625
 626 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 627 {
 628         if (adapter->msix_entries) {
 629                 pci_disable_msix(adapter->pdev);
 630                 kfree(adapter->msix_entries);
 631                 adapter->msix_entries = NULL;
 632         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 633                 pci_disable_msi(adapter->pdev);
 634         return;
 635 }
 636
 637
 638 /**
 639  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 640  *
 641  * Attempt to configure interrupts using the best available
 642  * capabilities of the hardware and kernel.
 643  **/
 644 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 645 {
 646         int err;
 647         int numvecs, i;
 648
 649         /* Number of supported queues. */
 650         /* Having more queues than CPUs doesn't make sense. */
 651         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 652         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 653
 654         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 655         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 656                                         GFP_KERNEL);
 657         if (!adapter->msix_entries)
 658                 goto msi_only;
 659
 660         for (i = 0; i < numvecs; i++)
 661                 adapter->msix_entries[i].entry = i;
 662
 663         err = pci_enable_msix(adapter->pdev,
 664                               adapter->msix_entries,
 665                               numvecs);
 666         if (err == 0)
 667                 goto out;
 668
 669         igb_reset_interrupt_capability(adapter);
 670
 671         /* If we can't do MSI-X, try MSI */
 672 msi_only:
 673 #ifdef CONFIG_PCI_IOV
 674         /* disable SR-IOV for non MSI-X configurations */
 675         if (adapter->vf_data) {
 676                 struct e1000_hw *hw = &adapter->hw;
 677                 /* disable iov and allow time for transactions to clear */
 678                 pci_disable_sriov(adapter->pdev);
 679                 msleep(500);
 680
 681                 kfree(adapter->vf_data);
 682                 adapter->vf_data = NULL;
 683                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
 684                 msleep(100);
 685                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
 686         }
 687 #endif
 688         adapter->num_rx_queues = 1;
 689         adapter->num_tx_queues = 1;
 690         if (!pci_enable_msi(adapter->pdev))
 691                 adapter->flags |= IGB_FLAG_HAS_MSI;
 692 out:
 693         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 694         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 695         return;
 696 }
 697
 698 /**
 699  * igb_request_irq - initialize interrupts
 700  *
 701  * Attempts to configure interrupts using the best available
 702  * capabilities of the hardware and kernel.
 703  **/
 704 static int igb_request_irq(struct igb_adapter *adapter)
 705 {
 706         struct net_device *netdev = adapter->netdev;
 707         struct e1000_hw *hw = &adapter->hw;
 708         int err = 0;
 709
 710         if (adapter->msix_entries) {
 711                 err = igb_request_msix(adapter);
 712                 if (!err)
 713                         goto request_done;
 714                 /* fall back to MSI */
 715                 igb_reset_interrupt_capability(adapter);
 716                 if (!pci_enable_msi(adapter->pdev))
 717                         adapter->flags |= IGB_FLAG_HAS_MSI;
 718                 igb_free_all_tx_resources(adapter);
 719                 igb_free_all_rx_resources(adapter);
 720                 adapter->num_rx_queues = 1;
 721                 igb_alloc_queues(adapter);
 722         } else {
 723                 switch (hw->mac.type) {
 724                 case e1000_82575:
 725                         wr32(E1000_MSIXBM(0),
 726                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 727                         break;
 728                 case e1000_82576:
 729                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 730                         break;
 731                 default:
 732                         break;
 733                 }
 734         }
 735
 736         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 737                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 738                                   netdev->name, netdev);
 739                 if (!err)
 740                         goto request_done;
 741                 /* fall back to legacy interrupts */
 742                 igb_reset_interrupt_capability(adapter);
 743                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 744         }
 745
 746         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 747                           netdev->name, netdev);
 748
 749         if (err)
 750                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 751                         err);
 752
 753 request_done:
 754         return err;
 755 }
 756
 757 static void igb_free_irq(struct igb_adapter *adapter)
 758 {
 759         struct net_device *netdev = adapter->netdev;
 760
 761         if (adapter->msix_entries) {
 762                 int vector = 0, i;
 763
 764                 for (i = 0; i < adapter->num_tx_queues; i++)
 765                         free_irq(adapter->msix_entries[vector++].vector,
 766                                 &(adapter->tx_ring[i]));
 767                 for (i = 0; i < adapter->num_rx_queues; i++)
 768                         free_irq(adapter->msix_entries[vector++].vector,
 769                                 &(adapter->rx_ring[i]));
 770
 771                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 772                 return;
 773         }
 774
 775         free_irq(adapter->pdev->irq, netdev);
 776 }
 777
 778 /**
 779  * igb_irq_disable - Mask off interrupt generation on the NIC
 780  * @adapter: board private structure
 781  **/
 782 static void igb_irq_disable(struct igb_adapter *adapter)
 783 {
 784         struct e1000_hw *hw = &adapter->hw;
 785
 786         if (adapter->msix_entries) {
 787                 wr32(E1000_EIAM, 0);
 788                 wr32(E1000_EIMC, ~0);
 789                 wr32(E1000_EIAC, 0);
 790         }
 791
 792         wr32(E1000_IAM, 0);
 793         wr32(E1000_IMC, ~0);
 794         wrfl();
 795         synchronize_irq(adapter->pdev->irq);
 796 }
 797
 798 /**
 799  * igb_irq_enable - Enable default interrupt generation settings
 800  * @adapter: board private structure
 801  **/
 802 static void igb_irq_enable(struct igb_adapter *adapter)
 803 {
 804         struct e1000_hw *hw = &adapter->hw;
 805
 806         if (adapter->msix_entries) {
 807                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 808                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 809                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 810                 if (adapter->vfs_allocated_count)
 811                         wr32(E1000_MBVFIMR, 0xFF);
 812                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 813                                  E1000_IMS_DOUTSYNC));
 814         } else {
 815                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 816                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 817         }
 818 }
 819
 820 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 821 {
 822         struct net_device *netdev = adapter->netdev;
 823         u16 vid = adapter->hw.mng_cookie.vlan_id;
 824         u16 old_vid = adapter->mng_vlan_id;
 825         if (adapter->vlgrp) {
 826                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 827                         if (adapter->hw.mng_cookie.status &
 828                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 829                                 igb_vlan_rx_add_vid(netdev, vid);
 830                                 adapter->mng_vlan_id = vid;
 831                         } else
 832                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 833
 834                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 835                                         (vid != old_vid) &&
 836                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 837                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 838                 } else
 839                         adapter->mng_vlan_id = vid;
 840         }
 841 }
 842
 843 /**
 844  * igb_release_hw_control - release control of the h/w to f/w
 845  * @adapter: address of board private structure
 846  *
 847  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 848  * For ASF and Pass Through versions of f/w this means that the
 849  * driver is no longer loaded.
 850  *
 851  **/
 852 static void igb_release_hw_control(struct igb_adapter *adapter)
 853 {
 854         struct e1000_hw *hw = &adapter->hw;
 855         u32 ctrl_ext;
 856
 857         /* Let firmware take over control of h/w */
 858         ctrl_ext = rd32(E1000_CTRL_EXT);
 859         wr32(E1000_CTRL_EXT,
 860                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 861 }
 862
 863
 864 /**
 865  * igb_get_hw_control - get control of the h/w from f/w
 866  * @adapter: address of board private structure
 867  *
 868  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 869  * For ASF and Pass Through versions of f/w this means that
 870  * the driver is loaded.
 871  *
 872  **/
 873 static void igb_get_hw_control(struct igb_adapter *adapter)
 874 {
 875         struct e1000_hw *hw = &adapter->hw;
 876         u32 ctrl_ext;
 877
 878         /* Let firmware know the driver has taken over */
 879         ctrl_ext = rd32(E1000_CTRL_EXT);
 880         wr32(E1000_CTRL_EXT,
 881                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 882 }
 883
 884 /**
 885  * igb_configure - configure the hardware for RX and TX
 886  * @adapter: private board structure
 887  **/
 888 static void igb_configure(struct igb_adapter *adapter)
 889 {
 890         struct net_device *netdev = adapter->netdev;
 891         int i;
 892
 893         igb_get_hw_control(adapter);
 894         igb_set_multi(netdev);
 895
 896         igb_restore_vlan(adapter);
 897
 898         igb_configure_tx(adapter);
 899         igb_setup_rctl(adapter);
 900         igb_configure_rx(adapter);
 901
 902         igb_rx_fifo_flush_82575(&adapter->hw);
 903
 904         /* call igb_desc_unused which always leaves
 905          * at least 1 descriptor unused to make sure
 906          * next_to_use != next_to_clean */
 907         for (i = 0; i < adapter->num_rx_queues; i++) {
 908                 struct igb_ring *ring = &adapter->rx_ring[i];
 909                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
 910         }
 911
 912
 913         adapter->tx_queue_len = netdev->tx_queue_len;
 914 }
 915
 916
 917 /**
 918  * igb_up - Open the interface and prepare it to handle traffic
 919  * @adapter: board private structure
 920  **/
 921
 922 int igb_up(struct igb_adapter *adapter)
 923 {
 924         struct e1000_hw *hw = &adapter->hw;
 925         int i;
 926
 927         /* hardware has been reset, we need to reload some things */
 928         igb_configure(adapter);
 929
 930         clear_bit(__IGB_DOWN, &adapter->state);
 931
 932         for (i = 0; i < adapter->num_rx_queues; i++)
 933                 napi_enable(&adapter->rx_ring[i].napi);
 934         if (adapter->msix_entries)
 935                 igb_configure_msix(adapter);
 936
 937         igb_vmm_control(adapter);
 938         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 939         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 940
 941         /* Clear any pending interrupts. */
 942         rd32(E1000_ICR);
 943         igb_irq_enable(adapter);
 944
 945         netif_tx_start_all_queues(adapter->netdev);
 946
 947         /* Fire a link change interrupt to start the watchdog. */
 948         wr32(E1000_ICS, E1000_ICS_LSC);
 949         return 0;
 950 }
 951
 952 void igb_down(struct igb_adapter *adapter)
 953 {
 954         struct e1000_hw *hw = &adapter->hw;
 955         struct net_device *netdev = adapter->netdev;
 956         u32 tctl, rctl;
 957         int i;
 958
 959         /* signal that we're down so the interrupt handler does not
 960          * reschedule our watchdog timer */
 961         set_bit(__IGB_DOWN, &adapter->state);
 962
 963         /* disable receives in the hardware */
 964         rctl = rd32(E1000_RCTL);
 965         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 966         /* flush and sleep below */
 967
 968         netif_tx_stop_all_queues(netdev);
 969
 970         /* disable transmits in the hardware */
 971         tctl = rd32(E1000_TCTL);
 972         tctl &= ~E1000_TCTL_EN;
 973         wr32(E1000_TCTL, tctl);
 974         /* flush both disables and wait for them to finish */
 975         wrfl();
 976         msleep(10);
 977
 978         for (i = 0; i < adapter->num_rx_queues; i++)
 979                 napi_disable(&adapter->rx_ring[i].napi);
 980
 981         igb_irq_disable(adapter);
 982
 983         del_timer_sync(&adapter->watchdog_timer);
 984         del_timer_sync(&adapter->phy_info_timer);
 985
 986         netdev->tx_queue_len = adapter->tx_queue_len;
 987         netif_carrier_off(netdev);
 988
 989         /* record the stats before reset*/
 990         igb_update_stats(adapter);
 991
 992         adapter->link_speed = 0;
 993         adapter->link_duplex = 0;
 994
 995         if (!pci_channel_offline(adapter->pdev))
 996                 igb_reset(adapter);
 997         igb_clean_all_tx_rings(adapter);
 998         igb_clean_all_rx_rings(adapter);
 999 }
1000
1001 void igb_reinit_locked(struct igb_adapter *adapter)
1002 {
1003         WARN_ON(in_interrupt());
1004         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1005                 msleep(1);
1006         igb_down(adapter);
1007         igb_up(adapter);
1008         clear_bit(__IGB_RESETTING, &adapter->state);
1009 }
1010
1011 void igb_reset(struct igb_adapter *adapter)
1012 {
1013         struct e1000_hw *hw = &adapter->hw;
1014         struct e1000_mac_info *mac = &hw->mac;
1015         struct e1000_fc_info *fc = &hw->fc;
1016         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1017         u16 hwm;
1018
1019         /* Repartition Pba for greater than 9k mtu
1020          * To take effect CTRL.RST is required.
1021          */
1022         switch (mac->type) {
1023         case e1000_82576:
1024                 pba = E1000_PBA_64K;
1025                 break;
1026         case e1000_82575:
1027         default:
1028                 pba = E1000_PBA_34K;
1029                 break;
1030         }
1031
1032         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1033             (mac->type < e1000_82576)) {
1034                 /* adjust PBA for jumbo frames */
1035                 wr32(E1000_PBA, pba);
1036
1037                 /* To maintain wire speed transmits, the Tx FIFO should be
1038                  * large enough to accommodate two full transmit packets,
1039                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1040                  * the Rx FIFO should be large enough to accommodate at least
1041                  * one full receive packet and is similarly rounded up and
1042                  * expressed in KB. */
1043                 pba = rd32(E1000_PBA);
1044                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1045                 tx_space = pba >> 16;
1046                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1047                 pba &= 0xffff;
1048                 /* the tx fifo also stores 16 bytes of information about the tx
1049                  * but don't include ethernet FCS because hardware appends it */
1050                 min_tx_space = (adapter->max_frame_size +
1051                                 sizeof(union e1000_adv_tx_desc) -
1052                                 ETH_FCS_LEN) * 2;
1053                 min_tx_space = ALIGN(min_tx_space, 1024);
1054                 min_tx_space >>= 10;
1055                 /* software strips receive CRC, so leave room for it */
1056                 min_rx_space = adapter->max_frame_size;
1057                 min_rx_space = ALIGN(min_rx_space, 1024);
1058                 min_rx_space >>= 10;
1059
1060                 /* If current Tx allocation is less than the min Tx FIFO size,
1061                  * and the min Tx FIFO size is less than the current Rx FIFO
1062                  * allocation, take space away from current Rx allocation */
1063                 if (tx_space < min_tx_space &&
1064                     ((min_tx_space - tx_space) < pba)) {
1065                         pba = pba - (min_tx_space - tx_space);
1066
1067                         /* if short on rx space, rx wins and must trump tx
1068                          * adjustment */
1069                         if (pba < min_rx_space)
1070                                 pba = min_rx_space;
1071                 }
1072                 wr32(E1000_PBA, pba);
1073         }
1074
1075         /* flow control settings */
1076         /* The high water mark must be low enough to fit one full frame
1077          * (or the size used for early receive) above it in the Rx FIFO.
1078          * Set it to the lower of:
1079          * - 90% of the Rx FIFO size, or
1080          * - the full Rx FIFO size minus one full frame */
1081         hwm = min(((pba << 10) * 9 / 10),
1082                         ((pba << 10) - 2 * adapter->max_frame_size));
1083
1084         if (mac->type < e1000_82576) {
1085                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1086                 fc->low_water = fc->high_water - 8;
1087         } else {
1088                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1089                 fc->low_water = fc->high_water - 16;
1090         }
1091         fc->pause_time = 0xFFFF;
1092         fc->send_xon = 1;
1093         fc->type = fc->original_type;
1094
1095         /* disable receive for all VFs and wait one second */
1096         if (adapter->vfs_allocated_count) {
1097                 int i;
1098                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1099                         adapter->vf_data[i].clear_to_send = false;
1100
1101                 /* ping all the active vfs to let them know we are going down */
1102                         igb_ping_all_vfs(adapter);
1103
1104                 /* disable transmits and receives */
1105                 wr32(E1000_VFRE, 0);
1106                 wr32(E1000_VFTE, 0);
1107         }
1108
1109         /* Allow time for pending master requests to run */
1110         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1111         wr32(E1000_WUC, 0);
1112
1113         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1114                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1115
1116         igb_update_mng_vlan(adapter);
1117
1118         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1119         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1120
1121         igb_reset_adaptive(&adapter->hw);
1122         igb_get_phy_info(&adapter->hw);
1123 }
1124
1125 static const struct net_device_ops igb_netdev_ops = {
1126         .ndo_open               = igb_open,
1127         .ndo_stop               = igb_close,
1128         .ndo_start_xmit         = igb_xmit_frame_adv,
1129         .ndo_get_stats          = igb_get_stats,
1130         .ndo_set_multicast_list = igb_set_multi,
1131         .ndo_set_mac_address    = igb_set_mac,
1132         .ndo_change_mtu         = igb_change_mtu,
1133         .ndo_do_ioctl           = igb_ioctl,
1134         .ndo_tx_timeout         = igb_tx_timeout,
1135         .ndo_validate_addr      = eth_validate_addr,
1136         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1137         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1138         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1139 #ifdef CONFIG_NET_POLL_CONTROLLER
1140         .ndo_poll_controller    = igb_netpoll,
1141 #endif
1142 };
1143
1144 /**
1145  * igb_probe - Device Initialization Routine
1146  * @pdev: PCI device information struct
1147  * @ent: entry in igb_pci_tbl
1148  *
1149  * Returns 0 on success, negative on failure
1150  *
1151  * igb_probe initializes an adapter identified by a pci_dev structure.
1152  * The OS initialization, configuring of the adapter private structure,
1153  * and a hardware reset occur.
1154  **/
1155 static int __devinit igb_probe(struct pci_dev *pdev,
1156                                const struct pci_device_id *ent)
1157 {
1158         struct net_device *netdev;
1159         struct igb_adapter *adapter;
1160         struct e1000_hw *hw;
1161         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1162         unsigned long mmio_start, mmio_len;
1163         int err, pci_using_dac;
1164         u16 eeprom_data = 0;
1165         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1166         u32 part_num;
1167
1168         err = pci_enable_device_mem(pdev);
1169         if (err)
1170                 return err;
1171
1172         pci_using_dac = 0;
1173         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1174         if (!err) {
1175                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1176                 if (!err)
1177                         pci_using_dac = 1;
1178         } else {
1179                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1180                 if (err) {
1181                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1182                         if (err) {
1183                                 dev_err(&pdev->dev, "No usable DMA "
1184                                         "configuration, aborting\n");
1185                                 goto err_dma;
1186                         }
1187                 }
1188         }
1189
1190         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1191                                            IORESOURCE_MEM),
1192                                            igb_driver_name);
1193         if (err)
1194                 goto err_pci_reg;
1195
1196         err = pci_enable_pcie_error_reporting(pdev);
1197         if (err) {
1198                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1199                         "0x%x\n", err);
1200                 /* non-fatal, continue */
1201         }
1202
1203         pci_set_master(pdev);
1204         pci_save_state(pdev);
1205
1206         err = -ENOMEM;
1207         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1208                                    IGB_ABS_MAX_TX_QUEUES);
1209         if (!netdev)
1210                 goto err_alloc_etherdev;
1211
1212         SET_NETDEV_DEV(netdev, &pdev->dev);
1213
1214         pci_set_drvdata(pdev, netdev);
1215         adapter = netdev_priv(netdev);
1216         adapter->netdev = netdev;
1217         adapter->pdev = pdev;
1218         hw = &adapter->hw;
1219         hw->back = adapter;
1220         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1221
1222         mmio_start = pci_resource_start(pdev, 0);
1223         mmio_len = pci_resource_len(pdev, 0);
1224
1225         err = -EIO;
1226         hw->hw_addr = ioremap(mmio_start, mmio_len);
1227         if (!hw->hw_addr)
1228                 goto err_ioremap;
1229
1230         netdev->netdev_ops = &igb_netdev_ops;
1231         igb_set_ethtool_ops(netdev);
1232         netdev->watchdog_timeo = 5 * HZ;
1233
1234         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1235
1236         netdev->mem_start = mmio_start;
1237         netdev->mem_end = mmio_start + mmio_len;
1238
1239         /* PCI config space info */
1240         hw->vendor_id = pdev->vendor;
1241         hw->device_id = pdev->device;
1242         hw->revision_id = pdev->revision;
1243         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1244         hw->subsystem_device_id = pdev->subsystem_device;
1245
1246         /* setup the private structure */
1247         hw->back = adapter;
1248         /* Copy the default MAC, PHY and NVM function pointers */
1249         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1250         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1251         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1252         /* Initialize skew-specific constants */
1253         err = ei->get_invariants(hw);
1254         if (err)
1255                 goto err_sw_init;
1256
1257 #ifdef CONFIG_PCI_IOV
1258         /* since iov functionality isn't critical to base device function we
1259          * can accept failure.  If it fails we don't allow iov to be enabled */
1260         if (hw->mac.type == e1000_82576) {
1261                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1262                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1263                 int i;
1264                 unsigned char mac_addr[ETH_ALEN];
1265
1266                 if (num_vfs) {
1267                         adapter->vf_data = kcalloc(num_vfs,
1268                                                 sizeof(struct vf_data_storage),
1269                                                 GFP_KERNEL);
1270                         if (!adapter->vf_data) {
1271                                 dev_err(&pdev->dev,
1272                                         "Could not allocate VF private data - "
1273                                         "IOV enable failed\n");
1274                         } else {
1275                                 err = pci_enable_sriov(pdev, num_vfs);
1276                                 if (!err) {
1277                                         adapter->vfs_allocated_count = num_vfs;
1278                                         dev_info(&pdev->dev,
1279                                                  "%d vfs allocated\n",
1280                                                  num_vfs);
1281                                         for (i = 0;
1282                                              i < adapter->vfs_allocated_count;
1283                                              i++) {
1284                                                 random_ether_addr(mac_addr);
1285                                                 igb_set_vf_mac(adapter, i,
1286                                                                mac_addr);
1287                                         }
1288                                 } else {
1289                                         kfree(adapter->vf_data);
1290                                         adapter->vf_data = NULL;
1291                                 }
1292                         }
1293                 }
1294         }
1295
1296 #endif
1297         /* setup the private structure */
1298         err = igb_sw_init(adapter);
1299         if (err)
1300                 goto err_sw_init;
1301
1302         igb_get_bus_info_pcie(hw);
1303
1304         /* set flags */
1305         switch (hw->mac.type) {
1306         case e1000_82575:
1307                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1308                 break;
1309         case e1000_82576:
1310         default:
1311                 break;
1312         }
1313
1314         hw->phy.autoneg_wait_to_complete = false;
1315         hw->mac.adaptive_ifs = true;
1316
1317         /* Copper options */
1318         if (hw->phy.media_type == e1000_media_type_copper) {
1319                 hw->phy.mdix = AUTO_ALL_MODES;
1320                 hw->phy.disable_polarity_correction = false;
1321                 hw->phy.ms_type = e1000_ms_hw_default;
1322         }
1323
1324         if (igb_check_reset_block(hw))
1325                 dev_info(&pdev->dev,
1326                         "PHY reset is blocked due to SOL/IDER session.\n");
1327
1328         netdev->features = NETIF_F_SG |
1329                            NETIF_F_IP_CSUM |
1330                            NETIF_F_HW_VLAN_TX |
1331                            NETIF_F_HW_VLAN_RX |
1332                            NETIF_F_HW_VLAN_FILTER;
1333
1334         netdev->features |= NETIF_F_IPV6_CSUM;
1335         netdev->features |= NETIF_F_TSO;
1336         netdev->features |= NETIF_F_TSO6;
1337
1338         netdev->features |= NETIF_F_GRO;
1339
1340         netdev->vlan_features |= NETIF_F_TSO;
1341         netdev->vlan_features |= NETIF_F_TSO6;
1342         netdev->vlan_features |= NETIF_F_IP_CSUM;
1343         netdev->vlan_features |= NETIF_F_SG;
1344
1345         if (pci_using_dac)
1346                 netdev->features |= NETIF_F_HIGHDMA;
1347
1348         if (adapter->hw.mac.type == e1000_82576)
1349                 netdev->features |= NETIF_F_SCTP_CSUM;
1350
1351         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1352
1353         /* before reading the NVM, reset the controller to put the device in a
1354          * known good starting state */
1355         hw->mac.ops.reset_hw(hw);
1356
1357         /* make sure the NVM is good */
1358         if (igb_validate_nvm_checksum(hw) < 0) {
1359                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1360                 err = -EIO;
1361                 goto err_eeprom;
1362         }
1363
1364         /* copy the MAC address out of the NVM */
1365         if (hw->mac.ops.read_mac_addr(hw))
1366                 dev_err(&pdev->dev, "NVM Read Error\n");
1367
1368         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1369         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1370
1371         if (!is_valid_ether_addr(netdev->perm_addr)) {
1372                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1373                 err = -EIO;
1374                 goto err_eeprom;
1375         }
1376
1377         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1378                     (unsigned long) adapter);
1379         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1380                     (unsigned long) adapter);
1381
1382         INIT_WORK(&adapter->reset_task, igb_reset_task);
1383         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1384
1385         /* Initialize link properties that are user-changeable */
1386         adapter->fc_autoneg = true;
1387         hw->mac.autoneg = true;
1388         hw->phy.autoneg_advertised = 0x2f;
1389
1390         hw->fc.original_type = e1000_fc_default;
1391         hw->fc.type = e1000_fc_default;
1392
1393         adapter->itr_setting = IGB_DEFAULT_ITR;
1394         adapter->itr = IGB_START_ITR;
1395
1396         igb_validate_mdi_setting(hw);
1397
1398         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1399          * enable the ACPI Magic Packet filter
1400          */
1401
1402         if (hw->bus.func == 0)
1403                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1404         else if (hw->bus.func == 1)
1405                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1406
1407         if (eeprom_data & eeprom_apme_mask)
1408                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1409
1410         /* now that we have the eeprom settings, apply the special cases where
1411          * the eeprom may be wrong or the board simply won't support wake on
1412          * lan on a particular port */
1413         switch (pdev->device) {
1414         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1415                 adapter->eeprom_wol = 0;
1416                 break;
1417         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1418         case E1000_DEV_ID_82576_FIBER:
1419         case E1000_DEV_ID_82576_SERDES:
1420                 /* Wake events only supported on port A for dual fiber
1421                  * regardless of eeprom setting */
1422                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1423                         adapter->eeprom_wol = 0;
1424                 break;
1425         case E1000_DEV_ID_82576_QUAD_COPPER:
1426                 /* if quad port adapter, disable WoL on all but port A */
1427                 if (global_quad_port_a != 0)
1428                         adapter->eeprom_wol = 0;
1429                 else
1430                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1431                 /* Reset for multiple quad port adapters */
1432                 if (++global_quad_port_a == 4)
1433                         global_quad_port_a = 0;
1434                 break;
1435         }
1436
1437         /* initialize the wol settings based on the eeprom settings */
1438         adapter->wol = adapter->eeprom_wol;
1439         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1440
1441         /* reset the hardware with the new settings */
1442         igb_reset(adapter);
1443
1444         /* let the f/w know that the h/w is now under the control of the
1445          * driver. */
1446         igb_get_hw_control(adapter);
1447
1448         strcpy(netdev->name, "eth%d");
1449         err = register_netdev(netdev);
1450         if (err)
1451                 goto err_register;
1452
1453         /* carrier off reporting is important to ethtool even BEFORE open */
1454         netif_carrier_off(netdev);
1455
1456 #ifdef CONFIG_IGB_DCA
1457         if (dca_add_requester(&pdev->dev) == 0) {
1458                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1459                 dev_info(&pdev->dev, "DCA enabled\n");
1460                 /* Always use CB2 mode, difference is masked
1461                  * in the CB driver. */
1462                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
1463                 igb_setup_dca(adapter);
1464         }
1465 #endif
1466
1467         /*
1468          * Initialize hardware timer: we keep it running just in case
1469          * that some program needs it later on.
1470          */
1471         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1472         adapter->cycles.read = igb_read_clock;
1473         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1474         adapter->cycles.mult = 1;
1475         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1476         wr32(E1000_TIMINCA,
1477              (1<<24) |
1478              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1479 #if 0
1480         /*
1481          * Avoid rollover while we initialize by resetting the time counter.
1482          */
1483         wr32(E1000_SYSTIML, 0x00000000);
1484         wr32(E1000_SYSTIMH, 0x00000000);
1485 #else
1486         /*
1487          * Set registers so that rollover occurs soon to test this.
1488          */
1489         wr32(E1000_SYSTIML, 0x00000000);
1490         wr32(E1000_SYSTIMH, 0xFF800000);
1491 #endif
1492         wrfl();
1493         timecounter_init(&adapter->clock,
1494                          &adapter->cycles,
1495                          ktime_to_ns(ktime_get_real()));
1496
1497         /*
1498          * Synchronize our NIC clock against system wall clock. NIC
1499          * time stamp reading requires ~3us per sample, each sample
1500          * was pretty stable even under load => only require 10
1501          * samples for each offset comparison.
1502          */
1503         memset(&adapter->compare, 0, sizeof(adapter->compare));
1504         adapter->compare.source = &adapter->clock;
1505         adapter->compare.target = ktime_get_real;
1506         adapter->compare.num_samples = 10;
1507         timecompare_update(&adapter->compare, 0);
1508
1509 #ifdef DEBUG
1510         {
1511                 char buffer[160];
1512                 printk(KERN_DEBUG
1513                         "igb: %s: hw %p initialized timer\n",
1514                         igb_get_time_str(adapter, buffer),
1515                         &adapter->hw);
1516         }
1517 #endif
1518
1519         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1520         /* print bus type/speed/width info */
1521         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1522                  netdev->name,
1523                  ((hw->bus.speed == e1000_bus_speed_2500)
1524                   ? "2.5Gb/s" : "unknown"),
1525                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1526                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1527                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1528                    "unknown"),
1529                  netdev->dev_addr);
1530
1531         igb_read_part_num(hw, &part_num);
1532         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1533                 (part_num >> 8), (part_num & 0xff));
1534
1535         dev_info(&pdev->dev,
1536                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1537                 adapter->msix_entries ? "MSI-X" :
1538                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1539                 adapter->num_rx_queues, adapter->num_tx_queues);
1540
1541         return 0;
1542
1543 err_register:
1544         igb_release_hw_control(adapter);
1545 err_eeprom:
1546         if (!igb_check_reset_block(hw))
1547                 igb_reset_phy(hw);
1548
1549         if (hw->flash_address)
1550                 iounmap(hw->flash_address);
1551
1552         igb_free_queues(adapter);
1553 err_sw_init:
1554         iounmap(hw->hw_addr);
1555 err_ioremap:
1556         free_netdev(netdev);
1557 err_alloc_etherdev:
1558         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1559                                      IORESOURCE_MEM));
1560 err_pci_reg:
1561 err_dma:
1562         pci_disable_device(pdev);
1563         return err;
1564 }
1565
1566 /**
1567  * igb_remove - Device Removal Routine
1568  * @pdev: PCI device information struct
1569  *
1570  * igb_remove is called by the PCI subsystem to alert the driver
1571  * that it should release a PCI device.  The could be caused by a
1572  * Hot-Plug event, or because the driver is going to be removed from
1573  * memory.
1574  **/
1575 static void __devexit igb_remove(struct pci_dev *pdev)
1576 {
1577         struct net_device *netdev = pci_get_drvdata(pdev);
1578         struct igb_adapter *adapter = netdev_priv(netdev);
1579         struct e1000_hw *hw = &adapter->hw;
1580         int err;
1581
1582         /* flush_scheduled work may reschedule our watchdog task, so
1583          * explicitly disable watchdog tasks from being rescheduled  */
1584         set_bit(__IGB_DOWN, &adapter->state);
1585         del_timer_sync(&adapter->watchdog_timer);
1586         del_timer_sync(&adapter->phy_info_timer);
1587
1588         flush_scheduled_work();
1589
1590 #ifdef CONFIG_IGB_DCA
1591         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1592                 dev_info(&pdev->dev, "DCA disabled\n");
1593                 dca_remove_requester(&pdev->dev);
1594                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1595                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1596         }
1597 #endif
1598
1599         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1600          * would have already happened in close and is redundant. */
1601         igb_release_hw_control(adapter);
1602
1603         unregister_netdev(netdev);
1604
1605         if (!igb_check_reset_block(&adapter->hw))
1606                 igb_reset_phy(&adapter->hw);
1607
1608         igb_reset_interrupt_capability(adapter);
1609
1610         igb_free_queues(adapter);
1611
1612 #ifdef CONFIG_PCI_IOV
1613         /* reclaim resources allocated to VFs */
1614         if (adapter->vf_data) {
1615                 /* disable iov and allow time for transactions to clear */
1616                 pci_disable_sriov(pdev);
1617                 msleep(500);
1618
1619                 kfree(adapter->vf_data);
1620                 adapter->vf_data = NULL;
1621                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1622                 msleep(100);
1623                 dev_info(&pdev->dev, "IOV Disabled\n");
1624         }
1625 #endif
1626         iounmap(hw->hw_addr);
1627         if (hw->flash_address)
1628                 iounmap(hw->flash_address);
1629         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1630                                      IORESOURCE_MEM));
1631
1632         free_netdev(netdev);
1633
1634         err = pci_disable_pcie_error_reporting(pdev);
1635         if (err)
1636                 dev_err(&pdev->dev,
1637                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1638
1639         pci_disable_device(pdev);
1640 }
1641
1642 /**
1643  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1644  * @adapter: board private structure to initialize
1645  *
1646  * igb_sw_init initializes the Adapter private data structure.
1647  * Fields are initialized based on PCI device information and
1648  * OS network device settings (MTU size).
1649  **/
1650 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1651 {
1652         struct e1000_hw *hw = &adapter->hw;
1653         struct net_device *netdev = adapter->netdev;
1654         struct pci_dev *pdev = adapter->pdev;
1655
1656         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1657
1658         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1659         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1660         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1661         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1662         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1663         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1664
1665         /* This call may decrease the number of queues depending on
1666          * interrupt mode. */
1667         igb_set_interrupt_capability(adapter);
1668
1669         if (igb_alloc_queues(adapter)) {
1670                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1671                 return -ENOMEM;
1672         }
1673
1674         /* Explicitly disable IRQ since the NIC can be in any state. */
1675         igb_irq_disable(adapter);
1676
1677         set_bit(__IGB_DOWN, &adapter->state);
1678         return 0;
1679 }
1680
1681 /**
1682  * igb_open - Called when a network interface is made active
1683  * @netdev: network interface device structure
1684  *
1685  * Returns 0 on success, negative value on failure
1686  *
1687  * The open entry point is called when a network interface is made
1688  * active by the system (IFF_UP).  At this point all resources needed
1689  * for transmit and receive operations are allocated, the interrupt
1690  * handler is registered with the OS, the watchdog timer is started,
1691  * and the stack is notified that the interface is ready.
1692  **/
1693 static int igb_open(struct net_device *netdev)
1694 {
1695         struct igb_adapter *adapter = netdev_priv(netdev);
1696         struct e1000_hw *hw = &adapter->hw;
1697         int err;
1698         int i;
1699
1700         /* disallow open during test */
1701         if (test_bit(__IGB_TESTING, &adapter->state))
1702                 return -EBUSY;
1703
1704         netif_carrier_off(netdev);
1705
1706         /* allocate transmit descriptors */
1707         err = igb_setup_all_tx_resources(adapter);
1708         if (err)
1709                 goto err_setup_tx;
1710
1711         /* allocate receive descriptors */
1712         err = igb_setup_all_rx_resources(adapter);
1713         if (err)
1714                 goto err_setup_rx;
1715
1716         /* e1000_power_up_phy(adapter); */
1717
1718         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1719         if ((adapter->hw.mng_cookie.status &
1720              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1721                 igb_update_mng_vlan(adapter);
1722
1723         /* before we allocate an interrupt, we must be ready to handle it.
1724          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1725          * as soon as we call pci_request_irq, so we have to setup our
1726          * clean_rx handler before we do so.  */
1727         igb_configure(adapter);
1728
1729         igb_vmm_control(adapter);
1730         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1731         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1732
1733         err = igb_request_irq(adapter);
1734         if (err)
1735                 goto err_req_irq;
1736
1737         /* From here on the code is the same as igb_up() */
1738         clear_bit(__IGB_DOWN, &adapter->state);
1739
1740         for (i = 0; i < adapter->num_rx_queues; i++)
1741                 napi_enable(&adapter->rx_ring[i].napi);
1742
1743         /* Clear any pending interrupts. */
1744         rd32(E1000_ICR);
1745
1746         igb_irq_enable(adapter);
1747
1748         netif_tx_start_all_queues(netdev);
1749
1750         /* Fire a link status change interrupt to start the watchdog. */
1751         wr32(E1000_ICS, E1000_ICS_LSC);
1752
1753         return 0;
1754
1755 err_req_irq:
1756         igb_release_hw_control(adapter);
1757         /* e1000_power_down_phy(adapter); */
1758         igb_free_all_rx_resources(adapter);
1759 err_setup_rx:
1760         igb_free_all_tx_resources(adapter);
1761 err_setup_tx:
1762         igb_reset(adapter);
1763
1764         return err;
1765 }
1766
1767 /**
1768  * igb_close - Disables a network interface
1769  * @netdev: network interface device structure
1770  *
1771  * Returns 0, this is not allowed to fail
1772  *
1773  * The close entry point is called when an interface is de-activated
1774  * by the OS.  The hardware is still under the driver's control, but
1775  * needs to be disabled.  A global MAC reset is issued to stop the
1776  * hardware, and all transmit and receive resources are freed.
1777  **/
1778 static int igb_close(struct net_device *netdev)
1779 {
1780         struct igb_adapter *adapter = netdev_priv(netdev);
1781
1782         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1783         igb_down(adapter);
1784
1785         igb_free_irq(adapter);
1786
1787         igb_free_all_tx_resources(adapter);
1788         igb_free_all_rx_resources(adapter);
1789
1790         /* kill manageability vlan ID if supported, but not if a vlan with
1791          * the same ID is registered on the host OS (let 8021q kill it) */
1792         if ((adapter->hw.mng_cookie.status &
1793                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1794              !(adapter->vlgrp &&
1795                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1796                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1797
1798         return 0;
1799 }
1800
1801 /**
1802  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1803  * @adapter: board private structure
1804  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1805  *
1806  * Return 0 on success, negative on failure
1807  **/
1808 int igb_setup_tx_resources(struct igb_adapter *adapter,
1809                            struct igb_ring *tx_ring)
1810 {
1811         struct pci_dev *pdev = adapter->pdev;
1812         int size;
1813
1814         size = sizeof(struct igb_buffer) * tx_ring->count;
1815         tx_ring->buffer_info = vmalloc(size);
1816         if (!tx_ring->buffer_info)
1817                 goto err;
1818         memset(tx_ring->buffer_info, 0, size);
1819
1820         /* round up to nearest 4K */
1821         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1822         tx_ring->size = ALIGN(tx_ring->size, 4096);
1823
1824         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1825                                              &tx_ring->dma);
1826
1827         if (!tx_ring->desc)
1828                 goto err;
1829
1830         tx_ring->adapter = adapter;
1831         tx_ring->next_to_use = 0;
1832         tx_ring->next_to_clean = 0;
1833         return 0;
1834
1835 err:
1836         vfree(tx_ring->buffer_info);
1837         dev_err(&adapter->pdev->dev,
1838                 "Unable to allocate memory for the transmit descriptor ring\n");
1839         return -ENOMEM;
1840 }
1841
1842 /**
1843  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1844  *                                (Descriptors) for all queues
1845  * @adapter: board private structure
1846  *
1847  * Return 0 on success, negative on failure
1848  **/
1849 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1850 {
1851         int i, err = 0;
1852         int r_idx;
1853
1854         for (i = 0; i < adapter->num_tx_queues; i++) {
1855                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1856                 if (err) {
1857                         dev_err(&adapter->pdev->dev,
1858                                 "Allocation for Tx Queue %u failed\n", i);
1859                         for (i--; i >= 0; i--)
1860                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1861                         break;
1862                 }
1863         }
1864
1865         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1866                 r_idx = i % adapter->num_tx_queues;
1867                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1868         }
1869         return err;
1870 }
1871
1872 /**
1873  * igb_configure_tx - Configure transmit Unit after Reset
1874  * @adapter: board private structure
1875  *
1876  * Configure the Tx unit of the MAC after a reset.
1877  **/
1878 static void igb_configure_tx(struct igb_adapter *adapter)
1879 {
1880         u64 tdba;
1881         struct e1000_hw *hw = &adapter->hw;
1882         u32 tctl;
1883         u32 txdctl, txctrl;
1884         int i, j;
1885
1886         for (i = 0; i < adapter->num_tx_queues; i++) {
1887                 struct igb_ring *ring = &adapter->tx_ring[i];
1888                 j = ring->reg_idx;
1889                 wr32(E1000_TDLEN(j),
1890                      ring->count * sizeof(union e1000_adv_tx_desc));
1891                 tdba = ring->dma;
1892                 wr32(E1000_TDBAL(j),
1893                      tdba & 0x00000000ffffffffULL);
1894                 wr32(E1000_TDBAH(j), tdba >> 32);
1895
1896                 ring->head = E1000_TDH(j);
1897                 ring->tail = E1000_TDT(j);
1898                 writel(0, hw->hw_addr + ring->tail);
1899                 writel(0, hw->hw_addr + ring->head);
1900                 txdctl = rd32(E1000_TXDCTL(j));
1901                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1902                 wr32(E1000_TXDCTL(j), txdctl);
1903
1904                 /* Turn off Relaxed Ordering on head write-backs.  The
1905                  * writebacks MUST be delivered in order or it will
1906                  * completely screw up our bookeeping.
1907                  */
1908                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1909                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1910                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1911         }
1912
1913         /* disable queue 0 to prevent tail bump w/o re-configuration */
1914         if (adapter->vfs_allocated_count)
1915                 wr32(E1000_TXDCTL(0), 0);
1916
1917         /* Program the Transmit Control Register */
1918         tctl = rd32(E1000_TCTL);
1919         tctl &= ~E1000_TCTL_CT;
1920         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1921                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1922
1923         igb_config_collision_dist(hw);
1924
1925         /* Setup Transmit Descriptor Settings for eop descriptor */
1926         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1927
1928         /* Enable transmits */
1929         tctl |= E1000_TCTL_EN;
1930
1931         wr32(E1000_TCTL, tctl);
1932 }
1933
1934 /**
1935  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1936  * @adapter: board private structure
1937  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1938  *
1939  * Returns 0 on success, negative on failure
1940  **/
1941 int igb_setup_rx_resources(struct igb_adapter *adapter,
1942                            struct igb_ring *rx_ring)
1943 {
1944         struct pci_dev *pdev = adapter->pdev;
1945         int size, desc_len;
1946
1947         size = sizeof(struct igb_buffer) * rx_ring->count;
1948         rx_ring->buffer_info = vmalloc(size);
1949         if (!rx_ring->buffer_info)
1950                 goto err;
1951         memset(rx_ring->buffer_info, 0, size);
1952
1953         desc_len = sizeof(union e1000_adv_rx_desc);
1954
1955         /* Round up to nearest 4K */
1956         rx_ring->size = rx_ring->count * desc_len;
1957         rx_ring->size = ALIGN(rx_ring->size, 4096);
1958
1959         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1960                                              &rx_ring->dma);
1961
1962         if (!rx_ring->desc)
1963                 goto err;
1964
1965         rx_ring->next_to_clean = 0;
1966         rx_ring->next_to_use = 0;
1967
1968         rx_ring->adapter = adapter;
1969
1970         return 0;
1971
1972 err:
1973         vfree(rx_ring->buffer_info);
1974         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1975                 "the receive descriptor ring\n");
1976         return -ENOMEM;
1977 }
1978
1979 /**
1980  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1981  *                                (Descriptors) for all queues
1982  * @adapter: board private structure
1983  *
1984  * Return 0 on success, negative on failure
1985  **/
1986 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1987 {
1988         int i, err = 0;
1989
1990         for (i = 0; i < adapter->num_rx_queues; i++) {
1991                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1992                 if (err) {
1993                         dev_err(&adapter->pdev->dev,
1994                                 "Allocation for Rx Queue %u failed\n", i);
1995                         for (i--; i >= 0; i--)
1996                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1997                         break;
1998                 }
1999         }
2000
2001         return err;
2002 }
2003
2004 /**
2005  * igb_setup_rctl - configure the receive control registers
2006  * @adapter: Board private structure
2007  **/
2008 static void igb_setup_rctl(struct igb_adapter *adapter)
2009 {
2010         struct e1000_hw *hw = &adapter->hw;
2011         u32 rctl;
2012         u32 srrctl = 0;
2013         int i;
2014
2015         rctl = rd32(E1000_RCTL);
2016
2017         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2018         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2019
2020         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2021                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2022
2023         /*
2024          * enable stripping of CRC. It's unlikely this will break BMC
2025          * redirection as it did with e1000. Newer features require
2026          * that the HW strips the CRC.
2027          */
2028         rctl |= E1000_RCTL_SECRC;
2029
2030         /*
2031          * disable store bad packets and clear size bits.
2032          */
2033         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2034
2035         /* enable LPE when to prevent packets larger than max_frame_size */
2036                 rctl |= E1000_RCTL_LPE;
2037
2038         /* Setup buffer sizes */
2039         switch (adapter->rx_buffer_len) {
2040         case IGB_RXBUFFER_256:
2041                 rctl |= E1000_RCTL_SZ_256;
2042                 break;
2043         case IGB_RXBUFFER_512:
2044                 rctl |= E1000_RCTL_SZ_512;
2045                 break;
2046         default:
2047                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2048                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2049                 break;
2050         }
2051
2052         /* 82575 and greater support packet-split where the protocol
2053          * header is placed in skb->data and the packet data is
2054          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2055          * In the case of a non-split, skb->data is linearly filled,
2056          * followed by the page buffers.  Therefore, skb->data is
2057          * sized to hold the largest protocol header.
2058          */
2059         /* allocations using alloc_page take too long for regular MTU
2060          * so only enable packet split for jumbo frames */
2061         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2062                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2063                 srrctl |= adapter->rx_ps_hdr_size <<
2064                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2065                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2066         } else {
2067                 adapter->rx_ps_hdr_size = 0;
2068                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2069         }
2070
2071         /* Attention!!!  For SR-IOV PF driver operations you must enable
2072          * queue drop for all VF and PF queues to prevent head of line blocking
2073          * if an un-trusted VF does not provide descriptors to hardware.
2074          */
2075         if (adapter->vfs_allocated_count) {
2076                 u32 vmolr;
2077
2078                 /* set all queue drop enable bits */
2079                 wr32(E1000_QDE, ALL_QUEUES);
2080                 srrctl |= E1000_SRRCTL_DROP_EN;
2081
2082                 /* disable queue 0 to prevent tail write w/o re-config */
2083                 wr32(E1000_RXDCTL(0), 0);
2084
2085                 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2086                 if (rctl & E1000_RCTL_LPE)
2087                         vmolr |= E1000_VMOLR_LPE;
2088                 if (adapter->num_rx_queues > 1)
2089                         vmolr |= E1000_VMOLR_RSSE;
2090                 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2091         }
2092
2093         for (i = 0; i < adapter->num_rx_queues; i++) {
2094                 int j = adapter->rx_ring[i].reg_idx;
2095                 wr32(E1000_SRRCTL(j), srrctl);
2096         }
2097
2098         wr32(E1000_RCTL, rctl);
2099 }
2100
2101 /**
2102  * igb_rlpml_set - set maximum receive packet size
2103  * @adapter: board private structure
2104  *
2105  * Configure maximum receivable packet size.
2106  **/
2107 static void igb_rlpml_set(struct igb_adapter *adapter)
2108 {
2109         u32 max_frame_size = adapter->max_frame_size;
2110         struct e1000_hw *hw = &adapter->hw;
2111         u16 pf_id = adapter->vfs_allocated_count;
2112
2113         if (adapter->vlgrp)
2114                 max_frame_size += VLAN_TAG_SIZE;
2115
2116         /* if vfs are enabled we set RLPML to the largest possible request
2117          * size and set the VMOLR RLPML to the size we need */
2118         if (pf_id) {
2119                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2120                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2121         }
2122
2123         wr32(E1000_RLPML, max_frame_size);
2124 }
2125
2126 /**
2127  * igb_configure_vt_default_pool - Configure VT default pool
2128  * @adapter: board private structure
2129  *
2130  * Configure the default pool
2131  **/
2132 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2133 {
2134         struct e1000_hw *hw = &adapter->hw;
2135         u16 pf_id = adapter->vfs_allocated_count;
2136         u32 vtctl;
2137
2138         /* not in sr-iov mode - do nothing */
2139         if (!pf_id)
2140                 return;
2141
2142         vtctl = rd32(E1000_VT_CTL);
2143         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2144                    E1000_VT_CTL_DISABLE_DEF_POOL);
2145         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2146         wr32(E1000_VT_CTL, vtctl);
2147 }
2148
2149 /**
2150  * igb_configure_rx - Configure receive Unit after Reset
2151  * @adapter: board private structure
2152  *
2153  * Configure the Rx unit of the MAC after a reset.
2154  **/
2155 static void igb_configure_rx(struct igb_adapter *adapter)
2156 {
2157         u64 rdba;
2158         struct e1000_hw *hw = &adapter->hw;
2159         u32 rctl, rxcsum;
2160         u32 rxdctl;
2161         int i;
2162
2163         /* disable receives while setting up the descriptors */
2164         rctl = rd32(E1000_RCTL);
2165         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2166         wrfl();
2167         mdelay(10);
2168
2169         if (adapter->itr_setting > 3)
2170                 wr32(E1000_ITR, adapter->itr);
2171
2172         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2173          * the Base and Length of the Rx Descriptor Ring */
2174         for (i = 0; i < adapter->num_rx_queues; i++) {
2175                 struct igb_ring *ring = &adapter->rx_ring[i];
2176                 int j = ring->reg_idx;
2177                 rdba = ring->dma;
2178                 wr32(E1000_RDBAL(j),
2179                      rdba & 0x00000000ffffffffULL);
2180                 wr32(E1000_RDBAH(j), rdba >> 32);
2181                 wr32(E1000_RDLEN(j),
2182                      ring->count * sizeof(union e1000_adv_rx_desc));
2183
2184                 ring->head = E1000_RDH(j);
2185                 ring->tail = E1000_RDT(j);
2186                 writel(0, hw->hw_addr + ring->tail);
2187                 writel(0, hw->hw_addr + ring->head);
2188
2189                 rxdctl = rd32(E1000_RXDCTL(j));
2190                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2191                 rxdctl &= 0xFFF00000;
2192                 rxdctl |= IGB_RX_PTHRESH;
2193                 rxdctl |= IGB_RX_HTHRESH << 8;
2194                 rxdctl |= IGB_RX_WTHRESH << 16;
2195                 wr32(E1000_RXDCTL(j), rxdctl);
2196         }
2197
2198         if (adapter->num_rx_queues > 1) {
2199                 u32 random[10];
2200                 u32 mrqc;
2201                 u32 j, shift;
2202                 union e1000_reta {
2203                         u32 dword;
2204                         u8  bytes[4];
2205                 } reta;
2206
2207                 get_random_bytes(&random[0], 40);
2208
2209                 if (hw->mac.type >= e1000_82576)
2210                         shift = 0;
2211                 else
2212                         shift = 6;
2213                 for (j = 0; j < (32 * 4); j++) {
2214                         reta.bytes[j & 3] =
2215                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2216                         if ((j & 3) == 3)
2217                                 writel(reta.dword,
2218                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2219                 }
2220                 if (adapter->vfs_allocated_count)
2221                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2222                 else
2223                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2224
2225                 /* Fill out hash function seeds */
2226                 for (j = 0; j < 10; j++)
2227                         array_wr32(E1000_RSSRK(0), j, random[j]);
2228
2229                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2230                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2231                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2232                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2233                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2234                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2235                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2236                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2237
2238                 wr32(E1000_MRQC, mrqc);
2239         } else if (adapter->vfs_allocated_count) {
2240                 /* Enable multi-queue for sr-iov */
2241                 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2242         }
2243
2244         /* Enable Receive Checksum Offload for TCP and UDP */
2245         rxcsum = rd32(E1000_RXCSUM);
2246         /* Disable raw packet checksumming */
2247         rxcsum |= E1000_RXCSUM_PCSD;
2248
2249         if (adapter->hw.mac.type == e1000_82576)
2250                 /* Enable Receive Checksum Offload for SCTP */
2251                 rxcsum |= E1000_RXCSUM_CRCOFL;
2252
2253         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2254         wr32(E1000_RXCSUM, rxcsum);
2255
2256         /* Set the default pool for the PF's first queue */
2257         igb_configure_vt_default_pool(adapter);
2258
2259         igb_rlpml_set(adapter);
2260
2261         /* Enable Receives */
2262         wr32(E1000_RCTL, rctl);
2263 }
2264
2265 /**
2266  * igb_free_tx_resources - Free Tx Resources per Queue
2267  * @tx_ring: Tx descriptor ring for a specific queue
2268  *
2269  * Free all transmit software resources
2270  **/
2271 void igb_free_tx_resources(struct igb_ring *tx_ring)
2272 {
2273         struct pci_dev *pdev = tx_ring->adapter->pdev;
2274
2275         igb_clean_tx_ring(tx_ring);
2276
2277         vfree(tx_ring->buffer_info);
2278         tx_ring->buffer_info = NULL;
2279
2280         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2281
2282         tx_ring->desc = NULL;
2283 }
2284
2285 /**
2286  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2287  * @adapter: board private structure
2288  *
2289  * Free all transmit software resources
2290  **/
2291 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2292 {
2293         int i;
2294
2295         for (i = 0; i < adapter->num_tx_queues; i++)
2296                 igb_free_tx_resources(&adapter->tx_ring[i]);
2297 }
2298
2299 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2300                                            struct igb_buffer *buffer_info)
2301 {
2302         buffer_info->dma = 0;
2303         if (buffer_info->skb) {
2304                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2305                               DMA_TO_DEVICE);
2306                 dev_kfree_skb_any(buffer_info->skb);
2307                 buffer_info->skb = NULL;
2308         }
2309         buffer_info->time_stamp = 0;
2310         /* buffer_info must be completely set up in the transmit path */
2311 }
2312
2313 /**
2314  * igb_clean_tx_ring - Free Tx Buffers
2315  * @tx_ring: ring to be cleaned
2316  **/
2317 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2318 {
2319         struct igb_adapter *adapter = tx_ring->adapter;
2320         struct igb_buffer *buffer_info;
2321         unsigned long size;
2322         unsigned int i;
2323
2324         if (!tx_ring->buffer_info)
2325                 return;
2326         /* Free all the Tx ring sk_buffs */
2327
2328         for (i = 0; i < tx_ring->count; i++) {
2329                 buffer_info = &tx_ring->buffer_info[i];
2330                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2331         }
2332
2333         size = sizeof(struct igb_buffer) * tx_ring->count;
2334         memset(tx_ring->buffer_info, 0, size);
2335
2336         /* Zero out the descriptor ring */
2337
2338         memset(tx_ring->desc, 0, tx_ring->size);
2339
2340         tx_ring->next_to_use = 0;
2341         tx_ring->next_to_clean = 0;
2342
2343         writel(0, adapter->hw.hw_addr + tx_ring->head);
2344         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2345 }
2346
2347 /**
2348  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2349  * @adapter: board private structure
2350  **/
2351 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2352 {
2353         int i;
2354
2355         for (i = 0; i < adapter->num_tx_queues; i++)
2356                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2357 }
2358
2359 /**
2360  * igb_free_rx_resources - Free Rx Resources
2361  * @rx_ring: ring to clean the resources from
2362  *
2363  * Free all receive software resources
2364  **/
2365 void igb_free_rx_resources(struct igb_ring *rx_ring)
2366 {
2367         struct pci_dev *pdev = rx_ring->adapter->pdev;
2368
2369         igb_clean_rx_ring(rx_ring);
2370
2371         vfree(rx_ring->buffer_info);
2372         rx_ring->buffer_info = NULL;
2373
2374         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2375
2376         rx_ring->desc = NULL;
2377 }
2378
2379 /**
2380  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2381  * @adapter: board private structure
2382  *
2383  * Free all receive software resources
2384  **/
2385 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2386 {
2387         int i;
2388
2389         for (i = 0; i < adapter->num_rx_queues; i++)
2390                 igb_free_rx_resources(&adapter->rx_ring[i]);
2391 }
2392
2393 /**
2394  * igb_clean_rx_ring - Free Rx Buffers per Queue
2395  * @rx_ring: ring to free buffers from
2396  **/
2397 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2398 {
2399         struct igb_adapter *adapter = rx_ring->adapter;
2400         struct igb_buffer *buffer_info;
2401         struct pci_dev *pdev = adapter->pdev;
2402         unsigned long size;
2403         unsigned int i;
2404
2405         if (!rx_ring->buffer_info)
2406                 return;
2407         /* Free all the Rx ring sk_buffs */
2408         for (i = 0; i < rx_ring->count; i++) {
2409                 buffer_info = &rx_ring->buffer_info[i];
2410                 if (buffer_info->dma) {
2411                         if (adapter->rx_ps_hdr_size)
2412                                 pci_unmap_single(pdev, buffer_info->dma,
2413                                                  adapter->rx_ps_hdr_size,
2414                                                  PCI_DMA_FROMDEVICE);
2415                         else
2416                                 pci_unmap_single(pdev, buffer_info->dma,
2417                                                  adapter->rx_buffer_len,
2418                                                  PCI_DMA_FROMDEVICE);
2419                         buffer_info->dma = 0;
2420                 }
2421
2422                 if (buffer_info->skb) {
2423                         dev_kfree_skb(buffer_info->skb);
2424                         buffer_info->skb = NULL;
2425                 }
2426                 if (buffer_info->page) {
2427                         if (buffer_info->page_dma)
2428                                 pci_unmap_page(pdev, buffer_info->page_dma,
2429                                                PAGE_SIZE / 2,
2430                                                PCI_DMA_FROMDEVICE);
2431                         put_page(buffer_info->page);
2432                         buffer_info->page = NULL;
2433                         buffer_info->page_dma = 0;
2434                         buffer_info->page_offset = 0;
2435                 }
2436         }
2437
2438         size = sizeof(struct igb_buffer) * rx_ring->count;
2439         memset(rx_ring->buffer_info, 0, size);
2440
2441         /* Zero out the descriptor ring */
2442         memset(rx_ring->desc, 0, rx_ring->size);
2443
2444         rx_ring->next_to_clean = 0;
2445         rx_ring->next_to_use = 0;
2446
2447         writel(0, adapter->hw.hw_addr + rx_ring->head);
2448         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2449 }
2450
2451 /**
2452  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2453  * @adapter: board private structure
2454  **/
2455 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2456 {
2457         int i;
2458
2459         for (i = 0; i < adapter->num_rx_queues; i++)
2460                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2461 }
2462
2463 /**
2464  * igb_set_mac - Change the Ethernet Address of the NIC
2465  * @netdev: network interface device structure
2466  * @p: pointer to an address structure
2467  *
2468  * Returns 0 on success, negative on failure
2469  **/
2470 static int igb_set_mac(struct net_device *netdev, void *p)
2471 {
2472         struct igb_adapter *adapter = netdev_priv(netdev);
2473         struct e1000_hw *hw = &adapter->hw;
2474         struct sockaddr *addr = p;
2475
2476         if (!is_valid_ether_addr(addr->sa_data))
2477                 return -EADDRNOTAVAIL;
2478
2479         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2480         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2481
2482         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2483
2484         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2485
2486         return 0;
2487 }
2488
2489 /**
2490  * igb_set_multi - Multicast and Promiscuous mode set
2491  * @netdev: network interface device structure
2492  *
2493  * The set_multi entry point is called whenever the multicast address
2494  * list or the network interface flags are updated.  This routine is
2495  * responsible for configuring the hardware for proper multicast,
2496  * promiscuous mode, and all-multi behavior.
2497  **/
2498 static void igb_set_multi(struct net_device *netdev)
2499 {
2500         struct igb_adapter *adapter = netdev_priv(netdev);
2501         struct e1000_hw *hw = &adapter->hw;
2502         struct e1000_mac_info *mac = &hw->mac;
2503         struct dev_mc_list *mc_ptr;
2504         u8  *mta_list = NULL;
2505         u32 rctl;
2506         int i;
2507
2508         /* Check for Promiscuous and All Multicast modes */
2509
2510         rctl = rd32(E1000_RCTL);
2511
2512         if (netdev->flags & IFF_PROMISC) {
2513                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2514                 rctl &= ~E1000_RCTL_VFE;
2515         } else {
2516                 if (netdev->flags & IFF_ALLMULTI) {
2517                         rctl |= E1000_RCTL_MPE;
2518                         rctl &= ~E1000_RCTL_UPE;
2519                 } else
2520                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2521                 rctl |= E1000_RCTL_VFE;
2522         }
2523         wr32(E1000_RCTL, rctl);
2524
2525         if (netdev->mc_count) {
2526                 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2527                 if (!mta_list) {
2528                         dev_err(&adapter->pdev->dev,
2529                                 "failed to allocate multicast filter list\n");
2530                         return;
2531                 }
2532         }
2533
2534         /* The shared function expects a packed array of only addresses. */
2535         mc_ptr = netdev->mc_list;
2536
2537         for (i = 0; i < netdev->mc_count; i++) {
2538                 if (!mc_ptr)
2539                         break;
2540                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2541                 mc_ptr = mc_ptr->next;
2542         }
2543         igb_update_mc_addr_list(hw, mta_list, i,
2544                                 adapter->vfs_allocated_count + 1,
2545                                 mac->rar_entry_count);
2546
2547         igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2548         igb_restore_vf_multicasts(adapter);
2549
2550         kfree(mta_list);
2551 }
2552
2553 /* Need to wait a few seconds after link up to get diagnostic information from
2554  * the phy */
2555 static void igb_update_phy_info(unsigned long data)
2556 {
2557         struct igb_adapter *adapter = (struct igb_adapter *) data;
2558         igb_get_phy_info(&adapter->hw);
2559 }
2560
2561 /**
2562  * igb_has_link - check shared code for link and determine up/down
2563  * @adapter: pointer to driver private info
2564  **/
2565 static bool igb_has_link(struct igb_adapter *adapter)
2566 {
2567         struct e1000_hw *hw = &adapter->hw;
2568         bool link_active = false;
2569         s32 ret_val = 0;
2570
2571         /* get_link_status is set on LSC (link status) interrupt or
2572          * rx sequence error interrupt.  get_link_status will stay
2573          * false until the e1000_check_for_link establishes link
2574          * for copper adapters ONLY
2575          */
2576         switch (hw->phy.media_type) {
2577         case e1000_media_type_copper:
2578                 if (hw->mac.get_link_status) {
2579                         ret_val = hw->mac.ops.check_for_link(hw);
2580                         link_active = !hw->mac.get_link_status;
2581                 } else {
2582                         link_active = true;
2583                 }
2584                 break;
2585         case e1000_media_type_fiber:
2586                 ret_val = hw->mac.ops.check_for_link(hw);
2587                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2588                 break;
2589         case e1000_media_type_internal_serdes:
2590                 ret_val = hw->mac.ops.check_for_link(hw);
2591                 link_active = hw->mac.serdes_has_link;
2592                 break;
2593         default:
2594         case e1000_media_type_unknown:
2595                 break;
2596         }
2597
2598         return link_active;
2599 }
2600
2601 /**
2602  * igb_watchdog - Timer Call-back
2603  * @data: pointer to adapter cast into an unsigned long
2604  **/
2605 static void igb_watchdog(unsigned long data)
2606 {
2607         struct igb_adapter *adapter = (struct igb_adapter *)data;
2608         /* Do the rest outside of interrupt context */
2609         schedule_work(&adapter->watchdog_task);
2610 }
2611
2612 static void igb_watchdog_task(struct work_struct *work)
2613 {
2614         struct igb_adapter *adapter = container_of(work,
2615                                         struct igb_adapter, watchdog_task);
2616         struct e1000_hw *hw = &adapter->hw;
2617         struct net_device *netdev = adapter->netdev;
2618         struct igb_ring *tx_ring = adapter->tx_ring;
2619         u32 link;
2620         u32 eics = 0;
2621         int i;
2622
2623         link = igb_has_link(adapter);
2624         if ((netif_carrier_ok(netdev)) && link)
2625                 goto link_up;
2626
2627         if (link) {
2628                 if (!netif_carrier_ok(netdev)) {
2629                         u32 ctrl;
2630                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2631                                                    &adapter->link_speed,
2632                                                    &adapter->link_duplex);
2633
2634                         ctrl = rd32(E1000_CTRL);
2635                         /* Links status message must follow this format */
2636                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2637                                  "Flow Control: %s\n",
2638                                  netdev->name,
2639                                  adapter->link_speed,
2640                                  adapter->link_duplex == FULL_DUPLEX ?
2641                                  "Full Duplex" : "Half Duplex",
2642                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2643                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2644                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2645                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2646
2647                         /* tweak tx_queue_len according to speed/duplex and
2648                          * adjust the timeout factor */
2649                         netdev->tx_queue_len = adapter->tx_queue_len;
2650                         adapter->tx_timeout_factor = 1;
2651                         switch (adapter->link_speed) {
2652                         case SPEED_10:
2653                                 netdev->tx_queue_len = 10;
2654                                 adapter->tx_timeout_factor = 14;
2655                                 break;
2656                         case SPEED_100:
2657                                 netdev->tx_queue_len = 100;
2658                                 /* maybe add some timeout factor ? */
2659                                 break;
2660                         }
2661
2662                         netif_carrier_on(netdev);
2663
2664                         igb_ping_all_vfs(adapter);
2665
2666                         /* link state has changed, schedule phy info update */
2667                         if (!test_bit(__IGB_DOWN, &adapter->state))
2668                                 mod_timer(&adapter->phy_info_timer,
2669                                           round_jiffies(jiffies + 2 * HZ));
2670                 }
2671         } else {
2672                 if (netif_carrier_ok(netdev)) {
2673                         adapter->link_speed = 0;
2674                         adapter->link_duplex = 0;
2675                         /* Links status message must follow this format */
2676                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2677                                netdev->name);
2678                         netif_carrier_off(netdev);
2679
2680                         igb_ping_all_vfs(adapter);
2681
2682                         /* link state has changed, schedule phy info update */
2683                         if (!test_bit(__IGB_DOWN, &adapter->state))
2684                                 mod_timer(&adapter->phy_info_timer,
2685                                           round_jiffies(jiffies + 2 * HZ));
2686                 }
2687         }
2688
2689 link_up:
2690         igb_update_stats(adapter);
2691
2692         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2693         adapter->tpt_old = adapter->stats.tpt;
2694         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2695         adapter->colc_old = adapter->stats.colc;
2696
2697         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2698         adapter->gorc_old = adapter->stats.gorc;
2699         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2700         adapter->gotc_old = adapter->stats.gotc;
2701
2702         igb_update_adaptive(&adapter->hw);
2703
2704         if (!netif_carrier_ok(netdev)) {
2705                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2706                         /* We've lost link, so the controller stops DMA,
2707                          * but we've got queued Tx work that's never going
2708                          * to get done, so reset controller to flush Tx.
2709                          * (Do the reset outside of interrupt context). */
2710                         adapter->tx_timeout_count++;
2711                         schedule_work(&adapter->reset_task);
2712                         /* return immediately since reset is imminent */
2713                         return;
2714                 }
2715         }
2716
2717         /* Cause software interrupt to ensure rx ring is cleaned */
2718         if (adapter->msix_entries) {
2719                 for (i = 0; i < adapter->num_rx_queues; i++)
2720                         eics |= adapter->rx_ring[i].eims_value;
2721                 wr32(E1000_EICS, eics);
2722         } else {
2723                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2724         }
2725
2726         /* Force detection of hung controller every watchdog period */
2727         tx_ring->detect_tx_hung = true;
2728
2729         /* Reset the timer */
2730         if (!test_bit(__IGB_DOWN, &adapter->state))
2731                 mod_timer(&adapter->watchdog_timer,
2732                           round_jiffies(jiffies + 2 * HZ));
2733 }
2734
2735 enum latency_range {
2736         lowest_latency = 0,
2737         low_latency = 1,
2738         bulk_latency = 2,
2739         latency_invalid = 255
2740 };
2741
2742
2743 /**
2744  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2745  *
2746  *      Stores a new ITR value based on strictly on packet size.  This
2747  *      algorithm is less sophisticated than that used in igb_update_itr,
2748  *      due to the difficulty of synchronizing statistics across multiple
2749  *      receive rings.  The divisors and thresholds used by this fuction
2750  *      were determined based on theoretical maximum wire speed and testing
2751  *      data, in order to minimize response time while increasing bulk
2752  *      throughput.
2753  *      This functionality is controlled by the InterruptThrottleRate module
2754  *      parameter (see igb_param.c)
2755  *      NOTE:  This function is called only when operating in a multiqueue
2756  *             receive environment.
2757  * @rx_ring: pointer to ring
2758  **/
2759 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2760 {
2761         int new_val = rx_ring->itr_val;
2762         int avg_wire_size = 0;
2763         struct igb_adapter *adapter = rx_ring->adapter;
2764
2765         if (!rx_ring->total_packets)
2766                 goto clear_counts; /* no packets, so don't do anything */
2767
2768         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2769          * ints/sec - ITR timer value of 120 ticks.
2770          */
2771         if (adapter->link_speed != SPEED_1000) {
2772                 new_val = 120;
2773                 goto set_itr_val;
2774         }
2775         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2776
2777         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2778         avg_wire_size += 24;
2779
2780         /* Don't starve jumbo frames */
2781         avg_wire_size = min(avg_wire_size, 3000);
2782
2783         /* Give a little boost to mid-size frames */
2784         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2785                 new_val = avg_wire_size / 3;
2786         else
2787                 new_val = avg_wire_size / 2;
2788
2789 set_itr_val:
2790         if (new_val != rx_ring->itr_val) {
2791                 rx_ring->itr_val = new_val;
2792                 rx_ring->set_itr = 1;
2793         }
2794 clear_counts:
2795         rx_ring->total_bytes = 0;
2796         rx_ring->total_packets = 0;
2797 }
2798
2799 /**
2800  * igb_update_itr - update the dynamic ITR value based on statistics
2801  *      Stores a new ITR value based on packets and byte
2802  *      counts during the last interrupt.  The advantage of per interrupt
2803  *      computation is faster updates and more accurate ITR for the current
2804  *      traffic pattern.  Constants in this function were computed
2805  *      based on theoretical maximum wire speed and thresholds were set based
2806  *      on testing data as well as attempting to minimize response time
2807  *      while increasing bulk throughput.
2808  *      this functionality is controlled by the InterruptThrottleRate module
2809  *      parameter (see igb_param.c)
2810  *      NOTE:  These calculations are only valid when operating in a single-
2811  *             queue environment.
2812  * @adapter: pointer to adapter
2813  * @itr_setting: current adapter->itr
2814  * @packets: the number of packets during this measurement interval
2815  * @bytes: the number of bytes during this measurement interval
2816  **/
2817 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2818                                    int packets, int bytes)
2819 {
2820         unsigned int retval = itr_setting;
2821
2822         if (packets == 0)
2823                 goto update_itr_done;
2824
2825         switch (itr_setting) {
2826         case lowest_latency:
2827                 /* handle TSO and jumbo frames */
2828                 if (bytes/packets > 8000)
2829                         retval = bulk_latency;
2830                 else if ((packets < 5) && (bytes > 512))
2831                         retval = low_latency;
2832                 break;
2833         case low_latency:  /* 50 usec aka 20000 ints/s */
2834                 if (bytes > 10000) {
2835                         /* this if handles the TSO accounting */
2836                         if (bytes/packets > 8000) {
2837                                 retval = bulk_latency;
2838                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2839                                 retval = bulk_latency;
2840                         } else if ((packets > 35)) {
2841                                 retval = lowest_latency;
2842                         }
2843                 } else if (bytes/packets > 2000) {
2844                         retval = bulk_latency;
2845                 } else if (packets <= 2 && bytes < 512) {
2846                         retval = lowest_latency;
2847                 }
2848                 break;
2849         case bulk_latency: /* 250 usec aka 4000 ints/s */
2850                 if (bytes > 25000) {
2851                         if (packets > 35)
2852                                 retval = low_latency;
2853                 } else if (bytes < 1500) {
2854                         retval = low_latency;
2855                 }
2856                 break;
2857         }
2858
2859 update_itr_done:
2860         return retval;
2861 }
2862
2863 static void igb_set_itr(struct igb_adapter *adapter)
2864 {
2865         u16 current_itr;
2866         u32 new_itr = adapter->itr;
2867
2868         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2869         if (adapter->link_speed != SPEED_1000) {
2870                 current_itr = 0;
2871                 new_itr = 4000;
2872                 goto set_itr_now;
2873         }
2874
2875         adapter->rx_itr = igb_update_itr(adapter,
2876                                     adapter->rx_itr,
2877                                     adapter->rx_ring->total_packets,
2878                                     adapter->rx_ring->total_bytes);
2879
2880         if (adapter->rx_ring->buddy) {
2881                 adapter->tx_itr = igb_update_itr(adapter,
2882                                             adapter->tx_itr,
2883                                             adapter->tx_ring->total_packets,
2884                                             adapter->tx_ring->total_bytes);
2885                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2886         } else {
2887                 current_itr = adapter->rx_itr;
2888         }
2889
2890         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2891         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2892                 current_itr = low_latency;
2893
2894         switch (current_itr) {
2895         /* counts and packets in update_itr are dependent on these numbers */
2896         case lowest_latency:
2897                 new_itr = 56;  /* aka 70,000 ints/sec */
2898                 break;
2899         case low_latency:
2900                 new_itr = 196; /* aka 20,000 ints/sec */
2901                 break;
2902         case bulk_latency:
2903                 new_itr = 980; /* aka 4,000 ints/sec */
2904                 break;
2905         default:
2906                 break;
2907         }
2908
2909 set_itr_now:
2910         adapter->rx_ring->total_bytes = 0;
2911         adapter->rx_ring->total_packets = 0;
2912         if (adapter->rx_ring->buddy) {
2913                 adapter->rx_ring->buddy->total_bytes = 0;
2914                 adapter->rx_ring->buddy->total_packets = 0;
2915         }
2916
2917         if (new_itr != adapter->itr) {
2918                 /* this attempts to bias the interrupt rate towards Bulk
2919                  * by adding intermediate steps when interrupt rate is
2920                  * increasing */
2921                 new_itr = new_itr > adapter->itr ?
2922                              max((new_itr * adapter->itr) /
2923                                  (new_itr + (adapter->itr >> 2)), new_itr) :
2924                              new_itr;
2925                 /* Don't write the value here; it resets the adapter's
2926                  * internal timer, and causes us to delay far longer than
2927                  * we should between interrupts.  Instead, we write the ITR
2928                  * value at the beginning of the next interrupt so the timing
2929                  * ends up being correct.
2930                  */
2931                 adapter->itr = new_itr;
2932                 adapter->rx_ring->itr_val = new_itr;
2933                 adapter->rx_ring->set_itr = 1;
2934         }
2935
2936         return;
2937 }
2938
2939
2940 #define IGB_TX_FLAGS_CSUM               0x00000001
2941 #define IGB_TX_FLAGS_VLAN               0x00000002
2942 #define IGB_TX_FLAGS_TSO                0x00000004
2943 #define IGB_TX_FLAGS_IPV4               0x00000008
2944 #define IGB_TX_FLAGS_TSTAMP             0x00000010
2945 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2946 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2947
2948 static inline int igb_tso_adv(struct igb_adapter *adapter,
2949                               struct igb_ring *tx_ring,
2950                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2951 {
2952         struct e1000_adv_tx_context_desc *context_desc;
2953         unsigned int i;
2954         int err;
2955         struct igb_buffer *buffer_info;
2956         u32 info = 0, tu_cmd = 0;
2957         u32 mss_l4len_idx, l4len;
2958         *hdr_len = 0;
2959
2960         if (skb_header_cloned(skb)) {
2961                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2962                 if (err)
2963                         return err;
2964         }
2965
2966         l4len = tcp_hdrlen(skb);
2967         *hdr_len += l4len;
2968
2969         if (skb->protocol == htons(ETH_P_IP)) {
2970                 struct iphdr *iph = ip_hdr(skb);
2971                 iph->tot_len = 0;
2972                 iph->check = 0;
2973                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2974                                                          iph->daddr, 0,
2975                                                          IPPROTO_TCP,
2976                                                          0);
2977         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2978                 ipv6_hdr(skb)->payload_len = 0;
2979                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2980                                                        &ipv6_hdr(skb)->daddr,
2981                                                        0, IPPROTO_TCP, 0);
2982         }
2983
2984         i = tx_ring->next_to_use;
2985
2986         buffer_info = &tx_ring->buffer_info[i];
2987         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2988         /* VLAN MACLEN IPLEN */
2989         if (tx_flags & IGB_TX_FLAGS_VLAN)
2990                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2991         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2992         *hdr_len += skb_network_offset(skb);
2993         info |= skb_network_header_len(skb);
2994         *hdr_len += skb_network_header_len(skb);
2995         context_desc->vlan_macip_lens = cpu_to_le32(info);
2996
2997         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2998         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2999
3000         if (skb->protocol == htons(ETH_P_IP))
3001                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3002         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3003
3004         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3005
3006         /* MSS L4LEN IDX */
3007         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3008         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3009
3010         /* For 82575, context index must be unique per ring. */
3011         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3012                 mss_l4len_idx |= tx_ring->queue_index << 4;
3013
3014         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3015         context_desc->seqnum_seed = 0;
3016
3017         buffer_info->time_stamp = jiffies;
3018         buffer_info->next_to_watch = i;
3019         buffer_info->dma = 0;
3020         i++;
3021         if (i == tx_ring->count)
3022                 i = 0;
3023
3024         tx_ring->next_to_use = i;
3025
3026         return true;
3027 }
3028
3029 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3030                                         struct igb_ring *tx_ring,
3031                                         struct sk_buff *skb, u32 tx_flags)
3032 {
3033         struct e1000_adv_tx_context_desc *context_desc;
3034         unsigned int i;
3035         struct igb_buffer *buffer_info;
3036         u32 info = 0, tu_cmd = 0;
3037
3038         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3039             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3040                 i = tx_ring->next_to_use;
3041                 buffer_info = &tx_ring->buffer_info[i];
3042                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3043
3044                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3045                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3046                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3047                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3048                         info |= skb_network_header_len(skb);
3049
3050                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3051
3052                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3053
3054                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3055                         __be16 protocol;
3056
3057                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3058                                 const struct vlan_ethhdr *vhdr =
3059                                           (const struct vlan_ethhdr*)skb->data;
3060
3061                                 protocol = vhdr->h_vlan_encapsulated_proto;
3062                         } else {
3063                                 protocol = skb->protocol;
3064                         }
3065
3066                         switch (protocol) {
3067                         case cpu_to_be16(ETH_P_IP):
3068                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3069                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3070                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3071                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3072                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3073                                 break;
3074                         case cpu_to_be16(ETH_P_IPV6):
3075                                 /* XXX what about other V6 headers?? */
3076                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3077                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3078                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3079                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3080                                 break;
3081                         default:
3082                                 if (unlikely(net_ratelimit()))
3083                                         dev_warn(&adapter->pdev->dev,
3084                                             "partial checksum but proto=%x!\n",
3085                                             skb->protocol);
3086                                 break;
3087                         }
3088                 }
3089
3090                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3091                 context_desc->seqnum_seed = 0;
3092                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3093                         context_desc->mss_l4len_idx =
3094                                 cpu_to_le32(tx_ring->queue_index << 4);
3095                 else
3096                         context_desc->mss_l4len_idx = 0;
3097
3098                 buffer_info->time_stamp = jiffies;
3099                 buffer_info->next_to_watch = i;
3100                 buffer_info->dma = 0;
3101
3102                 i++;
3103                 if (i == tx_ring->count)
3104                         i = 0;
3105                 tx_ring->next_to_use = i;
3106
3107                 return true;
3108         }
3109         return false;
3110 }
3111
3112 #define IGB_MAX_TXD_PWR 16
3113 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3114
3115 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3116                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3117                                  unsigned int first)
3118 {
3119         struct igb_buffer *buffer_info;
3120         unsigned int len = skb_headlen(skb);
3121         unsigned int count = 0, i;
3122         unsigned int f;
3123         dma_addr_t *map;
3124
3125         i = tx_ring->next_to_use;
3126
3127         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3128                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3129                 return 0;
3130         }
3131
3132         map = skb_shinfo(skb)->dma_maps;
3133
3134         buffer_info = &tx_ring->buffer_info[i];
3135         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3136         buffer_info->length = len;
3137         /* set time_stamp *before* dma to help avoid a possible race */
3138         buffer_info->time_stamp = jiffies;
3139         buffer_info->next_to_watch = i;
3140         buffer_info->dma = map[count];
3141         count++;
3142
3143         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3144                 struct skb_frag_struct *frag;
3145
3146                 i++;
3147                 if (i == tx_ring->count)
3148                         i = 0;
3149
3150                 frag = &skb_shinfo(skb)->frags[f];
3151                 len = frag->size;
3152
3153                 buffer_info = &tx_ring->buffer_info[i];
3154                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3155                 buffer_info->length = len;
3156                 buffer_info->time_stamp = jiffies;
3157                 buffer_info->next_to_watch = i;
3158                 buffer_info->dma = map[count];
3159                 count++;
3160         }
3161
3162         tx_ring->buffer_info[i].skb = skb;
3163         tx_ring->buffer_info[first].next_to_watch = i;
3164
3165         return count;
3166 }
3167
3168 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3169                                     struct igb_ring *tx_ring,
3170                                     int tx_flags, int count, u32 paylen,
3171                                     u8 hdr_len)
3172 {
3173         union e1000_adv_tx_desc *tx_desc = NULL;
3174         struct igb_buffer *buffer_info;
3175         u32 olinfo_status = 0, cmd_type_len;
3176         unsigned int i;
3177
3178         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3179                         E1000_ADVTXD_DCMD_DEXT);
3180
3181         if (tx_flags & IGB_TX_FLAGS_VLAN)
3182                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3183
3184         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3185                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3186
3187         if (tx_flags & IGB_TX_FLAGS_TSO) {
3188                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3189
3190                 /* insert tcp checksum */
3191                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3192
3193                 /* insert ip checksum */
3194                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3195                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3196
3197         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3198                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3199         }
3200
3201         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3202             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3203                          IGB_TX_FLAGS_VLAN)))
3204                 olinfo_status |= tx_ring->queue_index << 4;
3205
3206         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3207
3208         i = tx_ring->next_to_use;
3209         while (count--) {
3210                 buffer_info = &tx_ring->buffer_info[i];
3211                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3212                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3213                 tx_desc->read.cmd_type_len =
3214                         cpu_to_le32(cmd_type_len | buffer_info->length);
3215                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3216                 i++;
3217                 if (i == tx_ring->count)
3218                         i = 0;
3219         }
3220
3221         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3222         /* Force memory writes to complete before letting h/w
3223          * know there are new descriptors to fetch.  (Only
3224          * applicable for weak-ordered memory model archs,
3225          * such as IA-64). */
3226         wmb();
3227
3228         tx_ring->next_to_use = i;
3229         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3230         /* we need this if more than one processor can write to our tail
3231          * at a time, it syncronizes IO on IA64/Altix systems */
3232         mmiowb();
3233 }
3234
3235 static int __igb_maybe_stop_tx(struct net_device *netdev,
3236                                struct igb_ring *tx_ring, int size)
3237 {
3238         struct igb_adapter *adapter = netdev_priv(netdev);
3239
3240         netif_stop_subqueue(netdev, tx_ring->queue_index);
3241
3242         /* Herbert's original patch had:
3243          *  smp_mb__after_netif_stop_queue();
3244          * but since that doesn't exist yet, just open code it. */
3245         smp_mb();
3246
3247         /* We need to check again in a case another CPU has just
3248          * made room available. */
3249         if (igb_desc_unused(tx_ring) < size)
3250                 return -EBUSY;
3251
3252         /* A reprieve! */
3253         netif_wake_subqueue(netdev, tx_ring->queue_index);
3254         ++adapter->restart_queue;
3255         return 0;
3256 }
3257
3258 static int igb_maybe_stop_tx(struct net_device *netdev,
3259                              struct igb_ring *tx_ring, int size)
3260 {
3261         if (igb_desc_unused(tx_ring) >= size)
3262                 return 0;
3263         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3264 }
3265
3266 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3267                                    struct net_device *netdev,
3268                                    struct igb_ring *tx_ring)
3269 {
3270         struct igb_adapter *adapter = netdev_priv(netdev);
3271         unsigned int first;
3272         unsigned int tx_flags = 0;
3273         u8 hdr_len = 0;
3274         int count = 0;
3275         int tso = 0;
3276         union skb_shared_tx *shtx;
3277
3278         if (test_bit(__IGB_DOWN, &adapter->state)) {
3279                 dev_kfree_skb_any(skb);
3280                 return NETDEV_TX_OK;
3281         }
3282
3283         if (skb->len <= 0) {
3284                 dev_kfree_skb_any(skb);
3285                 return NETDEV_TX_OK;
3286         }
3287
3288         /* need: 1 descriptor per page,
3289          *       + 2 desc gap to keep tail from touching head,
3290          *       + 1 desc for skb->data,
3291          *       + 1 desc for context descriptor,
3292          * otherwise try next time */
3293         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3294                 /* this is a hard error */
3295                 return NETDEV_TX_BUSY;
3296         }
3297
3298         /*
3299          * TODO: check that there currently is no other packet with
3300          * time stamping in the queue
3301          *
3302          * When doing time stamping, keep the connection to the socket
3303          * a while longer: it is still needed by skb_hwtstamp_tx(),
3304          * called either in igb_tx_hwtstamp() or by our caller when
3305          * doing software time stamping.
3306          */
3307         shtx = skb_tx(skb);
3308         if (unlikely(shtx->hardware)) {
3309                 shtx->in_progress = 1;
3310                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3311         }
3312
3313         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3314                 tx_flags |= IGB_TX_FLAGS_VLAN;
3315                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3316         }
3317
3318         if (skb->protocol == htons(ETH_P_IP))
3319                 tx_flags |= IGB_TX_FLAGS_IPV4;
3320
3321         first = tx_ring->next_to_use;
3322         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3323                                               &hdr_len) : 0;
3324
3325         if (tso < 0) {
3326                 dev_kfree_skb_any(skb);
3327                 return NETDEV_TX_OK;
3328         }
3329
3330         if (tso)
3331                 tx_flags |= IGB_TX_FLAGS_TSO;
3332         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3333                  (skb->ip_summed == CHECKSUM_PARTIAL))
3334                 tx_flags |= IGB_TX_FLAGS_CSUM;
3335
3336         /*
3337          * count reflects descriptors mapped, if 0 then mapping error
3338          * has occured and we need to rewind the descriptor queue
3339          */
3340         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3341
3342         if (count) {
3343                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3344                                  skb->len, hdr_len);
3345                 netdev->trans_start = jiffies;
3346                 /* Make sure there is space in the ring for the next send. */
3347                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3348         } else {
3349                 dev_kfree_skb_any(skb);
3350                 tx_ring->buffer_info[first].time_stamp = 0;
3351                 tx_ring->next_to_use = first;
3352         }
3353
3354         return NETDEV_TX_OK;
3355 }
3356
3357 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3358 {
3359         struct igb_adapter *adapter = netdev_priv(netdev);
3360         struct igb_ring *tx_ring;
3361
3362         int r_idx = 0;
3363         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3364         tx_ring = adapter->multi_tx_table[r_idx];
3365
3366         /* This goes back to the question of how to logically map a tx queue
3367          * to a flow.  Right now, performance is impacted slightly negatively
3368          * if using multiple tx queues.  If the stack breaks away from a
3369          * single qdisc implementation, we can look at this again. */
3370         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3371 }
3372
3373 /**
3374  * igb_tx_timeout - Respond to a Tx Hang
3375  * @netdev: network interface device structure
3376  **/
3377 static void igb_tx_timeout(struct net_device *netdev)
3378 {
3379         struct igb_adapter *adapter = netdev_priv(netdev);
3380         struct e1000_hw *hw = &adapter->hw;
3381
3382         /* Do the reset outside of interrupt context */
3383         adapter->tx_timeout_count++;
3384         schedule_work(&adapter->reset_task);
3385         wr32(E1000_EICS,
3386              (adapter->eims_enable_mask & ~adapter->eims_other));
3387 }
3388
3389 static void igb_reset_task(struct work_struct *work)
3390 {
3391         struct igb_adapter *adapter;
3392         adapter = container_of(work, struct igb_adapter, reset_task);
3393
3394         igb_reinit_locked(adapter);
3395 }
3396
3397 /**
3398  * igb_get_stats - Get System Network Statistics
3399  * @netdev: network interface device structure
3400  *
3401  * Returns the address of the device statistics structure.
3402  * The statistics are actually updated from the timer callback.
3403  **/
3404 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3405 {
3406         struct igb_adapter *adapter = netdev_priv(netdev);
3407
3408         /* only return the current stats */
3409         return &adapter->net_stats;
3410 }
3411
3412 /**
3413  * igb_change_mtu - Change the Maximum Transfer Unit
3414  * @netdev: network interface device structure
3415  * @new_mtu: new value for maximum frame size
3416  *
3417  * Returns 0 on success, negative on failure
3418  **/
3419 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3420 {
3421         struct igb_adapter *adapter = netdev_priv(netdev);
3422         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3423
3424         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3425             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3426                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3427                 return -EINVAL;
3428         }
3429
3430         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3431                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3432                 return -EINVAL;
3433         }
3434
3435         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3436                 msleep(1);
3437
3438         /* igb_down has a dependency on max_frame_size */
3439         adapter->max_frame_size = max_frame;
3440         if (netif_running(netdev))
3441                 igb_down(adapter);
3442
3443         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3444          * means we reserve 2 more, this pushes us to allocate from the next
3445          * larger slab size.
3446          * i.e. RXBUFFER_2048 --> size-4096 slab
3447          */
3448
3449         if (max_frame <= IGB_RXBUFFER_256)
3450                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3451         else if (max_frame <= IGB_RXBUFFER_512)
3452                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3453         else if (max_frame <= IGB_RXBUFFER_1024)
3454                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3455         else if (max_frame <= IGB_RXBUFFER_2048)
3456                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3457         else
3458 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3459                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3460 #else
3461                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3462 #endif
3463
3464         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3465         if (adapter->vfs_allocated_count &&
3466             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3467                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3468
3469         /* adjust allocation if LPE protects us, and we aren't using SBP */
3470         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3471              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3472                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3473
3474         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3475                  netdev->mtu, new_mtu);
3476         netdev->mtu = new_mtu;
3477
3478         if (netif_running(netdev))
3479                 igb_up(adapter);
3480         else
3481                 igb_reset(adapter);
3482
3483         clear_bit(__IGB_RESETTING, &adapter->state);
3484
3485         return 0;
3486 }
3487
3488 /**
3489  * igb_update_stats - Update the board statistics counters
3490  * @adapter: board private structure
3491  **/
3492
3493 void igb_update_stats(struct igb_adapter *adapter)
3494 {
3495         struct e1000_hw *hw = &adapter->hw;
3496         struct pci_dev *pdev = adapter->pdev;
3497         u16 phy_tmp;
3498
3499 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3500
3501         /*
3502          * Prevent stats update while adapter is being reset, or if the pci
3503          * connection is down.
3504          */
3505         if (adapter->link_speed == 0)
3506                 return;
3507         if (pci_channel_offline(pdev))
3508                 return;
3509
3510         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3511         adapter->stats.gprc += rd32(E1000_GPRC);
3512         adapter->stats.gorc += rd32(E1000_GORCL);
3513         rd32(E1000_GORCH); /* clear GORCL */
3514         adapter->stats.bprc += rd32(E1000_BPRC);
3515         adapter->stats.mprc += rd32(E1000_MPRC);
3516         adapter->stats.roc += rd32(E1000_ROC);
3517
3518         adapter->stats.prc64 += rd32(E1000_PRC64);
3519         adapter->stats.prc127 += rd32(E1000_PRC127);
3520         adapter->stats.prc255 += rd32(E1000_PRC255);
3521         adapter->stats.prc511 += rd32(E1000_PRC511);
3522         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3523         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3524         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3525         adapter->stats.sec += rd32(E1000_SEC);
3526
3527         adapter->stats.mpc += rd32(E1000_MPC);
3528         adapter->stats.scc += rd32(E1000_SCC);
3529         adapter->stats.ecol += rd32(E1000_ECOL);
3530         adapter->stats.mcc += rd32(E1000_MCC);
3531         adapter->stats.latecol += rd32(E1000_LATECOL);
3532         adapter->stats.dc += rd32(E1000_DC);
3533         adapter->stats.rlec += rd32(E1000_RLEC);
3534         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3535         adapter->stats.xontxc += rd32(E1000_XONTXC);
3536         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3537         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3538         adapter->stats.fcruc += rd32(E1000_FCRUC);
3539         adapter->stats.gptc += rd32(E1000_GPTC);
3540         adapter->stats.gotc += rd32(E1000_GOTCL);
3541         rd32(E1000_GOTCH); /* clear GOTCL */
3542         adapter->stats.rnbc += rd32(E1000_RNBC);
3543         adapter->stats.ruc += rd32(E1000_RUC);
3544         adapter->stats.rfc += rd32(E1000_RFC);
3545         adapter->stats.rjc += rd32(E1000_RJC);
3546         adapter->stats.tor += rd32(E1000_TORH);
3547         adapter->stats.tot += rd32(E1000_TOTH);
3548         adapter->stats.tpr += rd32(E1000_TPR);
3549
3550         adapter->stats.ptc64 += rd32(E1000_PTC64);
3551         adapter->stats.ptc127 += rd32(E1000_PTC127);
3552         adapter->stats.ptc255 += rd32(E1000_PTC255);
3553         adapter->stats.ptc511 += rd32(E1000_PTC511);
3554         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3555         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3556
3557         adapter->stats.mptc += rd32(E1000_MPTC);
3558         adapter->stats.bptc += rd32(E1000_BPTC);
3559
3560         /* used for adaptive IFS */
3561
3562         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3563         adapter->stats.tpt += hw->mac.tx_packet_delta;
3564         hw->mac.collision_delta = rd32(E1000_COLC);
3565         adapter->stats.colc += hw->mac.collision_delta;
3566
3567         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3568         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3569         adapter->stats.tncrs += rd32(E1000_TNCRS);
3570         adapter->stats.tsctc += rd32(E1000_TSCTC);
3571         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3572
3573         adapter->stats.iac += rd32(E1000_IAC);
3574         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3575         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3576         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3577         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3578         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3579         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3580         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3581         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3582
3583         /* Fill out the OS statistics structure */
3584         adapter->net_stats.multicast = adapter->stats.mprc;
3585         adapter->net_stats.collisions = adapter->stats.colc;
3586
3587         /* Rx Errors */
3588
3589         /* RLEC on some newer hardware can be incorrect so build
3590         * our own version based on RUC and ROC */
3591         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3592                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3593                 adapter->stats.ruc + adapter->stats.roc +
3594                 adapter->stats.cexterr;
3595         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3596                                               adapter->stats.roc;
3597         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3598         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3599         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3600
3601         /* Tx Errors */
3602         adapter->net_stats.tx_errors = adapter->stats.ecol +
3603                                        adapter->stats.latecol;
3604         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3605         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3606         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3607
3608         /* Tx Dropped needs to be maintained elsewhere */
3609
3610         /* Phy Stats */
3611         if (hw->phy.media_type == e1000_media_type_copper) {
3612                 if ((adapter->link_speed == SPEED_1000) &&
3613                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3614                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3615                         adapter->phy_stats.idle_errors += phy_tmp;
3616                 }
3617         }
3618
3619         /* Management Stats */
3620         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3621         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3622         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3623 }
3624
3625 static irqreturn_t igb_msix_other(int irq, void *data)
3626 {
3627         struct net_device *netdev = data;
3628         struct igb_adapter *adapter = netdev_priv(netdev);
3629         struct e1000_hw *hw = &adapter->hw;
3630         u32 icr = rd32(E1000_ICR);
3631
3632         /* reading ICR causes bit 31 of EICR to be cleared */
3633
3634         if(icr & E1000_ICR_DOUTSYNC) {
3635                 /* HW is reporting DMA is out of sync */
3636                 adapter->stats.doosync++;
3637         }
3638
3639         /* Check for a mailbox event */
3640         if (icr & E1000_ICR_VMMB)
3641                 igb_msg_task(adapter);
3642
3643         if (icr & E1000_ICR_LSC) {
3644                 hw->mac.get_link_status = 1;
3645                 /* guard against interrupt when we're going down */
3646                 if (!test_bit(__IGB_DOWN, &adapter->state))
3647                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3648         }
3649
3650         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3651         wr32(E1000_EIMS, adapter->eims_other);
3652
3653         return IRQ_HANDLED;
3654 }
3655
3656 static irqreturn_t igb_msix_tx(int irq, void *data)
3657 {
3658         struct igb_ring *tx_ring = data;
3659         struct igb_adapter *adapter = tx_ring->adapter;
3660         struct e1000_hw *hw = &adapter->hw;
3661
3662 #ifdef CONFIG_IGB_DCA
3663         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3664                 igb_update_tx_dca(tx_ring);
3665 #endif
3666
3667         tx_ring->total_bytes = 0;
3668         tx_ring->total_packets = 0;
3669
3670         /* auto mask will automatically reenable the interrupt when we write
3671          * EICS */
3672         if (!igb_clean_tx_irq(tx_ring))
3673                 /* Ring was not completely cleaned, so fire another interrupt */
3674                 wr32(E1000_EICS, tx_ring->eims_value);
3675         else
3676                 wr32(E1000_EIMS, tx_ring->eims_value);
3677
3678         return IRQ_HANDLED;
3679 }
3680
3681 static void igb_write_itr(struct igb_ring *ring)
3682 {
3683         struct e1000_hw *hw = &ring->adapter->hw;
3684         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3685                 switch (hw->mac.type) {
3686                 case e1000_82576:
3687                         wr32(ring->itr_register, ring->itr_val |
3688                              0x80000000);
3689                         break;
3690                 default:
3691                         wr32(ring->itr_register, ring->itr_val |
3692                              (ring->itr_val << 16));
3693                         break;
3694                 }
3695                 ring->set_itr = 0;
3696         }
3697 }
3698
3699 static irqreturn_t igb_msix_rx(int irq, void *data)
3700 {
3701         struct igb_ring *rx_ring = data;
3702
3703         /* Write the ITR value calculated at the end of the
3704          * previous interrupt.
3705          */
3706
3707         igb_write_itr(rx_ring);
3708
3709         if (napi_schedule_prep(&rx_ring->napi))
3710                 __napi_schedule(&rx_ring->napi);
3711
3712 #ifdef CONFIG_IGB_DCA
3713         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3714                 igb_update_rx_dca(rx_ring);
3715 #endif
3716                 return IRQ_HANDLED;
3717 }
3718
3719 #ifdef CONFIG_IGB_DCA
3720 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3721 {
3722         u32 dca_rxctrl;
3723         struct igb_adapter *adapter = rx_ring->adapter;
3724         struct e1000_hw *hw = &adapter->hw;
3725         int cpu = get_cpu();
3726         int q = rx_ring->reg_idx;
3727
3728         if (rx_ring->cpu != cpu) {
3729                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3730                 if (hw->mac.type == e1000_82576) {
3731                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3732                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3733                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3734                 } else {
3735                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3736                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3737                 }
3738                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3739                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3740                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3741                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3742                 rx_ring->cpu = cpu;
3743         }
3744         put_cpu();
3745 }
3746
3747 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3748 {
3749         u32 dca_txctrl;
3750         struct igb_adapter *adapter = tx_ring->adapter;
3751         struct e1000_hw *hw = &adapter->hw;
3752         int cpu = get_cpu();
3753         int q = tx_ring->reg_idx;
3754
3755         if (tx_ring->cpu != cpu) {
3756                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3757                 if (hw->mac.type == e1000_82576) {
3758                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3759                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3760                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3761                 } else {
3762                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3763                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3764                 }
3765                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3766                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3767                 tx_ring->cpu = cpu;
3768         }
3769         put_cpu();
3770 }
3771
3772 static void igb_setup_dca(struct igb_adapter *adapter)
3773 {
3774         int i;
3775
3776         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3777                 return;
3778
3779         for (i = 0; i < adapter->num_tx_queues; i++) {
3780                 adapter->tx_ring[i].cpu = -1;
3781                 igb_update_tx_dca(&adapter->tx_ring[i]);
3782         }
3783         for (i = 0; i < adapter->num_rx_queues; i++) {
3784                 adapter->rx_ring[i].cpu = -1;
3785                 igb_update_rx_dca(&adapter->rx_ring[i]);
3786         }
3787 }
3788
3789 static int __igb_notify_dca(struct device *dev, void *data)
3790 {
3791         struct net_device *netdev = dev_get_drvdata(dev);
3792         struct igb_adapter *adapter = netdev_priv(netdev);
3793         struct e1000_hw *hw = &adapter->hw;
3794         unsigned long event = *(unsigned long *)data;
3795
3796         switch (event) {
3797         case DCA_PROVIDER_ADD:
3798                 /* if already enabled, don't do it again */
3799                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3800                         break;
3801                 /* Always use CB2 mode, difference is masked
3802                  * in the CB driver. */
3803                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3804                 if (dca_add_requester(dev) == 0) {
3805                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3806                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3807                         igb_setup_dca(adapter);
3808                         break;
3809                 }
3810                 /* Fall Through since DCA is disabled. */
3811         case DCA_PROVIDER_REMOVE:
3812                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3813                         /* without this a class_device is left
3814                          * hanging around in the sysfs model */
3815                         dca_remove_requester(dev);
3816                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3817                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3818                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3819                 }
3820                 break;
3821         }
3822
3823         return 0;
3824 }
3825
3826 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3827                           void *p)
3828 {
3829         int ret_val;
3830
3831         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3832                                          __igb_notify_dca);
3833
3834         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3835 }
3836 #endif /* CONFIG_IGB_DCA */
3837
3838 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3839 {
3840         struct e1000_hw *hw = &adapter->hw;
3841         u32 ping;
3842         int i;
3843
3844         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3845                 ping = E1000_PF_CONTROL_MSG;
3846                 if (adapter->vf_data[i].clear_to_send)
3847                         ping |= E1000_VT_MSGTYPE_CTS;
3848                 igb_write_mbx(hw, &ping, 1, i);
3849         }
3850 }
3851
3852 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3853                                   u32 *msgbuf, u32 vf)
3854 {
3855         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3856         u16 *hash_list = (u16 *)&msgbuf[1];
3857         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3858         int i;
3859
3860         /* only up to 30 hash values supported */
3861         if (n > 30)
3862                 n = 30;
3863
3864         /* salt away the number of multi cast addresses assigned
3865          * to this VF for later use to restore when the PF multi cast
3866          * list changes
3867          */
3868         vf_data->num_vf_mc_hashes = n;
3869
3870         /* VFs are limited to using the MTA hash table for their multicast
3871          * addresses */
3872         for (i = 0; i < n; i++)
3873                 vf_data->vf_mc_hashes[i] = hash_list[i];;
3874
3875         /* Flush and reset the mta with the new values */
3876         igb_set_multi(adapter->netdev);
3877
3878         return 0;
3879 }
3880
3881 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3882 {
3883         struct e1000_hw *hw = &adapter->hw;
3884         struct vf_data_storage *vf_data;
3885         int i, j;
3886
3887         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3888                 vf_data = &adapter->vf_data[i];
3889                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3890                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3891         }
3892 }
3893
3894 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3895 {
3896         struct e1000_hw *hw = &adapter->hw;
3897         u32 pool_mask, reg, vid;
3898         int i;
3899
3900         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3901
3902         /* Find the vlan filter for this id */
3903         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3904                 reg = rd32(E1000_VLVF(i));
3905
3906                 /* remove the vf from the pool */
3907                 reg &= ~pool_mask;
3908
3909                 /* if pool is empty then remove entry from vfta */
3910                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3911                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3912                         reg = 0;
3913                         vid = reg & E1000_VLVF_VLANID_MASK;
3914                         igb_vfta_set(hw, vid, false);
3915                 }
3916
3917                 wr32(E1000_VLVF(i), reg);
3918         }
3919 }
3920
3921 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3922 {
3923         struct e1000_hw *hw = &adapter->hw;
3924         u32 reg, i;
3925
3926         /* It is an error to call this function when VFs are not enabled */
3927         if (!adapter->vfs_allocated_count)
3928                 return -1;
3929
3930         /* Find the vlan filter for this id */
3931         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3932                 reg = rd32(E1000_VLVF(i));
3933                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3934                     vid == (reg & E1000_VLVF_VLANID_MASK))
3935                         break;
3936         }
3937
3938         if (add) {
3939                 if (i == E1000_VLVF_ARRAY_SIZE) {
3940                         /* Did not find a matching VLAN ID entry that was
3941                          * enabled.  Search for a free filter entry, i.e.
3942                          * one without the enable bit set
3943                          */
3944                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3945                                 reg = rd32(E1000_VLVF(i));
3946                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3947                                         break;
3948                         }
3949                 }
3950                 if (i < E1000_VLVF_ARRAY_SIZE) {
3951                         /* Found an enabled/available entry */
3952                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3953
3954                         /* if !enabled we need to set this up in vfta */
3955                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3956                                 /* add VID to filter table, if bit already set
3957                                  * PF must have added it outside of table */
3958                                 if (igb_vfta_set(hw, vid, true))
3959                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3960                                                 adapter->vfs_allocated_count);
3961                                 reg |= E1000_VLVF_VLANID_ENABLE;
3962                         }
3963                         reg &= ~E1000_VLVF_VLANID_MASK;
3964                         reg |= vid;
3965
3966                         wr32(E1000_VLVF(i), reg);
3967                         return 0;
3968                 }
3969         } else {
3970                 if (i < E1000_VLVF_ARRAY_SIZE) {
3971                         /* remove vf from the pool */
3972                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3973                         /* if pool is empty then remove entry from vfta */
3974                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3975                                 reg = 0;
3976                                 igb_vfta_set(hw, vid, false);
3977                         }
3978                         wr32(E1000_VLVF(i), reg);
3979                         return 0;
3980                 }
3981         }
3982         return -1;
3983 }
3984
3985 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3986 {
3987         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3988         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3989
3990         return igb_vlvf_set(adapter, vid, add, vf);
3991 }
3992
3993 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3994 {
3995         struct e1000_hw *hw = &adapter->hw;
3996
3997         /* disable mailbox functionality for vf */
3998         adapter->vf_data[vf].clear_to_send = false;
3999
4000         /* reset offloads to defaults */
4001         igb_set_vmolr(hw, vf);
4002
4003         /* reset vlans for device */
4004         igb_clear_vf_vfta(adapter, vf);
4005
4006         /* reset multicast table array for vf */
4007         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4008
4009         /* Flush and reset the mta with the new values */
4010         igb_set_multi(adapter->netdev);
4011 }
4012
4013 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4014 {
4015         struct e1000_hw *hw = &adapter->hw;
4016         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4017         u32 reg, msgbuf[3];
4018         u8 *addr = (u8 *)(&msgbuf[1]);
4019
4020         /* process all the same items cleared in a function level reset */
4021         igb_vf_reset_event(adapter, vf);
4022
4023         /* set vf mac address */
4024         igb_rar_set(hw, vf_mac, vf + 1);
4025         igb_set_rah_pool(hw, vf, vf + 1);
4026
4027         /* enable transmit and receive for vf */
4028         reg = rd32(E1000_VFTE);
4029         wr32(E1000_VFTE, reg | (1 << vf));
4030         reg = rd32(E1000_VFRE);
4031         wr32(E1000_VFRE, reg | (1 << vf));
4032
4033         /* enable mailbox functionality for vf */
4034         adapter->vf_data[vf].clear_to_send = true;
4035
4036         /* reply to reset with ack and vf mac address */
4037         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4038         memcpy(addr, vf_mac, 6);
4039         igb_write_mbx(hw, msgbuf, 3, vf);
4040 }
4041
4042 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4043 {
4044                 unsigned char *addr = (char *)&msg[1];
4045                 int err = -1;
4046
4047                 if (is_valid_ether_addr(addr))
4048                         err = igb_set_vf_mac(adapter, vf, addr);
4049
4050                 return err;
4051
4052 }
4053
4054 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4055 {
4056         struct e1000_hw *hw = &adapter->hw;
4057         u32 msg = E1000_VT_MSGTYPE_NACK;
4058
4059         /* if device isn't clear to send it shouldn't be reading either */
4060         if (!adapter->vf_data[vf].clear_to_send)
4061                 igb_write_mbx(hw, &msg, 1, vf);
4062 }
4063
4064
4065 static void igb_msg_task(struct igb_adapter *adapter)
4066 {
4067         struct e1000_hw *hw = &adapter->hw;
4068         u32 vf;
4069
4070         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4071                 /* process any reset requests */
4072                 if (!igb_check_for_rst(hw, vf)) {
4073                         adapter->vf_data[vf].clear_to_send = false;
4074                         igb_vf_reset_event(adapter, vf);
4075                 }
4076
4077                 /* process any messages pending */
4078                 if (!igb_check_for_msg(hw, vf))
4079                         igb_rcv_msg_from_vf(adapter, vf);
4080
4081                 /* process any acks */
4082                 if (!igb_check_for_ack(hw, vf))
4083                         igb_rcv_ack_from_vf(adapter, vf);
4084
4085         }
4086 }
4087
4088 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4089 {
4090         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4091         u32 msgbuf[mbx_size];
4092         struct e1000_hw *hw = &adapter->hw;
4093         s32 retval;
4094
4095         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4096
4097         if (retval)
4098                 dev_err(&adapter->pdev->dev,
4099                         "Error receiving message from VF\n");
4100
4101         /* this is a message we already processed, do nothing */
4102         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4103                 return retval;
4104
4105         /*
4106          * until the vf completes a reset it should not be
4107          * allowed to start any configuration.
4108          */
4109
4110         if (msgbuf[0] == E1000_VF_RESET) {
4111                 igb_vf_reset_msg(adapter, vf);
4112
4113                 return retval;
4114         }
4115
4116         if (!adapter->vf_data[vf].clear_to_send) {
4117                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4118                 igb_write_mbx(hw, msgbuf, 1, vf);
4119                 return retval;
4120         }
4121
4122         switch ((msgbuf[0] & 0xFFFF)) {
4123         case E1000_VF_SET_MAC_ADDR:
4124                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4125                 break;
4126         case E1000_VF_SET_MULTICAST:
4127                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4128                 break;
4129         case E1000_VF_SET_LPE:
4130                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4131                 break;
4132         case E1000_VF_SET_VLAN:
4133                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4134                 break;
4135         default:
4136                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4137                 retval = -1;
4138                 break;
4139         }
4140
4141         /* notify the VF of the results of what it sent us */
4142         if (retval)
4143                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4144         else
4145                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4146
4147         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4148
4149         igb_write_mbx(hw, msgbuf, 1, vf);
4150
4151         return retval;
4152 }
4153
4154 /**
4155  * igb_intr_msi - Interrupt Handler
4156  * @irq: interrupt number
4157  * @data: pointer to a network interface device structure
4158  **/
4159 static irqreturn_t igb_intr_msi(int irq, void *data)
4160 {
4161         struct net_device *netdev = data;
4162         struct igb_adapter *adapter = netdev_priv(netdev);
4163         struct e1000_hw *hw = &adapter->hw;
4164         /* read ICR disables interrupts using IAM */
4165         u32 icr = rd32(E1000_ICR);
4166
4167         igb_write_itr(adapter->rx_ring);
4168
4169         if(icr & E1000_ICR_DOUTSYNC) {
4170                 /* HW is reporting DMA is out of sync */
4171                 adapter->stats.doosync++;
4172         }
4173
4174         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4175                 hw->mac.get_link_status = 1;
4176                 if (!test_bit(__IGB_DOWN, &adapter->state))
4177                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4178         }
4179
4180         napi_schedule(&adapter->rx_ring[0].napi);
4181
4182         return IRQ_HANDLED;
4183 }
4184
4185 /**
4186  * igb_intr - Legacy Interrupt Handler
4187  * @irq: interrupt number
4188  * @data: pointer to a network interface device structure
4189  **/
4190 static irqreturn_t igb_intr(int irq, void *data)
4191 {
4192         struct net_device *netdev = data;
4193         struct igb_adapter *adapter = netdev_priv(netdev);
4194         struct e1000_hw *hw = &adapter->hw;
4195         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4196          * need for the IMC write */
4197         u32 icr = rd32(E1000_ICR);
4198         if (!icr)
4199                 return IRQ_NONE;  /* Not our interrupt */
4200
4201         igb_write_itr(adapter->rx_ring);
4202
4203         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4204          * not set, then the adapter didn't send an interrupt */
4205         if (!(icr & E1000_ICR_INT_ASSERTED))
4206                 return IRQ_NONE;
4207
4208         if(icr & E1000_ICR_DOUTSYNC) {
4209                 /* HW is reporting DMA is out of sync */
4210                 adapter->stats.doosync++;
4211         }
4212
4213         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4214                 hw->mac.get_link_status = 1;
4215                 /* guard against interrupt when we're going down */
4216                 if (!test_bit(__IGB_DOWN, &adapter->state))
4217                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4218         }
4219
4220         napi_schedule(&adapter->rx_ring[0].napi);
4221
4222         return IRQ_HANDLED;
4223 }
4224
4225 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4226 {
4227         struct igb_adapter *adapter = rx_ring->adapter;
4228         struct e1000_hw *hw = &adapter->hw;
4229
4230         if (adapter->itr_setting & 3) {
4231                 if (adapter->num_rx_queues == 1)
4232                         igb_set_itr(adapter);
4233                 else
4234                         igb_update_ring_itr(rx_ring);
4235         }
4236
4237         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4238                 if (adapter->msix_entries)
4239                         wr32(E1000_EIMS, rx_ring->eims_value);
4240                 else
4241                         igb_irq_enable(adapter);
4242         }
4243 }
4244
4245 /**
4246  * igb_poll - NAPI Rx polling callback
4247  * @napi: napi polling structure
4248  * @budget: count of how many packets we should handle
4249  **/
4250 static int igb_poll(struct napi_struct *napi, int budget)
4251 {
4252         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4253         int work_done = 0;
4254
4255 #ifdef CONFIG_IGB_DCA
4256         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4257                 igb_update_rx_dca(rx_ring);
4258 #endif
4259         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4260
4261         if (rx_ring->buddy) {
4262 #ifdef CONFIG_IGB_DCA
4263                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4264                         igb_update_tx_dca(rx_ring->buddy);
4265 #endif
4266                 if (!igb_clean_tx_irq(rx_ring->buddy))
4267                         work_done = budget;
4268         }
4269
4270         /* If not enough Rx work done, exit the polling mode */
4271         if (work_done < budget) {
4272                 napi_complete(napi);
4273                 igb_rx_irq_enable(rx_ring);
4274         }
4275
4276         return work_done;
4277 }
4278
4279 /**
4280  * igb_hwtstamp - utility function which checks for TX time stamp
4281  * @adapter: board private structure
4282  * @skb: packet that was just sent
4283  *
4284  * If we were asked to do hardware stamping and such a time stamp is
4285  * available, then it must have been for this skb here because we only
4286  * allow only one such packet into the queue.
4287  */
4288 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4289 {
4290         union skb_shared_tx *shtx = skb_tx(skb);
4291         struct e1000_hw *hw = &adapter->hw;
4292
4293         if (unlikely(shtx->hardware)) {
4294                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4295                 if (valid) {
4296                         u64 regval = rd32(E1000_TXSTMPL);
4297                         u64 ns;
4298                         struct skb_shared_hwtstamps shhwtstamps;
4299
4300                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4301                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4302                         ns = timecounter_cyc2time(&adapter->clock,
4303                                                   regval);
4304                         timecompare_update(&adapter->compare, ns);
4305                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4306                         shhwtstamps.syststamp =
4307                                 timecompare_transform(&adapter->compare, ns);
4308                         skb_tstamp_tx(skb, &shhwtstamps);
4309                 }
4310         }
4311 }
4312
4313 /**
4314  * igb_clean_tx_irq - Reclaim resources after transmit completes
4315  * @adapter: board private structure
4316  * returns true if ring is completely cleaned
4317  **/
4318 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4319 {
4320         struct igb_adapter *adapter = tx_ring->adapter;
4321         struct net_device *netdev = adapter->netdev;
4322         struct e1000_hw *hw = &adapter->hw;
4323         struct igb_buffer *buffer_info;
4324         struct sk_buff *skb;
4325         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4326         unsigned int total_bytes = 0, total_packets = 0;
4327         unsigned int i, eop, count = 0;
4328         bool cleaned = false;
4329
4330         i = tx_ring->next_to_clean;
4331         eop = tx_ring->buffer_info[i].next_to_watch;
4332         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4333
4334         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4335                (count < tx_ring->count)) {
4336                 for (cleaned = false; !cleaned; count++) {
4337                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4338                         buffer_info = &tx_ring->buffer_info[i];
4339                         cleaned = (i == eop);
4340                         skb = buffer_info->skb;
4341
4342                         if (skb) {
4343                                 unsigned int segs, bytecount;
4344                                 /* gso_segs is currently only valid for tcp */
4345                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4346                                 /* multiply data chunks by size of headers */
4347                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4348                                             skb->len;
4349                                 total_packets += segs;
4350                                 total_bytes += bytecount;
4351
4352                                 igb_tx_hwtstamp(adapter, skb);
4353                         }
4354
4355                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4356                         tx_desc->wb.status = 0;
4357
4358                         i++;
4359                         if (i == tx_ring->count)
4360                                 i = 0;
4361                 }
4362                 eop = tx_ring->buffer_info[i].next_to_watch;
4363                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4364         }
4365
4366         tx_ring->next_to_clean = i;
4367
4368         if (unlikely(count &&
4369                      netif_carrier_ok(netdev) &&
4370                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4371                 /* Make sure that anybody stopping the queue after this
4372                  * sees the new next_to_clean.
4373                  */
4374                 smp_mb();
4375                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4376                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4377                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4378                         ++adapter->restart_queue;
4379                 }
4380         }
4381
4382         if (tx_ring->detect_tx_hung) {
4383                 /* Detect a transmit hang in hardware, this serializes the
4384                  * check with the clearing of time_stamp and movement of i */
4385                 tx_ring->detect_tx_hung = false;
4386                 if (tx_ring->buffer_info[i].time_stamp &&
4387                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4388                                (adapter->tx_timeout_factor * HZ))
4389                     && !(rd32(E1000_STATUS) &
4390                          E1000_STATUS_TXOFF)) {
4391
4392                         /* detected Tx unit hang */
4393                         dev_err(&adapter->pdev->dev,
4394                                 "Detected Tx Unit Hang\n"
4395                                 "  Tx Queue             <%d>\n"
4396                                 "  TDH                  <%x>\n"
4397                                 "  TDT                  <%x>\n"
4398                                 "  next_to_use          <%x>\n"
4399                                 "  next_to_clean        <%x>\n"
4400                                 "buffer_info[next_to_clean]\n"
4401                                 "  time_stamp           <%lx>\n"
4402                                 "  next_to_watch        <%x>\n"
4403                                 "  jiffies              <%lx>\n"
4404                                 "  desc.status          <%x>\n",
4405                                 tx_ring->queue_index,
4406                                 readl(adapter->hw.hw_addr + tx_ring->head),
4407                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4408                                 tx_ring->next_to_use,
4409                                 tx_ring->next_to_clean,
4410                                 tx_ring->buffer_info[i].time_stamp,
4411                                 eop,
4412                                 jiffies,
4413                                 eop_desc->wb.status);
4414                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4415                 }
4416         }
4417         tx_ring->total_bytes += total_bytes;
4418         tx_ring->total_packets += total_packets;
4419         tx_ring->tx_stats.bytes += total_bytes;
4420         tx_ring->tx_stats.packets += total_packets;
4421         adapter->net_stats.tx_bytes += total_bytes;
4422         adapter->net_stats.tx_packets += total_packets;
4423         return (count < tx_ring->count);
4424 }
4425
4426 /**
4427  * igb_receive_skb - helper function to handle rx indications
4428  * @ring: pointer to receive ring receving this packet
4429  * @status: descriptor status field as written by hardware
4430  * @rx_desc: receive descriptor containing vlan and type information.
4431  * @skb: pointer to sk_buff to be indicated to stack
4432  **/
4433 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4434                             union e1000_adv_rx_desc * rx_desc,
4435                             struct sk_buff *skb)
4436 {
4437         struct igb_adapter * adapter = ring->adapter;
4438         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4439
4440         skb_record_rx_queue(skb, ring->queue_index);
4441         if (vlan_extracted)
4442                 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4443                                  le16_to_cpu(rx_desc->wb.upper.vlan),
4444                                  skb);
4445         else
4446                 napi_gro_receive(&ring->napi, skb);
4447 }
4448
4449 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4450                                        u32 status_err, struct sk_buff *skb)
4451 {
4452         skb->ip_summed = CHECKSUM_NONE;
4453
4454         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4455         if ((status_err & E1000_RXD_STAT_IXSM) ||
4456             (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
4457                 return;
4458         /* TCP/UDP checksum error bit is set */
4459         if (status_err &
4460             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4461                 /*
4462                  * work around errata with sctp packets where the TCPE aka
4463                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4464                  * packets, (aka let the stack check the crc32c)
4465                  */
4466                 if (!((adapter->hw.mac.type == e1000_82576) &&
4467                       (skb->len == 60)))
4468                         adapter->hw_csum_err++;
4469                 /* let the stack verify checksum errors */
4470                 return;
4471         }
4472         /* It must be a TCP or UDP packet with a valid checksum */
4473         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4474                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4475
4476         dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4477         adapter->hw_csum_good++;
4478 }
4479
4480 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4481                                  int *work_done, int budget)
4482 {
4483         struct igb_adapter *adapter = rx_ring->adapter;
4484         struct net_device *netdev = adapter->netdev;
4485         struct e1000_hw *hw = &adapter->hw;
4486         struct pci_dev *pdev = adapter->pdev;
4487         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4488         struct igb_buffer *buffer_info , *next_buffer;
4489         struct sk_buff *skb;
4490         bool cleaned = false;
4491         int cleaned_count = 0;
4492         unsigned int total_bytes = 0, total_packets = 0;
4493         unsigned int i;
4494         u32 length, hlen, staterr;
4495
4496         i = rx_ring->next_to_clean;
4497         buffer_info = &rx_ring->buffer_info[i];
4498         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4499         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4500
4501         while (staterr & E1000_RXD_STAT_DD) {
4502                 if (*work_done >= budget)
4503                         break;
4504                 (*work_done)++;
4505
4506                 skb = buffer_info->skb;
4507                 prefetch(skb->data - NET_IP_ALIGN);
4508                 buffer_info->skb = NULL;
4509
4510                 i++;
4511                 if (i == rx_ring->count)
4512                         i = 0;
4513                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4514                 prefetch(next_rxd);
4515                 next_buffer = &rx_ring->buffer_info[i];
4516
4517                 length = le16_to_cpu(rx_desc->wb.upper.length);
4518                 cleaned = true;
4519                 cleaned_count++;
4520
4521                 if (!adapter->rx_ps_hdr_size) {
4522                         pci_unmap_single(pdev, buffer_info->dma,
4523                                          adapter->rx_buffer_len +
4524                                            NET_IP_ALIGN,
4525                                          PCI_DMA_FROMDEVICE);
4526                         skb_put(skb, length);
4527                         goto send_up;
4528                 }
4529
4530                 /* HW will not DMA in data larger than the given buffer, even
4531                  * if it parses the (NFS, of course) header to be larger.  In
4532                  * that case, it fills the header buffer and spills the rest
4533                  * into the page.
4534                  */
4535                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4536                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4537                 if (hlen > adapter->rx_ps_hdr_size)
4538                         hlen = adapter->rx_ps_hdr_size;
4539
4540                 if (!skb_shinfo(skb)->nr_frags) {
4541                         pci_unmap_single(pdev, buffer_info->dma,
4542                                          adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4543                                          PCI_DMA_FROMDEVICE);
4544                         skb_put(skb, hlen);
4545                 }
4546
4547                 if (length) {
4548                         pci_unmap_page(pdev, buffer_info->page_dma,
4549                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4550                         buffer_info->page_dma = 0;
4551
4552                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4553                                                 buffer_info->page,
4554                                                 buffer_info->page_offset,
4555                                                 length);
4556
4557                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4558                             (page_count(buffer_info->page) != 1))
4559                                 buffer_info->page = NULL;
4560                         else
4561                                 get_page(buffer_info->page);
4562
4563                         skb->len += length;
4564                         skb->data_len += length;
4565
4566                         skb->truesize += length;
4567                 }
4568
4569                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4570                         buffer_info->skb = next_buffer->skb;
4571                         buffer_info->dma = next_buffer->dma;
4572                         next_buffer->skb = skb;
4573                         next_buffer->dma = 0;
4574                         goto next_desc;
4575                 }
4576 send_up:
4577                 /*
4578                  * If this bit is set, then the RX registers contain
4579                  * the time stamp. No other packet will be time
4580                  * stamped until we read these registers, so read the
4581                  * registers to make them available again. Because
4582                  * only one packet can be time stamped at a time, we
4583                  * know that the register values must belong to this
4584                  * one here and therefore we don't need to compare
4585                  * any of the additional attributes stored for it.
4586                  *
4587                  * If nothing went wrong, then it should have a
4588                  * skb_shared_tx that we can turn into a
4589                  * skb_shared_hwtstamps.
4590                  *
4591                  * TODO: can time stamping be triggered (thus locking
4592                  * the registers) without the packet reaching this point
4593                  * here? In that case RX time stamping would get stuck.
4594                  *
4595                  * TODO: in "time stamp all packets" mode this bit is
4596                  * not set. Need a global flag for this mode and then
4597                  * always read the registers. Cannot be done without
4598                  * a race condition.
4599                  */
4600                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4601                         u64 regval;
4602                         u64 ns;
4603                         struct skb_shared_hwtstamps *shhwtstamps =
4604                                 skb_hwtstamps(skb);
4605
4606                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4607                              "igb: no RX time stamp available for time stamped packet");
4608                         regval = rd32(E1000_RXSTMPL);
4609                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4610                         ns = timecounter_cyc2time(&adapter->clock, regval);
4611                         timecompare_update(&adapter->compare, ns);
4612                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4613                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4614                         shhwtstamps->syststamp =
4615                                 timecompare_transform(&adapter->compare, ns);
4616                 }
4617
4618                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4619                         dev_kfree_skb_irq(skb);
4620                         goto next_desc;
4621                 }
4622
4623                 total_bytes += skb->len;
4624                 total_packets++;
4625
4626                 igb_rx_checksum_adv(adapter, staterr, skb);
4627
4628                 skb->protocol = eth_type_trans(skb, netdev);
4629
4630                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4631
4632 next_desc:
4633                 rx_desc->wb.upper.status_error = 0;
4634
4635                 /* return some buffers to hardware, one at a time is too slow */
4636                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4637                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4638                         cleaned_count = 0;
4639                 }
4640
4641                 /* use prefetched values */
4642                 rx_desc = next_rxd;
4643                 buffer_info = next_buffer;
4644                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4645         }
4646
4647         rx_ring->next_to_clean = i;
4648         cleaned_count = igb_desc_unused(rx_ring);
4649
4650         if (cleaned_count)
4651                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4652
4653         rx_ring->total_packets += total_packets;
4654         rx_ring->total_bytes += total_bytes;
4655         rx_ring->rx_stats.packets += total_packets;
4656         rx_ring->rx_stats.bytes += total_bytes;
4657         adapter->net_stats.rx_bytes += total_bytes;
4658         adapter->net_stats.rx_packets += total_packets;
4659         return cleaned;
4660 }
4661
4662 /**
4663  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4664  * @adapter: address of board private structure
4665  **/
4666 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4667                                      int cleaned_count)
4668 {
4669         struct igb_adapter *adapter = rx_ring->adapter;
4670         struct net_device *netdev = adapter->netdev;
4671         struct pci_dev *pdev = adapter->pdev;
4672         union e1000_adv_rx_desc *rx_desc;
4673         struct igb_buffer *buffer_info;
4674         struct sk_buff *skb;
4675         unsigned int i;
4676         int bufsz;
4677
4678         i = rx_ring->next_to_use;
4679         buffer_info = &rx_ring->buffer_info[i];
4680
4681         if (adapter->rx_ps_hdr_size)
4682                 bufsz = adapter->rx_ps_hdr_size;
4683         else
4684                 bufsz = adapter->rx_buffer_len;
4685         bufsz += NET_IP_ALIGN;
4686
4687         while (cleaned_count--) {
4688                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4689
4690                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4691                         if (!buffer_info->page) {
4692                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4693                                 if (!buffer_info->page) {
4694                                         adapter->alloc_rx_buff_failed++;
4695                                         goto no_buffers;
4696                                 }
4697                                 buffer_info->page_offset = 0;
4698                         } else {
4699                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4700                         }
4701                         buffer_info->page_dma =
4702                                 pci_map_page(pdev, buffer_info->page,
4703                                              buffer_info->page_offset,
4704                                              PAGE_SIZE / 2,
4705                                              PCI_DMA_FROMDEVICE);
4706                 }
4707
4708                 if (!buffer_info->skb) {
4709                         skb = netdev_alloc_skb(netdev, bufsz);
4710                         if (!skb) {
4711                                 adapter->alloc_rx_buff_failed++;
4712                                 goto no_buffers;
4713                         }
4714
4715                         /* Make buffer alignment 2 beyond a 16 byte boundary
4716                          * this will result in a 16 byte aligned IP header after
4717                          * the 14 byte MAC header is removed
4718                          */
4719                         skb_reserve(skb, NET_IP_ALIGN);
4720
4721                         buffer_info->skb = skb;
4722                         buffer_info->dma = pci_map_single(pdev, skb->data,
4723                                                           bufsz,
4724                                                           PCI_DMA_FROMDEVICE);
4725                 }
4726                 /* Refresh the desc even if buffer_addrs didn't change because
4727                  * each write-back erases this info. */
4728                 if (adapter->rx_ps_hdr_size) {
4729                         rx_desc->read.pkt_addr =
4730                              cpu_to_le64(buffer_info->page_dma);
4731                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4732                 } else {
4733                         rx_desc->read.pkt_addr =
4734                              cpu_to_le64(buffer_info->dma);
4735                         rx_desc->read.hdr_addr = 0;
4736                 }
4737
4738                 i++;
4739                 if (i == rx_ring->count)
4740                         i = 0;
4741                 buffer_info = &rx_ring->buffer_info[i];
4742         }
4743
4744 no_buffers:
4745         if (rx_ring->next_to_use != i) {
4746                 rx_ring->next_to_use = i;
4747                 if (i == 0)
4748                         i = (rx_ring->count - 1);
4749                 else
4750                         i--;
4751
4752                 /* Force memory writes to complete before letting h/w
4753                  * know there are new descriptors to fetch.  (Only
4754                  * applicable for weak-ordered memory model archs,
4755                  * such as IA-64). */
4756                 wmb();
4757                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4758         }
4759 }
4760
4761 /**
4762  * igb_mii_ioctl -
4763  * @netdev:
4764  * @ifreq:
4765  * @cmd:
4766  **/
4767 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4768 {
4769         struct igb_adapter *adapter = netdev_priv(netdev);
4770         struct mii_ioctl_data *data = if_mii(ifr);
4771
4772         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4773                 return -EOPNOTSUPP;
4774
4775         switch (cmd) {
4776         case SIOCGMIIPHY:
4777                 data->phy_id = adapter->hw.phy.addr;
4778                 break;
4779         case SIOCGMIIREG:
4780                 if (!capable(CAP_NET_ADMIN))
4781                         return -EPERM;
4782                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4783                                      &data->val_out))
4784                         return -EIO;
4785                 break;
4786         case SIOCSMIIREG:
4787         default:
4788                 return -EOPNOTSUPP;
4789         }
4790         return 0;
4791 }
4792
4793 /**
4794  * igb_hwtstamp_ioctl - control hardware time stamping
4795  * @netdev:
4796  * @ifreq:
4797  * @cmd:
4798  *
4799  * Outgoing time stamping can be enabled and disabled. Play nice and
4800  * disable it when requested, although it shouldn't case any overhead
4801  * when no packet needs it. At most one packet in the queue may be
4802  * marked for time stamping, otherwise it would be impossible to tell
4803  * for sure to which packet the hardware time stamp belongs.
4804  *
4805  * Incoming time stamping has to be configured via the hardware
4806  * filters. Not all combinations are supported, in particular event
4807  * type has to be specified. Matching the kind of event packet is
4808  * not supported, with the exception of "all V2 events regardless of
4809  * level 2 or 4".
4810  *
4811  **/
4812 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4813                               struct ifreq *ifr, int cmd)
4814 {
4815         struct igb_adapter *adapter = netdev_priv(netdev);
4816         struct e1000_hw *hw = &adapter->hw;
4817         struct hwtstamp_config config;
4818         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4819         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4820         u32 tsync_rx_ctl_type = 0;
4821         u32 tsync_rx_cfg = 0;
4822         int is_l4 = 0;
4823         int is_l2 = 0;
4824         short port = 319; /* PTP */
4825         u32 regval;
4826
4827         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4828                 return -EFAULT;
4829
4830         /* reserved for future extensions */
4831         if (config.flags)
4832                 return -EINVAL;
4833
4834         switch (config.tx_type) {
4835         case HWTSTAMP_TX_OFF:
4836                 tsync_tx_ctl_bit = 0;
4837                 break;
4838         case HWTSTAMP_TX_ON:
4839                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4840                 break;
4841         default:
4842                 return -ERANGE;
4843         }
4844
4845         switch (config.rx_filter) {
4846         case HWTSTAMP_FILTER_NONE:
4847                 tsync_rx_ctl_bit = 0;
4848                 break;
4849         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4850         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4851         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4852         case HWTSTAMP_FILTER_ALL:
4853                 /*
4854                  * register TSYNCRXCFG must be set, therefore it is not
4855                  * possible to time stamp both Sync and Delay_Req messages
4856                  * => fall back to time stamping all packets
4857                  */
4858                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4859                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4860                 break;
4861         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4862                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4863                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4864                 is_l4 = 1;
4865                 break;
4866         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4867                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4868                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4869                 is_l4 = 1;
4870                 break;
4871         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4872         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4873                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4874                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4875                 is_l2 = 1;
4876                 is_l4 = 1;
4877                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4878                 break;
4879         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4880         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4881                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4882                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4883                 is_l2 = 1;
4884                 is_l4 = 1;
4885                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4886                 break;
4887         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4888         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4889         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4890                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4891                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4892                 is_l2 = 1;
4893                 break;
4894         default:
4895                 return -ERANGE;
4896         }
4897
4898         /* enable/disable TX */
4899         regval = rd32(E1000_TSYNCTXCTL);
4900         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4901         wr32(E1000_TSYNCTXCTL, regval);
4902
4903         /* enable/disable RX, define which PTP packets are time stamped */
4904         regval = rd32(E1000_TSYNCRXCTL);
4905         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4906         regval = (regval & ~0xE) | tsync_rx_ctl_type;
4907         wr32(E1000_TSYNCRXCTL, regval);
4908         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4909
4910         /*
4911          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4912          *                                          (Ethertype to filter on)
4913          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4914          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4915          */
4916         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4917
4918         /* L4 Queue Filter[0]: only filter by source and destination port */
4919         wr32(E1000_SPQF0, htons(port));
4920         wr32(E1000_IMIREXT(0), is_l4 ?
4921              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4922         wr32(E1000_IMIR(0), is_l4 ?
4923              (htons(port)
4924               | (0<<16) /* immediate interrupt disabled */
4925               | 0 /* (1<<17) bit cleared: do not bypass
4926                      destination port check */)
4927                 : 0);
4928         wr32(E1000_FTQF0, is_l4 ?
4929              (0x11 /* UDP */
4930               | (1<<15) /* VF not compared */
4931               | (1<<27) /* Enable Timestamping */
4932               | (7<<28) /* only source port filter enabled,
4933                            source/target address and protocol
4934                            masked */)
4935              : ((1<<15) | (15<<28) /* all mask bits set = filter not
4936                                       enabled */));
4937
4938         wrfl();
4939
4940         adapter->hwtstamp_config = config;
4941
4942         /* clear TX/RX time stamp registers, just to be sure */
4943         regval = rd32(E1000_TXSTMPH);
4944         regval = rd32(E1000_RXSTMPH);
4945
4946         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4947                 -EFAULT : 0;
4948 }
4949
4950 /**
4951  * igb_ioctl -
4952  * @netdev:
4953  * @ifreq:
4954  * @cmd:
4955  **/
4956 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4957 {
4958         switch (cmd) {
4959         case SIOCGMIIPHY:
4960         case SIOCGMIIREG:
4961         case SIOCSMIIREG:
4962                 return igb_mii_ioctl(netdev, ifr, cmd);
4963         case SIOCSHWTSTAMP:
4964                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4965         default:
4966                 return -EOPNOTSUPP;
4967         }
4968 }
4969
4970 static void igb_vlan_rx_register(struct net_device *netdev,
4971                                  struct vlan_group *grp)
4972 {
4973         struct igb_adapter *adapter = netdev_priv(netdev);
4974         struct e1000_hw *hw = &adapter->hw;
4975         u32 ctrl, rctl;
4976
4977         igb_irq_disable(adapter);
4978         adapter->vlgrp = grp;
4979
4980         if (grp) {
4981                 /* enable VLAN tag insert/strip */
4982                 ctrl = rd32(E1000_CTRL);
4983                 ctrl |= E1000_CTRL_VME;
4984                 wr32(E1000_CTRL, ctrl);
4985
4986                 /* enable VLAN receive filtering */
4987                 rctl = rd32(E1000_RCTL);
4988                 rctl &= ~E1000_RCTL_CFIEN;
4989                 wr32(E1000_RCTL, rctl);
4990                 igb_update_mng_vlan(adapter);
4991         } else {
4992                 /* disable VLAN tag insert/strip */
4993                 ctrl = rd32(E1000_CTRL);
4994                 ctrl &= ~E1000_CTRL_VME;
4995                 wr32(E1000_CTRL, ctrl);
4996
4997                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4998                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4999                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5000                 }
5001         }
5002
5003         igb_rlpml_set(adapter);
5004
5005         if (!test_bit(__IGB_DOWN, &adapter->state))
5006                 igb_irq_enable(adapter);
5007 }
5008
5009 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5010 {
5011         struct igb_adapter *adapter = netdev_priv(netdev);
5012         struct e1000_hw *hw = &adapter->hw;
5013         int pf_id = adapter->vfs_allocated_count;
5014
5015         if ((hw->mng_cookie.status &
5016              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5017             (vid == adapter->mng_vlan_id))
5018                 return;
5019
5020         /* add vid to vlvf if sr-iov is enabled,
5021          * if that fails add directly to filter table */
5022         if (igb_vlvf_set(adapter, vid, true, pf_id))
5023                 igb_vfta_set(hw, vid, true);
5024
5025 }
5026
5027 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5028 {
5029         struct igb_adapter *adapter = netdev_priv(netdev);
5030         struct e1000_hw *hw = &adapter->hw;
5031         int pf_id = adapter->vfs_allocated_count;
5032
5033         igb_irq_disable(adapter);
5034         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5035
5036         if (!test_bit(__IGB_DOWN, &adapter->state))
5037                 igb_irq_enable(adapter);
5038
5039         if ((adapter->hw.mng_cookie.status &
5040              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5041             (vid == adapter->mng_vlan_id)) {
5042                 /* release control to f/w */
5043                 igb_release_hw_control(adapter);
5044                 return;
5045         }
5046
5047         /* remove vid from vlvf if sr-iov is enabled,
5048          * if not in vlvf remove from vfta */
5049         if (igb_vlvf_set(adapter, vid, false, pf_id))
5050                 igb_vfta_set(hw, vid, false);
5051 }
5052
5053 static void igb_restore_vlan(struct igb_adapter *adapter)
5054 {
5055         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5056
5057         if (adapter->vlgrp) {
5058                 u16 vid;
5059                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5060                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5061                                 continue;
5062                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5063                 }
5064         }
5065 }
5066
5067 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5068 {
5069         struct e1000_mac_info *mac = &adapter->hw.mac;
5070
5071         mac->autoneg = 0;
5072
5073         /* Fiber NICs only allow 1000 gbps Full duplex */
5074         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5075                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5076                 dev_err(&adapter->pdev->dev,
5077                         "Unsupported Speed/Duplex configuration\n");
5078                 return -EINVAL;
5079         }
5080
5081         switch (spddplx) {
5082         case SPEED_10 + DUPLEX_HALF:
5083                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5084                 break;
5085         case SPEED_10 + DUPLEX_FULL:
5086                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5087                 break;
5088         case SPEED_100 + DUPLEX_HALF:
5089                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5090                 break;
5091         case SPEED_100 + DUPLEX_FULL:
5092                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5093                 break;
5094         case SPEED_1000 + DUPLEX_FULL:
5095                 mac->autoneg = 1;
5096                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5097                 break;
5098         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5099         default:
5100                 dev_err(&adapter->pdev->dev,
5101                         "Unsupported Speed/Duplex configuration\n");
5102                 return -EINVAL;
5103         }
5104         return 0;
5105 }
5106
5107 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5108 {
5109         struct net_device *netdev = pci_get_drvdata(pdev);
5110         struct igb_adapter *adapter = netdev_priv(netdev);
5111         struct e1000_hw *hw = &adapter->hw;
5112         u32 ctrl, rctl, status;
5113         u32 wufc = adapter->wol;
5114 #ifdef CONFIG_PM
5115         int retval = 0;
5116 #endif
5117
5118         netif_device_detach(netdev);
5119
5120         if (netif_running(netdev))
5121                 igb_close(netdev);
5122
5123         igb_reset_interrupt_capability(adapter);
5124
5125         igb_free_queues(adapter);
5126
5127 #ifdef CONFIG_PM
5128         retval = pci_save_state(pdev);
5129         if (retval)
5130                 return retval;
5131 #endif
5132
5133         status = rd32(E1000_STATUS);
5134         if (status & E1000_STATUS_LU)
5135                 wufc &= ~E1000_WUFC_LNKC;
5136
5137         if (wufc) {
5138                 igb_setup_rctl(adapter);
5139                 igb_set_multi(netdev);
5140
5141                 /* turn on all-multi mode if wake on multicast is enabled */
5142                 if (wufc & E1000_WUFC_MC) {
5143                         rctl = rd32(E1000_RCTL);
5144                         rctl |= E1000_RCTL_MPE;
5145                         wr32(E1000_RCTL, rctl);
5146                 }
5147
5148                 ctrl = rd32(E1000_CTRL);
5149                 /* advertise wake from D3Cold */
5150                 #define E1000_CTRL_ADVD3WUC 0x00100000
5151                 /* phy power management enable */
5152                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5153                 ctrl |= E1000_CTRL_ADVD3WUC;
5154                 wr32(E1000_CTRL, ctrl);
5155
5156                 /* Allow time for pending master requests to run */
5157                 igb_disable_pcie_master(&adapter->hw);
5158
5159                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5160                 wr32(E1000_WUFC, wufc);
5161         } else {
5162                 wr32(E1000_WUC, 0);
5163                 wr32(E1000_WUFC, 0);
5164         }
5165
5166         *enable_wake = wufc || adapter->en_mng_pt;
5167         if (!*enable_wake)
5168                 igb_shutdown_fiber_serdes_link_82575(hw);
5169
5170         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5171          * would have already happened in close and is redundant. */
5172         igb_release_hw_control(adapter);
5173
5174         pci_disable_device(pdev);
5175
5176         return 0;
5177 }
5178
5179 #ifdef CONFIG_PM
5180 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5181 {
5182         int retval;
5183         bool wake;
5184
5185         retval = __igb_shutdown(pdev, &wake);
5186         if (retval)
5187                 return retval;
5188
5189         if (wake) {
5190                 pci_prepare_to_sleep(pdev);
5191         } else {
5192                 pci_wake_from_d3(pdev, false);
5193                 pci_set_power_state(pdev, PCI_D3hot);
5194         }
5195
5196         return 0;
5197 }
5198
5199 static int igb_resume(struct pci_dev *pdev)
5200 {
5201         struct net_device *netdev = pci_get_drvdata(pdev);
5202         struct igb_adapter *adapter = netdev_priv(netdev);
5203         struct e1000_hw *hw = &adapter->hw;
5204         u32 err;
5205
5206         pci_set_power_state(pdev, PCI_D0);
5207         pci_restore_state(pdev);
5208
5209         err = pci_enable_device_mem(pdev);
5210         if (err) {
5211                 dev_err(&pdev->dev,
5212                         "igb: Cannot enable PCI device from suspend\n");
5213                 return err;
5214         }
5215         pci_set_master(pdev);
5216
5217         pci_enable_wake(pdev, PCI_D3hot, 0);
5218         pci_enable_wake(pdev, PCI_D3cold, 0);
5219
5220         igb_set_interrupt_capability(adapter);
5221
5222         if (igb_alloc_queues(adapter)) {
5223                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5224                 return -ENOMEM;
5225         }
5226
5227         /* e1000_power_up_phy(adapter); */
5228
5229         igb_reset(adapter);
5230
5231         /* let the f/w know that the h/w is now under the control of the
5232          * driver. */
5233         igb_get_hw_control(adapter);
5234
5235         wr32(E1000_WUS, ~0);
5236
5237         if (netif_running(netdev)) {
5238                 err = igb_open(netdev);
5239                 if (err)
5240                         return err;
5241         }
5242
5243         netif_device_attach(netdev);
5244
5245         return 0;
5246 }
5247 #endif
5248
5249 static void igb_shutdown(struct pci_dev *pdev)
5250 {
5251         bool wake;
5252
5253         __igb_shutdown(pdev, &wake);
5254
5255         if (system_state == SYSTEM_POWER_OFF) {
5256                 pci_wake_from_d3(pdev, wake);
5257                 pci_set_power_state(pdev, PCI_D3hot);
5258         }
5259 }
5260
5261 #ifdef CONFIG_NET_POLL_CONTROLLER
5262 /*
5263  * Polling 'interrupt' - used by things like netconsole to send skbs
5264  * without having to re-enable interrupts. It's not called while
5265  * the interrupt routine is executing.
5266  */
5267 static void igb_netpoll(struct net_device *netdev)
5268 {
5269         struct igb_adapter *adapter = netdev_priv(netdev);
5270         struct e1000_hw *hw = &adapter->hw;
5271         int i;
5272
5273         if (!adapter->msix_entries) {
5274                 igb_irq_disable(adapter);
5275                 napi_schedule(&adapter->rx_ring[0].napi);
5276                 return;
5277         }
5278
5279         for (i = 0; i < adapter->num_tx_queues; i++) {
5280                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5281                 wr32(E1000_EIMC, tx_ring->eims_value);
5282                 igb_clean_tx_irq(tx_ring);
5283                 wr32(E1000_EIMS, tx_ring->eims_value);
5284         }
5285
5286         for (i = 0; i < adapter->num_rx_queues; i++) {
5287                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5288                 wr32(E1000_EIMC, rx_ring->eims_value);
5289                 napi_schedule(&rx_ring->napi);
5290         }
5291 }
5292 #endif /* CONFIG_NET_POLL_CONTROLLER */
5293
5294 /**
5295  * igb_io_error_detected - called when PCI error is detected
5296  * @pdev: Pointer to PCI device
5297  * @state: The current pci connection state
5298  *
5299  * This function is called after a PCI bus error affecting
5300  * this device has been detected.
5301  */
5302 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5303                                               pci_channel_state_t state)
5304 {
5305         struct net_device *netdev = pci_get_drvdata(pdev);
5306         struct igb_adapter *adapter = netdev_priv(netdev);
5307
5308         netif_device_detach(netdev);
5309
5310         if (netif_running(netdev))
5311                 igb_down(adapter);
5312         pci_disable_device(pdev);
5313
5314         /* Request a slot slot reset. */
5315         return PCI_ERS_RESULT_NEED_RESET;
5316 }
5317
5318 /**
5319  * igb_io_slot_reset - called after the pci bus has been reset.
5320  * @pdev: Pointer to PCI device
5321  *
5322  * Restart the card from scratch, as if from a cold-boot. Implementation
5323  * resembles the first-half of the igb_resume routine.
5324  */
5325 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5326 {
5327         struct net_device *netdev = pci_get_drvdata(pdev);
5328         struct igb_adapter *adapter = netdev_priv(netdev);
5329         struct e1000_hw *hw = &adapter->hw;
5330         pci_ers_result_t result;
5331         int err;
5332
5333         if (pci_enable_device_mem(pdev)) {
5334                 dev_err(&pdev->dev,
5335                         "Cannot re-enable PCI device after reset.\n");
5336                 result = PCI_ERS_RESULT_DISCONNECT;
5337         } else {
5338                 pci_set_master(pdev);
5339                 pci_restore_state(pdev);
5340
5341                 pci_enable_wake(pdev, PCI_D3hot, 0);
5342                 pci_enable_wake(pdev, PCI_D3cold, 0);
5343
5344                 igb_reset(adapter);
5345                 wr32(E1000_WUS, ~0);
5346                 result = PCI_ERS_RESULT_RECOVERED;
5347         }
5348
5349         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5350         if (err) {
5351                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5352                         "failed 0x%0x\n", err);
5353                 /* non-fatal, continue */
5354         }
5355
5356         return result;
5357 }
5358
5359 /**
5360  * igb_io_resume - called when traffic can start flowing again.
5361  * @pdev: Pointer to PCI device
5362  *
5363  * This callback is called when the error recovery driver tells us that
5364  * its OK to resume normal operation. Implementation resembles the
5365  * second-half of the igb_resume routine.
5366  */
5367 static void igb_io_resume(struct pci_dev *pdev)
5368 {
5369         struct net_device *netdev = pci_get_drvdata(pdev);
5370         struct igb_adapter *adapter = netdev_priv(netdev);
5371
5372         if (netif_running(netdev)) {
5373                 if (igb_up(adapter)) {
5374                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5375                         return;
5376                 }
5377         }
5378
5379         netif_device_attach(netdev);
5380
5381         /* let the f/w know that the h/w is now under the control of the
5382          * driver. */
5383         igb_get_hw_control(adapter);
5384 }
5385
5386 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5387 {
5388         u32 reg_data;
5389
5390         reg_data = rd32(E1000_VMOLR(vfn));
5391         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
5392                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
5393                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
5394                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
5395                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5396         wr32(E1000_VMOLR(vfn), reg_data);
5397 }
5398
5399 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5400                                  int vfn)
5401 {
5402         struct e1000_hw *hw = &adapter->hw;
5403         u32 vmolr;
5404
5405         vmolr = rd32(E1000_VMOLR(vfn));
5406         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5407         vmolr |= size | E1000_VMOLR_LPE;
5408         wr32(E1000_VMOLR(vfn), vmolr);
5409
5410         return 0;
5411 }
5412
5413 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5414 {
5415         u32 reg_data;
5416
5417         reg_data = rd32(E1000_RAH(entry));
5418         reg_data &= ~E1000_RAH_POOL_MASK;
5419         reg_data |= E1000_RAH_POOL_1 << pool;;
5420         wr32(E1000_RAH(entry), reg_data);
5421 }
5422
5423 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5424                                   int entry_count, u16 total_rar_filters)
5425 {
5426         struct e1000_hw *hw = &adapter->hw;
5427         int i = adapter->vfs_allocated_count + 1;
5428
5429         if ((i + entry_count) < total_rar_filters)
5430                 total_rar_filters = i + entry_count;
5431
5432         for (; i < total_rar_filters; i++)
5433                 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5434 }
5435
5436 static int igb_set_vf_mac(struct igb_adapter *adapter,
5437                           int vf, unsigned char *mac_addr)
5438 {
5439         struct e1000_hw *hw = &adapter->hw;
5440         int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5441
5442         igb_rar_set(hw, mac_addr, rar_entry);
5443
5444         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5445
5446         igb_set_rah_pool(hw, vf, rar_entry);
5447
5448         return 0;
5449 }
5450
5451 static void igb_vmm_control(struct igb_adapter *adapter)
5452 {
5453         struct e1000_hw *hw = &adapter->hw;
5454         u32 reg_data;
5455
5456         if (!adapter->vfs_allocated_count)
5457                 return;
5458
5459         /* VF's need PF reset indication before they
5460          * can send/receive mail */
5461         reg_data = rd32(E1000_CTRL_EXT);
5462         reg_data |= E1000_CTRL_EXT_PFRSTD;
5463         wr32(E1000_CTRL_EXT, reg_data);
5464
5465         igb_vmdq_set_loopback_pf(hw, true);
5466         igb_vmdq_set_replication_pf(hw, true);
5467 }
5468
5469 /* igb_main.c */