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   1 /**************************************************************************
   2  *
   3  * Copyright © 2000-2008 Alacritech, Inc.  All rights reserved.
   4  *
   5  * $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above
  14  *    copyright notice, this list of conditions and the following
  15  *    disclaimer in the documentation and/or other materials provided
  16  *    with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
  19  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ALACRITECH, INC. OR
  22  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  25  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  27  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  28  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  * The views and conclusions contained in the software and documentation
  32  * are those of the authors and should not be interpreted as representing
  33  * official policies, either expressed or implied, of Alacritech, Inc.
  34  *
  35  **************************************************************************/
  36
  37 /*
  38  * FILENAME: sxg.h
  39  *
  40  * This is the base set of header definitions for the SXG driver.
  41  */
  42 #ifndef __SXG_DRIVER_H__
  43 #define __SXG_DRIVER_H__
  44
  45 #define p_net_device struct net_device *
  46 // SXG_STATS - Probably move these to someplace where
  47 // the slicstat (sxgstat?) program can get them.
  48 struct SXG_STATS {
  49         // Xmt
  50         u32                             XmtNBL;                         // Offload send NBL count
  51         u64                             DumbXmtBytes;           // Dumbnic send bytes
  52         u64                             SlowXmtBytes;           // Slowpath send bytes
  53         u64                             FastXmtBytes;           // Fastpath send bytes
  54         u64                             DumbXmtPkts;            // Dumbnic send packets
  55         u64                             SlowXmtPkts;            // Slowpath send packets
  56         u64                             FastXmtPkts;            // Fastpath send packets
  57     u64                         DumbXmtUcastPkts;       // directed packets
  58     u64                         DumbXmtMcastPkts;       // Multicast packets
  59     u64                         DumbXmtBcastPkts;       // OID_GEN_BROADCAST_FRAMES_RCV
  60     u64                         DumbXmtUcastBytes;      // OID_GEN_DIRECTED_BYTES_XMIT
  61     u64                         DumbXmtMcastBytes;      // OID_GEN_MULTICAST_BYTES_XMIT
  62     u64                         DumbXmtBcastBytes;      // OID_GEN_BROADCAST_BYTES_XMIT
  63     u64                         XmtErrors;                      // OID_GEN_XMIT_ERROR
  64     u64                         XmtDiscards;            // OID_GEN_XMIT_DISCARDS
  65         u64                             XmtOk;                          // OID_GEN_XMIT_OK
  66         u64                             XmtQLen;                        // OID_GEN_TRANSMIT_QUEUE_LENGTH
  67         u64                             XmtZeroFull;            // Transmit ring zero full
  68         // Rcv
  69         u32                             RcvNBL;                         // Offload recieve NBL count
  70         u64                             DumbRcvBytes;           // dumbnic recv bytes
  71     u64             DumbRcvUcastBytes;  // OID_GEN_DIRECTED_BYTES_RCV
  72     u64             DumbRcvMcastBytes;  // OID_GEN_MULTICAST_BYTES_RCV
  73     u64             DumbRcvBcastBytes;  // OID_GEN_BROADCAST_BYTES_RCV
  74         u64                             SlowRcvBytes;           // Slowpath recv bytes
  75         u64                             FastRcvBytes;           // Fastpath recv bytes
  76     u64                         DumbRcvPkts;            // OID_GEN_DIRECTED_FRAMES_RCV
  77         u64                             DumbRcvTcpPkts;         // See SxgCollectStats
  78     u64                         DumbRcvUcastPkts;       // directed packets
  79     u64                         DumbRcvMcastPkts;       // Multicast packets
  80     u64                         DumbRcvBcastPkts;       // OID_GEN_BROADCAST_FRAMES_RCV
  81         u64                             SlowRcvPkts;            // OID_GEN_DIRECTED_FRAMES_RCV
  82     u64                         RcvErrors;                      // OID_GEN_RCV_ERROR
  83     u64                         RcvDiscards;            // OID_GEN_RCV_DISCARDS
  84         u64                             RcvNoBuffer;            // OID_GEN_RCV_NO_BUFFER
  85     u64                         PdqFull;                        // Processed Data Queue Full
  86         u64                             EventRingFull;          // Event ring full
  87         // Verbose stats
  88         u64                             MaxSends;                       // Max sends outstanding
  89         u64                             NoSglBuf;                       // SGL buffer allocation failure
  90         u64                             SglFail;                        // NDIS SGL failure
  91         u64                             SglAsync;                       // NDIS SGL failure
  92         u64                             NoMem;                          // Memory allocation failure
  93         u64                             NumInts;                        // Interrupts
  94         u64                             FalseInts;                      // Interrupt with ISR == 0
  95         u64                             XmtDrops;                       // No sahara DRAM buffer for xmt
  96         // Sahara receive status
  97         u64                             TransportCsum;          // SXG_RCV_STATUS_TRANSPORT_CSUM
  98         u64                             TransportUflow;         // SXG_RCV_STATUS_TRANSPORT_UFLOW
  99         u64                             TransportHdrLen;        // SXG_RCV_STATUS_TRANSPORT_HDRLEN
 100         u64                             NetworkCsum;            // SXG_RCV_STATUS_NETWORK_CSUM:
 101         u64                             NetworkUflow;           // SXG_RCV_STATUS_NETWORK_UFLOW:
 102         u64                             NetworkHdrLen;          // SXG_RCV_STATUS_NETWORK_HDRLEN:
 103         u64                             Parity;                         // SXG_RCV_STATUS_PARITY
 104         u64                             LinkParity;                     // SXG_RCV_STATUS_LINK_PARITY:
 105         u64                             LinkEarly;                      // SXG_RCV_STATUS_LINK_EARLY:
 106         u64                             LinkBufOflow;           // SXG_RCV_STATUS_LINK_BUFOFLOW:
 107         u64                             LinkCode;                       // SXG_RCV_STATUS_LINK_CODE:
 108         u64                             LinkDribble;            // SXG_RCV_STATUS_LINK_DRIBBLE:
 109         u64                             LinkCrc;                        // SXG_RCV_STATUS_LINK_CRC:
 110         u64                             LinkOflow;                      // SXG_RCV_STATUS_LINK_OFLOW:
 111         u64                             LinkUflow;                      // SXG_RCV_STATUS_LINK_UFLOW:
 112 };
 113
 114
 115 /****************************************************************************
 116  * DUMB-NIC Send path definitions
 117  ****************************************************************************/
 118
 119 #define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) {                                         \
 120         ASSERT(_skb);                                                                                                                           \
 121     dev_kfree_skb_irq(_skb);                                                        \
 122 }
 123
 124 #define SXG_DROP_DUMB_SEND(_pAdapt, _skb) {                                             \
 125         ASSERT(_skb);                                                                                                                           \
 126     dev_kfree_skb(_skb);                                                            \
 127 }
 128
 129 // Locate current receive header buffer location.  Use this
 130 // instead of RcvDataHdr->VirtualAddress since the data
 131 // may have been offset by SXG_ADVANCE_MDL_OFFSET
 132 #define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr)        (_RcvDataHdr)->skb->data
 133
 134 /************************************************************************
 135  * Dumb-NIC receive processing
 136  ************************************************************************/
 137 // Define an SXG_PACKET as an NDIS_PACKET
 138 #define PSXG_PACKET       struct sk_buff *
 139 // Indications array size
 140 #define SXG_RCV_ARRAYSIZE       64
 141
 142 #define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr) {                           \
 143         struct sk_buff * skb;                                                                                               \
 144     skb = alloc_skb(2048, GFP_ATOMIC);                                      \
 145     if (skb) {                                                              \
 146         (_RcvDataBufferHdr)->skb = skb;                                     \
 147         skb->next = NULL;                                                   \
 148     } else {                                                                \
 149         (_RcvDataBufferHdr)->skb = NULL;                                    \
 150     }                                                                       \
 151 }
 152
 153 #define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) {                                                        \
 154         if((_RcvDataBufferHdr)->skb) {                                                                                  \
 155                 dev_kfree_skb((_RcvDataBufferHdr)->skb);                                                    \
 156     }                                                                       \
 157 }
 158
 159 // Macro to add a NDIS_PACKET to an indication array
 160 // If we fill up our array of packet pointers, then indicate this
 161 // block up now and start on a new one.
 162 #define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, _NumPackets) { \
 163         (_IndicationList)[_NumPackets] = (_Packet);                                                                             \
 164         (_NumPackets)++;                                                                                                                                \
 165         if((_NumPackets) == SXG_RCV_ARRAYSIZE) {                                                                                \
 166                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv",                           \
 167                                    (_NumPackets), 0, 0, 0);                                                                                     \
 168         netif_rx((_IndicationList),(_NumPackets));                                  \
 169                 (_NumPackets) = 0;                                                                                                                      \
 170         }                                                                                                                                                               \
 171 }
 172
 173 #define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) {                   \
 174         if(_NumPackets) {                                                                                                                       \
 175                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv",                   \
 176                                    (_NumPackets), 0, 0, 0);                                                                             \
 177         netif_rx((_IndicationList),(_NumPackets));                              \
 178                 (_NumPackets) = 0;                                                                                                              \
 179         }                                                                                                                                                       \
 180 }
 181
 182 #define SXG_REINIATIALIZE_PACKET(_Packet)                                                                               \
 183         {}  /*_NdisReinitializePacket(_Packet)*/  /*  this is not necessary with an skb */
 184
 185 // Definitions to initialize Dumb-nic Receive NBLs
 186 #define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((PSXG_RCV_NBL_RESERVED)((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
 187
 188 #define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi)        \
 189         NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
 190
 191 #define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) {            \
 192         NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz));                                             \
 193         NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type));                                                  \
 194         NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function));                                  \
 195 }
 196
 197 #define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) {                                    \
 198         NDIS_PACKET_8021Q_INFO  _Packet8021qInfo;                                                                       \
 199         _Packet8021qInfo.TagHeader.VlanId = (_VlanId);                                                          \
 200         _Packet8021qInfo.TagHeader.UserPriority = (_Priority);                                          \
 201         NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) =       \
 202                 _Packet8021qInfo.Value;                                                                                                 \
 203 }
 204
 205 #define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) {                     \
 206         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv",                    \
 207                            (_RcvDataBufferHdr), (_Packet),                                                              \
 208                            (_Event)->Status, 0);                                                        \
 209         ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size);                                  \
 210     Packet->len = (_Event)->Length;                                         \
 211 }
 212
 213 ///////////////////////////////////////////////////////////////////////////////
 214 // Macros to free a receive data buffer and receive data descriptor block
 215 ///////////////////////////////////////////////////////////////////////////////
 216 // NOTE - Lock must be held with RCV macros
 217 #define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) {                                                                \
 218         struct LIST_ENTRY                               *_ple;                                                                          \
 219         _Hdr = NULL;                                                                                                                            \
 220         if((_pAdapt)->FreeRcvBufferCount) {                                                                                     \
 221                 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers)));                                             \
 222                 _ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers);                                      \
 223                 (_Hdr) = container_of(_ple, struct SXG_RCV_DATA_BUFFER_HDR, FreeList);          \
 224                 (_pAdapt)->FreeRcvBufferCount--;                                                                                \
 225                 ASSERT((_Hdr)->State == SXG_BUFFER_FREE);                                                               \
 226         }                                                                                                                                                       \
 227 }
 228
 229 #define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) {                                                       \
 230         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr",                    \
 231                            (_Hdr), (_pAdapt)->FreeRcvBufferCount,                                               \
 232                            (_Hdr)->State, (_Hdr)->VirtualAddress);                                              \
 233 /*      SXG_RESTORE_MDL_OFFSET(_Hdr);   */                                                                              \
 234         (_pAdapt)->FreeRcvBufferCount++;                                                                                \
 235         ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) >= (_pAdapt)->FreeRcvBufferCount); \
 236         ASSERT((_Hdr)->State != SXG_BUFFER_FREE);                                                               \
 237         (_Hdr)->State = SXG_BUFFER_FREE;                                                                                \
 238         InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList));                \
 239 }
 240
 241 #define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) {                                          \
 242         ASSERT((_Hdr)->State != SXG_BUFFER_FREE);                                                               \
 243         (_Hdr)->State = SXG_BUFFER_FREE;                                                                                \
 244         (_pAdapt)->FreeRcvBlockCount++;                                                                                 \
 245         ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount);    \
 246         InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList);                   \
 247 }
 248
 249 // SGL macros
 250 #define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) {       \
 251         spin_lock(&(_pAdapt)->SglQLock);                \
 252         (_pAdapt)->FreeSglBufferCount++;                \
 253         ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount);\
 254         ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE));     \
 255         (_Sgl)->State = SXG_BUFFER_FREE;                \
 256         InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList);  \
 257         spin_unlock(&(_pAdapt)->SglQLock);              \
 258 }
 259
 260 // Get an SGL buffer from the free queue.  The first part of this macro
 261 // attempts to keep ahead of buffer depletion by allocating more when
 262 // we hit a minimum threshold.  Note that we don't grab the lock
 263 // until after that.  We're dealing with round numbers here, so we don't need to,
 264 // and not grabbing it avoids a possible double-trip.
 265 #define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) {                             \
 266         struct LIST_ENTRY *_ple;                                                \
 267         if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) &&      \
 268            (_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) &&        \
 269            (_pAdapt->AllocationsPending == 0)) {                        \
 270                 sxg_allocate_buffer_memory(_pAdapt,                     \
 271                         (sizeof(struct SXG_SCATTER_GATHER) + SXG_SGL_BUF_SIZE),\
 272                         SXG_BUFFER_TYPE_SGL);                           \
 273         }                                                               \
 274         _Sgl = NULL;                                                    \
 275         spin_lock(&(_pAdapt)->SglQLock);                                \
 276         if((_pAdapt)->FreeSglBufferCount) {                             \
 277                 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers)));     \
 278                 _ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers);      \
 279                 (_Sgl) = container_of(_ple, struct SXG_SCATTER_GATHER, FreeList); \
 280             (_pAdapt)->FreeSglBufferCount--;                            \
 281                 ASSERT((_Sgl)->State == SXG_BUFFER_FREE);               \
 282                 (_Sgl)->State = SXG_BUFFER_BUSY;                        \
 283                 (_Sgl)->pSgl = NULL;                                    \
 284         }                                                               \
 285         spin_unlock(&(_pAdapt)->SglQLock);                              \
 286 }
 287
 288 //
 289 // SXG_MULTICAST_ADDRESS
 290 //
 291 // Linked list of multicast addresses.
 292 struct SXG_MULTICAST_ADDRESS {
 293         unsigned char                                                   Address[6];
 294         struct SXG_MULTICAST_ADDRESS    *Next;
 295 };
 296
 297 // Structure to maintain chimney send and receive buffer queues.
 298 // This structure maintains NET_BUFFER_LIST queues that are
 299 // given to us via the Chimney MiniportTcpOffloadSend and
 300 // MiniportTcpOffloadReceive routines.  This structure DOES NOT
 301 // manage our data buffer queue
 302 struct SXG_BUFFER_QUEUE {
 303         u32                                             Type;                   // Slow or fast - See below
 304         u32                                             Direction;              // Xmt or Rcv
 305         u32                                             Bytes;                  // Byte count
 306         u32 *                           Head;                   // Send queue head
 307         u32 *                           Tail;                   // Send queue tail
 308 //      PNET_BUFFER_LIST                        NextNBL;                // Short cut - next NBL
 309 //      PNET_BUFFER                                     NextNB;                 // Short cut - next NB
 310 };
 311
 312 #define         SXG_SLOW_SEND_BUFFER    0
 313 #define         SXG_FAST_SEND_BUFFER    1
 314 #define         SXG_RECEIVE_BUFFER              2
 315
 316 #define SXG_INIT_BUFFER(_Buffer, _Type) {                                               \
 317         (_Buffer)->Type = (_Type);                                                                      \
 318         if((_Type) == SXG_RECEIVE_BUFFER) {                                                     \
 319                 (_Buffer)->Direction = 0;                                                               \
 320         } else {                                                                                                        \
 321                 (_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE;    \
 322         }                                                                                                                       \
 323         (_Buffer)->Bytes = 0;                                                                           \
 324         (_Buffer)->Head = NULL;                                                                         \
 325         (_Buffer)->Tail = NULL;                                                                         \
 326 }
 327
 328
 329 #define SXG_RSS_CPU_COUNT(_pAdapt)                                                              \
 330         ((_pAdapt)->RssEnabled  ?  NR_CPUS : 1)
 331
 332 /****************************************************************************
 333  * DRIVER and ADAPTER structures
 334  ****************************************************************************/
 335
 336 // Adapter states - These states closely match the adapter states
 337 // documented in the DDK (with a few exceptions).
 338 enum SXG_STATE {
 339         SXG_STATE_INITIALIZING,                 // Initializing
 340         SXG_STATE_BOOTDIAG,                             // Boot-Diagnostic mode
 341         SXG_STATE_PAUSING,                              // Pausing
 342         SXG_STATE_PAUSED,                               // Paused
 343         SXG_STATE_RUNNING,                              // Running
 344         SXG_STATE_RESETTING,                    // Reset in progress
 345         SXG_STATE_SLEEP,                                // Sleeping
 346         SXG_STATE_DIAG,                                 // Diagnostic mode
 347         SXG_STATE_HALTING,                              // Halting
 348         SXG_STATE_HALTED,                               // Down or not-initialized
 349         SXG_STATE_SHUTDOWN                              // shutdown
 350 };
 351
 352 // Link state
 353 enum SXG_LINK_STATE {
 354         SXG_LINK_DOWN,
 355         SXG_LINK_UP
 356 };
 357
 358 // Link initialization timeout in 100us units
 359 #define SXG_LINK_TIMEOUT        100000          // 10 Seconds - REDUCE!
 360
 361
 362 // Microcode file selection codes
 363 enum SXG_UCODE_SEL {
 364         SXG_UCODE_SAHARA,                               // Sahara ucode
 365         SXG_UCODE_SDIAGCPU,                             // Sahara CPU diagnostic ucode
 366         SXG_UCODE_SDIAGSYS                              // Sahara system diagnostic ucode
 367 };
 368
 369
 370 #define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
 371 #define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
 372
 373 // This probably lives in a proto.h file.  Move later
 374 #define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
 375 #define SXG_BROADCAST_PACKET(_pether) ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
 376                                 (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
 377
 378 // For DbgPrints
 379 #define SXG_ID      DPFLTR_IHVNETWORK_ID
 380 #define SXG_ERROR   DPFLTR_ERROR_LEVEL
 381
 382 //
 383 // SXG_DRIVER structure -
 384 //
 385 // contains information about the sxg driver.  There is only
 386 // one of these, and it is defined as a global.
 387 struct SXG_DRIVER {
 388         struct adapter_t        *Adapters;              // Linked list of adapters
 389         ushort                          AdapterID;              // Maintain unique adapter ID
 390 };
 391
 392 #ifdef STATUS_SUCCESS
 393 #undef STATUS_SUCCESS
 394 #endif
 395
 396 #define STATUS_SUCCESS              0
 397 #define STATUS_PENDING              0
 398 #define STATUS_FAILURE             -1
 399 #define STATUS_ERROR               -2
 400 #define STATUS_NOT_SUPPORTED       -3
 401 #define STATUS_BUFFER_TOO_SHORT    -4
 402 #define STATUS_RESOURCES           -5
 403
 404 #define SLIC_MAX_CARDS              32
 405 #define SLIC_MAX_PORTS              4        /* Max # of ports per card   */
 406 #if SLIC_DUMP_ENABLED
 407 // Dump buffer size
 408 //
 409 // This cannot be bigger than the max DMA size the card supports,
 410 // given the current code structure in the host and ucode.
 411 // Mojave supports 16K, Oasis supports 16K-1, so
 412 // just set this at 15K, shouldnt make that much of a diff.
 413 #define DUMP_BUF_SIZE               0x3C00
 414 #endif
 415
 416 #define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
 417 #define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
 418
 419 struct mcast_address_t {
 420     unsigned char                     address[6];
 421     struct mcast_address_t   *next;
 422 };
 423
 424 #define CARD_DOWN        0x00000000
 425 #define CARD_UP          0x00000001
 426 #define CARD_FAIL        0x00000002
 427 #define CARD_DIAG        0x00000003
 428 #define CARD_SLEEP       0x00000004
 429
 430 #define ADAPT_DOWN             0x00
 431 #define ADAPT_UP               0x01
 432 #define ADAPT_FAIL             0x02
 433 #define ADAPT_RESET            0x03
 434 #define ADAPT_SLEEP            0x04
 435
 436 #define ADAPT_FLAGS_BOOTTIME            0x0001
 437 #define ADAPT_FLAGS_IS64BIT             0x0002
 438 #define ADAPT_FLAGS_PENDINGLINKDOWN     0x0004
 439 #define ADAPT_FLAGS_FIBERMEDIA          0x0008
 440 #define ADAPT_FLAGS_LOCKS_ALLOCED       0x0010
 441 #define ADAPT_FLAGS_INT_REGISTERED      0x0020
 442 #define ADAPT_FLAGS_LOAD_TIMER_SET      0x0040
 443 #define ADAPT_FLAGS_STATS_TIMER_SET     0x0080
 444 #define ADAPT_FLAGS_RESET_TIMER_SET     0x0100
 445
 446 #define LINK_DOWN              0x00
 447 #define LINK_CONFIG            0x01
 448 #define LINK_UP                0x02
 449
 450 #define LINK_10MB              0x00
 451 #define LINK_100MB             0x01
 452 #define LINK_AUTOSPEED         0x02
 453 #define LINK_1000MB            0x03
 454 #define LINK_10000MB           0x04
 455
 456 #define LINK_HALFD             0x00
 457 #define LINK_FULLD             0x01
 458 #define LINK_AUTOD             0x02
 459
 460 #define MAC_DIRECTED     0x00000001
 461 #define MAC_BCAST        0x00000002
 462 #define MAC_MCAST        0x00000004
 463 #define MAC_PROMISC      0x00000008
 464 #define MAC_LOOPBACK     0x00000010
 465 #define MAC_ALLMCAST     0x00000020
 466
 467 #define SLIC_DUPLEX(x)    ((x==LINK_FULLD) ? "FDX" : "HDX")
 468 #define SLIC_SPEED(x)     ((x==LINK_100MB) ? "100Mb" : ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
 469 #define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up  ")
 470 #define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
 471 #define SLIC_CARD_STATE(x)    ((x==CARD_UP) ? "UP" : "Down")
 472
 473
 474 struct ether_header {
 475     unsigned char    ether_dhost[6];
 476     unsigned char    ether_shost[6];
 477     ushort   ether_type;
 478 };
 479
 480
 481 #define NUM_CFG_SPACES      2
 482 #define NUM_CFG_REGS        64
 483
 484 struct physcard_t {
 485     struct adapter_t  *adapter[SLIC_MAX_PORTS];
 486     struct physcard_t *next;
 487     unsigned int                adapters_allocd;
 488 };
 489
 490 struct sxgbase_driver_t {
 491         spinlock_t      driver_lock;
 492         unsigned long   flags;  /* irqsave for spinlock */
 493         u32             num_sxg_cards;
 494         u32             num_sxg_ports;
 495         u32             num_sxg_ports_active;
 496         u32             dynamic_intagg;
 497         struct physcard_t       *phys_card;
 498 };
 499
 500
 501 struct adapter_t {
 502         void *               ifp;
 503         unsigned int                port;
 504         struct physcard_t        *physcard;
 505         unsigned int                physport;
 506         unsigned int                cardindex;
 507         unsigned int                card_size;
 508         unsigned int                chipid;
 509         unsigned int                busnumber;
 510         unsigned int                slotnumber;
 511         unsigned int                functionnumber;
 512         ushort              vendid;
 513         ushort              devid;
 514         ushort              subsysid;
 515         u32             irq;
 516
 517         void *               sxg_adapter;
 518         u32             nBusySend;
 519
 520         void __iomem *  base_addr;
 521         u32             memorylength;
 522         u32             drambase;
 523         u32             dramlength;
 524         unsigned int                queues_initialized;
 525         unsigned int                allocated;
 526         unsigned int                activated;
 527         u32             intrregistered;
 528         unsigned int                isp_initialized;
 529         unsigned int                gennumber;
 530         u32             curaddrupper;
 531         u32             isrcopy;
 532         unsigned char               state;
 533         unsigned char               linkstate;
 534         unsigned char               linkspeed;
 535         unsigned char               linkduplex;
 536         unsigned int                flags;
 537         unsigned char               macaddr[6];
 538         unsigned char               currmacaddr[6];
 539         u32             macopts;
 540         ushort              devflags_prev;
 541         u64             mcastmask;
 542         struct mcast_address_t   *mcastaddrs;
 543         struct timer_list   pingtimer;
 544         u32             pingtimerset;
 545         struct timer_list   statstimer;
 546         u32             statstimerset;
 547         struct timer_list   vpci_timer;
 548         u32             vpci_timerset;
 549         struct timer_list   loadtimer;
 550         u32             loadtimerset;
 551
 552         u32             xmitq_full;
 553         u32             all_reg_writes;
 554         u32             icr_reg_writes;
 555         u32             isr_reg_writes;
 556         u32             error_interrupts;
 557         u32             error_rmiss_interrupts;
 558         u32             rx_errors;
 559         u32             rcv_drops;
 560         u32             rcv_interrupts;
 561         u32             xmit_interrupts;
 562         u32             linkevent_interrupts;
 563         u32             upr_interrupts;
 564         u32             num_isrs;
 565         u32             false_interrupts;
 566         u32             tx_packets;
 567         u32             xmit_completes;
 568         u32             tx_drops;
 569         u32             rcv_broadcasts;
 570         u32             rcv_multicasts;
 571         u32             rcv_unicasts;
 572         u32             max_isr_rcvs;
 573         u32             max_isr_xmits;
 574         u32             rcv_interrupt_yields;
 575         u32             intagg_period;
 576         struct net_device_stats stats;
 577         u32 *                                   MiniportHandle;         // Our miniport handle
 578         enum SXG_STATE                                  State;                          // Adapter state
 579         enum SXG_LINK_STATE                             LinkState;                      // Link state
 580         u64                                             LinkSpeed;                      // Link Speed
 581         u32                                             PowerState;                     // NDIS power state
 582         struct adapter_t                *Next;                          // Linked list
 583         ushort                                          AdapterID;                      // 1..n
 584         unsigned char                                           MacAddr[6];                     // Our permanent HW mac address
 585         unsigned char                                           CurrMacAddr[6];         // Our Current mac address
 586         p_net_device                netdev;
 587         p_net_device                next_netdevice;
 588         struct pci_dev            * pcidev;
 589
 590         struct SXG_MULTICAST_ADDRESS            *MulticastAddrs;                // Multicast list
 591         u64                                     MulticastMask;          // Multicast mask
 592         u32 *                                   InterruptHandle;        // Register Interrupt handle
 593         u32                                             InterruptLevel;         // From Resource list
 594         u32                                             InterruptVector;        // From Resource list
 595         spinlock_t      AdapterLock;    /* Serialize access adapter routines */
 596         spinlock_t      Bit64RegLock;   /* For writing 64-bit addresses */
 597         struct SXG_HW_REGS                      *HwRegs;                                // Sahara HW Register Memory (BAR0/1)
 598         struct SXG_UCODE_REGS                   *UcodeRegs;                     // Microcode Register Memory (BAR2/3)
 599         struct SXG_TCB_REGS                     *TcbRegs;                       // Same as Ucode regs - See sxghw.h
 600         ushort                                          ResetDpcCount;          // For timeout
 601         ushort                                          RssDpcCount;            // For timeout
 602         ushort                                          VendorID;                       // Vendor ID
 603         ushort                                          DeviceID;                       // Device ID
 604         ushort                                          SubSystemID;            // Sub-System ID
 605         ushort                                          FrameSize;                      // Maximum frame size
 606         u32 *                                   DmaHandle;                      // NDIS DMA handle
 607         u32 *                                   PacketPoolHandle;       // Used with NDIS 5.2 only.  Don't ifdef out
 608         u32 *                                   BufferPoolHandle;       // Used with NDIS 5.2 only.  Don't ifdef out
 609         u32                                             MacFilter;                      // NDIS MAC Filter
 610         ushort                                          IpId;                           // For slowpath
 611         struct SXG_EVENT_RING                   *EventRings;                    // Host event rings.  1/CPU to 16 max
 612         dma_addr_t                      PEventRings;            // Physical address
 613         u32                                             NextEvent[SXG_MAX_RSS]; // Current location in ring
 614         dma_addr_t                      PTcbBuffers;            // TCB Buffers - physical address
 615         dma_addr_t                      PTcbCompBuffers;        // TCB Composite Buffers - phys addr
 616         struct SXG_XMT_RING                             *XmtRings;                      // Transmit rings
 617         dma_addr_t                          PXmtRings;                  // Transmit rings - physical address
 618         struct SXG_RING_INFO                            XmtRingZeroInfo;        // Transmit ring 0 info
 619         spinlock_t      XmtZeroLock;    /* Transmit ring 0 lock */
 620         u32 *                                   XmtRingZeroIndex;       // Shared XMT ring 0 index
 621         dma_addr_t                      PXmtRingZeroIndex;      // Shared XMT ring 0 index - physical
 622         struct LIST_ENTRY                                       FreeProtocolHeaders;// Free protocol headers
 623         u32                                             FreeProtoHdrCount;      // Count
 624         void *                                          ProtocolHeaders;        // Block of protocol header
 625         dma_addr_t                      PProtocolHeaders;       // Block of protocol headers - phys
 626
 627         struct SXG_RCV_RING             *RcvRings;                      // Receive rings
 628         dma_addr_t                      PRcvRings;                      // Receive rings - physical address
 629         struct SXG_RING_INFO                            RcvRingZeroInfo;        // Receive ring 0 info
 630
 631         u32 *                                   Isr;                            // Interrupt status register
 632         dma_addr_t                      PIsr;                           // ISR - physical address
 633         u32                                             IsrCopy[SXG_MAX_RSS];   // Copy of ISR
 634         ushort                                          InterruptsEnabled;      // Bitmask of enabled vectors
 635         unsigned char *                                         IndirectionTable;       // RSS indirection table
 636         dma_addr_t                      PIndirectionTable;      // Physical address
 637         ushort                                          RssTableSize;           // From NDIS_RECEIVE_SCALE_PARAMETERS
 638         ushort                                          HashKeySize;            // From NDIS_RECEIVE_SCALE_PARAMETERS
 639         unsigned char                                           HashSecretKey[40];      // rss key
 640         u32                                             HashInformation;
 641         // Receive buffer queues
 642         spinlock_t      RcvQLock;       /* Receive Queue Lock */
 643         struct LIST_ENTRY                                       FreeRcvBuffers;         // Free SXG_DATA_BUFFER queue
 644         struct LIST_ENTRY                                       FreeRcvBlocks;          // Free SXG_RCV_DESCRIPTOR_BLOCK Q
 645         struct LIST_ENTRY                                       AllRcvBlocks;           // All SXG_RCV_BLOCKs
 646         ushort                                          FreeRcvBufferCount;     // Number of free rcv data buffers
 647         ushort                                          FreeRcvBlockCount;      // # of free rcv descriptor blocks
 648         ushort                                          AllRcvBlockCount;       // Number of total receive blocks
 649         ushort                                          ReceiveBufferSize;      // SXG_RCV_DATA/JUMBO_BUFFER_SIZE only
 650         u32                                             AllocationsPending;     // Receive allocation pending
 651         u32                                             RcvBuffersOnCard;       // SXG_DATA_BUFFERS owned by card
 652         // SGL buffers
 653         spinlock_t      SglQLock;       /* SGL Queue Lock */
 654         struct LIST_ENTRY                                       FreeSglBuffers;         // Free SXG_SCATTER_GATHER
 655         struct LIST_ENTRY                                       AllSglBuffers;          // All SXG_SCATTER_GATHER
 656         ushort                                          FreeSglBufferCount;     // Number of free SGL buffers
 657         ushort                                          AllSglBufferCount;      // Number of total SGL buffers
 658         u32                                             CurrentTime;            // Tick count
 659         u32                                             FastpathConnections;// # of fastpath connections
 660         // Various single-bit flags:
 661         u32                                             BasicAllocations:1;     // Locks and listheads
 662         u32                                             IntRegistered:1;        // Interrupt registered
 663         u32                                             PingOutstanding:1;      // Ping outstanding to card
 664         u32                                             Dead:1;                         // Card dead
 665         u32                                             DumpDriver:1;           // OID_SLIC_DRIVER_DUMP request
 666         u32                                             DumpCard:1;                     // OID_SLIC_CARD_DUMP request
 667         u32                                             DumpCmdRunning:1;       // Dump command in progress
 668         u32                                             DebugRunning:1;         // AGDB debug in progress
 669         u32                                             JumboEnabled:1;         // Jumbo frames enabled
 670         u32                                             MsiEnabled:1;           // MSI interrupt enabled
 671         u32                                             RssEnabled:1;           // RSS Enabled
 672         u32                                             FailOnBadEeprom:1;      // Fail on Bad Eeprom
 673         u32                                             DiagStart:1;            // Init adapter for diagnostic start
 674         // Stats
 675         u32                                             PendingRcvCount;        // Outstanding rcv indications
 676         u32                                             PendingXmtCount;        // Outstanding send requests
 677         struct SXG_STATS                                Stats;                          // Statistics
 678         u32                                             ReassBufs;                      // Number of reassembly buffers
 679         // Card Crash Info
 680         ushort                                          CrashLocation;          // Microcode crash location
 681         unsigned char                                           CrashCpu;                       // Sahara CPU ID
 682         // Diagnostics
 683         //      PDIAG_CMD                                       DiagCmds;                       // List of free diagnostic commands
 684         //      PDIAG_BUFFER                            DiagBuffers;            // List of free diagnostic buffers
 685         //      PDIAG_REQ                                       DiagReqQ;                       // List of outstanding (asynchronous) diag requests
 686         //      u32                                             DiagCmdTimeout;         // Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var?
 687         //      unsigned char                                           DiagDmaDesc[DMA_CPU_CTXS];              // Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx)
 688
 689         /////////////////////////////////////////////////////////////////////
 690         // Put preprocessor-conditional fields at the end so we don't
 691         // have to recompile sxgdbg everytime we reconfigure the driver
 692         /////////////////////////////////////////////////////////////////////
 693         void *                                          PendingSetRss;          // Pending RSS parameter change
 694         u32                                             IPv4HdrSize;            // Shared 5.2/6.0 encap param
 695         unsigned char *                                 InterruptInfo;          // Allocated by us during AddDevice
 696 #if defined(CONFIG_X86)
 697         u32                                             AddrUpper;                      // Upper 32 bits of 64-bit register
 698 #endif
 699         //#if SXG_FAILURE_DUMP
 700         //      NDIS_EVENT                                      DumpThreadEvent;        // syncronize dump thread
 701         //      BOOLEAN                                         DumpThreadRunning;      // termination flag
 702         //      PSXG_DUMP_CMD                           DumpBuffer;                     // 68k - Cmd and Buffer
 703         //      dma_addr_t              PDumpBuffer;            // Physical address
 704         //#endif // SXG_FAILURE_DUMP
 705
 706 };
 707
 708 #if SLIC_DUMP_ENABLED
 709 #define SLIC_DUMP_REQUESTED      1
 710 #define SLIC_DUMP_IN_PROGRESS    2
 711 #define SLIC_DUMP_DONE           3
 712
 713 /****************************************************************************
 714  *
 715  * Microcode crash information structure.  This
 716  * structure is written out to the card's SRAM when the microcode panic's.
 717  *
 718  ****************************************************************************/
 719 struct slic_crash_info {
 720     ushort  cpu_id;
 721     ushort  crash_pc;
 722 };
 723
 724 #define CRASH_INFO_OFFSET   0x155C
 725
 726 #endif
 727
 728 #define UPDATE_STATS(largestat, newstat, oldstat)                        \
 729 {                                                                        \
 730     if ((newstat) < (oldstat))                                           \
 731         (largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1));         \
 732     else                                                                 \
 733         (largestat) += ((newstat) - (oldstat));                          \
 734 }
 735
 736 #define UPDATE_STATS_GB(largestat, newstat, oldstat)                     \
 737 {                                                                        \
 738     (largestat) += ((newstat) - (oldstat));                              \
 739 }
 740
 741 #define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result)                           \
 742 {                                                                        \
 743     _Result = TRUE;                                                      \
 744     if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB))                      \
 745         _Result = FALSE;                                                 \
 746     if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4])))        \
 747         _Result = FALSE;                                                 \
 748 }
 749
 750 #define ETHERMAXFRAME   1514
 751 #define JUMBOMAXFRAME   9014
 752
 753 #if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
 754 #define   SXG_GET_ADDR_LOW(_addr)  (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
 755 #define   SXG_GET_ADDR_HIGH(_addr)  (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
 756 #else
 757 #define   SXG_GET_ADDR_LOW(_addr)   (u32)_addr
 758 #define   SXG_GET_ADDR_HIGH(_addr)  (u32)0
 759 #endif
 760
 761 #define FLUSH       TRUE
 762 #define DONT_FLUSH  FALSE
 763
 764 #define SIOCSLICDUMPCARD         SIOCDEVPRIVATE+9
 765 #define SIOCSLICSETINTAGG        SIOCDEVPRIVATE+10
 766 #define SIOCSLICTRACEDUMP        SIOCDEVPRIVATE+11
 767
 768 #endif /*  __SXG_DRIVER_H__ */