3 * (Compatible with Algo System ., LTD. - AP-320A)
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Author : Yusuke Goda <goda.yuske@renesas.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/mtd/sh_flctl.h>
19 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/smsc911x.h>
22 #include <linux/gpio.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/spi_gpio.h>
25 #include <media/ov772x.h>
26 #include <media/soc_camera.h>
27 #include <media/soc_camera_platform.h>
28 #include <media/sh_mobile_ceu.h>
29 #include <video/sh_mobile_lcdc.h>
31 #include <asm/clock.h>
32 #include <cpu/sh7723.h>
34 static struct smsc911x_platform_config smsc911x_config = {
35 .phy_interface = PHY_INTERFACE_MODE_MII,
36 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
37 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
38 .flags = SMSC911X_USE_32BIT,
41 static struct resource smsc9118_resources[] = {
45 .flags = IORESOURCE_MEM,
50 .flags = IORESOURCE_IRQ,
54 static struct platform_device smsc9118_device = {
57 .num_resources = ARRAY_SIZE(smsc9118_resources),
58 .resource = smsc9118_resources,
60 .platform_data = &smsc911x_config,
65 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
66 * If this area erased, this board can not boot.
68 static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
72 .size = (1 * 1024 * 1024),
73 .mask_flags = MTD_WRITEABLE, /* Read-only */
76 .offset = MTDPART_OFS_APPEND,
77 .size = (2 * 1024 * 1024),
80 .offset = MTDPART_OFS_APPEND,
81 .size = ((7 * 1024 * 1024) + (512 * 1024)),
84 .offset = MTDPART_OFS_APPEND,
85 .mask_flags = MTD_WRITEABLE, /* Read-only */
86 .size = (1024 * 128 * 2),
89 .offset = MTDPART_OFS_APPEND,
90 .size = MTDPART_SIZ_FULL,
94 static struct physmap_flash_data ap325rxa_nor_flash_data = {
96 .parts = ap325rxa_nor_flash_partitions,
97 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
100 static struct resource ap325rxa_nor_flash_resources[] = {
105 .flags = IORESOURCE_MEM,
109 static struct platform_device ap325rxa_nor_flash_device = {
110 .name = "physmap-flash",
111 .resource = ap325rxa_nor_flash_resources,
112 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
114 .platform_data = &ap325rxa_nor_flash_data,
118 static struct mtd_partition nand_partition_info[] = {
122 .size = MTDPART_SIZ_FULL,
126 static struct resource nand_flash_resources[] = {
130 .flags = IORESOURCE_MEM,
134 static struct sh_flctl_platform_data nand_flash_data = {
135 .parts = nand_partition_info,
136 .nr_parts = ARRAY_SIZE(nand_partition_info),
137 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
141 static struct platform_device nand_flash_device = {
143 .resource = nand_flash_resources,
144 .num_resources = ARRAY_SIZE(nand_flash_resources),
146 .platform_data = &nand_flash_data,
150 #define FPGA_LCDREG 0xB4100180
151 #define FPGA_BKLREG 0xB4100212
152 #define FPGA_LCDREG_VAL 0x0018
153 #define PORT_MSELCRB 0xA4050182
154 #define PORT_HIZCRC 0xA405015C
155 #define PORT_DRVCRA 0xA405018A
156 #define PORT_DRVCRB 0xA405018C
158 static void ap320_wvga_power_on(void *board_data)
162 /* ASD AP-320/325 LCD ON */
163 ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
166 gpio_set_value(GPIO_PTS3, 0);
167 ctrl_outw(0x100, FPGA_BKLREG);
170 static void ap320_wvga_power_off(void *board_data)
173 ctrl_outw(0, FPGA_BKLREG);
174 gpio_set_value(GPIO_PTS3, 1);
176 /* ASD AP-320/325 LCD OFF */
177 ctrl_outw(0, FPGA_LCDREG);
180 static struct sh_mobile_lcdc_info lcdc_info = {
181 .clock_source = LCDC_CLK_EXTERNAL,
183 .chan = LCDC_CHAN_MAINLCD,
185 .interface_type = RGB18,
197 .sync = 0, /* hsync and vsync are active low */
199 .lcd_size_cfg = { /* 7.0 inch */
204 .display_on = ap320_wvga_power_on,
205 .display_off = ap320_wvga_power_off,
210 static struct resource lcdc_resources[] = {
213 .start = 0xfe940000, /* P4-only space */
215 .flags = IORESOURCE_MEM,
219 .flags = IORESOURCE_IRQ,
223 static struct platform_device lcdc_device = {
224 .name = "sh_mobile_lcdc_fb",
225 .num_resources = ARRAY_SIZE(lcdc_resources),
226 .resource = lcdc_resources,
228 .platform_data = &lcdc_info,
232 static void camera_power(int val)
234 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
239 /* support for the old ncm03j camera */
240 static unsigned char camera_ncm03j_magic[] =
242 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
243 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
244 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
245 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
246 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
247 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
248 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
249 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
250 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
251 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
252 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
253 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
254 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
255 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
256 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
257 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
260 static int camera_probe(void)
262 struct i2c_adapter *a = i2c_get_adapter(0);
271 msg.buf = camera_ncm03j_magic;
274 ret = i2c_transfer(a, &msg, 1);
280 static int camera_set_capture(struct soc_camera_platform_info *info,
283 struct i2c_adapter *a = i2c_get_adapter(0);
290 return 0; /* no disable for now */
293 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
301 buf[0] = camera_ncm03j_magic[i];
302 buf[1] = camera_ncm03j_magic[i + 1];
304 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
310 static struct soc_camera_platform_info camera_info = {
312 .format_name = "UYVY",
315 .pixelformat = V4L2_PIX_FMT_UYVY,
316 .colorspace = V4L2_COLORSPACE_SMPTE170M,
320 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
321 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
322 .set_capture = camera_set_capture,
325 static struct platform_device camera_device = {
326 .name = "soc_camera_platform",
328 .platform_data = &camera_info,
332 static int __init camera_setup(void)
334 if (camera_probe() > 0)
335 platform_device_register(&camera_device);
339 late_initcall(camera_setup);
341 #endif /* CONFIG_I2C */
343 static int ov7725_power(struct device *dev, int mode)
352 static struct ov772x_camera_info ov7725_info = {
353 .buswidth = SOCAM_DATAWIDTH_8,
354 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
355 .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
357 .power = ov7725_power,
361 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
362 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
365 static struct resource ceu_resources[] = {
370 .flags = IORESOURCE_MEM,
374 .flags = IORESOURCE_IRQ,
377 /* place holder for contiguous memory */
381 static struct platform_device ceu_device = {
382 .name = "sh_mobile_ceu",
383 .id = 0, /* "ceu0" clock */
384 .num_resources = ARRAY_SIZE(ceu_resources),
385 .resource = ceu_resources,
387 .platform_data = &sh_mobile_ceu_info,
391 struct spi_gpio_platform_data sdcard_cn3_platform_data = {
398 static struct platform_device sdcard_cn3_device = {
401 .platform_data = &sdcard_cn3_platform_data,
405 static struct platform_device *ap325rxa_devices[] __initdata = {
407 &ap325rxa_nor_flash_device,
414 static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
416 I2C_BOARD_INFO("pcf8563", 0x51),
419 I2C_BOARD_INFO("ov772x", 0x21),
420 .platform_data = &ov7725_info,
424 static struct spi_board_info ap325rxa_spi_devices[] = {
426 .modalias = "mmc_spi",
427 .max_speed_hz = 5000000,
429 .controller_data = (void *) GPIO_PTD5,
433 static int __init ap325rxa_devices_setup(void)
435 /* LD3 and LD4 LEDs */
436 gpio_request(GPIO_PTX5, NULL); /* RUN */
437 gpio_direction_output(GPIO_PTX5, 1);
438 gpio_export(GPIO_PTX5, 0);
440 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
441 gpio_direction_output(GPIO_PTX4, 0);
442 gpio_export(GPIO_PTX4, 0);
445 gpio_request(GPIO_PTF7, NULL); /* MODE */
446 gpio_direction_input(GPIO_PTF7);
447 gpio_export(GPIO_PTF7, 0);
450 gpio_request(GPIO_FN_LCDD15, NULL);
451 gpio_request(GPIO_FN_LCDD14, NULL);
452 gpio_request(GPIO_FN_LCDD13, NULL);
453 gpio_request(GPIO_FN_LCDD12, NULL);
454 gpio_request(GPIO_FN_LCDD11, NULL);
455 gpio_request(GPIO_FN_LCDD10, NULL);
456 gpio_request(GPIO_FN_LCDD9, NULL);
457 gpio_request(GPIO_FN_LCDD8, NULL);
458 gpio_request(GPIO_FN_LCDD7, NULL);
459 gpio_request(GPIO_FN_LCDD6, NULL);
460 gpio_request(GPIO_FN_LCDD5, NULL);
461 gpio_request(GPIO_FN_LCDD4, NULL);
462 gpio_request(GPIO_FN_LCDD3, NULL);
463 gpio_request(GPIO_FN_LCDD2, NULL);
464 gpio_request(GPIO_FN_LCDD1, NULL);
465 gpio_request(GPIO_FN_LCDD0, NULL);
466 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
467 gpio_request(GPIO_FN_LCDDCK, NULL);
468 gpio_request(GPIO_FN_LCDVEPWC, NULL);
469 gpio_request(GPIO_FN_LCDVCPWC, NULL);
470 gpio_request(GPIO_FN_LCDVSYN, NULL);
471 gpio_request(GPIO_FN_LCDHSYN, NULL);
472 gpio_request(GPIO_FN_LCDDISP, NULL);
473 gpio_request(GPIO_FN_LCDDON, NULL);
476 gpio_request(GPIO_PTS3, NULL);
477 gpio_direction_output(GPIO_PTS3, 1);
480 gpio_request(GPIO_FN_VIO_CLK2, NULL);
481 gpio_request(GPIO_FN_VIO_VD2, NULL);
482 gpio_request(GPIO_FN_VIO_HD2, NULL);
483 gpio_request(GPIO_FN_VIO_FLD, NULL);
484 gpio_request(GPIO_FN_VIO_CKO, NULL);
485 gpio_request(GPIO_FN_VIO_D15, NULL);
486 gpio_request(GPIO_FN_VIO_D14, NULL);
487 gpio_request(GPIO_FN_VIO_D13, NULL);
488 gpio_request(GPIO_FN_VIO_D12, NULL);
489 gpio_request(GPIO_FN_VIO_D11, NULL);
490 gpio_request(GPIO_FN_VIO_D10, NULL);
491 gpio_request(GPIO_FN_VIO_D9, NULL);
492 gpio_request(GPIO_FN_VIO_D8, NULL);
494 gpio_request(GPIO_PTZ7, NULL);
495 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
496 gpio_request(GPIO_PTZ6, NULL);
497 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
498 gpio_request(GPIO_PTZ5, NULL);
499 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
500 gpio_request(GPIO_PTZ4, NULL);
501 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
503 ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
506 gpio_request(GPIO_FN_FCE, NULL);
507 gpio_request(GPIO_FN_NAF7, NULL);
508 gpio_request(GPIO_FN_NAF6, NULL);
509 gpio_request(GPIO_FN_NAF5, NULL);
510 gpio_request(GPIO_FN_NAF4, NULL);
511 gpio_request(GPIO_FN_NAF3, NULL);
512 gpio_request(GPIO_FN_NAF2, NULL);
513 gpio_request(GPIO_FN_NAF1, NULL);
514 gpio_request(GPIO_FN_NAF0, NULL);
515 gpio_request(GPIO_FN_FCDE, NULL);
516 gpio_request(GPIO_FN_FOE, NULL);
517 gpio_request(GPIO_FN_FSC, NULL);
518 gpio_request(GPIO_FN_FWE, NULL);
519 gpio_request(GPIO_FN_FRB, NULL);
521 ctrl_outw(0, PORT_HIZCRC);
522 ctrl_outw(0xFFFF, PORT_DRVCRA);
523 ctrl_outw(0xFFFF, PORT_DRVCRB);
525 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
527 i2c_register_board_info(0, ap325rxa_i2c_devices,
528 ARRAY_SIZE(ap325rxa_i2c_devices));
530 spi_register_board_info(ap325rxa_spi_devices,
531 ARRAY_SIZE(ap325rxa_spi_devices));
533 return platform_add_devices(ap325rxa_devices,
534 ARRAY_SIZE(ap325rxa_devices));
536 device_initcall(ap325rxa_devices_setup);
538 /* Return the board specific boot mode pin configuration */
539 static int ap325rxa_mode_pins(void)
541 /* MD0=0, MD1=0, MD2=0: Clock Mode 0
542 * MD3=0: 16-bit Area0 Bus Width
543 * MD5=1: Little Endian
544 * TSTMD=1, MD8=1: Test Mode Disabled
546 return MODE_PIN5 | MODE_PIN8;
549 static struct sh_machine_vector mv_ap325rxa __initmv = {
550 .mv_name = "AP-325RXA",
551 .mv_mode_pins = ap325rxa_mode_pins,