2 * P5 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
5 #include <linux/interrupt.h>
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
11 #include <asm/processor.h>
12 #include <asm/system.h>
17 /* By default disabled */
20 /* Machine check handler for Pentium class Intel CPUs: */
21 static void pentium_machine_check(struct pt_regs *regs, long error_code)
23 u32 loaddr, hi, lotype;
25 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
26 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
29 "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
30 smp_processor_id(), loaddr, lotype);
32 if (lotype & (1<<5)) {
34 "CPU#%d: Possible thermal failure (CPU on fire ?).\n",
38 add_taint(TAINT_MACHINE_CHECK);
41 /* Set up machine check reporting for processors with Intel style MCE: */
42 void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
46 /* Check for MCE support: */
47 if (!cpu_has(c, X86_FEATURE_MCE))
50 #ifdef CONFIG_X86_OLD_MCE
51 /* Default P5 to off as its often misconnected: */
52 if (mce_disabled != -1)
56 machine_check_vector = pentium_machine_check;
57 /* Make sure the vector pointer is visible before we enable MCEs: */
60 /* Read registers before enabling: */
61 rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
62 rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
64 "Intel old style machine check architecture supported.\n");
67 set_in_cr4(X86_CR4_MCE);
69 "Intel old style machine check reporting enabled on CPU#%d.\n",