Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[linux-2.6] / drivers / ide / pci / hpt34x.c
1 /*
2  * linux/drivers/ide/pci/hpt34x.c               Version 0.40    Sept 10, 2002
3  *
4  * Copyright (C) 1998-2000      Andre Hedrick <andre@linux-ide.org>
5  * May be copied or modified under the terms of the GNU General Public License
6  *
7  *
8  * 00:12.0 Unknown mass storage controller:
9  * Triones Technologies, Inc.
10  * Unknown device 0003 (rev 01)
11  *
12  * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
13  * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
14  * hde: DMA 2  (0x0000 0x0002) (0x0000 0x0010)
15  * hdf: DMA 2  (0x0002 0x0012) (0x0010 0x0030)
16  * hdg: DMA 1  (0x0012 0x0052) (0x0030 0x0070)
17  * hdh: DMA 1  (0x0052 0x0252) (0x0070 0x00f0)
18  *
19  * ide-pci.c reference
20  *
21  * Since there are two cards that report almost identically,
22  * the only discernable difference is the values reported in pcicmd.
23  * Booting-BIOS card or HPT363 :: pcicmd == 0x07
24  * Non-bootable card or HPT343 :: pcicmd == 0x05
25  */
26
27 #include <linux/module.h>
28 #include <linux/types.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/timer.h>
32 #include <linux/mm.h>
33 #include <linux/ioport.h>
34 #include <linux/blkdev.h>
35 #include <linux/hdreg.h>
36 #include <linux/interrupt.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/ide.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43
44 #define HPT343_DEBUG_DRIVE_INFO         0
45
46 static u8 hpt34x_ratemask (ide_drive_t *drive)
47 {
48         return 1;
49 }
50
51 static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
52 {
53         struct pci_dev *dev     = HWIF(drive)->pci_dev;
54         u8 speed        = ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
55         u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
56         u8                      hi_speed, lo_speed;
57
58         hi_speed = speed >> 4;
59         lo_speed = speed & 0x0f;
60
61         if (hi_speed & 7) {
62                 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
63         } else {
64                 lo_speed <<= 5;
65                 lo_speed >>= 5;
66         }
67
68         pci_read_config_dword(dev, 0x44, &reg1);
69         pci_read_config_dword(dev, 0x48, &reg2);
70         tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
71         tmp2 = ((hi_speed << drive->dn) | (reg2 & ~(0x11 << drive->dn)));
72         pci_write_config_dword(dev, 0x44, tmp1);
73         pci_write_config_dword(dev, 0x48, tmp2);
74
75 #if HPT343_DEBUG_DRIVE_INFO
76         printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
77                 " (0x%02x 0x%02x)\n",
78                 drive->name, ide_xfer_verbose(speed),
79                 drive->dn, reg1, tmp1, reg2, tmp2,
80                 hi_speed, lo_speed);
81 #endif /* HPT343_DEBUG_DRIVE_INFO */
82
83         return(ide_config_drive_speed(drive, speed));
84 }
85
86 static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
87 {
88         pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
89         (void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
90 }
91
92 /*
93  * This allows the configuration of ide_pci chipset registers
94  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
95  * after the drive is reported by the OS.  Initially for designed for
96  * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
97  */
98
99 static int config_chipset_for_dma (ide_drive_t *drive)
100 {
101         u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));
102
103         if (!(speed))
104                 return 0;
105
106         (void) hpt34x_tune_chipset(drive, speed);
107         return ide_dma_enable(drive);
108 }
109
110 static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
111 {
112         drive->init_speed = 0;
113
114         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
115 #ifndef CONFIG_HPT34X_AUTODMA
116                 return -1;
117 #else
118                 return 0;
119 #endif
120
121         if (ide_use_fast_pio(drive))
122                 hpt34x_tune_drive(drive, 255);
123
124         return -1;
125 }
126
127 /*
128  * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
129  */
130 #define HPT34X_PCI_INIT_REG             0x80
131
132 static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
133 {
134         int i = 0;
135         unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
136         unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
137         unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
138         u16 cmd;
139         unsigned long flags;
140
141         local_irq_save(flags);
142
143         pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
144         pci_read_config_word(dev, PCI_COMMAND, &cmd);
145
146         if (cmd & PCI_COMMAND_MEMORY) {
147                 if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
148                         pci_write_config_dword(dev, PCI_ROM_ADDRESS,
149                                 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
150                         printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
151                                 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
152                 }
153                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
154         } else {
155                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
156         }
157
158         /*
159          * Since 20-23 can be assigned and are R/W, we correct them.
160          */
161         pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
162         for(i=0; i<4; i++) {
163                 dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
164                 dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
165                 dev->resource[i].flags = IORESOURCE_IO;
166                 pci_write_config_dword(dev,
167                                 (PCI_BASE_ADDRESS_0 + (i * 4)),
168                                 dev->resource[i].start);
169         }
170         pci_write_config_word(dev, PCI_COMMAND, cmd);
171
172         local_irq_restore(flags);
173
174         return dev->irq;
175 }
176
177 static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
178 {
179         u16 pcicmd = 0;
180
181         hwif->autodma = 0;
182
183         hwif->tuneproc = &hpt34x_tune_drive;
184         hwif->speedproc = &hpt34x_tune_chipset;
185         hwif->drives[0].autotune = 1;
186         hwif->drives[1].autotune = 1;
187
188         pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
189
190         if (!hwif->dma_base)
191                 return;
192
193         hwif->ultra_mask = 0x07;
194         hwif->mwdma_mask = 0x07;
195         hwif->swdma_mask = 0x07;
196
197         hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
198         if (!noautodma)
199                 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
200         hwif->drives[0].autodma = hwif->autodma;
201         hwif->drives[1].autodma = hwif->autodma;
202 }
203
204 static ide_pci_device_t hpt34x_chipset __devinitdata = {
205         .name           = "HPT34X",
206         .init_chipset   = init_chipset_hpt34x,
207         .init_hwif      = init_hwif_hpt34x,
208         .channels       = 2,
209         .autodma        = NOAUTODMA,
210         .bootable       = NEVER_BOARD,
211         .extra          = 16
212 };
213
214 static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
215 {
216         ide_pci_device_t *d = &hpt34x_chipset;
217         static char *chipset_names[] = {"HPT343", "HPT345"};
218         u16 pcicmd = 0;
219
220         pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
221
222         d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
223         d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
224
225         return ide_setup_pci_device(dev, d);
226 }
227
228 static struct pci_device_id hpt34x_pci_tbl[] = {
229         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
230         { 0, },
231 };
232 MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
233
234 static struct pci_driver driver = {
235         .name           = "HPT34x_IDE",
236         .id_table       = hpt34x_pci_tbl,
237         .probe          = hpt34x_init_one,
238 };
239
240 static int __init hpt34x_ide_init(void)
241 {
242         return ide_pci_register_driver(&driver);
243 }
244
245 module_init(hpt34x_ide_init);
246
247 MODULE_AUTHOR("Andre Hedrick");
248 MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
249 MODULE_LICENSE("GPL");