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   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *
   6  * Description:
   7  * Internal header file for UCC Gigabit Ethernet unit routines.
   8  *
   9  * Changelog:
  10  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  11  * - Rearrange code and style fixes
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18 #ifndef __UCC_GETH_H__
  19 #define __UCC_GETH_H__
  20
  21 #include <linux/kernel.h>
  22 #include <linux/list.h>
  23 #include <linux/fsl_devices.h>
  24
  25 #include <asm/immap_qe.h>
  26 #include <asm/qe.h>
  27
  28 #include <asm/ucc.h>
  29 #include <asm/ucc_fast.h>
  30
  31 #define NUM_TX_QUEUES                   8
  32 #define NUM_RX_QUEUES                   8
  33 #define NUM_BDS_IN_PREFETCHED_BDS       4
  34 #define TX_IP_OFFSET_ENTRY_MAX          8
  35 #define NUM_OF_PADDRS                   4
  36 #define ENET_INIT_PARAM_MAX_ENTRIES_RX  9
  37 #define ENET_INIT_PARAM_MAX_ENTRIES_TX  8
  38
  39 struct ucc_mii_mng {
  40         u32 miimcfg;            /* MII management configuration reg */
  41         u32 miimcom;            /* MII management command reg */
  42         u32 miimadd;            /* MII management address reg */
  43         u32 miimcon;            /* MII management control reg */
  44         u32 miimstat;           /* MII management status reg */
  45         u32 miimind;            /* MII management indication reg */
  46 } __attribute__ ((packed));
  47
  48 struct ucc_geth {
  49         struct ucc_fast uccf;
  50
  51         u32 maccfg1;            /* mac configuration reg. 1 */
  52         u32 maccfg2;            /* mac configuration reg. 2 */
  53         u32 ipgifg;             /* interframe gap reg.  */
  54         u32 hafdup;             /* half-duplex reg.  */
  55         u8 res1[0x10];
  56         struct ucc_mii_mng miimng;      /* MII management structure */
  57         u32 ifctl;              /* interface control reg */
  58         u32 ifstat;             /* interface statux reg */
  59         u32 macstnaddr1;        /* mac station address part 1 reg */
  60         u32 macstnaddr2;        /* mac station address part 2 reg */
  61         u8 res2[0x8];
  62         u32 uempr;              /* UCC Ethernet Mac parameter reg */
  63         u32 utbipar;            /* UCC tbi address reg */
  64         u16 uescr;              /* UCC Ethernet statistics control reg */
  65         u8 res3[0x180 - 0x15A];
  66         u32 tx64;               /* Total number of frames (including bad
  67                                    frames) transmitted that were exactly of the
  68                                    minimal length (64 for un tagged, 68 for
  69                                    tagged, or with length exactly equal to the
  70                                    parameter MINLength */
  71         u32 tx127;              /* Total number of frames (including bad
  72                                    frames) transmitted that were between
  73                                    MINLength (Including FCS length==4) and 127
  74                                    octets */
  75         u32 tx255;              /* Total number of frames (including bad
  76                                    frames) transmitted that were between 128
  77                                    (Including FCS length==4) and 255 octets */
  78         u32 rx64;               /* Total number of frames received including
  79                                    bad frames that were exactly of the mninimal
  80                                    length (64 bytes) */
  81         u32 rx127;              /* Total number of frames (including bad
  82                                    frames) received that were between MINLength
  83                                    (Including FCS length==4) and 127 octets */
  84         u32 rx255;              /* Total number of frames (including bad
  85                                    frames) received that were between 128
  86                                    (Including FCS length==4) and 255 octets */
  87         u32 txok;               /* Total number of octets residing in frames
  88                                    that where involved in succesfull
  89                                    transmission */
  90         u16 txcf;               /* Total number of PAUSE control frames
  91                                    transmitted by this MAC */
  92         u8 res4[0x2];
  93         u32 tmca;               /* Total number of frames that were transmitted
  94                                    succesfully with the group address bit set
  95                                    that are not broadcast frames */
  96         u32 tbca;               /* Total number of frames transmitted
  97                                    succesfully that had destination address
  98                                    field equal to the broadcast address */
  99         u32 rxfok;              /* Total number of frames received OK */
 100         u32 rxbok;              /* Total number of octets received OK */
 101         u32 rbyt;               /* Total number of octets received including
 102                                    octets in bad frames. Must be implemented in
 103                                    HW because it includes octets in frames that
 104                                    never even reach the UCC */
 105         u32 rmca;               /* Total number of frames that were received
 106                                    succesfully with the group address bit set
 107                                    that are not broadcast frames */
 108         u32 rbca;               /* Total number of frames received succesfully
 109                                    that had destination address equal to the
 110                                    broadcast address */
 111         u32 scar;               /* Statistics carry register */
 112         u32 scam;               /* Statistics caryy mask register */
 113         u8 res5[0x200 - 0x1c4];
 114 } __attribute__ ((packed));
 115
 116 /* UCC GETH TEMODR Register */
 117 #define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100  /* enable Tx statistics
 118                                                          */
 119 #define TEMODER_SCHEDULER_ENABLE                0x2000  /* enable scheduler */
 120 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400  /* generate IPv4
 121                                                            checksums */
 122 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200  /* enable performance
 123                                                            optimization
 124                                                            enhancement (mode1) */
 125 #define TEMODER_RMON_STATISTICS                 0x0100  /* enable tx statistics
 126                                                          */
 127 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15) /* Number of queues <<
 128                                                            shift */
 129
 130 /* UCC GETH TEMODR Register */
 131 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000      /* enable Rx
 132                                                                    statistics */
 133 #define REMODER_RX_EXTENDED_FEATURES            0x80000000      /* enable
 134                                                                    extended
 135                                                                    features */
 136 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 ) /* vlan operation
 137                                                            tagged << shift */
 138 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
 139                                                            tagged << shift */
 140 #define REMODER_RX_QOS_MODE_SHIFT               (31-15) /* rx QoS mode << shift
 141                                                          */
 142 #define REMODER_RMON_STATISTICS                 0x00001000      /* enable rx
 143                                                                    statistics */
 144 #define REMODER_RX_EXTENDED_FILTERING           0x00000800      /* extended
 145                                                                    filtering
 146                                                                    vs.
 147                                                                    mpc82xx-like
 148                                                                    filtering */
 149 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23) /* Number of queues <<
 150                                                            shift */
 151 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008      /* enable
 152                                                                    dynamic max
 153                                                                    frame length
 154                                                                  */
 155 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004      /* enable
 156                                                                    dynamic min
 157                                                                    frame length
 158                                                                  */
 159 #define REMODER_IP_CHECKSUM_CHECK               0x00000002      /* check IPv4
 160                                                                    checksums */
 161 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001      /* align ip
 162                                                                    address to
 163                                                                    4-byte
 164                                                                    boundary */
 165
 166 /* UCC GETH Event Register */
 167 #define UCCE_MPD                                0x80000000      /* Magic packet
 168                                                                    detection */
 169 #define UCCE_SCAR                               0x40000000
 170 #define UCCE_GRA                                0x20000000      /* Tx graceful
 171                                                                    stop
 172                                                                    complete */
 173 #define UCCE_CBPR                               0x10000000
 174 #define UCCE_BSY                                0x08000000
 175 #define UCCE_RXC                                0x04000000
 176 #define UCCE_TXC                                0x02000000
 177 #define UCCE_TXE                                0x01000000
 178 #define UCCE_TXB7                               0x00800000
 179 #define UCCE_TXB6                               0x00400000
 180 #define UCCE_TXB5                               0x00200000
 181 #define UCCE_TXB4                               0x00100000
 182 #define UCCE_TXB3                               0x00080000
 183 #define UCCE_TXB2                               0x00040000
 184 #define UCCE_TXB1                               0x00020000
 185 #define UCCE_TXB0                               0x00010000
 186 #define UCCE_RXB7                               0x00008000
 187 #define UCCE_RXB6                               0x00004000
 188 #define UCCE_RXB5                               0x00002000
 189 #define UCCE_RXB4                               0x00001000
 190 #define UCCE_RXB3                               0x00000800
 191 #define UCCE_RXB2                               0x00000400
 192 #define UCCE_RXB1                               0x00000200
 193 #define UCCE_RXB0                               0x00000100
 194 #define UCCE_RXF7                               0x00000080
 195 #define UCCE_RXF6                               0x00000040
 196 #define UCCE_RXF5                               0x00000020
 197 #define UCCE_RXF4                               0x00000010
 198 #define UCCE_RXF3                               0x00000008
 199 #define UCCE_RXF2                               0x00000004
 200 #define UCCE_RXF1                               0x00000002
 201 #define UCCE_RXF0                               0x00000001
 202
 203 #define UCCE_RXBF_SINGLE_MASK                   (UCCE_RXF0)
 204 #define UCCE_TXBF_SINGLE_MASK                   (UCCE_TXB0)
 205
 206 #define UCCE_TXB         (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\
 207                         UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
 208 #define UCCE_RXB         (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\
 209                         UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
 210 #define UCCE_RXF         (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\
 211                         UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
 212 #define UCCE_OTHER       (UCCE_SCAR | UCCE_GRA  | UCCE_CBPR | UCCE_BSY  |\
 213                         UCCE_RXC  | UCCE_TXC  | UCCE_TXE)
 214
 215 /* UCC GETH UPSMR (Protocol Specific Mode Register) */
 216 #define UPSMR_ECM                               0x04000000      /* Enable CAM
 217                                                                    Miss or
 218                                                                    Enable
 219                                                                    Filtering
 220                                                                    Miss */
 221 #define UPSMR_HSE                               0x02000000      /* Hardware
 222                                                                    Statistics
 223                                                                    Enable */
 224 #define UPSMR_PRO                               0x00400000      /* Promiscuous*/
 225 #define UPSMR_CAP                               0x00200000      /* CAM polarity
 226                                                                  */
 227 #define UPSMR_RSH                               0x00100000      /* Receive
 228                                                                    Short Frames
 229                                                                  */
 230 #define UPSMR_RPM                               0x00080000      /* Reduced Pin
 231                                                                    Mode
 232                                                                    interfaces */
 233 #define UPSMR_R10M                              0x00040000      /* RGMII/RMII
 234                                                                    10 Mode */
 235 #define UPSMR_RLPB                              0x00020000      /* RMII
 236                                                                    Loopback
 237                                                                    Mode */
 238 #define UPSMR_TBIM                              0x00010000      /* Ten-bit
 239                                                                    Interface
 240                                                                    Mode */
 241 #define UPSMR_RMM                               0x00001000      /* RMII/RGMII
 242                                                                    Mode */
 243 #define UPSMR_CAM                               0x00000400      /* CAM Address
 244                                                                    Matching */
 245 #define UPSMR_BRO                               0x00000200      /* Broadcast
 246                                                                    Address */
 247 #define UPSMR_RES1                              0x00002000      /* Reserved
 248                                                                    feild - must
 249                                                                    be 1 */
 250
 251 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
 252 #define MACCFG1_FLOW_RX                         0x00000020      /* Flow Control
 253                                                                    Rx */
 254 #define MACCFG1_FLOW_TX                         0x00000010      /* Flow Control
 255                                                                    Tx */
 256 #define MACCFG1_ENABLE_SYNCHED_RX               0x00000008      /* Rx Enable
 257                                                                    synchronized
 258                                                                    to Rx stream
 259                                                                  */
 260 #define MACCFG1_ENABLE_RX                       0x00000004      /* Enable Rx */
 261 #define MACCFG1_ENABLE_SYNCHED_TX               0x00000002      /* Tx Enable
 262                                                                    synchronized
 263                                                                    to Tx stream
 264                                                                  */
 265 #define MACCFG1_ENABLE_TX                       0x00000001      /* Enable Tx */
 266
 267 /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
 268 #define MACCFG2_PREL_SHIFT                      (31 - 19)       /* Preamble
 269                                                                    Length <<
 270                                                                    shift */
 271 #define MACCFG2_PREL_MASK                       0x0000f000      /* Preamble
 272                                                                    Length mask */
 273 #define MACCFG2_SRP                             0x00000080      /* Soft Receive
 274                                                                    Preamble */
 275 #define MACCFG2_STP                             0x00000040      /* Soft
 276                                                                    Transmit
 277                                                                    Preamble */
 278 #define MACCFG2_RESERVED_1                      0x00000020      /* Reserved -
 279                                                                    must be set
 280                                                                    to 1 */
 281 #define MACCFG2_LC                              0x00000010      /* Length Check
 282                                                                  */
 283 #define MACCFG2_MPE                             0x00000008      /* Magic packet
 284                                                                    detect */
 285 #define MACCFG2_FDX                             0x00000001      /* Full Duplex */
 286 #define MACCFG2_FDX_MASK                        0x00000001      /* Full Duplex
 287                                                                    mask */
 288 #define MACCFG2_PAD_CRC                         0x00000004
 289 #define MACCFG2_CRC_EN                          0x00000002
 290 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000      /* Neither
 291                                                                    Padding
 292                                                                    short frames
 293                                                                    nor CRC */
 294 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002      /* Append CRC
 295                                                                    only */
 296 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
 297 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100      /* nibble mode
 298                                                                    (MII/RMII/RGMII
 299                                                                    10/100bps) */
 300 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200      /* byte mode
 301                                                                    (GMII/TBI/RTB/RGMII
 302                                                                    1000bps ) */
 303 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300      /* mask
 304                                                                    covering all
 305                                                                    relevant
 306                                                                    bits */
 307
 308 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
 309 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 -  7)       /* Non
 310                                                                    back-to-back
 311                                                                    inter frame
 312                                                                    gap part 1.
 313                                                                    << shift */
 314 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)       /* Non
 315                                                                    back-to-back
 316                                                                    inter frame
 317                                                                    gap part 2.
 318                                                                    << shift */
 319 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT    (31 - 23)       /* Mimimum IFG
 320                                                                    Enforcement
 321                                                                    << shift */
 322 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT           (31 - 31)       /* back-to-back
 323                                                                    inter frame
 324                                                                    gap << shift
 325                                                                  */
 326 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX   127     /* Non back-to-back
 327                                                            inter frame gap part
 328                                                            1. max val */
 329 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX   127     /* Non back-to-back
 330                                                            inter frame gap part
 331                                                            2. max val */
 332 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX      255     /* Mimimum IFG
 333                                                            Enforcement max val */
 334 #define IPGIFG_BACK_TO_BACK_IFG_MAX             127     /* back-to-back inter
 335                                                            frame gap max val */
 336 #define IPGIFG_NBTB_CS_IPG_MASK                 0x7F000000
 337 #define IPGIFG_NBTB_IPG_MASK                    0x007F0000
 338 #define IPGIFG_MIN_IFG_MASK                     0x0000FF00
 339 #define IPGIFG_BTB_IPG_MASK                     0x0000007F
 340
 341 /* UCC GETH HAFDUP (Half Duplex Register) */
 342 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT        (31 - 11)       /* Alternate
 343                                                                    Binary
 344                                                                    Exponential
 345                                                                    Backoff
 346                                                                    Truncation
 347                                                                    << shift */
 348 #define HALFDUP_ALT_BEB_TRUNCATION_MAX          0xf     /* Alternate Binary
 349                                                            Exponential Backoff
 350                                                            Truncation max val */
 351 #define HALFDUP_ALT_BEB                         0x00080000      /* Alternate
 352                                                                    Binary
 353                                                                    Exponential
 354                                                                    Backoff */
 355 #define HALFDUP_BACK_PRESSURE_NO_BACKOFF        0x00040000      /* Back
 356                                                                    pressure no
 357                                                                    backoff */
 358 #define HALFDUP_NO_BACKOFF                      0x00020000      /* No Backoff */
 359 #define HALFDUP_EXCESSIVE_DEFER                 0x00010000      /* Excessive
 360                                                                    Defer */
 361 #define HALFDUP_MAX_RETRANSMISSION_SHIFT        (31 - 19)       /* Maximum
 362                                                                    Retransmission
 363                                                                    << shift */
 364 #define HALFDUP_MAX_RETRANSMISSION_MAX          0xf     /* Maximum
 365                                                            Retransmission max
 366                                                            val */
 367 #define HALFDUP_COLLISION_WINDOW_SHIFT          (31 - 31)       /* Collision
 368                                                                    Window <<
 369                                                                    shift */
 370 #define HALFDUP_COLLISION_WINDOW_MAX            0x3f    /* Collision Window max
 371                                                            val */
 372 #define HALFDUP_ALT_BEB_TR_MASK                 0x00F00000
 373 #define HALFDUP_RETRANS_MASK                    0x0000F000
 374 #define HALFDUP_COL_WINDOW_MASK                 0x0000003F
 375
 376 /* UCC GETH UCCS (Ethernet Status Register) */
 377 #define UCCS_BPR                                0x02    /* Back pressure (in
 378                                                            half duplex mode) */
 379 #define UCCS_PAU                                0x02    /* Pause state (in full
 380                                                            duplex mode) */
 381 #define UCCS_MPD                                0x01    /* Magic Packet
 382                                                            Detected */
 383
 384 /* UCC GETH MIIMCFG (MII Management Configuration Register) */
 385 #define MIIMCFG_RESET_MANAGEMENT                0x80000000      /* Reset
 386                                                                    management */
 387 #define MIIMCFG_NO_PREAMBLE                     0x00000010      /* Preamble
 388                                                                    suppress */
 389 #define MIIMCFG_CLOCK_DIVIDE_SHIFT              (31 - 31)       /* clock divide
 390                                                                    << shift */
 391 #define MIIMCFG_CLOCK_DIVIDE_MAX                0xf     /* clock divide max val
 392                                                          */
 393 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_2    0x00000000      /* divide by 2 */
 394 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4    0x00000001      /* divide by 4 */
 395 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6    0x00000002      /* divide by 6 */
 396 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8    0x00000003      /* divide by 8 */
 397 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10   0x00000004      /* divide by 10
 398                                                                  */
 399 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14   0x00000005      /* divide by 14
 400                                                                  */
 401 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_16   0x00000008      /* divide by 16
 402                                                                  */
 403 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20   0x00000006      /* divide by 20
 404                                                                  */
 405 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28   0x00000007      /* divide by 28
 406                                                                  */
 407 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_32   0x00000009      /* divide by 32
 408                                                                  */
 409 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_48   0x0000000a      /* divide by 48
 410                                                                  */
 411 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_64   0x0000000b      /* divide by 64
 412                                                                  */
 413 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_80   0x0000000c      /* divide by 80
 414                                                                  */
 415 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112  0x0000000d      /* divide by
 416                                                                    112 */
 417 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_160  0x0000000e      /* divide by
 418                                                                    160 */
 419 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_224  0x0000000f      /* divide by
 420                                                                    224 */
 421
 422 /* UCC GETH MIIMCOM (MII Management Command Register) */
 423 #define MIIMCOM_SCAN_CYCLE                      0x00000002      /* Scan cycle */
 424 #define MIIMCOM_READ_CYCLE                      0x00000001      /* Read cycle */
 425
 426 /* UCC GETH MIIMADD (MII Management Address Register) */
 427 #define MIIMADD_PHY_ADDRESS_SHIFT               (31 - 23)       /* PHY Address
 428                                                                    << shift */
 429 #define MIIMADD_PHY_REGISTER_SHIFT              (31 - 31)       /* PHY Register
 430                                                                    << shift */
 431
 432 /* UCC GETH MIIMCON (MII Management Control Register) */
 433 #define MIIMCON_PHY_CONTROL_SHIFT               (31 - 31)       /* PHY Control
 434                                                                    << shift */
 435 #define MIIMCON_PHY_STATUS_SHIFT                (31 - 31)       /* PHY Status
 436                                                                    << shift */
 437
 438 /* UCC GETH MIIMIND (MII Management Indicator Register) */
 439 #define MIIMIND_NOT_VALID                       0x00000004      /* Not valid */
 440 #define MIIMIND_SCAN                            0x00000002      /* Scan in
 441                                                                    progress */
 442 #define MIIMIND_BUSY                            0x00000001
 443
 444 /* UCC GETH IFSTAT (Interface Status Register) */
 445 #define IFSTAT_EXCESS_DEFER                     0x00000200      /* Excessive
 446                                                                    transmission
 447                                                                    defer */
 448
 449 /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
 450 #define MACSTNADDR1_OCTET_6_SHIFT               (31 -  7)       /* Station
 451                                                                    address 6th
 452                                                                    octet <<
 453                                                                    shift */
 454 #define MACSTNADDR1_OCTET_5_SHIFT               (31 - 15)       /* Station
 455                                                                    address 5th
 456                                                                    octet <<
 457                                                                    shift */
 458 #define MACSTNADDR1_OCTET_4_SHIFT               (31 - 23)       /* Station
 459                                                                    address 4th
 460                                                                    octet <<
 461                                                                    shift */
 462 #define MACSTNADDR1_OCTET_3_SHIFT               (31 - 31)       /* Station
 463                                                                    address 3rd
 464                                                                    octet <<
 465                                                                    shift */
 466
 467 /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
 468 #define MACSTNADDR2_OCTET_2_SHIFT               (31 -  7)       /* Station
 469                                                                    address 2nd
 470                                                                    octet <<
 471                                                                    shift */
 472 #define MACSTNADDR2_OCTET_1_SHIFT               (31 - 15)       /* Station
 473                                                                    address 1st
 474                                                                    octet <<
 475                                                                    shift */
 476
 477 /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
 478 #define UEMPR_PAUSE_TIME_VALUE_SHIFT            (31 - 15)       /* Pause time
 479                                                                    value <<
 480                                                                    shift */
 481 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT   (31 - 31)       /* Extended
 482                                                                    pause time
 483                                                                    value <<
 484                                                                    shift */
 485
 486 /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
 487 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)       /* Phy address
 488                                                                    << shift */
 489 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f      /* Phy address
 490                                                                    mask */
 491
 492 /* UCC GETH UESCR (Ethernet Statistics Control Register) */
 493 #define UESCR_AUTOZ                             0x8000  /* Automatically zero
 494                                                            addressed
 495                                                            statistical counter
 496                                                            values */
 497 #define UESCR_CLRCNT                            0x4000  /* Clear all statistics
 498                                                            counters */
 499 #define UESCR_MAXCOV_SHIFT                      (15 -  7)       /* Max
 500                                                                    Coalescing
 501                                                                    Value <<
 502                                                                    shift */
 503 #define UESCR_SCOV_SHIFT                        (15 - 15)       /* Status
 504                                                                    Coalescing
 505                                                                    Value <<
 506                                                                    shift */
 507
 508 /* UCC GETH UDSR (Data Synchronization Register) */
 509 #define UDSR_MAGIC                              0x067E
 510
 511 struct ucc_geth_thread_data_tx {
 512         u8 res0[104];
 513 } __attribute__ ((packed));
 514
 515 struct ucc_geth_thread_data_rx {
 516         u8 res0[40];
 517 } __attribute__ ((packed));
 518
 519 /* Send Queue Queue-Descriptor */
 520 struct ucc_geth_send_queue_qd {
 521         u32 bd_ring_base;       /* pointer to BD ring base address */
 522         u8 res0[0x8];
 523         u32 last_bd_completed_address;/* initialize to last entry in BD ring */
 524         u8 res1[0x30];
 525 } __attribute__ ((packed));
 526
 527 struct ucc_geth_send_queue_mem_region {
 528         struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
 529 } __attribute__ ((packed));
 530
 531 struct ucc_geth_thread_tx_pram {
 532         u8 res0[64];
 533 } __attribute__ ((packed));
 534
 535 struct ucc_geth_thread_rx_pram {
 536         u8 res0[128];
 537 } __attribute__ ((packed));
 538
 539 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64
 540 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64
 541 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96
 542
 543 struct ucc_geth_scheduler {
 544         u16 cpucount0;          /* CPU packet counter */
 545         u16 cpucount1;          /* CPU packet counter */
 546         u16 cecount0;           /* QE packet counter */
 547         u16 cecount1;           /* QE packet counter */
 548         u16 cpucount2;          /* CPU packet counter */
 549         u16 cpucount3;          /* CPU packet counter */
 550         u16 cecount2;           /* QE packet counter */
 551         u16 cecount3;           /* QE packet counter */
 552         u16 cpucount4;          /* CPU packet counter */
 553         u16 cpucount5;          /* CPU packet counter */
 554         u16 cecount4;           /* QE packet counter */
 555         u16 cecount5;           /* QE packet counter */
 556         u16 cpucount6;          /* CPU packet counter */
 557         u16 cpucount7;          /* CPU packet counter */
 558         u16 cecount6;           /* QE packet counter */
 559         u16 cecount7;           /* QE packet counter */
 560         u32 weightstatus[NUM_TX_QUEUES];        /* accumulated weight factor */
 561         u32 rtsrshadow;         /* temporary variable handled by QE */
 562         u32 time;               /* temporary variable handled by QE */
 563         u32 ttl;                /* temporary variable handled by QE */
 564         u32 mblinterval;        /* max burst length interval */
 565         u16 nortsrbytetime;     /* normalized value of byte time in tsr units */
 566         u8 fracsiz;             /* radix 2 log value of denom. of
 567                                    NorTSRByteTime */
 568         u8 res0[1];
 569         u8 strictpriorityq;     /* Strict Priority Mask register */
 570         u8 txasap;              /* Transmit ASAP register */
 571         u8 extrabw;             /* Extra BandWidth register */
 572         u8 oldwfqmask;          /* temporary variable handled by QE */
 573         u8 weightfactor[NUM_TX_QUEUES];
 574                                       /**< weight factor for queues   */
 575         u32 minw;               /* temporary variable handled by QE */
 576         u8 res1[0x70 - 0x64];
 577 } __attribute__ ((packed));
 578
 579 struct ucc_geth_tx_firmware_statistics_pram {
 580         u32 sicoltx;            /* single collision */
 581         u32 mulcoltx;           /* multiple collision */
 582         u32 latecoltxfr;        /* late collision */
 583         u32 frabortduecol;      /* frames aborted due to transmit collision */
 584         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 585                                    transmission that are not counted on any
 586                                    other counter */
 587         u32 carriersenseertx;   /* carrier sense error */
 588         u32 frtxok;             /* frames transmitted OK */
 589         u32 txfrexcessivedefer; /* frames with defferal time greater than
 590                                    specified threshold */
 591         u32 txpkts256;          /* total packets (including bad) between 256
 592                                    and 511 octets */
 593         u32 txpkts512;          /* total packets (including bad) between 512
 594                                    and 1023 octets */
 595         u32 txpkts1024;         /* total packets (including bad) between 1024
 596                                    and 1518 octets */
 597         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 598                                    and MAXLength octets */
 599 } __attribute__ ((packed));
 600
 601 struct ucc_geth_rx_firmware_statistics_pram {
 602         u32 frrxfcser;          /* frames with crc error */
 603         u32 fraligner;          /* frames with alignment error */
 604         u32 inrangelenrxer;     /* in range length error */
 605         u32 outrangelenrxer;    /* out of range length error */
 606         u32 frtoolong;          /* frame too long */
 607         u32 runt;               /* runt */
 608         u32 verylongevent;      /* very long event */
 609         u32 symbolerror;        /* symbol error */
 610         u32 dropbsy;            /* drop because of BD not ready */
 611         u8 res0[0x8];
 612         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 613                                    or type mismatch) */
 614         u32 underpkts;          /* total frames less than 64 octets */
 615         u32 pkts256;            /* total frames (including bad) between 256 and
 616                                    511 octets */
 617         u32 pkts512;            /* total frames (including bad) between 512 and
 618                                    1023 octets */
 619         u32 pkts1024;           /* total frames (including bad) between 1024
 620                                    and 1518 octets */
 621         u32 pktsjumbo;          /* total frames (including bad) between 1024
 622                                    and MAXLength octets */
 623         u32 frlossinmacer;      /* frames lost because of internal MAC error
 624                                    that is not counted in any other counter */
 625         u32 pausefr;            /* pause frames */
 626         u8 res1[0x4];
 627         u32 removevlan;         /* total frames that had their VLAN tag removed
 628                                  */
 629         u32 replacevlan;        /* total frames that had their VLAN tag
 630                                    replaced */
 631         u32 insertvlan;         /* total frames that had their VLAN tag
 632                                    inserted */
 633 } __attribute__ ((packed));
 634
 635 struct ucc_geth_rx_interrupt_coalescing_entry {
 636         u32 interruptcoalescingmaxvalue;        /* interrupt coalescing max
 637                                                    value */
 638         u32 interruptcoalescingcounter; /* interrupt coalescing counter,
 639                                            initialize to
 640                                            interruptcoalescingmaxvalue */
 641 } __attribute__ ((packed));
 642
 643 struct ucc_geth_rx_interrupt_coalescing_table {
 644         struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
 645                                        /**< interrupt coalescing entry */
 646 } __attribute__ ((packed));
 647
 648 struct ucc_geth_rx_prefetched_bds {
 649         struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS];     /* prefetched bd */
 650 } __attribute__ ((packed));
 651
 652 struct ucc_geth_rx_bd_queues_entry {
 653         u32 bdbaseptr;          /* BD base pointer */
 654         u32 bdptr;              /* BD pointer */
 655         u32 externalbdbaseptr;  /* external BD base pointer */
 656         u32 externalbdptr;      /* external BD pointer */
 657 } __attribute__ ((packed));
 658
 659 struct ucc_geth_tx_global_pram {
 660         u16 temoder;
 661         u8 res0[0x38 - 0x02];
 662         u32 sqptr;              /* a base pointer to send queue memory region */
 663         u32 schedulerbasepointer;       /* a base pointer to scheduler memory
 664                                            region */
 665         u32 txrmonbaseptr;      /* base pointer to Tx RMON statistics counter */
 666         u32 tstate;             /* tx internal state. High byte contains
 667                                    function code */
 668         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
 669         u32 vtagtable[0x8];     /* 8 4-byte VLAN tags */
 670         u32 tqptr;              /* a base pointer to the Tx Queues Memory
 671                                    Region */
 672         u8 res2[0x80 - 0x74];
 673 } __attribute__ ((packed));
 674
 675 /* structure representing Extended Filtering Global Parameters in PRAM */
 676 struct ucc_geth_exf_global_pram {
 677         u32 l2pcdptr;           /* individual address filter, high */
 678         u8 res0[0x10 - 0x04];
 679 } __attribute__ ((packed));
 680
 681 struct ucc_geth_rx_global_pram {
 682         u32 remoder;            /* ethernet mode reg. */
 683         u32 rqptr;              /* base pointer to the Rx Queues Memory Region*/
 684         u32 res0[0x1];
 685         u8 res1[0x20 - 0xC];
 686         u16 typeorlen;          /* cutoff point less than which, type/len field
 687                                    is considered length */
 688         u8 res2[0x1];
 689         u8 rxgstpack;           /* acknowledgement on GRACEFUL STOP RX command*/
 690         u32 rxrmonbaseptr;      /* base pointer to Rx RMON statistics counter */
 691         u8 res3[0x30 - 0x28];
 692         u32 intcoalescingptr;   /* Interrupt coalescing table pointer */
 693         u8 res4[0x36 - 0x34];
 694         u8 rstate;              /* rx internal state. High byte contains
 695                                    function code */
 696         u8 res5[0x46 - 0x37];
 697         u16 mrblr;              /* max receive buffer length reg. */
 698         u32 rbdqptr;            /* base pointer to RxBD parameter table
 699                                    description */
 700         u16 mflr;               /* max frame length reg. */
 701         u16 minflr;             /* min frame length reg. */
 702         u16 maxd1;              /* max dma1 length reg. */
 703         u16 maxd2;              /* max dma2 length reg. */
 704         u32 ecamptr;            /* external CAM address */
 705         u32 l2qt;               /* VLAN priority mapping table. */
 706         u32 l3qt[0x8];          /* IP priority mapping table. */
 707         u16 vlantype;           /* vlan type */
 708         u16 vlantci;            /* default vlan tci */
 709         u8 addressfiltering[64];        /* address filtering data structure */
 710         u32 exfGlobalParam;     /* base address for extended filtering global
 711                                    parameters */
 712         u8 res6[0x100 - 0xC4];  /* Initialize to zero */
 713 } __attribute__ ((packed));
 714
 715 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 716
 717 /* structure representing InitEnet command */
 718 struct ucc_geth_init_pram {
 719         u8 resinit1;
 720         u8 resinit2;
 721         u8 resinit3;
 722         u8 resinit4;
 723         u16 resinit5;
 724         u8 res1[0x1];
 725         u8 largestexternallookupkeysize;
 726         u32 rgftgfrxglobal;
 727         u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX];   /* rx threads */
 728         u8 res2[0x38 - 0x30];
 729         u32 txglobal;           /* tx global */
 730         u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];   /* tx threads */
 731         u8 res3[0x1];
 732 } __attribute__ ((packed));
 733
 734 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
 735 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
 736
 737 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
 738 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
 739 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
 740 #define ENET_INIT_PARAM_SNUM_SHIFT              24
 741
 742 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x06
 743 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0x30
 744 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0xff
 745 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x00
 746 #define ENET_INIT_PARAM_MAGIC_RES_INIT5         0x0400
 747
 748 /* structure representing 82xx Address Filtering Enet Address in PRAM */
 749 struct ucc_geth_82xx_enet_address {
 750         u8 res1[0x2];
 751         u16 h;                  /* address (MSB) */
 752         u16 m;                  /* address */
 753         u16 l;                  /* address (LSB) */
 754 } __attribute__ ((packed));
 755
 756 /* structure representing 82xx Address Filtering PRAM */
 757 struct ucc_geth_82xx_address_filtering_pram {
 758         u32 iaddr_h;            /* individual address filter, high */
 759         u32 iaddr_l;            /* individual address filter, low */
 760         u32 gaddr_h;            /* group address filter, high */
 761         u32 gaddr_l;            /* group address filter, low */
 762         struct ucc_geth_82xx_enet_address taddr;
 763         struct ucc_geth_82xx_enet_address paddr[NUM_OF_PADDRS];
 764         u8 res0[0x40 - 0x38];
 765 } __attribute__ ((packed));
 766
 767 /* GETH Tx firmware statistics structure, used when calling
 768    UCC_GETH_GetStatistics. */
 769 struct ucc_geth_tx_firmware_statistics {
 770         u32 sicoltx;            /* single collision */
 771         u32 mulcoltx;           /* multiple collision */
 772         u32 latecoltxfr;        /* late collision */
 773         u32 frabortduecol;      /* frames aborted due to transmit collision */
 774         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 775                                    transmission that are not counted on any
 776                                    other counter */
 777         u32 carriersenseertx;   /* carrier sense error */
 778         u32 frtxok;             /* frames transmitted OK */
 779         u32 txfrexcessivedefer; /* frames with defferal time greater than
 780                                    specified threshold */
 781         u32 txpkts256;          /* total packets (including bad) between 256
 782                                    and 511 octets */
 783         u32 txpkts512;          /* total packets (including bad) between 512
 784                                    and 1023 octets */
 785         u32 txpkts1024;         /* total packets (including bad) between 1024
 786                                    and 1518 octets */
 787         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 788                                    and MAXLength octets */
 789 } __attribute__ ((packed));
 790
 791 /* GETH Rx firmware statistics structure, used when calling
 792    UCC_GETH_GetStatistics. */
 793 struct ucc_geth_rx_firmware_statistics {
 794         u32 frrxfcser;          /* frames with crc error */
 795         u32 fraligner;          /* frames with alignment error */
 796         u32 inrangelenrxer;     /* in range length error */
 797         u32 outrangelenrxer;    /* out of range length error */
 798         u32 frtoolong;          /* frame too long */
 799         u32 runt;               /* runt */
 800         u32 verylongevent;      /* very long event */
 801         u32 symbolerror;        /* symbol error */
 802         u32 dropbsy;            /* drop because of BD not ready */
 803         u8 res0[0x8];
 804         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 805                                    or type mismatch) */
 806         u32 underpkts;          /* total frames less than 64 octets */
 807         u32 pkts256;            /* total frames (including bad) between 256 and
 808                                    511 octets */
 809         u32 pkts512;            /* total frames (including bad) between 512 and
 810                                    1023 octets */
 811         u32 pkts1024;           /* total frames (including bad) between 1024
 812                                    and 1518 octets */
 813         u32 pktsjumbo;          /* total frames (including bad) between 1024
 814                                    and MAXLength octets */
 815         u32 frlossinmacer;      /* frames lost because of internal MAC error
 816                                    that is not counted in any other counter */
 817         u32 pausefr;            /* pause frames */
 818         u8 res1[0x4];
 819         u32 removevlan;         /* total frames that had their VLAN tag removed
 820                                  */
 821         u32 replacevlan;        /* total frames that had their VLAN tag
 822                                    replaced */
 823         u32 insertvlan;         /* total frames that had their VLAN tag
 824                                    inserted */
 825 } __attribute__ ((packed));
 826
 827 /* GETH hardware statistics structure, used when calling
 828    UCC_GETH_GetStatistics. */
 829 struct ucc_geth_hardware_statistics {
 830         u32 tx64;               /* Total number of frames (including bad
 831                                    frames) transmitted that were exactly of the
 832                                    minimal length (64 for un tagged, 68 for
 833                                    tagged, or with length exactly equal to the
 834                                    parameter MINLength */
 835         u32 tx127;              /* Total number of frames (including bad
 836                                    frames) transmitted that were between
 837                                    MINLength (Including FCS length==4) and 127
 838                                    octets */
 839         u32 tx255;              /* Total number of frames (including bad
 840                                    frames) transmitted that were between 128
 841                                    (Including FCS length==4) and 255 octets */
 842         u32 rx64;               /* Total number of frames received including
 843                                    bad frames that were exactly of the mninimal
 844                                    length (64 bytes) */
 845         u32 rx127;              /* Total number of frames (including bad
 846                                    frames) received that were between MINLength
 847                                    (Including FCS length==4) and 127 octets */
 848         u32 rx255;              /* Total number of frames (including bad
 849                                    frames) received that were between 128
 850                                    (Including FCS length==4) and 255 octets */
 851         u32 txok;               /* Total number of octets residing in frames
 852                                    that where involved in succesfull
 853                                    transmission */
 854         u16 txcf;               /* Total number of PAUSE control frames
 855                                    transmitted by this MAC */
 856         u32 tmca;               /* Total number of frames that were transmitted
 857                                    succesfully with the group address bit set
 858                                    that are not broadcast frames */
 859         u32 tbca;               /* Total number of frames transmitted
 860                                    succesfully that had destination address
 861                                    field equal to the broadcast address */
 862         u32 rxfok;              /* Total number of frames received OK */
 863         u32 rxbok;              /* Total number of octets received OK */
 864         u32 rbyt;               /* Total number of octets received including
 865                                    octets in bad frames. Must be implemented in
 866                                    HW because it includes octets in frames that
 867                                    never even reach the UCC */
 868         u32 rmca;               /* Total number of frames that were received
 869                                    succesfully with the group address bit set
 870                                    that are not broadcast frames */
 871         u32 rbca;               /* Total number of frames received succesfully
 872                                    that had destination address equal to the
 873                                    broadcast address */
 874 } __attribute__ ((packed));
 875
 876 /* UCC GETH Tx errors returned via TxConf callback */
 877 #define TX_ERRORS_DEF      0x0200
 878 #define TX_ERRORS_EXDEF    0x0100
 879 #define TX_ERRORS_LC       0x0080
 880 #define TX_ERRORS_RL       0x0040
 881 #define TX_ERRORS_RC_MASK  0x003C
 882 #define TX_ERRORS_RC_SHIFT 2
 883 #define TX_ERRORS_UN       0x0002
 884 #define TX_ERRORS_CSL      0x0001
 885
 886 /* UCC GETH Rx errors returned via RxStore callback */
 887 #define RX_ERRORS_CMR      0x0200
 888 #define RX_ERRORS_M        0x0100
 889 #define RX_ERRORS_BC       0x0080
 890 #define RX_ERRORS_MC       0x0040
 891
 892 /* Transmit BD. These are in addition to values defined in uccf. */
 893 #define T_VID      0x003c0000   /* insert VLAN id index mask. */
 894 #define T_DEF      (((u32) TX_ERRORS_DEF     ) << 16)
 895 #define T_EXDEF    (((u32) TX_ERRORS_EXDEF   ) << 16)
 896 #define T_LC       (((u32) TX_ERRORS_LC      ) << 16)
 897 #define T_RL       (((u32) TX_ERRORS_RL      ) << 16)
 898 #define T_RC_MASK  (((u32) TX_ERRORS_RC_MASK ) << 16)
 899 #define T_UN       (((u32) TX_ERRORS_UN      ) << 16)
 900 #define T_CSL      (((u32) TX_ERRORS_CSL     ) << 16)
 901 #define T_ERRORS_REPORT  (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
 902                 | T_UN | T_CSL) /* transmit errors to report */
 903
 904 /* Receive BD. These are in addition to values defined in uccf. */
 905 #define R_LG    0x00200000      /* Frame length violation.  */
 906 #define R_NO    0x00100000      /* Non-octet aligned frame.  */
 907 #define R_SH    0x00080000      /* Short frame.  */
 908 #define R_CR    0x00040000      /* CRC error.  */
 909 #define R_OV    0x00020000      /* Overrun.  */
 910 #define R_IPCH  0x00010000      /* IP checksum check failed. */
 911 #define R_CMR   (((u32) RX_ERRORS_CMR  ) << 16)
 912 #define R_M     (((u32) RX_ERRORS_M    ) << 16)
 913 #define R_BC    (((u32) RX_ERRORS_BC   ) << 16)
 914 #define R_MC    (((u32) RX_ERRORS_MC   ) << 16)
 915 #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC)     /* receive errors to
 916                                                            report */
 917 #define R_ERRORS_FATAL  (R_LG  | R_NO | R_SH | R_CR | \
 918                 R_OV | R_IPCH)  /* receive errors to discard */
 919
 920 /* Alignments */
 921 #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT       256
 922 #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT       128
 923 #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT       128
 924 #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT       64
 925 #define UCC_GETH_THREAD_DATA_ALIGNMENT          256     /* spec gives values
 926                                                            based on num of
 927                                                            threads, but always
 928                                                            using the maximum is
 929                                                            easier */
 930 #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT  32
 931 #define UCC_GETH_SCHEDULER_ALIGNMENT            4       /* This is a guess */
 932 #define UCC_GETH_TX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 933 #define UCC_GETH_RX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 934 #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT      4       /* This is a
 935                                                                    guess */
 936 #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT         8       /* This is a guess */
 937 #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT    128     /* This is a guess */
 938 #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4    /* This
 939                                                                            is a
 940                                                                            guess
 941                                                                          */
 942 #define UCC_GETH_RX_BD_RING_ALIGNMENT           32
 943 #define UCC_GETH_TX_BD_RING_ALIGNMENT           32
 944 #define UCC_GETH_MRBLR_ALIGNMENT                128
 945 #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT      4
 946 #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT       32
 947 #define UCC_GETH_RX_DATA_BUF_ALIGNMENT          64
 948
 949 #define UCC_GETH_TAD_EF                         0x80
 950 #define UCC_GETH_TAD_V                          0x40
 951 #define UCC_GETH_TAD_REJ                        0x20
 952 #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT        2
 953 #define UCC_GETH_TAD_VTAG_OP_SHIFT              6
 954 #define UCC_GETH_TAD_V_NON_VTAG_OP              0x20
 955 #define UCC_GETH_TAD_RQOS_SHIFT                 0
 956 #define UCC_GETH_TAD_V_PRIORITY_SHIFT           5
 957 #define UCC_GETH_TAD_CFI                        0x10
 958
 959 #define UCC_GETH_VLAN_PRIORITY_MAX              8
 960 #define UCC_GETH_IP_PRIORITY_MAX                64
 961 #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX        8
 962 #define UCC_GETH_RX_BD_RING_SIZE_MIN            8
 963 #define UCC_GETH_TX_BD_RING_SIZE_MIN            2
 964
 965 #define UCC_GETH_SIZE_OF_BD                     QE_SIZEOF_BD
 966
 967 /* Driver definitions */
 968 #define TX_BD_RING_LEN                          0x10
 969 #define RX_BD_RING_LEN                          0x10
 970 #define UCC_GETH_DEV_WEIGHT                     TX_BD_RING_LEN
 971
 972 #define TX_RING_MOD_MASK(size)                  (size-1)
 973 #define RX_RING_MOD_MASK(size)                  (size-1)
 974
 975 #define ENET_NUM_OCTETS_PER_ADDRESS             6
 976 #define ENET_GROUP_ADDR                         0x01    /* Group address mask
 977                                                            for ethernet
 978                                                            addresses */
 979
 980 #define TX_TIMEOUT                              (1*HZ)
 981 #define SKB_ALLOC_TIMEOUT                       100000
 982 #define PHY_INIT_TIMEOUT                        100000
 983 #define PHY_CHANGE_TIME                         2
 984
 985 /* Fast Ethernet (10/100 Mbps) */
 986 #define UCC_GETH_URFS_INIT                      512     /* Rx virtual FIFO size
 987                                                          */
 988 #define UCC_GETH_URFET_INIT                     256     /* 1/2 urfs */
 989 #define UCC_GETH_URFSET_INIT                    384     /* 3/4 urfs */
 990 #define UCC_GETH_UTFS_INIT                      512     /* Tx virtual FIFO size
 991                                                          */
 992 #define UCC_GETH_UTFET_INIT                     256     /* 1/2 utfs */
 993 #define UCC_GETH_UTFTT_INIT                     128
 994 /* Gigabit Ethernet (1000 Mbps) */
 995 #define UCC_GETH_URFS_GIGA_INIT                 4096/*2048*/    /* Rx virtual
 996                                                                    FIFO size */
 997 #define UCC_GETH_URFET_GIGA_INIT                2048/*1024*/    /* 1/2 urfs */
 998 #define UCC_GETH_URFSET_GIGA_INIT               3072/*1536*/    /* 3/4 urfs */
 999 #define UCC_GETH_UTFS_GIGA_INIT                 8192/*2048*/    /* Tx virtual
1000                                                                    FIFO size */
1001 #define UCC_GETH_UTFET_GIGA_INIT                4096/*1024*/    /* 1/2 utfs */
1002 #define UCC_GETH_UTFTT_GIGA_INIT                0x400/*0x40*/   /* */
1003
1004 #define UCC_GETH_REMODER_INIT                   0       /* bits that must be
1005                                                            set */
1006 #define UCC_GETH_TEMODER_INIT                   0xC000  /* bits that must */
1007 #define UCC_GETH_UPSMR_INIT                     (UPSMR_RES1)    /* Start value
1008                                                                    for this
1009                                                                    register */
1010 #define UCC_GETH_MACCFG1_INIT                   0
1011 #define UCC_GETH_MACCFG2_INIT                   (MACCFG2_RESERVED_1)
1012 #define UCC_GETH_MIIMCFG_MNGMNT_CLC_DIV_INIT    \
1013                                 (MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112)
1014
1015 /* Ethernet speed */
1016 enum enet_speed {
1017         ENET_SPEED_10BT,        /* 10 Base T */
1018         ENET_SPEED_100BT,       /* 100 Base T */
1019         ENET_SPEED_1000BT       /* 1000 Base T */
1020 };
1021
1022 /* Ethernet Address Type. */
1023 enum enet_addr_type {
1024         ENET_ADDR_TYPE_INDIVIDUAL,
1025         ENET_ADDR_TYPE_GROUP,
1026         ENET_ADDR_TYPE_BROADCAST
1027 };
1028
1029 /* TBI / MII Set Register */
1030 enum enet_tbi_mii_reg {
1031         ENET_TBI_MII_CR = 0x00, /* Control (CR ) */
1032         ENET_TBI_MII_SR = 0x01, /* Status (SR ) */
1033         ENET_TBI_MII_ANA = 0x04,        /* AN advertisement (ANA ) */
1034         ENET_TBI_MII_ANLPBPA = 0x05,    /* AN link partner base page ability
1035                                            (ANLPBPA) */
1036         ENET_TBI_MII_ANEX = 0x06,       /* AN expansion (ANEX ) */
1037         ENET_TBI_MII_ANNPT = 0x07,      /* AN next page transmit (ANNPT ) */
1038         ENET_TBI_MII_ANLPANP = 0x08,    /* AN link partner ability next page
1039                                            (ANLPANP) */
1040         ENET_TBI_MII_EXST = 0x0F,       /* Extended status (EXST ) */
1041         ENET_TBI_MII_JD = 0x10, /* Jitter diagnostics (JD ) */
1042         ENET_TBI_MII_TBICON = 0x11      /* TBI control (TBICON ) */
1043 };
1044
1045 /* UCC GETH 82xx Ethernet Address Recognition Location */
1046 enum ucc_geth_enet_address_recognition_location {
1047         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
1048                                                                       address */
1049         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
1050                                                                    station
1051                                                                    address
1052                                                                    paddr1 */
1053         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2,      /* additional
1054                                                                    station
1055                                                                    address
1056                                                                    paddr2 */
1057         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3,      /* additional
1058                                                                    station
1059                                                                    address
1060                                                                    paddr3 */
1061         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST,  /* additional
1062                                                                    station
1063                                                                    address
1064                                                                    paddr4 */
1065         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,  /* group hash */
1066         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
1067                                                                       hash */
1068 };
1069
1070 /* UCC GETH vlan operation tagged */
1071 enum ucc_geth_vlan_operation_tagged {
1072         UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,       /* Tagged - nop */
1073         UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
1074                 = 0x1,  /* Tagged - replace vid portion of q tag */
1075         UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
1076                 = 0x2,  /* Tagged - if vid0 replace vid with default value  */
1077         UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
1078                 = 0x3   /* Tagged - extract q tag from frame */
1079 };
1080
1081 /* UCC GETH vlan operation non-tagged */
1082 enum ucc_geth_vlan_operation_non_tagged {
1083         UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,   /* Non tagged - nop */
1084         UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1   /* Non tagged -
1085                                                                    q tag insert
1086                                                                  */
1087 };
1088
1089 /* UCC GETH Rx Quality of Service Mode */
1090 enum ucc_geth_qos_mode {
1091         UCC_GETH_QOS_MODE_DEFAULT = 0x0,        /* default queue */
1092         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1,     /* queue
1093                                                                    determined
1094                                                                    by L2
1095                                                                    criteria */
1096         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2      /* queue
1097                                                                    determined
1098                                                                    by L3
1099                                                                    criteria */
1100 };
1101
1102 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
1103    for combined functionality */
1104 enum ucc_geth_statistics_gathering_mode {
1105         UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,   /* No
1106                                                                    statistics
1107                                                                    gathering */
1108         UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
1109                                                                     hardware
1110                                                                     statistics
1111                                                                     gathering
1112                                                                   */
1113         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
1114                                                                       firmware
1115                                                                       tx
1116                                                                       statistics
1117                                                                       gathering
1118                                                                      */
1119         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
1120                                                                       firmware
1121                                                                       rx
1122                                                                       statistics
1123                                                                       gathering
1124                                                                     */
1125 };
1126
1127 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
1128 enum ucc_geth_maccfg2_pad_and_crc_mode {
1129         UCC_GETH_PAD_AND_CRC_MODE_NONE
1130                 = MACCFG2_PAD_AND_CRC_MODE_NONE,        /* Neither Padding
1131                                                            short frames
1132                                                            nor CRC */
1133         UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
1134                 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY,    /* Append
1135                                                            CRC only */
1136         UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
1137             MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1138 };
1139
1140 /* UCC GETH upsmr Flow Control Mode */
1141 enum ucc_geth_flow_control_mode {
1142         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,    /* No automatic
1143                                                                    flow control
1144                                                                  */
1145         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1146                 = 0x00004000    /* Send pause frame when RxFIFO reaches its
1147                                    emergency threshold */
1148 };
1149
1150 /* UCC GETH number of threads */
1151 enum ucc_geth_num_of_threads {
1152         UCC_GETH_NUM_OF_THREADS_1 = 0x1,        /* 1 */
1153         UCC_GETH_NUM_OF_THREADS_2 = 0x2,        /* 2 */
1154         UCC_GETH_NUM_OF_THREADS_4 = 0x0,        /* 4 */
1155         UCC_GETH_NUM_OF_THREADS_6 = 0x3,        /* 6 */
1156         UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1157 };
1158
1159 /* UCC GETH number of station addresses */
1160 enum ucc_geth_num_of_station_addresses {
1161         UCC_GETH_NUM_OF_STATION_ADDRESSES_1,    /* 1 */
1162         UCC_GETH_NUM_OF_STATION_ADDRESSES_5     /* 5 */
1163 };
1164
1165 /* UCC GETH 82xx Ethernet Address Container */
1166 struct enet_addr_container {
1167         u8 address[ENET_NUM_OCTETS_PER_ADDRESS];        /* ethernet address */
1168         enum ucc_geth_enet_address_recognition_location location;       /* location in
1169                                                                    82xx address
1170                                                                    recognition
1171                                                                    hardware */
1172         struct list_head node;
1173 };
1174
1175 #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1176
1177 /* UCC GETH Termination Action Descriptor (TAD) structure. */
1178 struct ucc_geth_tad_params {
1179         int rx_non_dynamic_extended_features_mode;
1180         int reject_frame;
1181         enum ucc_geth_vlan_operation_tagged vtag_op;
1182         enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1183         enum ucc_geth_qos_mode rqos;
1184         u8 vpri;
1185         u16 vid;
1186 };
1187
1188 /* GETH protocol initialization structure */
1189 struct ucc_geth_info {
1190         struct ucc_fast_info uf_info;
1191         u8 numQueuesTx;
1192         u8 numQueuesRx;
1193         int ipCheckSumCheck;
1194         int ipCheckSumGenerate;
1195         int rxExtendedFiltering;
1196         u32 extendedFilteringChainPointer;
1197         u16 typeorlen;
1198         int dynamicMaxFrameLength;
1199         int dynamicMinFrameLength;
1200         u8 nonBackToBackIfgPart1;
1201         u8 nonBackToBackIfgPart2;
1202         u8 miminumInterFrameGapEnforcement;
1203         u8 backToBackInterFrameGap;
1204         int ipAddressAlignment;
1205         int lengthCheckRx;
1206         u32 mblinterval;
1207         u16 nortsrbytetime;
1208         u8 fracsiz;
1209         u8 strictpriorityq;
1210         u8 txasap;
1211         u8 extrabw;
1212         int miiPreambleSupress;
1213         u8 altBebTruncation;
1214         int altBeb;
1215         int backPressureNoBackoff;
1216         int noBackoff;
1217         int excessDefer;
1218         u8 maxRetransmission;
1219         u8 collisionWindow;
1220         int pro;
1221         int cap;
1222         int rsh;
1223         int rlpb;
1224         int cam;
1225         int bro;
1226         int ecm;
1227         int receiveFlowControl;
1228         u8 maxGroupAddrInHash;
1229         u8 maxIndAddrInHash;
1230         u8 prel;
1231         u16 maxFrameLength;
1232         u16 minFrameLength;
1233         u16 maxD1Length;
1234         u16 maxD2Length;
1235         u16 vlantype;
1236         u16 vlantci;
1237         u32 ecamptr;
1238         u32 eventRegMask;
1239         u16 pausePeriod;
1240         u16 extensionField;
1241         u8 phy_address;
1242         u32 board_flags;
1243         u32 phy_interrupt;
1244         u8 weightfactor[NUM_TX_QUEUES];
1245         u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1246         u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1247         u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1248         u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1249         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1250         u16 bdRingLenTx[NUM_TX_QUEUES];
1251         u16 bdRingLenRx[NUM_RX_QUEUES];
1252         enum enet_interface enet_interface;
1253         enum ucc_geth_num_of_station_addresses numStationAddresses;
1254         enum qe_fltr_largest_external_tbl_lookup_key_size
1255             largestexternallookupkeysize;
1256         enum ucc_geth_statistics_gathering_mode statisticsMode;
1257         enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1258         enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1259         enum ucc_geth_qos_mode rxQoSMode;
1260         enum ucc_geth_flow_control_mode aufc;
1261         enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1262         enum ucc_geth_num_of_threads numThreadsTx;
1263         enum ucc_geth_num_of_threads numThreadsRx;
1264         enum qe_risc_allocation riscTx;
1265         enum qe_risc_allocation riscRx;
1266 };
1267
1268 /* structure representing UCC GETH */
1269 struct ucc_geth_private {
1270         struct ucc_geth_info *ug_info;
1271         struct ucc_fast_private *uccf;
1272         struct net_device *dev;
1273         struct net_device_stats stats;  /* linux network statistics */
1274         struct ucc_geth *ug_regs;
1275         struct ucc_geth_init_pram *p_init_enet_param_shadow;
1276         struct ucc_geth_exf_global_pram *p_exf_glbl_param;
1277         u32 exf_glbl_param_offset;
1278         struct ucc_geth_rx_global_pram *p_rx_glbl_pram;
1279         u32 rx_glbl_pram_offset;
1280         struct ucc_geth_tx_global_pram *p_tx_glbl_pram;
1281         u32 tx_glbl_pram_offset;
1282         struct ucc_geth_send_queue_mem_region *p_send_q_mem_reg;
1283         u32 send_q_mem_reg_offset;
1284         struct ucc_geth_thread_data_tx *p_thread_data_tx;
1285         u32 thread_dat_tx_offset;
1286         struct ucc_geth_thread_data_rx *p_thread_data_rx;
1287         u32 thread_dat_rx_offset;
1288         struct ucc_geth_scheduler *p_scheduler;
1289         u32 scheduler_offset;
1290         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
1291         u32 tx_fw_statistics_pram_offset;
1292         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
1293         u32 rx_fw_statistics_pram_offset;
1294         struct ucc_geth_rx_interrupt_coalescing_table *p_rx_irq_coalescing_tbl;
1295         u32 rx_irq_coalescing_tbl_offset;
1296         struct ucc_geth_rx_bd_queues_entry *p_rx_bd_qs_tbl;
1297         u32 rx_bd_qs_tbl_offset;
1298         u8 *p_tx_bd_ring[NUM_TX_QUEUES];
1299         u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1300         u8 *p_rx_bd_ring[NUM_RX_QUEUES];
1301         u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1302         u8 *confBd[NUM_TX_QUEUES];
1303         u8 *txBd[NUM_TX_QUEUES];
1304         u8 *rxBd[NUM_RX_QUEUES];
1305         int badFrame[NUM_RX_QUEUES];
1306         u16 cpucount[NUM_TX_QUEUES];
1307         volatile u16 *p_cpucount[NUM_TX_QUEUES];
1308         int indAddrRegUsed[NUM_OF_PADDRS];
1309         u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS];   /* ethernet address */
1310         u8 numGroupAddrInHash;
1311         u8 numIndAddrInHash;
1312         u8 numIndAddrInReg;
1313         int rx_extended_features;
1314         int rx_non_dynamic_extended_features;
1315         struct list_head conf_skbs;
1316         struct list_head group_hash_q;
1317         struct list_head ind_hash_q;
1318         u32 saved_uccm;
1319         spinlock_t lock;
1320         /* pointers to arrays of skbuffs for tx and rx */
1321         struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1322         struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1323         /* indices pointing to the next free sbk in skb arrays */
1324         u16 skb_curtx[NUM_TX_QUEUES];
1325         u16 skb_currx[NUM_RX_QUEUES];
1326         /* index of the first skb which hasn't been transmitted yet. */
1327         u16 skb_dirtytx[NUM_TX_QUEUES];
1328
1329         struct work_struct tq;
1330         struct timer_list phy_info_timer;
1331         struct ugeth_mii_info *mii_info;
1332         int oldspeed;
1333         int oldduplex;
1334         int oldlink;
1335 };
1336
1337 #endif                          /* __UCC_GETH_H__ */