git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2500pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2500pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2500pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 192         .owner  = THIS_MODULE,
 193         .csr    = {
 194                 .read           = rt2x00pci_register_read,
 195                 .write          = rt2x00pci_register_write,
 196                 .flags          = RT2X00DEBUGFS_OFFSET,
 197                 .word_base      = CSR_REG_BASE,
 198                 .word_size      = sizeof(u32),
 199                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 200         },
 201         .eeprom = {
 202                 .read           = rt2x00_eeprom_read,
 203                 .write          = rt2x00_eeprom_write,
 204                 .word_base      = EEPROM_BASE,
 205                 .word_size      = sizeof(u16),
 206                 .word_count     = EEPROM_SIZE / sizeof(u16),
 207         },
 208         .bbp    = {
 209                 .read           = rt2500pci_bbp_read,
 210                 .write          = rt2500pci_bbp_write,
 211                 .word_base      = BBP_BASE,
 212                 .word_size      = sizeof(u8),
 213                 .word_count     = BBP_SIZE / sizeof(u8),
 214         },
 215         .rf     = {
 216                 .read           = rt2x00_rf_read,
 217                 .write          = rt2500pci_rf_write,
 218                 .word_base      = RF_BASE,
 219                 .word_size      = sizeof(u32),
 220                 .word_count     = RF_SIZE / sizeof(u32),
 221         },
 222 };
 223 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 224
 225 #ifdef CONFIG_RT2X00_LIB_RFKILL
 226 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 227 {
 228         u32 reg;
 229
 230         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 231         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 232 }
 233 #else
 234 #define rt2500pci_rfkill_poll   NULL
 235 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 236
 237 #ifdef CONFIG_RT2X00_LIB_LEDS
 238 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 239                                      enum led_brightness brightness)
 240 {
 241         struct rt2x00_led *led =
 242             container_of(led_cdev, struct rt2x00_led, led_dev);
 243         unsigned int enabled = brightness != LED_OFF;
 244         u32 reg;
 245
 246         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 247
 248         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 249                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 250         else if (led->type == LED_TYPE_ACTIVITY)
 251                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 252
 253         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 254 }
 255
 256 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 257                                unsigned long *delay_on,
 258                                unsigned long *delay_off)
 259 {
 260         struct rt2x00_led *led =
 261             container_of(led_cdev, struct rt2x00_led, led_dev);
 262         u32 reg;
 263
 264         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 265         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 266         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 267         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 268
 269         return 0;
 270 }
 271
 272 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 273                                struct rt2x00_led *led,
 274                                enum led_type type)
 275 {
 276         led->rt2x00dev = rt2x00dev;
 277         led->type = type;
 278         led->led_dev.brightness_set = rt2500pci_brightness_set;
 279         led->led_dev.blink_set = rt2500pci_blink_set;
 280         led->flags = LED_INITIALIZED;
 281 }
 282 #endif /* CONFIG_RT2X00_LIB_LEDS */
 283
 284 /*
 285  * Configuration handlers.
 286  */
 287 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 288                                     const unsigned int filter_flags)
 289 {
 290         u32 reg;
 291
 292         /*
 293          * Start configuration steps.
 294          * Note that the version error will always be dropped
 295          * and broadcast frames will always be accepted since
 296          * there is no filter for it at this time.
 297          */
 298         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 299         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 300                            !(filter_flags & FIF_FCSFAIL));
 301         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 302                            !(filter_flags & FIF_PLCPFAIL));
 303         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 304                            !(filter_flags & FIF_CONTROL));
 305         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 306                            !(filter_flags & FIF_PROMISC_IN_BSS));
 307         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 308                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 309                            !rt2x00dev->intf_ap_count);
 310         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 311         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 312                            !(filter_flags & FIF_ALLMULTI));
 313         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 314         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 315 }
 316
 317 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 318                                   struct rt2x00_intf *intf,
 319                                   struct rt2x00intf_conf *conf,
 320                                   const unsigned int flags)
 321 {
 322         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
 323         unsigned int bcn_preload;
 324         u32 reg;
 325
 326         if (flags & CONFIG_UPDATE_TYPE) {
 327                 /*
 328                  * Enable beacon config
 329                  */
 330                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 331                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 332                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 333                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 334                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 335
 336                 /*
 337                  * Enable synchronisation.
 338                  */
 339                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 340                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 341                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 342                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 343                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 344         }
 345
 346         if (flags & CONFIG_UPDATE_MAC)
 347                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 348                                               conf->mac, sizeof(conf->mac));
 349
 350         if (flags & CONFIG_UPDATE_BSSID)
 351                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 352                                               conf->bssid, sizeof(conf->bssid));
 353 }
 354
 355 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 356                                  struct rt2x00lib_erp *erp)
 357 {
 358         int preamble_mask;
 359         u32 reg;
 360
 361         /*
 362          * When short preamble is enabled, we should set bit 0x08
 363          */
 364         preamble_mask = erp->short_preamble << 3;
 365
 366         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 367         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 368                            erp->ack_timeout);
 369         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 370                            erp->ack_consume_time);
 371         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 372
 373         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 374         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 375         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 376         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 377         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 378
 379         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 380         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 381         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 382         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 383         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 384
 385         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 386         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 387         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 388         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 389         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 390
 391         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 392         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 393         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 394         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 395         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 396
 397         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 398
 399         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 400         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 401         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 402
 403         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 404         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 405         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 406         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 407
 408         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 409         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 410         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 411         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 412 }
 413
 414 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 415                                  struct antenna_setup *ant)
 416 {
 417         u32 reg;
 418         u8 r14;
 419         u8 r2;
 420
 421         /*
 422          * We should never come here because rt2x00lib is supposed
 423          * to catch this and send us the correct antenna explicitely.
 424          */
 425         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 426                ant->tx == ANTENNA_SW_DIVERSITY);
 427
 428         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 429         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 430         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 431
 432         /*
 433          * Configure the TX antenna.
 434          */
 435         switch (ant->tx) {
 436         case ANTENNA_A:
 437                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 438                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 439                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 440                 break;
 441         case ANTENNA_B:
 442         default:
 443                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 444                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 445                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 446                 break;
 447         }
 448
 449         /*
 450          * Configure the RX antenna.
 451          */
 452         switch (ant->rx) {
 453         case ANTENNA_A:
 454                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 455                 break;
 456         case ANTENNA_B:
 457         default:
 458                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 459                 break;
 460         }
 461
 462         /*
 463          * RT2525E and RT5222 need to flip TX I/Q
 464          */
 465         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 466             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 467                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 468                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 469                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 470
 471                 /*
 472                  * RT2525E does not need RX I/Q Flip.
 473                  */
 474                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 475                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 476         } else {
 477                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 478                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 479         }
 480
 481         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 482         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 483         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 484 }
 485
 486 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 487                                      struct rf_channel *rf, const int txpower)
 488 {
 489         u8 r70;
 490
 491         /*
 492          * Set TXpower.
 493          */
 494         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 495
 496         /*
 497          * Switch on tuning bits.
 498          * For RT2523 devices we do not need to update the R1 register.
 499          */
 500         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 501                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 502         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 503
 504         /*
 505          * For RT2525 we should first set the channel to half band higher.
 506          */
 507         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 508                 static const u32 vals[] = {
 509                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 510                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 511                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 512                         0x00080d2e, 0x00080d3a
 513                 };
 514
 515                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 516                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 517                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 518                 if (rf->rf4)
 519                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 520         }
 521
 522         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 523         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 524         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 525         if (rf->rf4)
 526                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 527
 528         /*
 529          * Channel 14 requires the Japan filter bit to be set.
 530          */
 531         r70 = 0x46;
 532         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 533         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 534
 535         msleep(1);
 536
 537         /*
 538          * Switch off tuning bits.
 539          * For RT2523 devices we do not need to update the R1 register.
 540          */
 541         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 542                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 543                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 544         }
 545
 546         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 547         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 548
 549         /*
 550          * Clear false CRC during channel switch.
 551          */
 552         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 553 }
 554
 555 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 556                                      const int txpower)
 557 {
 558         u32 rf3;
 559
 560         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 561         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 562         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 563 }
 564
 565 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 566                                          struct rt2x00lib_conf *libconf)
 567 {
 568         u32 reg;
 569
 570         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 571         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 572                            libconf->conf->long_frame_max_tx_count);
 573         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 574                            libconf->conf->short_frame_max_tx_count);
 575         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 576 }
 577
 578 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 579                                       struct rt2x00lib_conf *libconf)
 580 {
 581         u32 reg;
 582
 583         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 584         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 585         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 586         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 587
 588         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 589         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 590                            libconf->conf->beacon_int * 16);
 591         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 592                            libconf->conf->beacon_int * 16);
 593         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 594 }
 595
 596 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 597                              struct rt2x00lib_conf *libconf,
 598                              const unsigned int flags)
 599 {
 600         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 601                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 602                                          libconf->conf->power_level);
 603         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 604             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 605                 rt2500pci_config_txpower(rt2x00dev,
 606                                          libconf->conf->power_level);
 607         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 608                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 609         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
 610                 rt2500pci_config_duration(rt2x00dev, libconf);
 611 }
 612
 613 /*
 614  * Link tuning
 615  */
 616 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 617                                  struct link_qual *qual)
 618 {
 619         u32 reg;
 620
 621         /*
 622          * Update FCS error count from register.
 623          */
 624         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 625         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 626
 627         /*
 628          * Update False CCA count from register.
 629          */
 630         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 631         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 632 }
 633
 634 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 635 {
 636         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 637         rt2x00dev->link.vgc_level = 0x48;
 638 }
 639
 640 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 641 {
 642         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 643         u8 r17;
 644
 645         /*
 646          * To prevent collisions with MAC ASIC on chipsets
 647          * up to version C the link tuning should halt after 20
 648          * seconds while being associated.
 649          */
 650         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 651             rt2x00dev->intf_associated &&
 652             rt2x00dev->link.count > 20)
 653                 return;
 654
 655         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 656
 657         /*
 658          * Chipset versions C and lower should directly continue
 659          * to the dynamic CCA tuning. Chipset version D and higher
 660          * should go straight to dynamic CCA tuning when they
 661          * are not associated.
 662          */
 663         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
 664             !rt2x00dev->intf_associated)
 665                 goto dynamic_cca_tune;
 666
 667         /*
 668          * A too low RSSI will cause too much false CCA which will
 669          * then corrupt the R17 tuning. To remidy this the tuning should
 670          * be stopped (While making sure the R17 value will not exceed limits)
 671          */
 672         if (rssi < -80 && rt2x00dev->link.count > 20) {
 673                 if (r17 >= 0x41) {
 674                         r17 = rt2x00dev->link.vgc_level;
 675                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 676                 }
 677                 return;
 678         }
 679
 680         /*
 681          * Special big-R17 for short distance
 682          */
 683         if (rssi >= -58) {
 684                 if (r17 != 0x50)
 685                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 686                 return;
 687         }
 688
 689         /*
 690          * Special mid-R17 for middle distance
 691          */
 692         if (rssi >= -74) {
 693                 if (r17 != 0x41)
 694                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 695                 return;
 696         }
 697
 698         /*
 699          * Leave short or middle distance condition, restore r17
 700          * to the dynamic tuning range.
 701          */
 702         if (r17 >= 0x41) {
 703                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 704                 return;
 705         }
 706
 707 dynamic_cca_tune:
 708
 709         /*
 710          * R17 is inside the dynamic tuning range,
 711          * start tuning the link based on the false cca counter.
 712          */
 713         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
 714                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 715                 rt2x00dev->link.vgc_level = r17;
 716         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
 717                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 718                 rt2x00dev->link.vgc_level = r17;
 719         }
 720 }
 721
 722 /*
 723  * Initialization functions.
 724  */
 725 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 726                                    struct queue_entry *entry)
 727 {
 728         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 729         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 730         u32 word;
 731
 732         rt2x00_desc_read(entry_priv->desc, 1, &word);
 733         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 734         rt2x00_desc_write(entry_priv->desc, 1, word);
 735
 736         rt2x00_desc_read(entry_priv->desc, 0, &word);
 737         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 738         rt2x00_desc_write(entry_priv->desc, 0, word);
 739 }
 740
 741 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 742                                    struct queue_entry *entry)
 743 {
 744         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 745         u32 word;
 746
 747         rt2x00_desc_read(entry_priv->desc, 0, &word);
 748         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 749         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 750         rt2x00_desc_write(entry_priv->desc, 0, word);
 751 }
 752
 753 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 754 {
 755         struct queue_entry_priv_pci *entry_priv;
 756         u32 reg;
 757
 758         /*
 759          * Initialize registers.
 760          */
 761         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 762         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 763         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 764         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 765         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 766         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 767
 768         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 769         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 770         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 771                            entry_priv->desc_dma);
 772         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 773
 774         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 775         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 776         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 777                            entry_priv->desc_dma);
 778         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 779
 780         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 781         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 782         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 783                            entry_priv->desc_dma);
 784         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 785
 786         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 787         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 788         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 789                            entry_priv->desc_dma);
 790         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 791
 792         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 793         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 794         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 795         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 796
 797         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 798         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 799         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 800                            entry_priv->desc_dma);
 801         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 802
 803         return 0;
 804 }
 805
 806 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 807 {
 808         u32 reg;
 809
 810         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 811         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 812         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 813         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 814
 815         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 816         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 817         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 818         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 819         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 820
 821         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 822         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 823                            rt2x00dev->rx->data_size / 128);
 824         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 825
 826         /*
 827          * Always use CWmin and CWmax set in descriptor.
 828          */
 829         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 830         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 831         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 832
 833         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 834         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 835         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 836         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 837         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 838         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 839         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 840         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 841         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 842         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 843
 844         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 845
 846         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 847         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 848         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 849         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 850         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 851         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 852         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 853         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 854         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 855         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 856
 857         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 858         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 859         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 860         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 861         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 862         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 863
 864         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 865         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 866         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 867         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 868         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 869         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 870
 871         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 872         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 873         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 874         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 875         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 876         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 877
 878         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 879         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 880         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 881         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 882         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 883         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 884         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 885         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 886         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 887         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 888
 889         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 890         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 891         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 892         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 893         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 894         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 895         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 896         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 897         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 898
 899         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 900
 901         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 902         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 903
 904         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 905                 return -EBUSY;
 906
 907         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 908         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 909
 910         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 911         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 912         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 913
 914         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 915         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 916         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 917         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 918         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 919         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 920         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 921         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 922
 923         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 924
 925         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 926
 927         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 928         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 929         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 930         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 931         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 932
 933         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 934         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 935         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 936         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 937
 938         /*
 939          * We must clear the FCS and FIFO error count.
 940          * These registers are cleared on read,
 941          * so we may pass a useless variable to store the value.
 942          */
 943         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 944         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 945
 946         return 0;
 947 }
 948
 949 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 950 {
 951         unsigned int i;
 952         u8 value;
 953
 954         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 955                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 956                 if ((value != 0xff) && (value != 0x00))
 957                         return 0;
 958                 udelay(REGISTER_BUSY_DELAY);
 959         }
 960
 961         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 962         return -EACCES;
 963 }
 964
 965 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 966 {
 967         unsigned int i;
 968         u16 eeprom;
 969         u8 reg_id;
 970         u8 value;
 971
 972         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
 973                 return -EACCES;
 974
 975         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 976         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 977         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 978         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 979         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 980         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 981         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 982         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 983         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 984         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 985         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 986         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 987         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 988         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 989         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 990         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 991         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 992         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 993         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 994         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 995         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 996         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 997         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 998         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 999         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1000         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1001         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1002         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1003         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1004         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1005
1006         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1007                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1008
1009                 if (eeprom != 0xffff && eeprom != 0x0000) {
1010                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1011                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1012                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1013                 }
1014         }
1015
1016         return 0;
1017 }
1018
1019 /*
1020  * Device state switch handlers.
1021  */
1022 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1023                                 enum dev_state state)
1024 {
1025         u32 reg;
1026
1027         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1028         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1029                            (state == STATE_RADIO_RX_OFF) ||
1030                            (state == STATE_RADIO_RX_OFF_LINK));
1031         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1032 }
1033
1034 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1035                                  enum dev_state state)
1036 {
1037         int mask = (state == STATE_RADIO_IRQ_OFF);
1038         u32 reg;
1039
1040         /*
1041          * When interrupts are being enabled, the interrupt registers
1042          * should clear the register to assure a clean state.
1043          */
1044         if (state == STATE_RADIO_IRQ_ON) {
1045                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1046                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1047         }
1048
1049         /*
1050          * Only toggle the interrupts bits we are going to use.
1051          * Non-checked interrupt bits are disabled by default.
1052          */
1053         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1054         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1055         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1056         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1057         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1058         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1059         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1060 }
1061
1062 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1063 {
1064         /*
1065          * Initialize all registers.
1066          */
1067         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1068                      rt2500pci_init_registers(rt2x00dev) ||
1069                      rt2500pci_init_bbp(rt2x00dev)))
1070                 return -EIO;
1071
1072         return 0;
1073 }
1074
1075 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1076 {
1077         u32 reg;
1078
1079         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1080
1081         /*
1082          * Disable synchronisation.
1083          */
1084         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1085
1086         /*
1087          * Cancel RX and TX.
1088          */
1089         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1090         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1091         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1092 }
1093
1094 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1095                                enum dev_state state)
1096 {
1097         u32 reg;
1098         unsigned int i;
1099         char put_to_sleep;
1100         char bbp_state;
1101         char rf_state;
1102
1103         put_to_sleep = (state != STATE_AWAKE);
1104
1105         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1106         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1107         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1108         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1109         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1110         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1111
1112         /*
1113          * Device is not guaranteed to be in the requested state yet.
1114          * We must wait until the register indicates that the
1115          * device has entered the correct state.
1116          */
1117         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1118                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1119                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1120                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1121                 if (bbp_state == state && rf_state == state)
1122                         return 0;
1123                 msleep(10);
1124         }
1125
1126         return -EBUSY;
1127 }
1128
1129 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1130                                       enum dev_state state)
1131 {
1132         int retval = 0;
1133
1134         switch (state) {
1135         case STATE_RADIO_ON:
1136                 retval = rt2500pci_enable_radio(rt2x00dev);
1137                 break;
1138         case STATE_RADIO_OFF:
1139                 rt2500pci_disable_radio(rt2x00dev);
1140                 break;
1141         case STATE_RADIO_RX_ON:
1142         case STATE_RADIO_RX_ON_LINK:
1143         case STATE_RADIO_RX_OFF:
1144         case STATE_RADIO_RX_OFF_LINK:
1145                 rt2500pci_toggle_rx(rt2x00dev, state);
1146                 break;
1147         case STATE_RADIO_IRQ_ON:
1148         case STATE_RADIO_IRQ_OFF:
1149                 rt2500pci_toggle_irq(rt2x00dev, state);
1150                 break;
1151         case STATE_DEEP_SLEEP:
1152         case STATE_SLEEP:
1153         case STATE_STANDBY:
1154         case STATE_AWAKE:
1155                 retval = rt2500pci_set_state(rt2x00dev, state);
1156                 break;
1157         default:
1158                 retval = -ENOTSUPP;
1159                 break;
1160         }
1161
1162         if (unlikely(retval))
1163                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1164                       state, retval);
1165
1166         return retval;
1167 }
1168
1169 /*
1170  * TX descriptor initialization
1171  */
1172 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1173                                     struct sk_buff *skb,
1174                                     struct txentry_desc *txdesc)
1175 {
1176         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1177         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1178         __le32 *txd = skbdesc->desc;
1179         u32 word;
1180
1181         /*
1182          * Start writing the descriptor words.
1183          */
1184         rt2x00_desc_read(entry_priv->desc, 1, &word);
1185         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1186         rt2x00_desc_write(entry_priv->desc, 1, word);
1187
1188         rt2x00_desc_read(txd, 2, &word);
1189         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1190         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1191         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1192         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1193         rt2x00_desc_write(txd, 2, word);
1194
1195         rt2x00_desc_read(txd, 3, &word);
1196         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1197         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1198         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1199         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1200         rt2x00_desc_write(txd, 3, word);
1201
1202         rt2x00_desc_read(txd, 10, &word);
1203         rt2x00_set_field32(&word, TXD_W10_RTS,
1204                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1205         rt2x00_desc_write(txd, 10, word);
1206
1207         rt2x00_desc_read(txd, 0, &word);
1208         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1209         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1210         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1211                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1212         rt2x00_set_field32(&word, TXD_W0_ACK,
1213                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1214         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1215                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1216         rt2x00_set_field32(&word, TXD_W0_OFDM,
1217                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1218         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1219         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1220         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1221                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1222         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1223         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1224         rt2x00_desc_write(txd, 0, word);
1225 }
1226
1227 /*
1228  * TX data initialization
1229  */
1230 static void rt2500pci_write_beacon(struct queue_entry *entry)
1231 {
1232         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1233         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1234         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1235         u32 word;
1236         u32 reg;
1237
1238         /*
1239          * Disable beaconing while we are reloading the beacon data,
1240          * otherwise we might be sending out invalid data.
1241          */
1242         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1243         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1244         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1245         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1246         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1247
1248         /*
1249          * Replace rt2x00lib allocated descriptor with the
1250          * pointer to the _real_ hardware descriptor.
1251          * After that, map the beacon to DMA and update the
1252          * descriptor.
1253          */
1254         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1255         skbdesc->desc = entry_priv->desc;
1256
1257         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1258
1259         rt2x00_desc_read(entry_priv->desc, 1, &word);
1260         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1261         rt2x00_desc_write(entry_priv->desc, 1, word);
1262 }
1263
1264 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1265                                     const enum data_queue_qid queue)
1266 {
1267         u32 reg;
1268
1269         if (queue == QID_BEACON) {
1270                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1271                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1272                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1273                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1274                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1275                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1276                 }
1277                 return;
1278         }
1279
1280         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1281         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1282         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1283         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1284         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1285 }
1286
1287 /*
1288  * RX control handlers
1289  */
1290 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1291                                   struct rxdone_entry_desc *rxdesc)
1292 {
1293         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1294         u32 word0;
1295         u32 word2;
1296
1297         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1298         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1299
1300         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1301                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1302         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1303                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1304
1305         /*
1306          * Obtain the status about this packet.
1307          * When frame was received with an OFDM bitrate,
1308          * the signal is the PLCP value. If it was received with
1309          * a CCK bitrate the signal is the rate in 100kbit/s.
1310          */
1311         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1312         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1313             entry->queue->rt2x00dev->rssi_offset;
1314         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1315
1316         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1317                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1318         else
1319                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1320         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1321                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1322 }
1323
1324 /*
1325  * Interrupt functions.
1326  */
1327 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1328                              const enum data_queue_qid queue_idx)
1329 {
1330         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1331         struct queue_entry_priv_pci *entry_priv;
1332         struct queue_entry *entry;
1333         struct txdone_entry_desc txdesc;
1334         u32 word;
1335
1336         while (!rt2x00queue_empty(queue)) {
1337                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1338                 entry_priv = entry->priv_data;
1339                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1340
1341                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1342                     !rt2x00_get_field32(word, TXD_W0_VALID))
1343                         break;
1344
1345                 /*
1346                  * Obtain the status about this packet.
1347                  */
1348                 txdesc.flags = 0;
1349                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1350                 case 0: /* Success */
1351                 case 1: /* Success with retry */
1352                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1353                         break;
1354                 case 2: /* Failure, excessive retries */
1355                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1356                         /* Don't break, this is a failed frame! */
1357                 default: /* Failure */
1358                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1359                 }
1360                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1361
1362                 rt2x00lib_txdone(entry, &txdesc);
1363         }
1364 }
1365
1366 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1367 {
1368         struct rt2x00_dev *rt2x00dev = dev_instance;
1369         u32 reg;
1370
1371         /*
1372          * Get the interrupt sources & saved to local variable.
1373          * Write register value back to clear pending interrupts.
1374          */
1375         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1376         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1377
1378         if (!reg)
1379                 return IRQ_NONE;
1380
1381         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1382                 return IRQ_HANDLED;
1383
1384         /*
1385          * Handle interrupts, walk through all bits
1386          * and run the tasks, the bits are checked in order of
1387          * priority.
1388          */
1389
1390         /*
1391          * 1 - Beacon timer expired interrupt.
1392          */
1393         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1394                 rt2x00lib_beacondone(rt2x00dev);
1395
1396         /*
1397          * 2 - Rx ring done interrupt.
1398          */
1399         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1400                 rt2x00pci_rxdone(rt2x00dev);
1401
1402         /*
1403          * 3 - Atim ring transmit done interrupt.
1404          */
1405         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1406                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1407
1408         /*
1409          * 4 - Priority ring transmit done interrupt.
1410          */
1411         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1412                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1413
1414         /*
1415          * 5 - Tx ring transmit done interrupt.
1416          */
1417         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1418                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1419
1420         return IRQ_HANDLED;
1421 }
1422
1423 /*
1424  * Device probe functions.
1425  */
1426 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1427 {
1428         struct eeprom_93cx6 eeprom;
1429         u32 reg;
1430         u16 word;
1431         u8 *mac;
1432
1433         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1434
1435         eeprom.data = rt2x00dev;
1436         eeprom.register_read = rt2500pci_eepromregister_read;
1437         eeprom.register_write = rt2500pci_eepromregister_write;
1438         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1439             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1440         eeprom.reg_data_in = 0;
1441         eeprom.reg_data_out = 0;
1442         eeprom.reg_data_clock = 0;
1443         eeprom.reg_chip_select = 0;
1444
1445         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1446                                EEPROM_SIZE / sizeof(u16));
1447
1448         /*
1449          * Start validation of the data that has been read.
1450          */
1451         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1452         if (!is_valid_ether_addr(mac)) {
1453                 random_ether_addr(mac);
1454                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1455         }
1456
1457         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1458         if (word == 0xffff) {
1459                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1460                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1461                                    ANTENNA_SW_DIVERSITY);
1462                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1463                                    ANTENNA_SW_DIVERSITY);
1464                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1465                                    LED_MODE_DEFAULT);
1466                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1467                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1468                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1469                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1470                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1471         }
1472
1473         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1474         if (word == 0xffff) {
1475                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1476                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1477                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1478                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1479                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1480         }
1481
1482         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1483         if (word == 0xffff) {
1484                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1485                                    DEFAULT_RSSI_OFFSET);
1486                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1487                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1488         }
1489
1490         return 0;
1491 }
1492
1493 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1494 {
1495         u32 reg;
1496         u16 value;
1497         u16 eeprom;
1498
1499         /*
1500          * Read EEPROM word for configuration.
1501          */
1502         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1503
1504         /*
1505          * Identify RF chipset.
1506          */
1507         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1508         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1509         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1510
1511         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1512             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1513             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1514             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1515             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1516             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1517                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1518                 return -ENODEV;
1519         }
1520
1521         /*
1522          * Identify default antenna configuration.
1523          */
1524         rt2x00dev->default_ant.tx =
1525             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1526         rt2x00dev->default_ant.rx =
1527             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1528
1529         /*
1530          * Store led mode, for correct led behaviour.
1531          */
1532 #ifdef CONFIG_RT2X00_LIB_LEDS
1533         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1534
1535         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1536         if (value == LED_MODE_TXRX_ACTIVITY)
1537                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1538                                    LED_TYPE_ACTIVITY);
1539 #endif /* CONFIG_RT2X00_LIB_LEDS */
1540
1541         /*
1542          * Detect if this device has an hardware controlled radio.
1543          */
1544 #ifdef CONFIG_RT2X00_LIB_RFKILL
1545         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1546                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1547 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1548
1549         /*
1550          * Check if the BBP tuning should be enabled.
1551          */
1552         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1553
1554         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1555                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1556
1557         /*
1558          * Read the RSSI <-> dBm offset information.
1559          */
1560         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1561         rt2x00dev->rssi_offset =
1562             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1563
1564         return 0;
1565 }
1566
1567 /*
1568  * RF value list for RF2522
1569  * Supports: 2.4 GHz
1570  */
1571 static const struct rf_channel rf_vals_bg_2522[] = {
1572         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1573         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1574         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1575         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1576         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1577         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1578         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1579         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1580         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1581         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1582         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1583         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1584         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1585         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1586 };
1587
1588 /*
1589  * RF value list for RF2523
1590  * Supports: 2.4 GHz
1591  */
1592 static const struct rf_channel rf_vals_bg_2523[] = {
1593         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1594         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1595         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1596         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1597         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1598         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1599         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1600         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1601         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1602         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1603         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1604         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1605         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1606         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1607 };
1608
1609 /*
1610  * RF value list for RF2524
1611  * Supports: 2.4 GHz
1612  */
1613 static const struct rf_channel rf_vals_bg_2524[] = {
1614         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1615         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1616         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1617         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1618         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1619         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1620         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1621         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1622         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1623         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1624         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1625         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1626         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1627         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1628 };
1629
1630 /*
1631  * RF value list for RF2525
1632  * Supports: 2.4 GHz
1633  */
1634 static const struct rf_channel rf_vals_bg_2525[] = {
1635         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1636         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1637         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1638         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1639         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1640         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1641         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1642         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1643         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1644         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1645         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1646         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1647         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1648         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1649 };
1650
1651 /*
1652  * RF value list for RF2525e
1653  * Supports: 2.4 GHz
1654  */
1655 static const struct rf_channel rf_vals_bg_2525e[] = {
1656         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1657         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1658         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1659         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1660         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1661         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1662         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1663         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1664         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1665         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1666         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1667         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1668         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1669         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1670 };
1671
1672 /*
1673  * RF value list for RF5222
1674  * Supports: 2.4 GHz & 5.2 GHz
1675  */
1676 static const struct rf_channel rf_vals_5222[] = {
1677         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1678         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1679         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1680         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1681         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1682         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1683         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1684         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1685         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1686         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1687         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1688         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1689         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1690         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1691
1692         /* 802.11 UNI / HyperLan 2 */
1693         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1694         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1695         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1696         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1697         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1698         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1699         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1700         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1701
1702         /* 802.11 HyperLan 2 */
1703         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1704         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1705         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1706         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1707         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1708         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1709         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1710         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1711         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1712         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1713
1714         /* 802.11 UNII */
1715         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1716         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1717         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1718         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1719         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1720 };
1721
1722 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1723 {
1724         struct hw_mode_spec *spec = &rt2x00dev->spec;
1725         struct channel_info *info;
1726         char *tx_power;
1727         unsigned int i;
1728
1729         /*
1730          * Initialize all hw fields.
1731          */
1732         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1733                                IEEE80211_HW_SIGNAL_DBM;
1734
1735         rt2x00dev->hw->extra_tx_headroom = 0;
1736
1737         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1738         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1739                                 rt2x00_eeprom_addr(rt2x00dev,
1740                                                    EEPROM_MAC_ADDR_0));
1741
1742         /*
1743          * Initialize hw_mode information.
1744          */
1745         spec->supported_bands = SUPPORT_BAND_2GHZ;
1746         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1747
1748         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1749                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1750                 spec->channels = rf_vals_bg_2522;
1751         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1752                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1753                 spec->channels = rf_vals_bg_2523;
1754         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1755                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1756                 spec->channels = rf_vals_bg_2524;
1757         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1758                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1759                 spec->channels = rf_vals_bg_2525;
1760         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1761                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1762                 spec->channels = rf_vals_bg_2525e;
1763         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1764                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1765                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1766                 spec->channels = rf_vals_5222;
1767         }
1768
1769         /*
1770          * Create channel information array
1771          */
1772         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1773         if (!info)
1774                 return -ENOMEM;
1775
1776         spec->channels_info = info;
1777
1778         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1779         for (i = 0; i < 14; i++)
1780                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1781
1782         if (spec->num_channels > 14) {
1783                 for (i = 14; i < spec->num_channels; i++)
1784                         info[i].tx_power1 = DEFAULT_TXPOWER;
1785         }
1786
1787         return 0;
1788 }
1789
1790 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1791 {
1792         int retval;
1793
1794         /*
1795          * Allocate eeprom data.
1796          */
1797         retval = rt2500pci_validate_eeprom(rt2x00dev);
1798         if (retval)
1799                 return retval;
1800
1801         retval = rt2500pci_init_eeprom(rt2x00dev);
1802         if (retval)
1803                 return retval;
1804
1805         /*
1806          * Initialize hw specifications.
1807          */
1808         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1809         if (retval)
1810                 return retval;
1811
1812         /*
1813          * This device requires the atim queue and DMA-mapped skbs.
1814          */
1815         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1816         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1817
1818         /*
1819          * Set the rssi offset.
1820          */
1821         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1822
1823         return 0;
1824 }
1825
1826 /*
1827  * IEEE80211 stack callback functions.
1828  */
1829 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1830 {
1831         struct rt2x00_dev *rt2x00dev = hw->priv;
1832         u64 tsf;
1833         u32 reg;
1834
1835         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1836         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1837         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1838         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1839
1840         return tsf;
1841 }
1842
1843 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1844 {
1845         struct rt2x00_dev *rt2x00dev = hw->priv;
1846         u32 reg;
1847
1848         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1849         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1850 }
1851
1852 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1853         .tx                     = rt2x00mac_tx,
1854         .start                  = rt2x00mac_start,
1855         .stop                   = rt2x00mac_stop,
1856         .add_interface          = rt2x00mac_add_interface,
1857         .remove_interface       = rt2x00mac_remove_interface,
1858         .config                 = rt2x00mac_config,
1859         .config_interface       = rt2x00mac_config_interface,
1860         .configure_filter       = rt2x00mac_configure_filter,
1861         .get_stats              = rt2x00mac_get_stats,
1862         .bss_info_changed       = rt2x00mac_bss_info_changed,
1863         .conf_tx                = rt2x00mac_conf_tx,
1864         .get_tx_stats           = rt2x00mac_get_tx_stats,
1865         .get_tsf                = rt2500pci_get_tsf,
1866         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1867 };
1868
1869 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1870         .irq_handler            = rt2500pci_interrupt,
1871         .probe_hw               = rt2500pci_probe_hw,
1872         .initialize             = rt2x00pci_initialize,
1873         .uninitialize           = rt2x00pci_uninitialize,
1874         .init_rxentry           = rt2500pci_init_rxentry,
1875         .init_txentry           = rt2500pci_init_txentry,
1876         .set_device_state       = rt2500pci_set_device_state,
1877         .rfkill_poll            = rt2500pci_rfkill_poll,
1878         .link_stats             = rt2500pci_link_stats,
1879         .reset_tuner            = rt2500pci_reset_tuner,
1880         .link_tuner             = rt2500pci_link_tuner,
1881         .write_tx_desc          = rt2500pci_write_tx_desc,
1882         .write_tx_data          = rt2x00pci_write_tx_data,
1883         .write_beacon           = rt2500pci_write_beacon,
1884         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1885         .fill_rxdone            = rt2500pci_fill_rxdone,
1886         .config_filter          = rt2500pci_config_filter,
1887         .config_intf            = rt2500pci_config_intf,
1888         .config_erp             = rt2500pci_config_erp,
1889         .config_ant             = rt2500pci_config_ant,
1890         .config                 = rt2500pci_config,
1891 };
1892
1893 static const struct data_queue_desc rt2500pci_queue_rx = {
1894         .entry_num              = RX_ENTRIES,
1895         .data_size              = DATA_FRAME_SIZE,
1896         .desc_size              = RXD_DESC_SIZE,
1897         .priv_size              = sizeof(struct queue_entry_priv_pci),
1898 };
1899
1900 static const struct data_queue_desc rt2500pci_queue_tx = {
1901         .entry_num              = TX_ENTRIES,
1902         .data_size              = DATA_FRAME_SIZE,
1903         .desc_size              = TXD_DESC_SIZE,
1904         .priv_size              = sizeof(struct queue_entry_priv_pci),
1905 };
1906
1907 static const struct data_queue_desc rt2500pci_queue_bcn = {
1908         .entry_num              = BEACON_ENTRIES,
1909         .data_size              = MGMT_FRAME_SIZE,
1910         .desc_size              = TXD_DESC_SIZE,
1911         .priv_size              = sizeof(struct queue_entry_priv_pci),
1912 };
1913
1914 static const struct data_queue_desc rt2500pci_queue_atim = {
1915         .entry_num              = ATIM_ENTRIES,
1916         .data_size              = DATA_FRAME_SIZE,
1917         .desc_size              = TXD_DESC_SIZE,
1918         .priv_size              = sizeof(struct queue_entry_priv_pci),
1919 };
1920
1921 static const struct rt2x00_ops rt2500pci_ops = {
1922         .name           = KBUILD_MODNAME,
1923         .max_sta_intf   = 1,
1924         .max_ap_intf    = 1,
1925         .eeprom_size    = EEPROM_SIZE,
1926         .rf_size        = RF_SIZE,
1927         .tx_queues      = NUM_TX_QUEUES,
1928         .rx             = &rt2500pci_queue_rx,
1929         .tx             = &rt2500pci_queue_tx,
1930         .bcn            = &rt2500pci_queue_bcn,
1931         .atim           = &rt2500pci_queue_atim,
1932         .lib            = &rt2500pci_rt2x00_ops,
1933         .hw             = &rt2500pci_mac80211_ops,
1934 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1935         .debugfs        = &rt2500pci_rt2x00debug,
1936 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1937 };
1938
1939 /*
1940  * RT2500pci module information.
1941  */
1942 static struct pci_device_id rt2500pci_device_table[] = {
1943         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1944         { 0, }
1945 };
1946
1947 MODULE_AUTHOR(DRV_PROJECT);
1948 MODULE_VERSION(DRV_VERSION);
1949 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1950 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1951 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1952 MODULE_LICENSE("GPL");
1953
1954 static struct pci_driver rt2500pci_driver = {
1955         .name           = KBUILD_MODNAME,
1956         .id_table       = rt2500pci_device_table,
1957         .probe          = rt2x00pci_probe,
1958         .remove         = __devexit_p(rt2x00pci_remove),
1959         .suspend        = rt2x00pci_suspend,
1960         .resume         = rt2x00pci_resume,
1961 };
1962
1963 static int __init rt2500pci_init(void)
1964 {
1965         return pci_register_driver(&rt2500pci_driver);
1966 }
1967
1968 static void __exit rt2500pci_exit(void)
1969 {
1970         pci_unregister_driver(&rt2500pci_driver);
1971 }
1972
1973 module_init(rt2500pci_init);
1974 module_exit(rt2500pci_exit);