Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
[linux-2.6] / drivers / net / ucc_geth_phy.c
1 /*
2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
3  *
4  * Author: Shlomi Gridish <gridish@freescale.com>
5  *
6  * Description:
7  * UCC GETH Driver -- PHY handling
8  *
9  * Changelog:
10  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
11  * - Rearrange code and style fixes
12  *
13  * This program is free software; you can redistribute  it and/or modify it
14  * under  the terms of  the GNU General  Public License as published by the
15  * Free Software Foundation;  either version 2 of the  License, or (at your
16  * option) any later version.
17  *
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/slab.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/spinlock.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/version.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
37 #include <linux/ethtool.h>
38
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/uaccess.h>
42
43 #include "ucc_geth.h"
44 #include "ucc_geth_phy.h"
45
46 #define ugphy_printk(level, format, arg...)  \
47         printk(level format "\n", ## arg)
48
49 #define ugphy_dbg(format, arg...)            \
50         ugphy_printk(KERN_DEBUG, format , ## arg)
51 #define ugphy_err(format, arg...)            \
52         ugphy_printk(KERN_ERR, format , ## arg)
53 #define ugphy_info(format, arg...)           \
54         ugphy_printk(KERN_INFO, format , ## arg)
55 #define ugphy_warn(format, arg...)           \
56         ugphy_printk(KERN_WARNING, format , ## arg)
57
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugphy_vdbg ugphy_dbg
60 #else
61 #define ugphy_vdbg(fmt, args...) do { } while (0)
62 #endif                          /* UGETH_VERBOSE_DEBUG */
63
64 static void config_genmii_advert(struct ugeth_mii_info *mii_info);
65 static void genmii_setup_forced(struct ugeth_mii_info *mii_info);
66 static void genmii_restart_aneg(struct ugeth_mii_info *mii_info);
67 static int gbit_config_aneg(struct ugeth_mii_info *mii_info);
68 static int genmii_config_aneg(struct ugeth_mii_info *mii_info);
69 static int genmii_update_link(struct ugeth_mii_info *mii_info);
70 static int genmii_read_status(struct ugeth_mii_info *mii_info);
71 u16 phy_read(struct ugeth_mii_info *mii_info, u16 regnum);
72 void phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val);
73
74 /* Write value to the PHY for this device to the register at regnum, */
75 /* waiting until the write is done before it returns.  All PHY */
76 /* configuration has to be done through the TSEC1 MIIM regs */
77 void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value)
78 {
79         struct ucc_geth_private *ugeth = netdev_priv(dev);
80         struct ucc_mii_mng *mii_regs;
81         enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;
82         u32 tmp_reg;
83
84         ugphy_vdbg("%s: IN", __FUNCTION__);
85
86         spin_lock_irq(&ugeth->lock);
87
88         mii_regs = ugeth->mii_info->mii_regs;
89
90         /* Set this UCC to be the master of the MII managment */
91         ucc_set_qe_mux_mii_mng(ugeth->ug_info->uf_info.ucc_num);
92
93         /* Stop the MII management read cycle */
94         out_be32(&mii_regs->miimcom, 0);
95         /* Setting up the MII Mangement Address Register */
96         tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
97         out_be32(&mii_regs->miimadd, tmp_reg);
98
99         /* Setting up the MII Mangement Control Register with the value */
100         out_be32(&mii_regs->miimcon, (u32) value);
101
102         /* Wait till MII management write is complete */
103         while ((in_be32(&mii_regs->miimind)) & MIIMIND_BUSY)
104                 cpu_relax();
105
106         spin_unlock_irq(&ugeth->lock);
107
108         udelay(10000);
109 }
110
111 /* Reads from register regnum in the PHY for device dev, */
112 /* returning the value.  Clears miimcom first.  All PHY */
113 /* configuration has to be done through the TSEC1 MIIM regs */
114 int read_phy_reg(struct net_device *dev, int mii_id, int regnum)
115 {
116         struct ucc_geth_private *ugeth = netdev_priv(dev);
117         struct ucc_mii_mng *mii_regs;
118         enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;
119         u32 tmp_reg;
120         u16 value;
121
122         ugphy_vdbg("%s: IN", __FUNCTION__);
123
124         spin_lock_irq(&ugeth->lock);
125
126         mii_regs = ugeth->mii_info->mii_regs;
127
128         /* Setting up the MII Mangement Address Register */
129         tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
130         out_be32(&mii_regs->miimadd, tmp_reg);
131
132         /* Perform an MII management read cycle */
133         out_be32(&mii_regs->miimcom, MIIMCOM_READ_CYCLE);
134
135         /* Wait till MII management write is complete */
136         while ((in_be32(&mii_regs->miimind)) & MIIMIND_BUSY)
137                 cpu_relax();
138
139         udelay(10000);
140
141         /* Read MII management status  */
142         value = (u16) in_be32(&mii_regs->miimstat);
143         out_be32(&mii_regs->miimcom, 0);
144         if (value == 0xffff)
145                 ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x",
146                            mii_id, mii_reg, (u32) & (mii_regs->miimcfg));
147
148         spin_unlock_irq(&ugeth->lock);
149
150         return (value);
151 }
152
153 void mii_clear_phy_interrupt(struct ugeth_mii_info *mii_info)
154 {
155         ugphy_vdbg("%s: IN", __FUNCTION__);
156
157         if (mii_info->phyinfo->ack_interrupt)
158                 mii_info->phyinfo->ack_interrupt(mii_info);
159 }
160
161 void mii_configure_phy_interrupt(struct ugeth_mii_info *mii_info,
162                                  u32 interrupts)
163 {
164         ugphy_vdbg("%s: IN", __FUNCTION__);
165
166         mii_info->interrupts = interrupts;
167         if (mii_info->phyinfo->config_intr)
168                 mii_info->phyinfo->config_intr(mii_info);
169 }
170
171 /* Writes MII_ADVERTISE with the appropriate values, after
172  * sanitizing advertise to make sure only supported features
173  * are advertised
174  */
175 static void config_genmii_advert(struct ugeth_mii_info *mii_info)
176 {
177         u32 advertise;
178         u16 adv;
179
180         ugphy_vdbg("%s: IN", __FUNCTION__);
181
182         /* Only allow advertising what this PHY supports */
183         mii_info->advertising &= mii_info->phyinfo->features;
184         advertise = mii_info->advertising;
185
186         /* Setup standard advertisement */
187         adv = phy_read(mii_info, MII_ADVERTISE);
188         adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
189         if (advertise & ADVERTISED_10baseT_Half)
190                 adv |= ADVERTISE_10HALF;
191         if (advertise & ADVERTISED_10baseT_Full)
192                 adv |= ADVERTISE_10FULL;
193         if (advertise & ADVERTISED_100baseT_Half)
194                 adv |= ADVERTISE_100HALF;
195         if (advertise & ADVERTISED_100baseT_Full)
196                 adv |= ADVERTISE_100FULL;
197         phy_write(mii_info, MII_ADVERTISE, adv);
198 }
199
200 static void genmii_setup_forced(struct ugeth_mii_info *mii_info)
201 {
202         u16 ctrl;
203         u32 features = mii_info->phyinfo->features;
204
205         ugphy_vdbg("%s: IN", __FUNCTION__);
206
207         ctrl = phy_read(mii_info, MII_BMCR);
208
209         ctrl &=
210             ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
211         ctrl |= BMCR_RESET;
212
213         switch (mii_info->speed) {
214         case SPEED_1000:
215                 if (features & (SUPPORTED_1000baseT_Half
216                                 | SUPPORTED_1000baseT_Full)) {
217                         ctrl |= BMCR_SPEED1000;
218                         break;
219                 }
220                 mii_info->speed = SPEED_100;
221         case SPEED_100:
222                 if (features & (SUPPORTED_100baseT_Half
223                                 | SUPPORTED_100baseT_Full)) {
224                         ctrl |= BMCR_SPEED100;
225                         break;
226                 }
227                 mii_info->speed = SPEED_10;
228         case SPEED_10:
229                 if (features & (SUPPORTED_10baseT_Half
230                                 | SUPPORTED_10baseT_Full))
231                         break;
232         default:                /* Unsupported speed! */
233                 ugphy_err("%s: Bad speed!", mii_info->dev->name);
234                 break;
235         }
236
237         phy_write(mii_info, MII_BMCR, ctrl);
238 }
239
240 /* Enable and Restart Autonegotiation */
241 static void genmii_restart_aneg(struct ugeth_mii_info *mii_info)
242 {
243         u16 ctl;
244
245         ugphy_vdbg("%s: IN", __FUNCTION__);
246
247         ctl = phy_read(mii_info, MII_BMCR);
248         ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
249         phy_write(mii_info, MII_BMCR, ctl);
250 }
251
252 static int gbit_config_aneg(struct ugeth_mii_info *mii_info)
253 {
254         u16 adv;
255         u32 advertise;
256
257         ugphy_vdbg("%s: IN", __FUNCTION__);
258
259         if (mii_info->autoneg) {
260                 /* Configure the ADVERTISE register */
261                 config_genmii_advert(mii_info);
262                 advertise = mii_info->advertising;
263
264                 adv = phy_read(mii_info, MII_1000BASETCONTROL);
265                 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
266                          MII_1000BASETCONTROL_HALFDUPLEXCAP);
267                 if (advertise & SUPPORTED_1000baseT_Half)
268                         adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
269                 if (advertise & SUPPORTED_1000baseT_Full)
270                         adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
271                 phy_write(mii_info, MII_1000BASETCONTROL, adv);
272
273                 /* Start/Restart aneg */
274                 genmii_restart_aneg(mii_info);
275         } else
276                 genmii_setup_forced(mii_info);
277
278         return 0;
279 }
280
281 static int genmii_config_aneg(struct ugeth_mii_info *mii_info)
282 {
283         ugphy_vdbg("%s: IN", __FUNCTION__);
284
285         if (mii_info->autoneg) {
286                 config_genmii_advert(mii_info);
287                 genmii_restart_aneg(mii_info);
288         } else
289                 genmii_setup_forced(mii_info);
290
291         return 0;
292 }
293
294 static int genmii_update_link(struct ugeth_mii_info *mii_info)
295 {
296         u16 status;
297
298         ugphy_vdbg("%s: IN", __FUNCTION__);
299
300         /* Do a fake read */
301         phy_read(mii_info, MII_BMSR);
302
303         /* Read link and autonegotiation status */
304         status = phy_read(mii_info, MII_BMSR);
305         if ((status & BMSR_LSTATUS) == 0)
306                 mii_info->link = 0;
307         else
308                 mii_info->link = 1;
309
310         /* If we are autonegotiating, and not done,
311          * return an error */
312         if (mii_info->autoneg && !(status & BMSR_ANEGCOMPLETE))
313                 return -EAGAIN;
314
315         return 0;
316 }
317
318 static int genmii_read_status(struct ugeth_mii_info *mii_info)
319 {
320         u16 status;
321         int err;
322
323         ugphy_vdbg("%s: IN", __FUNCTION__);
324
325         /* Update the link, but return if there
326          * was an error */
327         err = genmii_update_link(mii_info);
328         if (err)
329                 return err;
330
331         if (mii_info->autoneg) {
332                 status = phy_read(mii_info, MII_LPA);
333
334                 if (status & (LPA_10FULL | LPA_100FULL))
335                         mii_info->duplex = DUPLEX_FULL;
336                 else
337                         mii_info->duplex = DUPLEX_HALF;
338                 if (status & (LPA_100FULL | LPA_100HALF))
339                         mii_info->speed = SPEED_100;
340                 else
341                         mii_info->speed = SPEED_10;
342                 mii_info->pause = 0;
343         }
344         /* On non-aneg, we assume what we put in BMCR is the speed,
345          * though magic-aneg shouldn't prevent this case from occurring
346          */
347
348         return 0;
349 }
350
351 static int marvell_init(struct ugeth_mii_info *mii_info)
352 {
353         ugphy_vdbg("%s: IN", __FUNCTION__);
354
355         phy_write(mii_info, 0x14, 0x0cd2);
356         phy_write(mii_info, MII_BMCR,
357                   phy_read(mii_info, MII_BMCR) | BMCR_RESET);
358         msleep(4000);
359
360         return 0;
361 }
362
363 static int marvell_config_aneg(struct ugeth_mii_info *mii_info)
364 {
365         ugphy_vdbg("%s: IN", __FUNCTION__);
366
367         /* The Marvell PHY has an errata which requires
368          * that certain registers get written in order
369          * to restart autonegotiation */
370         phy_write(mii_info, MII_BMCR, BMCR_RESET);
371
372         phy_write(mii_info, 0x1d, 0x1f);
373         phy_write(mii_info, 0x1e, 0x200c);
374         phy_write(mii_info, 0x1d, 0x5);
375         phy_write(mii_info, 0x1e, 0);
376         phy_write(mii_info, 0x1e, 0x100);
377
378         gbit_config_aneg(mii_info);
379
380         return 0;
381 }
382
383 static int marvell_read_status(struct ugeth_mii_info *mii_info)
384 {
385         u16 status;
386         int err;
387
388         ugphy_vdbg("%s: IN", __FUNCTION__);
389
390         /* Update the link, but return if there
391          * was an error */
392         err = genmii_update_link(mii_info);
393         if (err)
394                 return err;
395
396         /* If the link is up, read the speed and duplex */
397         /* If we aren't autonegotiating, assume speeds
398          * are as set */
399         if (mii_info->autoneg && mii_info->link) {
400                 int speed;
401                 status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
402
403                 /* Get the duplexity */
404                 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
405                         mii_info->duplex = DUPLEX_FULL;
406                 else
407                         mii_info->duplex = DUPLEX_HALF;
408
409                 /* Get the speed */
410                 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
411                 switch (speed) {
412                 case MII_M1011_PHY_SPEC_STATUS_1000:
413                         mii_info->speed = SPEED_1000;
414                         break;
415                 case MII_M1011_PHY_SPEC_STATUS_100:
416                         mii_info->speed = SPEED_100;
417                         break;
418                 default:
419                         mii_info->speed = SPEED_10;
420                         break;
421                 }
422                 mii_info->pause = 0;
423         }
424
425         return 0;
426 }
427
428 static int marvell_ack_interrupt(struct ugeth_mii_info *mii_info)
429 {
430         ugphy_vdbg("%s: IN", __FUNCTION__);
431
432         /* Clear the interrupts by reading the reg */
433         phy_read(mii_info, MII_M1011_IEVENT);
434
435         return 0;
436 }
437
438 static int marvell_config_intr(struct ugeth_mii_info *mii_info)
439 {
440         ugphy_vdbg("%s: IN", __FUNCTION__);
441
442         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
443                 phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
444         else
445                 phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
446
447         return 0;
448 }
449
450 static int cis820x_init(struct ugeth_mii_info *mii_info)
451 {
452         ugphy_vdbg("%s: IN", __FUNCTION__);
453
454         phy_write(mii_info, MII_CIS8201_AUX_CONSTAT,
455                   MII_CIS8201_AUXCONSTAT_INIT);
456         phy_write(mii_info, MII_CIS8201_EXT_CON1, MII_CIS8201_EXTCON1_INIT);
457
458         return 0;
459 }
460
461 static int cis820x_read_status(struct ugeth_mii_info *mii_info)
462 {
463         u16 status;
464         int err;
465
466         ugphy_vdbg("%s: IN", __FUNCTION__);
467
468         /* Update the link, but return if there
469          * was an error */
470         err = genmii_update_link(mii_info);
471         if (err)
472                 return err;
473
474         /* If the link is up, read the speed and duplex */
475         /* If we aren't autonegotiating, assume speeds
476          * are as set */
477         if (mii_info->autoneg && mii_info->link) {
478                 int speed;
479
480                 status = phy_read(mii_info, MII_CIS8201_AUX_CONSTAT);
481                 if (status & MII_CIS8201_AUXCONSTAT_DUPLEX)
482                         mii_info->duplex = DUPLEX_FULL;
483                 else
484                         mii_info->duplex = DUPLEX_HALF;
485
486                 speed = status & MII_CIS8201_AUXCONSTAT_SPEED;
487
488                 switch (speed) {
489                 case MII_CIS8201_AUXCONSTAT_GBIT:
490                         mii_info->speed = SPEED_1000;
491                         break;
492                 case MII_CIS8201_AUXCONSTAT_100:
493                         mii_info->speed = SPEED_100;
494                         break;
495                 default:
496                         mii_info->speed = SPEED_10;
497                         break;
498                 }
499         }
500
501         return 0;
502 }
503
504 static int cis820x_ack_interrupt(struct ugeth_mii_info *mii_info)
505 {
506         ugphy_vdbg("%s: IN", __FUNCTION__);
507
508         phy_read(mii_info, MII_CIS8201_ISTAT);
509
510         return 0;
511 }
512
513 static int cis820x_config_intr(struct ugeth_mii_info *mii_info)
514 {
515         ugphy_vdbg("%s: IN", __FUNCTION__);
516
517         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
518                 phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK);
519         else
520                 phy_write(mii_info, MII_CIS8201_IMASK, 0);
521
522         return 0;
523 }
524
525 #define DM9161_DELAY 10
526
527 static int dm9161_read_status(struct ugeth_mii_info *mii_info)
528 {
529         u16 status;
530         int err;
531
532         ugphy_vdbg("%s: IN", __FUNCTION__);
533
534         /* Update the link, but return if there
535          * was an error */
536         err = genmii_update_link(mii_info);
537         if (err)
538                 return err;
539
540         /* If the link is up, read the speed and duplex */
541         /* If we aren't autonegotiating, assume speeds
542          * are as set */
543         if (mii_info->autoneg && mii_info->link) {
544                 status = phy_read(mii_info, MII_DM9161_SCSR);
545                 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
546                         mii_info->speed = SPEED_100;
547                 else
548                         mii_info->speed = SPEED_10;
549
550                 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
551                         mii_info->duplex = DUPLEX_FULL;
552                 else
553                         mii_info->duplex = DUPLEX_HALF;
554         }
555
556         return 0;
557 }
558
559 static int dm9161_config_aneg(struct ugeth_mii_info *mii_info)
560 {
561         struct dm9161_private *priv = mii_info->priv;
562
563         ugphy_vdbg("%s: IN", __FUNCTION__);
564
565         if (0 == priv->resetdone)
566                 return -EAGAIN;
567
568         return 0;
569 }
570
571 static void dm9161_timer(unsigned long data)
572 {
573         struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data;
574         struct dm9161_private *priv = mii_info->priv;
575         u16 status = phy_read(mii_info, MII_BMSR);
576
577         ugphy_vdbg("%s: IN", __FUNCTION__);
578
579         if (status & BMSR_ANEGCOMPLETE) {
580                 priv->resetdone = 1;
581         } else
582                 mod_timer(&priv->timer, jiffies + DM9161_DELAY * HZ);
583 }
584
585 static int dm9161_init(struct ugeth_mii_info *mii_info)
586 {
587         struct dm9161_private *priv;
588
589         ugphy_vdbg("%s: IN", __FUNCTION__);
590
591         /* Allocate the private data structure */
592         priv = kmalloc(sizeof(struct dm9161_private), GFP_KERNEL);
593
594         if (NULL == priv)
595                 return -ENOMEM;
596
597         mii_info->priv = priv;
598
599         /* Reset is not done yet */
600         priv->resetdone = 0;
601
602         phy_write(mii_info, MII_BMCR,
603                   phy_read(mii_info, MII_BMCR) | BMCR_RESET);
604
605         phy_write(mii_info, MII_BMCR,
606                   phy_read(mii_info, MII_BMCR) & ~BMCR_ISOLATE);
607
608         config_genmii_advert(mii_info);
609         /* Start/Restart aneg */
610         genmii_config_aneg(mii_info);
611
612         /* Start a timer for DM9161_DELAY seconds to wait
613          * for the PHY to be ready */
614         init_timer(&priv->timer);
615         priv->timer.function = &dm9161_timer;
616         priv->timer.data = (unsigned long)mii_info;
617         mod_timer(&priv->timer, jiffies + DM9161_DELAY * HZ);
618
619         return 0;
620 }
621
622 static void dm9161_close(struct ugeth_mii_info *mii_info)
623 {
624         struct dm9161_private *priv = mii_info->priv;
625
626         ugphy_vdbg("%s: IN", __FUNCTION__);
627
628         del_timer_sync(&priv->timer);
629         kfree(priv);
630 }
631
632 static int dm9161_ack_interrupt(struct ugeth_mii_info *mii_info)
633 {
634         ugphy_vdbg("%s: IN", __FUNCTION__);
635
636         /* Clear the interrupts by reading the reg */
637         phy_read(mii_info, MII_DM9161_INTR);
638
639
640         return 0;
641 }
642
643 static int dm9161_config_intr(struct ugeth_mii_info *mii_info)
644 {
645         ugphy_vdbg("%s: IN", __FUNCTION__);
646
647         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
648                 phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
649         else
650                 phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
651
652         return 0;
653 }
654
655 /* Cicada 820x */
656 static struct phy_info phy_info_cis820x = {
657         .phy_id = 0x000fc440,
658         .name = "Cicada Cis8204",
659         .phy_id_mask = 0x000fffc0,
660         .features = MII_GBIT_FEATURES,
661         .init = &cis820x_init,
662         .config_aneg = &gbit_config_aneg,
663         .read_status = &cis820x_read_status,
664         .ack_interrupt = &cis820x_ack_interrupt,
665         .config_intr = &cis820x_config_intr,
666 };
667
668 static struct phy_info phy_info_dm9161 = {
669         .phy_id = 0x0181b880,
670         .phy_id_mask = 0x0ffffff0,
671         .name = "Davicom DM9161E",
672         .init = dm9161_init,
673         .config_aneg = dm9161_config_aneg,
674         .read_status = dm9161_read_status,
675         .close = dm9161_close,
676 };
677
678 static struct phy_info phy_info_dm9161a = {
679         .phy_id = 0x0181b8a0,
680         .phy_id_mask = 0x0ffffff0,
681         .name = "Davicom DM9161A",
682         .features = MII_BASIC_FEATURES,
683         .init = dm9161_init,
684         .config_aneg = dm9161_config_aneg,
685         .read_status = dm9161_read_status,
686         .ack_interrupt = dm9161_ack_interrupt,
687         .config_intr = dm9161_config_intr,
688         .close = dm9161_close,
689 };
690
691 static struct phy_info phy_info_marvell = {
692         .phy_id = 0x01410c00,
693         .phy_id_mask = 0xffffff00,
694         .name = "Marvell 88E11x1",
695         .features = MII_GBIT_FEATURES,
696         .init = &marvell_init,
697         .config_aneg = &marvell_config_aneg,
698         .read_status = &marvell_read_status,
699         .ack_interrupt = &marvell_ack_interrupt,
700         .config_intr = &marvell_config_intr,
701 };
702
703 static struct phy_info phy_info_genmii = {
704         .phy_id = 0x00000000,
705         .phy_id_mask = 0x00000000,
706         .name = "Generic MII",
707         .features = MII_BASIC_FEATURES,
708         .config_aneg = genmii_config_aneg,
709         .read_status = genmii_read_status,
710 };
711
712 static struct phy_info *phy_info[] = {
713         &phy_info_cis820x,
714         &phy_info_marvell,
715         &phy_info_dm9161,
716         &phy_info_dm9161a,
717         &phy_info_genmii,
718         NULL
719 };
720
721 u16 phy_read(struct ugeth_mii_info *mii_info, u16 regnum)
722 {
723         u16 retval;
724         unsigned long flags;
725
726         ugphy_vdbg("%s: IN", __FUNCTION__);
727
728         spin_lock_irqsave(&mii_info->mdio_lock, flags);
729         retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
730         spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
731
732         return retval;
733 }
734
735 void phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val)
736 {
737         unsigned long flags;
738
739         ugphy_vdbg("%s: IN", __FUNCTION__);
740
741         spin_lock_irqsave(&mii_info->mdio_lock, flags);
742         mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
743         spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
744 }
745
746 /* Use the PHY ID registers to determine what type of PHY is attached
747  * to device dev.  return a struct phy_info structure describing that PHY
748  */
749 struct phy_info *get_phy_info(struct ugeth_mii_info *mii_info)
750 {
751         u16 phy_reg;
752         u32 phy_ID;
753         int i;
754         struct phy_info *theInfo = NULL;
755         struct net_device *dev = mii_info->dev;
756
757         ugphy_vdbg("%s: IN", __FUNCTION__);
758
759         /* Grab the bits from PHYIR1, and put them in the upper half */
760         phy_reg = phy_read(mii_info, MII_PHYSID1);
761         phy_ID = (phy_reg & 0xffff) << 16;
762
763         /* Grab the bits from PHYIR2, and put them in the lower half */
764         phy_reg = phy_read(mii_info, MII_PHYSID2);
765         phy_ID |= (phy_reg & 0xffff);
766
767         /* loop through all the known PHY types, and find one that */
768         /* matches the ID we read from the PHY. */
769         for (i = 0; phy_info[i]; i++)
770                 if (phy_info[i]->phy_id == (phy_ID & phy_info[i]->phy_id_mask)){
771                         theInfo = phy_info[i];
772                         break;
773                 }
774
775         /* This shouldn't happen, as we have generic PHY support */
776         if (theInfo == NULL) {
777                 ugphy_info("%s: PHY id %x is not supported!", dev->name,
778                            phy_ID);
779                 return NULL;
780         } else {
781                 ugphy_info("%s: PHY is %s (%x)", dev->name, theInfo->name,
782                            phy_ID);
783         }
784
785         return theInfo;
786 }