git.oblomov.eu Git - linux-2.6/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int single_cmd;
  62 static int enable_msi;
  63
  64 module_param_array(index, int, NULL, 0444);
  65 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  66 module_param_array(id, charp, NULL, 0444);
  67 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  68 module_param_array(enable, bool, NULL, 0444);
  69 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  70 module_param_array(model, charp, NULL, 0444);
  71 MODULE_PARM_DESC(model, "Use the given board model.");
  72 module_param_array(position_fix, int, NULL, 0444);
  73 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  74                  "(0 = auto, 1 = none, 2 = POSBUF).");
  75 module_param_array(bdl_pos_adj, int, NULL, 0644);
  76 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  77 module_param_array(probe_mask, int, NULL, 0444);
  78 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  79 module_param(single_cmd, bool, 0444);
  80 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  81                  "(for debugging only).");
  82 module_param(enable_msi, int, 0444);
  83 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  84
  85 #ifdef CONFIG_SND_HDA_POWER_SAVE
  86 /* power_save option is defined in hda_codec.c */
  87
  88 /* reset the HD-audio controller in power save mode.
  89  * this may give more power-saving, but will take longer time to
  90  * wake up.
  91  */
  92 static int power_save_controller = 1;
  93 module_param(power_save_controller, bool, 0644);
  94 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  95 #endif
  96
  97 MODULE_LICENSE("GPL");
  98 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  99                          "{Intel, ICH6M},"
 100                          "{Intel, ICH7},"
 101                          "{Intel, ESB2},"
 102                          "{Intel, ICH8},"
 103                          "{Intel, ICH9},"
 104                          "{Intel, ICH10},"
 105                          "{Intel, PCH},"
 106                          "{Intel, SCH},"
 107                          "{ATI, SB450},"
 108                          "{ATI, SB600},"
 109                          "{ATI, RS600},"
 110                          "{ATI, RS690},"
 111                          "{ATI, RS780},"
 112                          "{ATI, R600},"
 113                          "{ATI, RV630},"
 114                          "{ATI, RV610},"
 115                          "{ATI, RV670},"
 116                          "{ATI, RV635},"
 117                          "{ATI, RV620},"
 118                          "{ATI, RV770},"
 119                          "{VIA, VT8251},"
 120                          "{VIA, VT8237A},"
 121                          "{SiS, SIS966},"
 122                          "{ULI, M5461}}");
 123 MODULE_DESCRIPTION("Intel HDA driver");
 124
 125 #define SFX     "hda-intel: "
 126
 127
 128 /*
 129  * registers
 130  */
 131 #define ICH6_REG_GCAP                   0x00
 132 #define ICH6_REG_VMIN                   0x02
 133 #define ICH6_REG_VMAJ                   0x03
 134 #define ICH6_REG_OUTPAY                 0x04
 135 #define ICH6_REG_INPAY                  0x06
 136 #define ICH6_REG_GCTL                   0x08
 137 #define ICH6_REG_WAKEEN                 0x0c
 138 #define ICH6_REG_STATESTS               0x0e
 139 #define ICH6_REG_GSTS                   0x10
 140 #define ICH6_REG_INTCTL                 0x20
 141 #define ICH6_REG_INTSTS                 0x24
 142 #define ICH6_REG_WALCLK                 0x30
 143 #define ICH6_REG_SYNC                   0x34
 144 #define ICH6_REG_CORBLBASE              0x40
 145 #define ICH6_REG_CORBUBASE              0x44
 146 #define ICH6_REG_CORBWP                 0x48
 147 #define ICH6_REG_CORBRP                 0x4A
 148 #define ICH6_REG_CORBCTL                0x4c
 149 #define ICH6_REG_CORBSTS                0x4d
 150 #define ICH6_REG_CORBSIZE               0x4e
 151
 152 #define ICH6_REG_RIRBLBASE              0x50
 153 #define ICH6_REG_RIRBUBASE              0x54
 154 #define ICH6_REG_RIRBWP                 0x58
 155 #define ICH6_REG_RINTCNT                0x5a
 156 #define ICH6_REG_RIRBCTL                0x5c
 157 #define ICH6_REG_RIRBSTS                0x5d
 158 #define ICH6_REG_RIRBSIZE               0x5e
 159
 160 #define ICH6_REG_IC                     0x60
 161 #define ICH6_REG_IR                     0x64
 162 #define ICH6_REG_IRS                    0x68
 163 #define   ICH6_IRS_VALID        (1<<1)
 164 #define   ICH6_IRS_BUSY         (1<<0)
 165
 166 #define ICH6_REG_DPLBASE                0x70
 167 #define ICH6_REG_DPUBASE                0x74
 168 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 169
 170 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 171 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 172
 173 /* stream register offsets from stream base */
 174 #define ICH6_REG_SD_CTL                 0x00
 175 #define ICH6_REG_SD_STS                 0x03
 176 #define ICH6_REG_SD_LPIB                0x04
 177 #define ICH6_REG_SD_CBL                 0x08
 178 #define ICH6_REG_SD_LVI                 0x0c
 179 #define ICH6_REG_SD_FIFOW               0x0e
 180 #define ICH6_REG_SD_FIFOSIZE            0x10
 181 #define ICH6_REG_SD_FORMAT              0x12
 182 #define ICH6_REG_SD_BDLPL               0x18
 183 #define ICH6_REG_SD_BDLPU               0x1c
 184
 185 /* PCI space */
 186 #define ICH6_PCIREG_TCSEL       0x44
 187
 188 /*
 189  * other constants
 190  */
 191
 192 /* max number of SDs */
 193 /* ICH, ATI and VIA have 4 playback and 4 capture */
 194 #define ICH6_NUM_CAPTURE        4
 195 #define ICH6_NUM_PLAYBACK       4
 196
 197 /* ULI has 6 playback and 5 capture */
 198 #define ULI_NUM_CAPTURE         5
 199 #define ULI_NUM_PLAYBACK        6
 200
 201 /* ATI HDMI has 1 playback and 0 capture */
 202 #define ATIHDMI_NUM_CAPTURE     0
 203 #define ATIHDMI_NUM_PLAYBACK    1
 204
 205 /* TERA has 4 playback and 3 capture */
 206 #define TERA_NUM_CAPTURE        3
 207 #define TERA_NUM_PLAYBACK       4
 208
 209 /* this number is statically defined for simplicity */
 210 #define MAX_AZX_DEV             16
 211
 212 /* max number of fragments - we may use more if allocating more pages for BDL */
 213 #define BDL_SIZE                4096
 214 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 215 #define AZX_MAX_FRAG            32
 216 /* max buffer size - no h/w limit, you can increase as you like */
 217 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 218 /* max number of PCM devics per card */
 219 #define AZX_MAX_PCMS            8
 220
 221 /* RIRB int mask: overrun[2], response[0] */
 222 #define RIRB_INT_RESPONSE       0x01
 223 #define RIRB_INT_OVERRUN        0x04
 224 #define RIRB_INT_MASK           0x05
 225
 226 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 227 #define AZX_MAX_CODECS          4
 228 #define STATESTS_INT_MASK       0x0f
 229
 230 /* SD_CTL bits */
 231 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 232 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 233 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 234 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 235 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 236 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 237 #define SD_CTL_STREAM_TAG_SHIFT 20
 238
 239 /* SD_CTL and SD_STS */
 240 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 241 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 242 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 243 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 244                                  SD_INT_COMPLETE)
 245
 246 /* SD_STS */
 247 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 248
 249 /* INTCTL and INTSTS */
 250 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 251 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 252 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 253
 254 /* GCTL unsolicited response enable bit */
 255 #define ICH6_GCTL_UREN          (1<<8)
 256
 257 /* GCTL reset bit */
 258 #define ICH6_GCTL_RESET         (1<<0)
 259
 260 /* CORB/RIRB control, read/write pointer */
 261 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 262 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 263 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 264 /* below are so far hardcoded - should read registers in future */
 265 #define ICH6_MAX_CORB_ENTRIES   256
 266 #define ICH6_MAX_RIRB_ENTRIES   256
 267
 268 /* position fix mode */
 269 enum {
 270         POS_FIX_AUTO,
 271         POS_FIX_LPIB,
 272         POS_FIX_POSBUF,
 273 };
 274
 275 /* Defines for ATI HD Audio support in SB450 south bridge */
 276 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 277 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 278
 279 /* Defines for Nvidia HDA support */
 280 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 281 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 282 #define NVIDIA_HDA_ISTRM_COH          0x4d
 283 #define NVIDIA_HDA_OSTRM_COH          0x4c
 284 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 285
 286 /* Defines for Intel SCH HDA snoop control */
 287 #define INTEL_SCH_HDA_DEVC      0x78
 288 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 289
 290 /* Define IN stream 0 FIFO size offset in VIA controller */
 291 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 292 /* Define VIA HD Audio Device ID*/
 293 #define VIA_HDAC_DEVICE_ID              0x3288
 294
 295
 296 /*
 297  */
 298
 299 struct azx_dev {
 300         struct snd_dma_buffer bdl; /* BDL buffer */
 301         u32 *posbuf;            /* position buffer pointer */
 302
 303         unsigned int bufsize;   /* size of the play buffer in bytes */
 304         unsigned int period_bytes; /* size of the period in bytes */
 305         unsigned int frags;     /* number for period in the play buffer */
 306         unsigned int fifo_size; /* FIFO size */
 307
 308         void __iomem *sd_addr;  /* stream descriptor pointer */
 309
 310         u32 sd_int_sta_mask;    /* stream int status mask */
 311
 312         /* pcm support */
 313         struct snd_pcm_substream *substream;    /* assigned substream,
 314                                                  * set in PCM open
 315                                                  */
 316         unsigned int format_val;        /* format value to be set in the
 317                                          * controller and the codec
 318                                          */
 319         unsigned char stream_tag;       /* assigned stream */
 320         unsigned char index;            /* stream index */
 321
 322         unsigned int opened :1;
 323         unsigned int running :1;
 324         unsigned int irq_pending :1;
 325         unsigned int irq_ignore :1;
 326         /*
 327          * For VIA:
 328          *  A flag to ensure DMA position is 0
 329          *  when link position is not greater than FIFO size
 330          */
 331         unsigned int insufficient :1;
 332 };
 333
 334 /* CORB/RIRB */
 335 struct azx_rb {
 336         u32 *buf;               /* CORB/RIRB buffer
 337                                  * Each CORB entry is 4byte, RIRB is 8byte
 338                                  */
 339         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 340         /* for RIRB */
 341         unsigned short rp, wp;  /* read/write pointers */
 342         int cmds;               /* number of pending requests */
 343         u32 res;                /* last read value */
 344 };
 345
 346 struct azx {
 347         struct snd_card *card;
 348         struct pci_dev *pci;
 349         int dev_index;
 350
 351         /* chip type specific */
 352         int driver_type;
 353         int playback_streams;
 354         int playback_index_offset;
 355         int capture_streams;
 356         int capture_index_offset;
 357         int num_streams;
 358
 359         /* pci resources */
 360         unsigned long addr;
 361         void __iomem *remap_addr;
 362         int irq;
 363
 364         /* locks */
 365         spinlock_t reg_lock;
 366         struct mutex open_mutex;
 367
 368         /* streams (x num_streams) */
 369         struct azx_dev *azx_dev;
 370
 371         /* PCM */
 372         struct snd_pcm *pcm[AZX_MAX_PCMS];
 373
 374         /* HD codec */
 375         unsigned short codec_mask;
 376         struct hda_bus *bus;
 377
 378         /* CORB/RIRB */
 379         struct azx_rb corb;
 380         struct azx_rb rirb;
 381
 382         /* CORB/RIRB and position buffers */
 383         struct snd_dma_buffer rb;
 384         struct snd_dma_buffer posbuf;
 385
 386         /* flags */
 387         int position_fix;
 388         unsigned int running :1;
 389         unsigned int initialized :1;
 390         unsigned int single_cmd :1;
 391         unsigned int polling_mode :1;
 392         unsigned int msi :1;
 393         unsigned int irq_pending_warned :1;
 394         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 395
 396         /* for debugging */
 397         unsigned int last_cmd;  /* last issued command (to sync) */
 398
 399         /* for pending irqs */
 400         struct work_struct irq_pending_work;
 401
 402         /* reboot notifier (for mysterious hangup problem at power-down) */
 403         struct notifier_block reboot_notifier;
 404 };
 405
 406 /* driver types */
 407 enum {
 408         AZX_DRIVER_ICH,
 409         AZX_DRIVER_SCH,
 410         AZX_DRIVER_ATI,
 411         AZX_DRIVER_ATIHDMI,
 412         AZX_DRIVER_VIA,
 413         AZX_DRIVER_SIS,
 414         AZX_DRIVER_ULI,
 415         AZX_DRIVER_NVIDIA,
 416         AZX_DRIVER_TERA,
 417         AZX_NUM_DRIVERS, /* keep this as last entry */
 418 };
 419
 420 static char *driver_short_names[] __devinitdata = {
 421         [AZX_DRIVER_ICH] = "HDA Intel",
 422         [AZX_DRIVER_SCH] = "HDA Intel MID",
 423         [AZX_DRIVER_ATI] = "HDA ATI SB",
 424         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 425         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 426         [AZX_DRIVER_SIS] = "HDA SIS966",
 427         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 428         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 429         [AZX_DRIVER_TERA] = "HDA Teradici",
 430 };
 431
 432 /*
 433  * macros for easy use
 434  */
 435 #define azx_writel(chip,reg,value) \
 436         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 437 #define azx_readl(chip,reg) \
 438         readl((chip)->remap_addr + ICH6_REG_##reg)
 439 #define azx_writew(chip,reg,value) \
 440         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 441 #define azx_readw(chip,reg) \
 442         readw((chip)->remap_addr + ICH6_REG_##reg)
 443 #define azx_writeb(chip,reg,value) \
 444         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 445 #define azx_readb(chip,reg) \
 446         readb((chip)->remap_addr + ICH6_REG_##reg)
 447
 448 #define azx_sd_writel(dev,reg,value) \
 449         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 450 #define azx_sd_readl(dev,reg) \
 451         readl((dev)->sd_addr + ICH6_REG_##reg)
 452 #define azx_sd_writew(dev,reg,value) \
 453         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 454 #define azx_sd_readw(dev,reg) \
 455         readw((dev)->sd_addr + ICH6_REG_##reg)
 456 #define azx_sd_writeb(dev,reg,value) \
 457         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 458 #define azx_sd_readb(dev,reg) \
 459         readb((dev)->sd_addr + ICH6_REG_##reg)
 460
 461 /* for pcm support */
 462 #define get_azx_dev(substream) (substream->runtime->private_data)
 463
 464 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 465
 466 /*
 467  * Interface for HD codec
 468  */
 469
 470 /*
 471  * CORB / RIRB interface
 472  */
 473 static int azx_alloc_cmd_io(struct azx *chip)
 474 {
 475         int err;
 476
 477         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 478         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 479                                   snd_dma_pci_data(chip->pci),
 480                                   PAGE_SIZE, &chip->rb);
 481         if (err < 0) {
 482                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 483                 return err;
 484         }
 485         return 0;
 486 }
 487
 488 static void azx_init_cmd_io(struct azx *chip)
 489 {
 490         /* CORB set up */
 491         chip->corb.addr = chip->rb.addr;
 492         chip->corb.buf = (u32 *)chip->rb.area;
 493         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 494         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 495
 496         /* set the corb size to 256 entries (ULI requires explicitly) */
 497         azx_writeb(chip, CORBSIZE, 0x02);
 498         /* set the corb write pointer to 0 */
 499         azx_writew(chip, CORBWP, 0);
 500         /* reset the corb hw read pointer */
 501         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 502         /* enable corb dma */
 503         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 504
 505         /* RIRB set up */
 506         chip->rirb.addr = chip->rb.addr + 2048;
 507         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 508         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 509         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 510
 511         /* set the rirb size to 256 entries (ULI requires explicitly) */
 512         azx_writeb(chip, RIRBSIZE, 0x02);
 513         /* reset the rirb hw write pointer */
 514         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 515         /* set N=1, get RIRB response interrupt for new entry */
 516         azx_writew(chip, RINTCNT, 1);
 517         /* enable rirb dma and response irq */
 518         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 519         chip->rirb.rp = chip->rirb.cmds = 0;
 520 }
 521
 522 static void azx_free_cmd_io(struct azx *chip)
 523 {
 524         /* disable ringbuffer DMAs */
 525         azx_writeb(chip, RIRBCTL, 0);
 526         azx_writeb(chip, CORBCTL, 0);
 527 }
 528
 529 /* send a command */
 530 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
 531 {
 532         struct azx *chip = codec->bus->private_data;
 533         unsigned int wp;
 534
 535         /* add command to corb */
 536         wp = azx_readb(chip, CORBWP);
 537         wp++;
 538         wp %= ICH6_MAX_CORB_ENTRIES;
 539
 540         spin_lock_irq(&chip->reg_lock);
 541         chip->rirb.cmds++;
 542         chip->corb.buf[wp] = cpu_to_le32(val);
 543         azx_writel(chip, CORBWP, wp);
 544         spin_unlock_irq(&chip->reg_lock);
 545
 546         return 0;
 547 }
 548
 549 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 550
 551 /* retrieve RIRB entry - called from interrupt handler */
 552 static void azx_update_rirb(struct azx *chip)
 553 {
 554         unsigned int rp, wp;
 555         u32 res, res_ex;
 556
 557         wp = azx_readb(chip, RIRBWP);
 558         if (wp == chip->rirb.wp)
 559                 return;
 560         chip->rirb.wp = wp;
 561
 562         while (chip->rirb.rp != wp) {
 563                 chip->rirb.rp++;
 564                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 565
 566                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 567                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 568                 res = le32_to_cpu(chip->rirb.buf[rp]);
 569                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 570                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 571                 else if (chip->rirb.cmds) {
 572                         chip->rirb.res = res;
 573                         smp_wmb();
 574                         chip->rirb.cmds--;
 575                 }
 576         }
 577 }
 578
 579 /* receive a response */
 580 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
 581 {
 582         struct azx *chip = codec->bus->private_data;
 583         unsigned long timeout;
 584
 585  again:
 586         timeout = jiffies + msecs_to_jiffies(1000);
 587         for (;;) {
 588                 if (chip->polling_mode) {
 589                         spin_lock_irq(&chip->reg_lock);
 590                         azx_update_rirb(chip);
 591                         spin_unlock_irq(&chip->reg_lock);
 592                 }
 593                 if (!chip->rirb.cmds) {
 594                         smp_rmb();
 595                         return chip->rirb.res; /* the last value */
 596                 }
 597                 if (time_after(jiffies, timeout))
 598                         break;
 599                 if (codec->bus->needs_damn_long_delay)
 600                         msleep(2); /* temporary workaround */
 601                 else {
 602                         udelay(10);
 603                         cond_resched();
 604                 }
 605         }
 606
 607         if (chip->msi) {
 608                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 609                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 610                 free_irq(chip->irq, chip);
 611                 chip->irq = -1;
 612                 pci_disable_msi(chip->pci);
 613                 chip->msi = 0;
 614                 if (azx_acquire_irq(chip, 1) < 0)
 615                         return -1;
 616                 goto again;
 617         }
 618
 619         if (!chip->polling_mode) {
 620                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 621                            "switching to polling mode: last cmd=0x%08x\n",
 622                            chip->last_cmd);
 623                 chip->polling_mode = 1;
 624                 goto again;
 625         }
 626
 627         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 628                    "switching to single_cmd mode: last cmd=0x%08x\n",
 629                    chip->last_cmd);
 630         chip->rirb.rp = azx_readb(chip, RIRBWP);
 631         chip->rirb.cmds = 0;
 632         /* switch to single_cmd mode */
 633         chip->single_cmd = 1;
 634         azx_free_cmd_io(chip);
 635         return -1;
 636 }
 637
 638 /*
 639  * Use the single immediate command instead of CORB/RIRB for simplicity
 640  *
 641  * Note: according to Intel, this is not preferred use.  The command was
 642  *       intended for the BIOS only, and may get confused with unsolicited
 643  *       responses.  So, we shouldn't use it for normal operation from the
 644  *       driver.
 645  *       I left the codes, however, for debugging/testing purposes.
 646  */
 647
 648 /* send a command */
 649 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
 650 {
 651         struct azx *chip = codec->bus->private_data;
 652         int timeout = 50;
 653
 654         while (timeout--) {
 655                 /* check ICB busy bit */
 656                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 657                         /* Clear IRV valid bit */
 658                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 659                                    ICH6_IRS_VALID);
 660                         azx_writel(chip, IC, val);
 661                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 662                                    ICH6_IRS_BUSY);
 663                         return 0;
 664                 }
 665                 udelay(1);
 666         }
 667         if (printk_ratelimit())
 668                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 669                            azx_readw(chip, IRS), val);
 670         return -EIO;
 671 }
 672
 673 /* receive a response */
 674 static unsigned int azx_single_get_response(struct hda_codec *codec)
 675 {
 676         struct azx *chip = codec->bus->private_data;
 677         int timeout = 50;
 678
 679         while (timeout--) {
 680                 /* check IRV busy bit */
 681                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 682                         return azx_readl(chip, IR);
 683                 udelay(1);
 684         }
 685         if (printk_ratelimit())
 686                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 687                            azx_readw(chip, IRS));
 688         return (unsigned int)-1;
 689 }
 690
 691 /*
 692  * The below are the main callbacks from hda_codec.
 693  *
 694  * They are just the skeleton to call sub-callbacks according to the
 695  * current setting of chip->single_cmd.
 696  */
 697
 698 /* send a command */
 699 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
 700                         int direct, unsigned int verb,
 701                         unsigned int para)
 702 {
 703         struct azx *chip = codec->bus->private_data;
 704         u32 val;
 705
 706         val = (u32)(codec->addr & 0x0f) << 28;
 707         val |= (u32)direct << 27;
 708         val |= (u32)nid << 20;
 709         val |= verb << 8;
 710         val |= para;
 711         chip->last_cmd = val;
 712
 713         if (chip->single_cmd)
 714                 return azx_single_send_cmd(codec, val);
 715         else
 716                 return azx_corb_send_cmd(codec, val);
 717 }
 718
 719 /* get a response */
 720 static unsigned int azx_get_response(struct hda_codec *codec)
 721 {
 722         struct azx *chip = codec->bus->private_data;
 723         if (chip->single_cmd)
 724                 return azx_single_get_response(codec);
 725         else
 726                 return azx_rirb_get_response(codec);
 727 }
 728
 729 #ifdef CONFIG_SND_HDA_POWER_SAVE
 730 static void azx_power_notify(struct hda_codec *codec);
 731 #endif
 732
 733 /* reset codec link */
 734 static int azx_reset(struct azx *chip)
 735 {
 736         int count;
 737
 738         /* clear STATESTS */
 739         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 740
 741         /* reset controller */
 742         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 743
 744         count = 50;
 745         while (azx_readb(chip, GCTL) && --count)
 746                 msleep(1);
 747
 748         /* delay for >= 100us for codec PLL to settle per spec
 749          * Rev 0.9 section 5.5.1
 750          */
 751         msleep(1);
 752
 753         /* Bring controller out of reset */
 754         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 755
 756         count = 50;
 757         while (!azx_readb(chip, GCTL) && --count)
 758                 msleep(1);
 759
 760         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 761         msleep(1);
 762
 763         /* check to see if controller is ready */
 764         if (!azx_readb(chip, GCTL)) {
 765                 snd_printd("azx_reset: controller not ready!\n");
 766                 return -EBUSY;
 767         }
 768
 769         /* Accept unsolicited responses */
 770         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 771
 772         /* detect codecs */
 773         if (!chip->codec_mask) {
 774                 chip->codec_mask = azx_readw(chip, STATESTS);
 775                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 776         }
 777
 778         return 0;
 779 }
 780
 781
 782 /*
 783  * Lowlevel interface
 784  */
 785
 786 /* enable interrupts */
 787 static void azx_int_enable(struct azx *chip)
 788 {
 789         /* enable controller CIE and GIE */
 790         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 791                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 792 }
 793
 794 /* disable interrupts */
 795 static void azx_int_disable(struct azx *chip)
 796 {
 797         int i;
 798
 799         /* disable interrupts in stream descriptor */
 800         for (i = 0; i < chip->num_streams; i++) {
 801                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 802                 azx_sd_writeb(azx_dev, SD_CTL,
 803                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 804         }
 805
 806         /* disable SIE for all streams */
 807         azx_writeb(chip, INTCTL, 0);
 808
 809         /* disable controller CIE and GIE */
 810         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 811                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 812 }
 813
 814 /* clear interrupts */
 815 static void azx_int_clear(struct azx *chip)
 816 {
 817         int i;
 818
 819         /* clear stream status */
 820         for (i = 0; i < chip->num_streams; i++) {
 821                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 822                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 823         }
 824
 825         /* clear STATESTS */
 826         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 827
 828         /* clear rirb status */
 829         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 830
 831         /* clear int status */
 832         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 833 }
 834
 835 /* start a stream */
 836 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 837 {
 838         /*
 839          * Before stream start, initialize parameter
 840          */
 841         azx_dev->insufficient = 1;
 842
 843         /* enable SIE */
 844         azx_writeb(chip, INTCTL,
 845                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 846         /* set DMA start and interrupt mask */
 847         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 848                       SD_CTL_DMA_START | SD_INT_MASK);
 849 }
 850
 851 /* stop a stream */
 852 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 853 {
 854         /* stop DMA */
 855         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 856                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 857         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 858         /* disable SIE */
 859         azx_writeb(chip, INTCTL,
 860                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 861 }
 862
 863
 864 /*
 865  * reset and start the controller registers
 866  */
 867 static void azx_init_chip(struct azx *chip)
 868 {
 869         if (chip->initialized)
 870                 return;
 871
 872         /* reset controller */
 873         azx_reset(chip);
 874
 875         /* initialize interrupts */
 876         azx_int_clear(chip);
 877         azx_int_enable(chip);
 878
 879         /* initialize the codec command I/O */
 880         if (!chip->single_cmd)
 881                 azx_init_cmd_io(chip);
 882
 883         /* program the position buffer */
 884         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 885         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 886
 887         chip->initialized = 1;
 888 }
 889
 890 /*
 891  * initialize the PCI registers
 892  */
 893 /* update bits in a PCI register byte */
 894 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 895                             unsigned char mask, unsigned char val)
 896 {
 897         unsigned char data;
 898
 899         pci_read_config_byte(pci, reg, &data);
 900         data &= ~mask;
 901         data |= (val & mask);
 902         pci_write_config_byte(pci, reg, data);
 903 }
 904
 905 static void azx_init_pci(struct azx *chip)
 906 {
 907         unsigned short snoop;
 908
 909         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 910          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 911          * Ensuring these bits are 0 clears playback static on some HD Audio
 912          * codecs
 913          */
 914         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 915
 916         switch (chip->driver_type) {
 917         case AZX_DRIVER_ATI:
 918                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 919                 update_pci_byte(chip->pci,
 920                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 921                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 922                 break;
 923         case AZX_DRIVER_NVIDIA:
 924                 /* For NVIDIA HDA, enable snoop */
 925                 update_pci_byte(chip->pci,
 926                                 NVIDIA_HDA_TRANSREG_ADDR,
 927                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 928                 update_pci_byte(chip->pci,
 929                                 NVIDIA_HDA_ISTRM_COH,
 930                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 931                 update_pci_byte(chip->pci,
 932                                 NVIDIA_HDA_OSTRM_COH,
 933                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 934                 break;
 935         case AZX_DRIVER_SCH:
 936                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 937                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 938                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 939                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 940                         pci_read_config_word(chip->pci,
 941                                 INTEL_SCH_HDA_DEVC, &snoop);
 942                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 943                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 944                                 ? "Failed" : "OK");
 945                 }
 946                 break;
 947
 948         }
 949 }
 950
 951
 952 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 953
 954 /*
 955  * interrupt handler
 956  */
 957 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 958 {
 959         struct azx *chip = dev_id;
 960         struct azx_dev *azx_dev;
 961         u32 status;
 962         int i;
 963
 964         spin_lock(&chip->reg_lock);
 965
 966         status = azx_readl(chip, INTSTS);
 967         if (status == 0) {
 968                 spin_unlock(&chip->reg_lock);
 969                 return IRQ_NONE;
 970         }
 971
 972         for (i = 0; i < chip->num_streams; i++) {
 973                 azx_dev = &chip->azx_dev[i];
 974                 if (status & azx_dev->sd_int_sta_mask) {
 975                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 976                         if (!azx_dev->substream || !azx_dev->running)
 977                                 continue;
 978                         /* ignore the first dummy IRQ (due to pos_adj) */
 979                         if (azx_dev->irq_ignore) {
 980                                 azx_dev->irq_ignore = 0;
 981                                 continue;
 982                         }
 983                         /* check whether this IRQ is really acceptable */
 984                         if (azx_position_ok(chip, azx_dev)) {
 985                                 azx_dev->irq_pending = 0;
 986                                 spin_unlock(&chip->reg_lock);
 987                                 snd_pcm_period_elapsed(azx_dev->substream);
 988                                 spin_lock(&chip->reg_lock);
 989                         } else {
 990                                 /* bogus IRQ, process it later */
 991                                 azx_dev->irq_pending = 1;
 992                                 schedule_work(&chip->irq_pending_work);
 993                         }
 994                 }
 995         }
 996
 997         /* clear rirb int */
 998         status = azx_readb(chip, RIRBSTS);
 999         if (status & RIRB_INT_MASK) {
1000                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1001                         azx_update_rirb(chip);
1002                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1003         }
1004
1005 #if 0
1006         /* clear state status int */
1007         if (azx_readb(chip, STATESTS) & 0x04)
1008                 azx_writeb(chip, STATESTS, 0x04);
1009 #endif
1010         spin_unlock(&chip->reg_lock);
1011
1012         return IRQ_HANDLED;
1013 }
1014
1015
1016 /*
1017  * set up a BDL entry
1018  */
1019 static int setup_bdle(struct snd_pcm_substream *substream,
1020                       struct azx_dev *azx_dev, u32 **bdlp,
1021                       int ofs, int size, int with_ioc)
1022 {
1023         u32 *bdl = *bdlp;
1024
1025         while (size > 0) {
1026                 dma_addr_t addr;
1027                 int chunk;
1028
1029                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1030                         return -EINVAL;
1031
1032                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1033                 /* program the address field of the BDL entry */
1034                 bdl[0] = cpu_to_le32((u32)addr);
1035                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1036                 /* program the size field of the BDL entry */
1037                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1038                 bdl[2] = cpu_to_le32(chunk);
1039                 /* program the IOC to enable interrupt
1040                  * only when the whole fragment is processed
1041                  */
1042                 size -= chunk;
1043                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1044                 bdl += 4;
1045                 azx_dev->frags++;
1046                 ofs += chunk;
1047         }
1048         *bdlp = bdl;
1049         return ofs;
1050 }
1051
1052 /*
1053  * set up BDL entries
1054  */
1055 static int azx_setup_periods(struct azx *chip,
1056                              struct snd_pcm_substream *substream,
1057                              struct azx_dev *azx_dev)
1058 {
1059         u32 *bdl;
1060         int i, ofs, periods, period_bytes;
1061         int pos_adj;
1062
1063         /* reset BDL address */
1064         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1065         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1066
1067         period_bytes = snd_pcm_lib_period_bytes(substream);
1068         azx_dev->period_bytes = period_bytes;
1069         periods = azx_dev->bufsize / period_bytes;
1070
1071         /* program the initial BDL entries */
1072         bdl = (u32 *)azx_dev->bdl.area;
1073         ofs = 0;
1074         azx_dev->frags = 0;
1075         azx_dev->irq_ignore = 0;
1076         pos_adj = bdl_pos_adj[chip->dev_index];
1077         if (pos_adj > 0) {
1078                 struct snd_pcm_runtime *runtime = substream->runtime;
1079                 int pos_align = pos_adj;
1080                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1081                 if (!pos_adj)
1082                         pos_adj = pos_align;
1083                 else
1084                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1085                                 pos_align;
1086                 pos_adj = frames_to_bytes(runtime, pos_adj);
1087                 if (pos_adj >= period_bytes) {
1088                         snd_printk(KERN_WARNING "Too big adjustment %d\n",
1089                                    bdl_pos_adj[chip->dev_index]);
1090                         pos_adj = 0;
1091                 } else {
1092                         ofs = setup_bdle(substream, azx_dev,
1093                                          &bdl, ofs, pos_adj, 1);
1094                         if (ofs < 0)
1095                                 goto error;
1096                         azx_dev->irq_ignore = 1;
1097                 }
1098         } else
1099                 pos_adj = 0;
1100         for (i = 0; i < periods; i++) {
1101                 if (i == periods - 1 && pos_adj)
1102                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1103                                          period_bytes - pos_adj, 0);
1104                 else
1105                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1106                                          period_bytes, 1);
1107                 if (ofs < 0)
1108                         goto error;
1109         }
1110         return 0;
1111
1112  error:
1113         snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1114                    azx_dev->bufsize, period_bytes);
1115         /* reset */
1116         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1117         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1118         return -EINVAL;
1119 }
1120
1121 /*
1122  * set up the SD for streaming
1123  */
1124 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1125 {
1126         unsigned char val;
1127         int timeout;
1128
1129         /* make sure the run bit is zero for SD */
1130         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1131                       ~SD_CTL_DMA_START);
1132         /* reset stream */
1133         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1134                       SD_CTL_STREAM_RESET);
1135         udelay(3);
1136         timeout = 300;
1137         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1138                --timeout)
1139                 ;
1140         val &= ~SD_CTL_STREAM_RESET;
1141         azx_sd_writeb(azx_dev, SD_CTL, val);
1142         udelay(3);
1143
1144         timeout = 300;
1145         /* waiting for hardware to report that the stream is out of reset */
1146         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1147                --timeout)
1148                 ;
1149
1150         /* program the stream_tag */
1151         azx_sd_writel(azx_dev, SD_CTL,
1152                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1153                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1154
1155         /* program the length of samples in cyclic buffer */
1156         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1157
1158         /* program the stream format */
1159         /* this value needs to be the same as the one programmed */
1160         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1161
1162         /* program the stream LVI (last valid index) of the BDL */
1163         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1164
1165         /* program the BDL address */
1166         /* lower BDL address */
1167         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1168         /* upper BDL address */
1169         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1170
1171         /* enable the position buffer */
1172         if (chip->position_fix == POS_FIX_POSBUF ||
1173             chip->position_fix == POS_FIX_AUTO ||
1174             chip->via_dmapos_patch) {
1175                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1176                         azx_writel(chip, DPLBASE,
1177                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1178         }
1179
1180         /* set the interrupt enable bits in the descriptor control register */
1181         azx_sd_writel(azx_dev, SD_CTL,
1182                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1183
1184         return 0;
1185 }
1186
1187
1188 /*
1189  * Codec initialization
1190  */
1191
1192 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1193 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1194         [AZX_DRIVER_TERA] = 1,
1195 };
1196
1197 /* number of slots to probe as default
1198  * this can be different from azx_max_codecs[] -- e.g. some boards
1199  * report wrongly the non-existing 4th slot availability
1200  */
1201 static unsigned int azx_default_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1202         [AZX_DRIVER_ICH] = 3,
1203         [AZX_DRIVER_ATI] = 3,
1204 };
1205
1206 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1207                                       unsigned int codec_probe_mask)
1208 {
1209         struct hda_bus_template bus_temp;
1210         int c, codecs, audio_codecs, err;
1211         int def_slots, max_slots;
1212
1213         memset(&bus_temp, 0, sizeof(bus_temp));
1214         bus_temp.private_data = chip;
1215         bus_temp.modelname = model;
1216         bus_temp.pci = chip->pci;
1217         bus_temp.ops.command = azx_send_cmd;
1218         bus_temp.ops.get_response = azx_get_response;
1219 #ifdef CONFIG_SND_HDA_POWER_SAVE
1220         bus_temp.ops.pm_notify = azx_power_notify;
1221 #endif
1222
1223         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1224         if (err < 0)
1225                 return err;
1226
1227         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1228                 chip->bus->needs_damn_long_delay = 1;
1229
1230         codecs = audio_codecs = 0;
1231         max_slots = azx_max_codecs[chip->driver_type];
1232         if (!max_slots)
1233                 max_slots = AZX_MAX_CODECS;
1234         def_slots = azx_default_codecs[chip->driver_type];
1235         if (!def_slots)
1236                 def_slots = max_slots;
1237         for (c = 0; c < def_slots; c++) {
1238                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1239                         struct hda_codec *codec;
1240                         err = snd_hda_codec_new(chip->bus, c, &codec);
1241                         if (err < 0)
1242                                 continue;
1243                         codecs++;
1244                         if (codec->afg)
1245                                 audio_codecs++;
1246                 }
1247         }
1248         if (!audio_codecs) {
1249                 /* probe additional slots if no codec is found */
1250                 for (; c < max_slots; c++) {
1251                         if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1252                                 err = snd_hda_codec_new(chip->bus, c, NULL);
1253                                 if (err < 0)
1254                                         continue;
1255                                 codecs++;
1256                         }
1257                 }
1258         }
1259         if (!codecs) {
1260                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1261                 return -ENXIO;
1262         }
1263
1264         return 0;
1265 }
1266
1267
1268 /*
1269  * PCM support
1270  */
1271
1272 /* assign a stream for the PCM */
1273 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1274 {
1275         int dev, i, nums;
1276         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1277                 dev = chip->playback_index_offset;
1278                 nums = chip->playback_streams;
1279         } else {
1280                 dev = chip->capture_index_offset;
1281                 nums = chip->capture_streams;
1282         }
1283         for (i = 0; i < nums; i++, dev++)
1284                 if (!chip->azx_dev[dev].opened) {
1285                         chip->azx_dev[dev].opened = 1;
1286                         return &chip->azx_dev[dev];
1287                 }
1288         return NULL;
1289 }
1290
1291 /* release the assigned stream */
1292 static inline void azx_release_device(struct azx_dev *azx_dev)
1293 {
1294         azx_dev->opened = 0;
1295 }
1296
1297 static struct snd_pcm_hardware azx_pcm_hw = {
1298         .info =                 (SNDRV_PCM_INFO_MMAP |
1299                                  SNDRV_PCM_INFO_INTERLEAVED |
1300                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1301                                  SNDRV_PCM_INFO_MMAP_VALID |
1302                                  /* No full-resume yet implemented */
1303                                  /* SNDRV_PCM_INFO_RESUME |*/
1304                                  SNDRV_PCM_INFO_PAUSE |
1305                                  SNDRV_PCM_INFO_SYNC_START),
1306         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1307         .rates =                SNDRV_PCM_RATE_48000,
1308         .rate_min =             48000,
1309         .rate_max =             48000,
1310         .channels_min =         2,
1311         .channels_max =         2,
1312         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1313         .period_bytes_min =     128,
1314         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1315         .periods_min =          2,
1316         .periods_max =          AZX_MAX_FRAG,
1317         .fifo_size =            0,
1318 };
1319
1320 struct azx_pcm {
1321         struct azx *chip;
1322         struct hda_codec *codec;
1323         struct hda_pcm_stream *hinfo[2];
1324 };
1325
1326 static int azx_pcm_open(struct snd_pcm_substream *substream)
1327 {
1328         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1329         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1330         struct azx *chip = apcm->chip;
1331         struct azx_dev *azx_dev;
1332         struct snd_pcm_runtime *runtime = substream->runtime;
1333         unsigned long flags;
1334         int err;
1335
1336         mutex_lock(&chip->open_mutex);
1337         azx_dev = azx_assign_device(chip, substream->stream);
1338         if (azx_dev == NULL) {
1339                 mutex_unlock(&chip->open_mutex);
1340                 return -EBUSY;
1341         }
1342         runtime->hw = azx_pcm_hw;
1343         runtime->hw.channels_min = hinfo->channels_min;
1344         runtime->hw.channels_max = hinfo->channels_max;
1345         runtime->hw.formats = hinfo->formats;
1346         runtime->hw.rates = hinfo->rates;
1347         snd_pcm_limit_hw_rates(runtime);
1348         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1349         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1350                                    128);
1351         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1352                                    128);
1353         snd_hda_power_up(apcm->codec);
1354         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1355         if (err < 0) {
1356                 azx_release_device(azx_dev);
1357                 snd_hda_power_down(apcm->codec);
1358                 mutex_unlock(&chip->open_mutex);
1359                 return err;
1360         }
1361         spin_lock_irqsave(&chip->reg_lock, flags);
1362         azx_dev->substream = substream;
1363         azx_dev->running = 0;
1364         spin_unlock_irqrestore(&chip->reg_lock, flags);
1365
1366         runtime->private_data = azx_dev;
1367         snd_pcm_set_sync(substream);
1368         mutex_unlock(&chip->open_mutex);
1369         return 0;
1370 }
1371
1372 static int azx_pcm_close(struct snd_pcm_substream *substream)
1373 {
1374         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1375         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1376         struct azx *chip = apcm->chip;
1377         struct azx_dev *azx_dev = get_azx_dev(substream);
1378         unsigned long flags;
1379
1380         mutex_lock(&chip->open_mutex);
1381         spin_lock_irqsave(&chip->reg_lock, flags);
1382         azx_dev->substream = NULL;
1383         azx_dev->running = 0;
1384         spin_unlock_irqrestore(&chip->reg_lock, flags);
1385         azx_release_device(azx_dev);
1386         hinfo->ops.close(hinfo, apcm->codec, substream);
1387         snd_hda_power_down(apcm->codec);
1388         mutex_unlock(&chip->open_mutex);
1389         return 0;
1390 }
1391
1392 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1393                              struct snd_pcm_hw_params *hw_params)
1394 {
1395         return snd_pcm_lib_malloc_pages(substream,
1396                                         params_buffer_bytes(hw_params));
1397 }
1398
1399 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1400 {
1401         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1402         struct azx_dev *azx_dev = get_azx_dev(substream);
1403         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1404
1405         /* reset BDL address */
1406         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1407         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1408         azx_sd_writel(azx_dev, SD_CTL, 0);
1409
1410         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1411
1412         return snd_pcm_lib_free_pages(substream);
1413 }
1414
1415 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1416 {
1417         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1418         struct azx *chip = apcm->chip;
1419         struct azx_dev *azx_dev = get_azx_dev(substream);
1420         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1421         struct snd_pcm_runtime *runtime = substream->runtime;
1422
1423         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1424         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1425                                                          runtime->channels,
1426                                                          runtime->format,
1427                                                          hinfo->maxbps);
1428         if (!azx_dev->format_val) {
1429                 snd_printk(KERN_ERR SFX
1430                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1431                            runtime->rate, runtime->channels, runtime->format);
1432                 return -EINVAL;
1433         }
1434
1435         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1436                     azx_dev->bufsize, azx_dev->format_val);
1437         if (azx_setup_periods(chip, substream, azx_dev) < 0)
1438                 return -EINVAL;
1439         azx_setup_controller(chip, azx_dev);
1440         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1441                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1442         else
1443                 azx_dev->fifo_size = 0;
1444
1445         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1446                                   azx_dev->format_val, substream);
1447 }
1448
1449 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1450 {
1451         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1452         struct azx *chip = apcm->chip;
1453         struct azx_dev *azx_dev;
1454         struct snd_pcm_substream *s;
1455         int start, nsync = 0, sbits = 0;
1456         int nwait, timeout;
1457
1458         switch (cmd) {
1459         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1460         case SNDRV_PCM_TRIGGER_RESUME:
1461         case SNDRV_PCM_TRIGGER_START:
1462                 start = 1;
1463                 break;
1464         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1465         case SNDRV_PCM_TRIGGER_SUSPEND:
1466         case SNDRV_PCM_TRIGGER_STOP:
1467                 start = 0;
1468                 break;
1469         default:
1470                 return -EINVAL;
1471         }
1472
1473         snd_pcm_group_for_each_entry(s, substream) {
1474                 if (s->pcm->card != substream->pcm->card)
1475                         continue;
1476                 azx_dev = get_azx_dev(s);
1477                 sbits |= 1 << azx_dev->index;
1478                 nsync++;
1479                 snd_pcm_trigger_done(s, substream);
1480         }
1481
1482         spin_lock(&chip->reg_lock);
1483         if (nsync > 1) {
1484                 /* first, set SYNC bits of corresponding streams */
1485                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1486         }
1487         snd_pcm_group_for_each_entry(s, substream) {
1488                 if (s->pcm->card != substream->pcm->card)
1489                         continue;
1490                 azx_dev = get_azx_dev(s);
1491                 if (start)
1492                         azx_stream_start(chip, azx_dev);
1493                 else
1494                         azx_stream_stop(chip, azx_dev);
1495                 azx_dev->running = start;
1496         }
1497         spin_unlock(&chip->reg_lock);
1498         if (start) {
1499                 if (nsync == 1)
1500                         return 0;
1501                 /* wait until all FIFOs get ready */
1502                 for (timeout = 5000; timeout; timeout--) {
1503                         nwait = 0;
1504                         snd_pcm_group_for_each_entry(s, substream) {
1505                                 if (s->pcm->card != substream->pcm->card)
1506                                         continue;
1507                                 azx_dev = get_azx_dev(s);
1508                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1509                                       SD_STS_FIFO_READY))
1510                                         nwait++;
1511                         }
1512                         if (!nwait)
1513                                 break;
1514                         cpu_relax();
1515                 }
1516         } else {
1517                 /* wait until all RUN bits are cleared */
1518                 for (timeout = 5000; timeout; timeout--) {
1519                         nwait = 0;
1520                         snd_pcm_group_for_each_entry(s, substream) {
1521                                 if (s->pcm->card != substream->pcm->card)
1522                                         continue;
1523                                 azx_dev = get_azx_dev(s);
1524                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1525                                     SD_CTL_DMA_START)
1526                                         nwait++;
1527                         }
1528                         if (!nwait)
1529                                 break;
1530                         cpu_relax();
1531                 }
1532         }
1533         if (nsync > 1) {
1534                 spin_lock(&chip->reg_lock);
1535                 /* reset SYNC bits */
1536                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1537                 spin_unlock(&chip->reg_lock);
1538         }
1539         return 0;
1540 }
1541
1542 /* get the current DMA position with correction on VIA chips */
1543 static unsigned int azx_via_get_position(struct azx *chip,
1544                                          struct azx_dev *azx_dev)
1545 {
1546         unsigned int link_pos, mini_pos, bound_pos;
1547         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1548         unsigned int fifo_size;
1549
1550         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1551         if (azx_dev->index >= 4) {
1552                 /* Playback, no problem using link position */
1553                 return link_pos;
1554         }
1555
1556         /* Capture */
1557         /* For new chipset,
1558          * use mod to get the DMA position just like old chipset
1559          */
1560         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1561         mod_dma_pos %= azx_dev->period_bytes;
1562
1563         /* azx_dev->fifo_size can't get FIFO size of in stream.
1564          * Get from base address + offset.
1565          */
1566         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1567
1568         if (azx_dev->insufficient) {
1569                 /* Link position never gather than FIFO size */
1570                 if (link_pos <= fifo_size)
1571                         return 0;
1572
1573                 azx_dev->insufficient = 0;
1574         }
1575
1576         if (link_pos <= fifo_size)
1577                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1578         else
1579                 mini_pos = link_pos - fifo_size;
1580
1581         /* Find nearest previous boudary */
1582         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1583         mod_link_pos = link_pos % azx_dev->period_bytes;
1584         if (mod_link_pos >= fifo_size)
1585                 bound_pos = link_pos - mod_link_pos;
1586         else if (mod_dma_pos >= mod_mini_pos)
1587                 bound_pos = mini_pos - mod_mini_pos;
1588         else {
1589                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1590                 if (bound_pos >= azx_dev->bufsize)
1591                         bound_pos = 0;
1592         }
1593
1594         /* Calculate real DMA position we want */
1595         return bound_pos + mod_dma_pos;
1596 }
1597
1598 static unsigned int azx_get_position(struct azx *chip,
1599                                      struct azx_dev *azx_dev)
1600 {
1601         unsigned int pos;
1602
1603         if (chip->via_dmapos_patch)
1604                 pos = azx_via_get_position(chip, azx_dev);
1605         else if (chip->position_fix == POS_FIX_POSBUF ||
1606                  chip->position_fix == POS_FIX_AUTO) {
1607                 /* use the position buffer */
1608                 pos = le32_to_cpu(*azx_dev->posbuf);
1609         } else {
1610                 /* read LPIB */
1611                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1612         }
1613         if (pos >= azx_dev->bufsize)
1614                 pos = 0;
1615         return pos;
1616 }
1617
1618 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1619 {
1620         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1621         struct azx *chip = apcm->chip;
1622         struct azx_dev *azx_dev = get_azx_dev(substream);
1623         return bytes_to_frames(substream->runtime,
1624                                azx_get_position(chip, azx_dev));
1625 }
1626
1627 /*
1628  * Check whether the current DMA position is acceptable for updating
1629  * periods.  Returns non-zero if it's OK.
1630  *
1631  * Many HD-audio controllers appear pretty inaccurate about
1632  * the update-IRQ timing.  The IRQ is issued before actually the
1633  * data is processed.  So, we need to process it afterwords in a
1634  * workqueue.
1635  */
1636 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1637 {
1638         unsigned int pos;
1639
1640         pos = azx_get_position(chip, azx_dev);
1641         if (chip->position_fix == POS_FIX_AUTO) {
1642                 if (!pos) {
1643                         printk(KERN_WARNING
1644                                "hda-intel: Invalid position buffer, "
1645                                "using LPIB read method instead.\n");
1646                         chip->position_fix = POS_FIX_LPIB;
1647                         pos = azx_get_position(chip, azx_dev);
1648                 } else
1649                         chip->position_fix = POS_FIX_POSBUF;
1650         }
1651
1652         if (!bdl_pos_adj[chip->dev_index])
1653                 return 1; /* no delayed ack */
1654         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1655                 return 0; /* NG - it's below the period boundary */
1656         return 1; /* OK, it's fine */
1657 }
1658
1659 /*
1660  * The work for pending PCM period updates.
1661  */
1662 static void azx_irq_pending_work(struct work_struct *work)
1663 {
1664         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1665         int i, pending;
1666
1667         if (!chip->irq_pending_warned) {
1668                 printk(KERN_WARNING
1669                        "hda-intel: IRQ timing workaround is activated "
1670                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1671                        chip->card->number);
1672                 chip->irq_pending_warned = 1;
1673         }
1674
1675         for (;;) {
1676                 pending = 0;
1677                 spin_lock_irq(&chip->reg_lock);
1678                 for (i = 0; i < chip->num_streams; i++) {
1679                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1680                         if (!azx_dev->irq_pending ||
1681                             !azx_dev->substream ||
1682                             !azx_dev->running)
1683                                 continue;
1684                         if (azx_position_ok(chip, azx_dev)) {
1685                                 azx_dev->irq_pending = 0;
1686                                 spin_unlock(&chip->reg_lock);
1687                                 snd_pcm_period_elapsed(azx_dev->substream);
1688                                 spin_lock(&chip->reg_lock);
1689                         } else
1690                                 pending++;
1691                 }
1692                 spin_unlock_irq(&chip->reg_lock);
1693                 if (!pending)
1694                         return;
1695                 cond_resched();
1696         }
1697 }
1698
1699 /* clear irq_pending flags and assure no on-going workq */
1700 static void azx_clear_irq_pending(struct azx *chip)
1701 {
1702         int i;
1703
1704         spin_lock_irq(&chip->reg_lock);
1705         for (i = 0; i < chip->num_streams; i++)
1706                 chip->azx_dev[i].irq_pending = 0;
1707         spin_unlock_irq(&chip->reg_lock);
1708         flush_scheduled_work();
1709 }
1710
1711 static struct snd_pcm_ops azx_pcm_ops = {
1712         .open = azx_pcm_open,
1713         .close = azx_pcm_close,
1714         .ioctl = snd_pcm_lib_ioctl,
1715         .hw_params = azx_pcm_hw_params,
1716         .hw_free = azx_pcm_hw_free,
1717         .prepare = azx_pcm_prepare,
1718         .trigger = azx_pcm_trigger,
1719         .pointer = azx_pcm_pointer,
1720         .page = snd_pcm_sgbuf_ops_page,
1721 };
1722
1723 static void azx_pcm_free(struct snd_pcm *pcm)
1724 {
1725         kfree(pcm->private_data);
1726 }
1727
1728 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1729                                       struct hda_pcm *cpcm)
1730 {
1731         int err;
1732         struct snd_pcm *pcm;
1733         struct azx_pcm *apcm;
1734
1735         /* if no substreams are defined for both playback and capture,
1736          * it's just a placeholder.  ignore it.
1737          */
1738         if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1739                 return 0;
1740
1741         if (snd_BUG_ON(!cpcm->name))
1742                 return -EINVAL;
1743
1744         err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1745                           cpcm->stream[0].substreams,
1746                           cpcm->stream[1].substreams,
1747                           &pcm);
1748         if (err < 0)
1749                 return err;
1750         strcpy(pcm->name, cpcm->name);
1751         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1752         if (apcm == NULL)
1753                 return -ENOMEM;
1754         apcm->chip = chip;
1755         apcm->codec = codec;
1756         apcm->hinfo[0] = &cpcm->stream[0];
1757         apcm->hinfo[1] = &cpcm->stream[1];
1758         pcm->private_data = apcm;
1759         pcm->private_free = azx_pcm_free;
1760         if (cpcm->stream[0].substreams)
1761                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1762         if (cpcm->stream[1].substreams)
1763                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1764         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1765                                               snd_dma_pci_data(chip->pci),
1766                                               1024 * 64, 32 * 1024 * 1024);
1767         chip->pcm[cpcm->device] = pcm;
1768         return 0;
1769 }
1770
1771 static int __devinit azx_pcm_create(struct azx *chip)
1772 {
1773         static const char *dev_name[HDA_PCM_NTYPES] = {
1774                 "Audio", "SPDIF", "HDMI", "Modem"
1775         };
1776         /* starting device index for each PCM type */
1777         static int dev_idx[HDA_PCM_NTYPES] = {
1778                 [HDA_PCM_TYPE_AUDIO] = 0,
1779                 [HDA_PCM_TYPE_SPDIF] = 1,
1780                 [HDA_PCM_TYPE_HDMI] = 3,
1781                 [HDA_PCM_TYPE_MODEM] = 6
1782         };
1783         /* normal audio device indices; not linear to keep compatibility */
1784         static int audio_idx[4] = { 0, 2, 4, 5 };
1785         struct hda_codec *codec;
1786         int c, err;
1787         int num_devs[HDA_PCM_NTYPES];
1788
1789         err = snd_hda_build_pcms(chip->bus);
1790         if (err < 0)
1791                 return err;
1792
1793         /* create audio PCMs */
1794         memset(num_devs, 0, sizeof(num_devs));
1795         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1796                 for (c = 0; c < codec->num_pcms; c++) {
1797                         struct hda_pcm *cpcm = &codec->pcm_info[c];
1798                         int type = cpcm->pcm_type;
1799                         switch (type) {
1800                         case HDA_PCM_TYPE_AUDIO:
1801                                 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1802                                         snd_printk(KERN_WARNING
1803                                                    "Too many audio devices\n");
1804                                         continue;
1805                                 }
1806                                 cpcm->device = audio_idx[num_devs[type]];
1807                                 break;
1808                         case HDA_PCM_TYPE_SPDIF:
1809                         case HDA_PCM_TYPE_HDMI:
1810                         case HDA_PCM_TYPE_MODEM:
1811                                 if (num_devs[type]) {
1812                                         snd_printk(KERN_WARNING
1813                                                    "%s already defined\n",
1814                                                    dev_name[type]);
1815                                         continue;
1816                                 }
1817                                 cpcm->device = dev_idx[type];
1818                                 break;
1819                         default:
1820                                 snd_printk(KERN_WARNING
1821                                            "Invalid PCM type %d\n", type);
1822                                 continue;
1823                         }
1824                         num_devs[type]++;
1825                         err = create_codec_pcm(chip, codec, cpcm);
1826                         if (err < 0)
1827                                 return err;
1828                 }
1829         }
1830         return 0;
1831 }
1832
1833 /*
1834  * mixer creation - all stuff is implemented in hda module
1835  */
1836 static int __devinit azx_mixer_create(struct azx *chip)
1837 {
1838         return snd_hda_build_controls(chip->bus);
1839 }
1840
1841
1842 /*
1843  * initialize SD streams
1844  */
1845 static int __devinit azx_init_stream(struct azx *chip)
1846 {
1847         int i;
1848
1849         /* initialize each stream (aka device)
1850          * assign the starting bdl address to each stream (device)
1851          * and initialize
1852          */
1853         for (i = 0; i < chip->num_streams; i++) {
1854                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1855                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1856                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1857                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1858                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1859                 azx_dev->sd_int_sta_mask = 1 << i;
1860                 /* stream tag: must be non-zero and unique */
1861                 azx_dev->index = i;
1862                 azx_dev->stream_tag = i + 1;
1863         }
1864
1865         return 0;
1866 }
1867
1868 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1869 {
1870         if (request_irq(chip->pci->irq, azx_interrupt,
1871                         chip->msi ? 0 : IRQF_SHARED,
1872                         "HDA Intel", chip)) {
1873                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1874                        "disabling device\n", chip->pci->irq);
1875                 if (do_disconnect)
1876                         snd_card_disconnect(chip->card);
1877                 return -1;
1878         }
1879         chip->irq = chip->pci->irq;
1880         pci_intx(chip->pci, !chip->msi);
1881         return 0;
1882 }
1883
1884
1885 static void azx_stop_chip(struct azx *chip)
1886 {
1887         if (!chip->initialized)
1888                 return;
1889
1890         /* disable interrupts */
1891         azx_int_disable(chip);
1892         azx_int_clear(chip);
1893
1894         /* disable CORB/RIRB */
1895         azx_free_cmd_io(chip);
1896
1897         /* disable position buffer */
1898         azx_writel(chip, DPLBASE, 0);
1899         azx_writel(chip, DPUBASE, 0);
1900
1901         chip->initialized = 0;
1902 }
1903
1904 #ifdef CONFIG_SND_HDA_POWER_SAVE
1905 /* power-up/down the controller */
1906 static void azx_power_notify(struct hda_codec *codec)
1907 {
1908         struct azx *chip = codec->bus->private_data;
1909         struct hda_codec *c;
1910         int power_on = 0;
1911
1912         list_for_each_entry(c, &codec->bus->codec_list, list) {
1913                 if (c->power_on) {
1914                         power_on = 1;
1915                         break;
1916                 }
1917         }
1918         if (power_on)
1919                 azx_init_chip(chip);
1920         else if (chip->running && power_save_controller)
1921                 azx_stop_chip(chip);
1922 }
1923 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1924
1925 #ifdef CONFIG_PM
1926 /*
1927  * power management
1928  */
1929 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1930 {
1931         struct snd_card *card = pci_get_drvdata(pci);
1932         struct azx *chip = card->private_data;
1933         int i;
1934
1935         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1936         azx_clear_irq_pending(chip);
1937         for (i = 0; i < AZX_MAX_PCMS; i++)
1938                 snd_pcm_suspend_all(chip->pcm[i]);
1939         if (chip->initialized)
1940                 snd_hda_suspend(chip->bus, state);
1941         azx_stop_chip(chip);
1942         if (chip->irq >= 0) {
1943                 free_irq(chip->irq, chip);
1944                 chip->irq = -1;
1945         }
1946         if (chip->msi)
1947                 pci_disable_msi(chip->pci);
1948         pci_disable_device(pci);
1949         pci_save_state(pci);
1950         pci_set_power_state(pci, pci_choose_state(pci, state));
1951         return 0;
1952 }
1953
1954 static int azx_resume(struct pci_dev *pci)
1955 {
1956         struct snd_card *card = pci_get_drvdata(pci);
1957         struct azx *chip = card->private_data;
1958
1959         pci_set_power_state(pci, PCI_D0);
1960         pci_restore_state(pci);
1961         if (pci_enable_device(pci) < 0) {
1962                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1963                        "disabling device\n");
1964                 snd_card_disconnect(card);
1965                 return -EIO;
1966         }
1967         pci_set_master(pci);
1968         if (chip->msi)
1969                 if (pci_enable_msi(pci) < 0)
1970                         chip->msi = 0;
1971         if (azx_acquire_irq(chip, 1) < 0)
1972                 return -EIO;
1973         azx_init_pci(chip);
1974
1975         if (snd_hda_codecs_inuse(chip->bus))
1976                 azx_init_chip(chip);
1977
1978         snd_hda_resume(chip->bus);
1979         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1980         return 0;
1981 }
1982 #endif /* CONFIG_PM */
1983
1984
1985 /*
1986  * reboot notifier for hang-up problem at power-down
1987  */
1988 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1989 {
1990         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1991         azx_stop_chip(chip);
1992         return NOTIFY_OK;
1993 }
1994
1995 static void azx_notifier_register(struct azx *chip)
1996 {
1997         chip->reboot_notifier.notifier_call = azx_halt;
1998         register_reboot_notifier(&chip->reboot_notifier);
1999 }
2000
2001 static void azx_notifier_unregister(struct azx *chip)
2002 {
2003         if (chip->reboot_notifier.notifier_call)
2004                 unregister_reboot_notifier(&chip->reboot_notifier);
2005 }
2006
2007 /*
2008  * destructor
2009  */
2010 static int azx_free(struct azx *chip)
2011 {
2012         int i;
2013
2014         azx_notifier_unregister(chip);
2015
2016         if (chip->initialized) {
2017                 azx_clear_irq_pending(chip);
2018                 for (i = 0; i < chip->num_streams; i++)
2019                         azx_stream_stop(chip, &chip->azx_dev[i]);
2020                 azx_stop_chip(chip);
2021         }
2022
2023         if (chip->irq >= 0)
2024                 free_irq(chip->irq, (void*)chip);
2025         if (chip->msi)
2026                 pci_disable_msi(chip->pci);
2027         if (chip->remap_addr)
2028                 iounmap(chip->remap_addr);
2029
2030         if (chip->azx_dev) {
2031                 for (i = 0; i < chip->num_streams; i++)
2032                         if (chip->azx_dev[i].bdl.area)
2033                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2034         }
2035         if (chip->rb.area)
2036                 snd_dma_free_pages(&chip->rb);
2037         if (chip->posbuf.area)
2038                 snd_dma_free_pages(&chip->posbuf);
2039         pci_release_regions(chip->pci);
2040         pci_disable_device(chip->pci);
2041         kfree(chip->azx_dev);
2042         kfree(chip);
2043
2044         return 0;
2045 }
2046
2047 static int azx_dev_free(struct snd_device *device)
2048 {
2049         return azx_free(device->device_data);
2050 }
2051
2052 /*
2053  * white/black-listing for position_fix
2054  */
2055 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2056         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2057         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2058         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2059         {}
2060 };
2061
2062 static int __devinit check_position_fix(struct azx *chip, int fix)
2063 {
2064         const struct snd_pci_quirk *q;
2065
2066         /* Check VIA HD Audio Controller exist */
2067         if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
2068             chip->pci->device == VIA_HDAC_DEVICE_ID) {
2069                 chip->via_dmapos_patch = 1;
2070                 /* Use link position directly, avoid any transfer problem. */
2071                 return POS_FIX_LPIB;
2072         }
2073         chip->via_dmapos_patch = 0;
2074
2075         if (fix == POS_FIX_AUTO) {
2076                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2077                 if (q) {
2078                         printk(KERN_INFO
2079                                     "hda_intel: position_fix set to %d "
2080                                     "for device %04x:%04x\n",
2081                                     q->value, q->subvendor, q->subdevice);
2082                         return q->value;
2083                 }
2084         }
2085         return fix;
2086 }
2087
2088 /*
2089  * black-lists for probe_mask
2090  */
2091 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2092         /* Thinkpad often breaks the controller communication when accessing
2093          * to the non-working (or non-existing) modem codec slot.
2094          */
2095         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2096         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2097         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2098         {}
2099 };
2100
2101 static void __devinit check_probe_mask(struct azx *chip, int dev)
2102 {
2103         const struct snd_pci_quirk *q;
2104
2105         if (probe_mask[dev] == -1) {
2106                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2107                 if (q) {
2108                         printk(KERN_INFO
2109                                "hda_intel: probe_mask set to 0x%x "
2110                                "for device %04x:%04x\n",
2111                                q->value, q->subvendor, q->subdevice);
2112                         probe_mask[dev] = q->value;
2113                 }
2114         }
2115 }
2116
2117
2118 /*
2119  * constructor
2120  */
2121 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2122                                 int dev, int driver_type,
2123                                 struct azx **rchip)
2124 {
2125         struct azx *chip;
2126         int i, err;
2127         unsigned short gcap;
2128         static struct snd_device_ops ops = {
2129                 .dev_free = azx_dev_free,
2130         };
2131
2132         *rchip = NULL;
2133
2134         err = pci_enable_device(pci);
2135         if (err < 0)
2136                 return err;
2137
2138         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2139         if (!chip) {
2140                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2141                 pci_disable_device(pci);
2142                 return -ENOMEM;
2143         }
2144
2145         spin_lock_init(&chip->reg_lock);
2146         mutex_init(&chip->open_mutex);
2147         chip->card = card;
2148         chip->pci = pci;
2149         chip->irq = -1;
2150         chip->driver_type = driver_type;
2151         chip->msi = enable_msi;
2152         chip->dev_index = dev;
2153         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2154
2155         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2156         check_probe_mask(chip, dev);
2157
2158         chip->single_cmd = single_cmd;
2159
2160         if (bdl_pos_adj[dev] < 0) {
2161                 switch (chip->driver_type) {
2162                 case AZX_DRIVER_ICH:
2163                         bdl_pos_adj[dev] = 1;
2164                         break;
2165                 default:
2166                         bdl_pos_adj[dev] = 32;
2167                         break;
2168                 }
2169         }
2170
2171 #if BITS_PER_LONG != 64
2172         /* Fix up base address on ULI M5461 */
2173         if (chip->driver_type == AZX_DRIVER_ULI) {
2174                 u16 tmp3;
2175                 pci_read_config_word(pci, 0x40, &tmp3);
2176                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2177                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2178         }
2179 #endif
2180
2181         err = pci_request_regions(pci, "ICH HD audio");
2182         if (err < 0) {
2183                 kfree(chip);
2184                 pci_disable_device(pci);
2185                 return err;
2186         }
2187
2188         chip->addr = pci_resource_start(pci, 0);
2189         chip->remap_addr = pci_ioremap_bar(pci, 0);
2190         if (chip->remap_addr == NULL) {
2191                 snd_printk(KERN_ERR SFX "ioremap error\n");
2192                 err = -ENXIO;
2193                 goto errout;
2194         }
2195
2196         if (chip->msi)
2197                 if (pci_enable_msi(pci) < 0)
2198                         chip->msi = 0;
2199
2200         if (azx_acquire_irq(chip, 0) < 0) {
2201                 err = -EBUSY;
2202                 goto errout;
2203         }
2204
2205         pci_set_master(pci);
2206         synchronize_irq(chip->irq);
2207
2208         gcap = azx_readw(chip, GCAP);
2209         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2210
2211         /* allow 64bit DMA address if supported by H/W */
2212         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2213                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2214
2215         /* read number of streams from GCAP register instead of using
2216          * hardcoded value
2217          */
2218         chip->capture_streams = (gcap >> 8) & 0x0f;
2219         chip->playback_streams = (gcap >> 12) & 0x0f;
2220         if (!chip->playback_streams && !chip->capture_streams) {
2221                 /* gcap didn't give any info, switching to old method */
2222
2223                 switch (chip->driver_type) {
2224                 case AZX_DRIVER_ULI:
2225                         chip->playback_streams = ULI_NUM_PLAYBACK;
2226                         chip->capture_streams = ULI_NUM_CAPTURE;
2227                         break;
2228                 case AZX_DRIVER_ATIHDMI:
2229                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2230                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2231                         break;
2232                 default:
2233                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2234                         chip->capture_streams = ICH6_NUM_CAPTURE;
2235                         break;
2236                 }
2237         }
2238         chip->capture_index_offset = 0;
2239         chip->playback_index_offset = chip->capture_streams;
2240         chip->num_streams = chip->playback_streams + chip->capture_streams;
2241         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2242                                 GFP_KERNEL);
2243         if (!chip->azx_dev) {
2244                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2245                 goto errout;
2246         }
2247
2248         for (i = 0; i < chip->num_streams; i++) {
2249                 /* allocate memory for the BDL for each stream */
2250                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2251                                           snd_dma_pci_data(chip->pci),
2252                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2253                 if (err < 0) {
2254                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2255                         goto errout;
2256                 }
2257         }
2258         /* allocate memory for the position buffer */
2259         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2260                                   snd_dma_pci_data(chip->pci),
2261                                   chip->num_streams * 8, &chip->posbuf);
2262         if (err < 0) {
2263                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2264                 goto errout;
2265         }
2266         /* allocate CORB/RIRB */
2267         if (!chip->single_cmd) {
2268                 err = azx_alloc_cmd_io(chip);
2269                 if (err < 0)
2270                         goto errout;
2271         }
2272
2273         /* initialize streams */
2274         azx_init_stream(chip);
2275
2276         /* initialize chip */
2277         azx_init_pci(chip);
2278         azx_init_chip(chip);
2279
2280         /* codec detection */
2281         if (!chip->codec_mask) {
2282                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2283                 err = -ENODEV;
2284                 goto errout;
2285         }
2286
2287         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2288         if (err <0) {
2289                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2290                 goto errout;
2291         }
2292
2293         strcpy(card->driver, "HDA-Intel");
2294         strcpy(card->shortname, driver_short_names[chip->driver_type]);
2295         sprintf(card->longname, "%s at 0x%lx irq %i",
2296                 card->shortname, chip->addr, chip->irq);
2297
2298         *rchip = chip;
2299         return 0;
2300
2301  errout:
2302         azx_free(chip);
2303         return err;
2304 }
2305
2306 static void power_down_all_codecs(struct azx *chip)
2307 {
2308 #ifdef CONFIG_SND_HDA_POWER_SAVE
2309         /* The codecs were powered up in snd_hda_codec_new().
2310          * Now all initialization done, so turn them down if possible
2311          */
2312         struct hda_codec *codec;
2313         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2314                 snd_hda_power_down(codec);
2315         }
2316 #endif
2317 }
2318
2319 static int __devinit azx_probe(struct pci_dev *pci,
2320                                const struct pci_device_id *pci_id)
2321 {
2322         static int dev;
2323         struct snd_card *card;
2324         struct azx *chip;
2325         int err;
2326
2327         if (dev >= SNDRV_CARDS)
2328                 return -ENODEV;
2329         if (!enable[dev]) {
2330                 dev++;
2331                 return -ENOENT;
2332         }
2333
2334         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2335         if (!card) {
2336                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2337                 return -ENOMEM;
2338         }
2339
2340         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2341         if (err < 0) {
2342                 snd_card_free(card);
2343                 return err;
2344         }
2345         card->private_data = chip;
2346
2347         /* create codec instances */
2348         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2349         if (err < 0) {
2350                 snd_card_free(card);
2351                 return err;
2352         }
2353
2354         /* create PCM streams */
2355         err = azx_pcm_create(chip);
2356         if (err < 0) {
2357                 snd_card_free(card);
2358                 return err;
2359         }
2360
2361         /* create mixer controls */
2362         err = azx_mixer_create(chip);
2363         if (err < 0) {
2364                 snd_card_free(card);
2365                 return err;
2366         }
2367
2368         snd_card_set_dev(card, &pci->dev);
2369
2370         err = snd_card_register(card);
2371         if (err < 0) {
2372                 snd_card_free(card);
2373                 return err;
2374         }
2375
2376         pci_set_drvdata(pci, card);
2377         chip->running = 1;
2378         power_down_all_codecs(chip);
2379         azx_notifier_register(chip);
2380
2381         dev++;
2382         return err;
2383 }
2384
2385 static void __devexit azx_remove(struct pci_dev *pci)
2386 {
2387         snd_card_free(pci_get_drvdata(pci));
2388         pci_set_drvdata(pci, NULL);
2389 }
2390
2391 /* PCI IDs */
2392 static struct pci_device_id azx_ids[] = {
2393         /* ICH 6..10 */
2394         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2395         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2396         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2397         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2398         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2399         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2400         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2401         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2402         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2403         /* PCH */
2404         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2405         /* SCH */
2406         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2407         /* ATI SB 450/600 */
2408         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2409         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2410         /* ATI HDMI */
2411         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2412         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2413         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2414         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2415         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2416         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2417         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2418         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2419         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2420         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2421         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2422         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2423         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2424         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2425         /* VIA VT8251/VT8237A */
2426         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2427         /* SIS966 */
2428         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2429         /* ULI M5461 */
2430         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2431         /* NVIDIA MCP */
2432         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2433         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2434         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2435         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2436         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2437         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2438         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2439         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2440         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2441         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2442         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2443         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2444         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2445         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2446         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2447         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2448         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2449         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2450         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2451         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2452         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2453         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2454         /* Teradici */
2455         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2456         { 0, }
2457 };
2458 MODULE_DEVICE_TABLE(pci, azx_ids);
2459
2460 /* pci_driver definition */
2461 static struct pci_driver driver = {
2462         .name = "HDA Intel",
2463         .id_table = azx_ids,
2464         .probe = azx_probe,
2465         .remove = __devexit_p(azx_remove),
2466 #ifdef CONFIG_PM
2467         .suspend = azx_suspend,
2468         .resume = azx_resume,
2469 #endif
2470 };
2471
2472 static int __init alsa_card_azx_init(void)
2473 {
2474         return pci_register_driver(&driver);
2475 }
2476
2477 static void __exit alsa_card_azx_exit(void)
2478 {
2479         pci_unregister_driver(&driver);
2480 }
2481
2482 module_init(alsa_card_azx_init)
2483 module_exit(alsa_card_azx_exit)