2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
53 #include <net/ieee80211_radiotap.h>
55 #include <asm/unaligned.h>
61 /* unaligned little endian access */
62 #define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63 #define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
70 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.1.1 (EXPERIMENTAL)");
87 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
109 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
112 static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
121 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
122 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
123 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
124 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
125 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
126 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
127 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
128 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
129 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
130 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
131 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
132 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
136 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
142 * Prototypes - PCI stack related functions
144 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
145 const struct pci_device_id *id);
146 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
148 static int ath5k_pci_suspend(struct pci_dev *pdev,
150 static int ath5k_pci_resume(struct pci_dev *pdev);
152 #define ath5k_pci_suspend NULL
153 #define ath5k_pci_resume NULL
154 #endif /* CONFIG_PM */
156 static struct pci_driver ath5k_pci_drv_id = {
158 .id_table = ath5k_pci_id_table,
159 .probe = ath5k_pci_probe,
160 .remove = __devexit_p(ath5k_pci_remove),
161 .suspend = ath5k_pci_suspend,
162 .resume = ath5k_pci_resume,
168 * Prototypes - MAC 802.11 stack related functions
170 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
171 struct ieee80211_tx_control *ctl);
172 static int ath5k_reset(struct ieee80211_hw *hw);
173 static int ath5k_start(struct ieee80211_hw *hw);
174 static void ath5k_stop(struct ieee80211_hw *hw);
175 static int ath5k_add_interface(struct ieee80211_hw *hw,
176 struct ieee80211_if_init_conf *conf);
177 static void ath5k_remove_interface(struct ieee80211_hw *hw,
178 struct ieee80211_if_init_conf *conf);
179 static int ath5k_config(struct ieee80211_hw *hw,
180 struct ieee80211_conf *conf);
181 static int ath5k_config_interface(struct ieee80211_hw *hw,
182 struct ieee80211_vif *vif,
183 struct ieee80211_if_conf *conf);
184 static void ath5k_configure_filter(struct ieee80211_hw *hw,
185 unsigned int changed_flags,
186 unsigned int *new_flags,
187 int mc_count, struct dev_mc_list *mclist);
188 static int ath5k_set_key(struct ieee80211_hw *hw,
189 enum set_key_cmd cmd,
190 const u8 *local_addr, const u8 *addr,
191 struct ieee80211_key_conf *key);
192 static int ath5k_get_stats(struct ieee80211_hw *hw,
193 struct ieee80211_low_level_stats *stats);
194 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
195 struct ieee80211_tx_queue_stats *stats);
196 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198 static int ath5k_beacon_update(struct ieee80211_hw *hw,
200 struct ieee80211_tx_control *ctl);
202 static struct ieee80211_ops ath5k_hw_ops = {
204 .start = ath5k_start,
206 .add_interface = ath5k_add_interface,
207 .remove_interface = ath5k_remove_interface,
208 .config = ath5k_config,
209 .config_interface = ath5k_config_interface,
210 .configure_filter = ath5k_configure_filter,
211 .set_key = ath5k_set_key,
212 .get_stats = ath5k_get_stats,
214 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
221 * Prototypes - Internal functions
224 static int ath5k_attach(struct pci_dev *pdev,
225 struct ieee80211_hw *hw);
226 static void ath5k_detach(struct pci_dev *pdev,
227 struct ieee80211_hw *hw);
228 /* Channel/mode setup */
229 static inline short ath5k_ieee2mhz(short chan);
230 static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
231 const struct ath5k_rate_table *rt,
233 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
234 struct ieee80211_channel *channels,
237 static int ath5k_getchannels(struct ieee80211_hw *hw);
238 static int ath5k_chan_set(struct ath5k_softc *sc,
239 struct ieee80211_channel *chan);
240 static void ath5k_setcurmode(struct ath5k_softc *sc,
242 static void ath5k_mode_setup(struct ath5k_softc *sc);
243 /* Descriptor setup */
244 static int ath5k_desc_alloc(struct ath5k_softc *sc,
245 struct pci_dev *pdev);
246 static void ath5k_desc_free(struct ath5k_softc *sc,
247 struct pci_dev *pdev);
249 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
250 struct ath5k_buf *bf);
251 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf,
253 struct ieee80211_tx_control *ctl);
255 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
256 struct ath5k_buf *bf)
261 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
263 dev_kfree_skb(bf->skb);
268 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
269 int qtype, int subtype);
270 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
271 static int ath5k_beaconq_config(struct ath5k_softc *sc);
272 static void ath5k_txq_drainq(struct ath5k_softc *sc,
273 struct ath5k_txq *txq);
274 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
275 static void ath5k_txq_release(struct ath5k_softc *sc);
277 static int ath5k_rx_start(struct ath5k_softc *sc);
278 static void ath5k_rx_stop(struct ath5k_softc *sc);
279 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
280 struct ath5k_desc *ds,
281 struct sk_buff *skb);
282 static void ath5k_tasklet_rx(unsigned long data);
284 static void ath5k_tx_processq(struct ath5k_softc *sc,
285 struct ath5k_txq *txq);
286 static void ath5k_tasklet_tx(unsigned long data);
287 /* Beacon handling */
288 static int ath5k_beacon_setup(struct ath5k_softc *sc,
289 struct ath5k_buf *bf,
290 struct ieee80211_tx_control *ctl);
291 static void ath5k_beacon_send(struct ath5k_softc *sc);
292 static void ath5k_beacon_config(struct ath5k_softc *sc);
294 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
296 u64 tsf = ath5k_hw_get_tsf64(ah);
298 if ((tsf & 0x7fff) < rstamp)
301 return (tsf & ~0x7fff) | rstamp;
304 /* Interrupt handling */
305 static int ath5k_init(struct ath5k_softc *sc);
306 static int ath5k_stop_locked(struct ath5k_softc *sc);
307 static int ath5k_stop_hw(struct ath5k_softc *sc);
308 static irqreturn_t ath5k_intr(int irq, void *dev_id);
309 static void ath5k_tasklet_reset(unsigned long data);
311 static void ath5k_calibrate(unsigned long data);
313 static void ath5k_led_off(unsigned long data);
314 static void ath5k_led_blink(struct ath5k_softc *sc,
317 static void ath5k_led_event(struct ath5k_softc *sc,
322 * Module init/exit functions
331 ret = pci_register_driver(&ath5k_pci_drv_id);
333 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
343 pci_unregister_driver(&ath5k_pci_drv_id);
345 ath5k_debug_finish();
348 module_init(init_ath5k_pci);
349 module_exit(exit_ath5k_pci);
352 /********************\
353 * PCI Initialization *
354 \********************/
357 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
359 const char *name = "xxxxx";
362 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
363 if (srev_names[i].sr_type != type)
365 if ((val & 0xff) < srev_names[i + 1].sr_val) {
366 name = srev_names[i].sr_name;
375 ath5k_pci_probe(struct pci_dev *pdev,
376 const struct pci_device_id *id)
379 struct ath5k_softc *sc;
380 struct ieee80211_hw *hw;
384 ret = pci_enable_device(pdev);
386 dev_err(&pdev->dev, "can't enable device\n");
390 /* XXX 32-bit addressing only */
391 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
393 dev_err(&pdev->dev, "32-bit DMA not available\n");
398 * Cache line size is used to size and align various
399 * structures used to communicate with the hardware.
401 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
404 * Linux 2.4.18 (at least) writes the cache line size
405 * register as a 16-bit wide register which is wrong.
406 * We must have this setup properly for rx buffer
407 * DMA to work so force a reasonable value here if it
410 csz = L1_CACHE_BYTES / sizeof(u32);
411 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
414 * The default setting of latency timer yields poor results,
415 * set it to the value used by other systems. It may be worth
416 * tweaking this setting more.
418 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
420 /* Enable bus mastering */
421 pci_set_master(pdev);
424 * Disable the RETRY_TIMEOUT register (0x41) to keep
425 * PCI Tx retries from interfering with C3 CPU state.
427 pci_write_config_byte(pdev, 0x41, 0);
429 ret = pci_request_region(pdev, 0, "ath5k");
431 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
435 mem = pci_iomap(pdev, 0, 0);
437 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
443 * Allocate hw (mac80211 main struct)
444 * and hw->priv (driver private data)
446 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
448 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
453 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
455 /* Initialize driver private data */
456 SET_IEEE80211_DEV(hw, &pdev->dev);
457 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
458 hw->extra_tx_headroom = 2;
459 hw->channel_change_time = 5000;
460 /* these names are misleading */
461 hw->max_rssi = -110; /* signal in dBm */
462 hw->max_noise = -110; /* noise in dBm */
463 hw->max_signal = 100; /* we will provide a percentage based on rssi */
468 ath5k_debug_init_device(sc);
471 * Mark the device as detached to avoid processing
472 * interrupts until setup is complete.
474 __set_bit(ATH_STAT_INVALID, sc->status);
476 sc->iobase = mem; /* So we can unmap it on detach */
477 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
478 sc->opmode = IEEE80211_IF_TYPE_STA;
479 mutex_init(&sc->lock);
480 spin_lock_init(&sc->rxbuflock);
481 spin_lock_init(&sc->txbuflock);
483 /* Set private data */
484 pci_set_drvdata(pdev, hw);
486 /* Enable msi for devices that support it */
487 pci_enable_msi(pdev);
489 /* Setup interrupt handler */
490 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
492 ATH5K_ERR(sc, "request_irq failed\n");
496 /* Initialize device */
497 sc->ah = ath5k_hw_attach(sc, id->driver_data);
498 if (IS_ERR(sc->ah)) {
499 ret = PTR_ERR(sc->ah);
503 /* Finish private driver data initialization */
504 ret = ath5k_attach(pdev, hw);
508 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
509 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
511 sc->ah->ah_phy_revision);
513 if(!sc->ah->ah_single_chip){
514 /* Single chip radio (!RF5111) */
515 if(sc->ah->ah_radio_5ghz_revision && !sc->ah->ah_radio_2ghz_revision) {
516 /* No 5GHz support -> report 2GHz radio */
517 if(!test_bit(MODE_IEEE80211A, sc->ah->ah_capabilities.cap_mode)){
518 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
519 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
520 sc->ah->ah_radio_5ghz_revision);
521 /* No 2GHz support (5110 and some 5Ghz only cards) -> report 5Ghz radio */
522 } else if(!test_bit(MODE_IEEE80211B, sc->ah->ah_capabilities.cap_mode)){
523 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
524 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
525 sc->ah->ah_radio_5ghz_revision);
526 /* Multiband radio */
528 ATH5K_INFO(sc, "RF%s multiband radio found"
530 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
531 sc->ah->ah_radio_5ghz_revision);
534 /* Multi chip radio (RF5111 - RF2111) -> report both 2GHz/5GHz radios */
535 else if(sc->ah->ah_radio_5ghz_revision && sc->ah->ah_radio_2ghz_revision){
536 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
537 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
538 sc->ah->ah_radio_5ghz_revision);
539 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
540 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_2ghz_revision),
541 sc->ah->ah_radio_2ghz_revision);
546 /* ready to process interrupts */
547 __clear_bit(ATH_STAT_INVALID, sc->status);
551 ath5k_hw_detach(sc->ah);
553 free_irq(pdev->irq, sc);
555 pci_disable_msi(pdev);
556 ieee80211_free_hw(hw);
558 pci_iounmap(pdev, mem);
560 pci_release_region(pdev, 0);
562 pci_disable_device(pdev);
567 static void __devexit
568 ath5k_pci_remove(struct pci_dev *pdev)
570 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
571 struct ath5k_softc *sc = hw->priv;
573 ath5k_debug_finish_device(sc);
574 ath5k_detach(pdev, hw);
575 ath5k_hw_detach(sc->ah);
576 free_irq(pdev->irq, sc);
577 pci_disable_msi(pdev);
578 pci_iounmap(pdev, sc->iobase);
579 pci_release_region(pdev, 0);
580 pci_disable_device(pdev);
581 ieee80211_free_hw(hw);
586 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
588 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
589 struct ath5k_softc *sc = hw->priv;
591 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
592 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
595 pci_save_state(pdev);
596 pci_disable_device(pdev);
597 pci_set_power_state(pdev, PCI_D3hot);
603 ath5k_pci_resume(struct pci_dev *pdev)
605 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
606 struct ath5k_softc *sc = hw->priv;
607 struct ath5k_hw *ah = sc->ah;
610 err = pci_set_power_state(pdev, PCI_D0);
614 err = pci_enable_device(pdev);
618 pci_restore_state(pdev);
620 * Suspend/Resume resets the PCI configuration space, so we have to
621 * re-disable the RETRY_TIMEOUT register (0x41) to keep
622 * PCI Tx retries from interfering with C3 CPU state
624 pci_write_config_byte(pdev, 0x41, 0);
627 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
628 ath5k_hw_set_gpio_output(ah, sc->led_pin);
629 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
633 * Reset the key cache since some parts do not
634 * reset the contents on initial power up or resume.
636 * FIXME: This may need to be revisited when mac80211 becomes
637 * aware of suspend/resume.
639 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
640 ath5k_hw_reset_key(ah, i);
644 #endif /* CONFIG_PM */
648 /***********************\
649 * Driver Initialization *
650 \***********************/
653 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
655 struct ath5k_softc *sc = hw->priv;
656 struct ath5k_hw *ah = sc->ah;
661 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
664 * Check if the MAC has multi-rate retry support.
665 * We do this by trying to setup a fake extended
666 * descriptor. MAC's that don't have support will
667 * return false w/o doing anything. MAC's that do
668 * support it will return true w/o doing anything.
670 if (ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0))
671 __set_bit(ATH_STAT_MRRETRY, sc->status);
674 * Reset the key cache since some parts do not
675 * reset the contents on initial power up.
677 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
678 ath5k_hw_reset_key(ah, i);
681 * Collect the channel list. The 802.11 layer
682 * is resposible for filtering this list based
683 * on settings like the phy mode and regulatory
684 * domain restrictions.
686 ret = ath5k_getchannels(hw);
688 ATH5K_ERR(sc, "can't get channels\n");
692 /* NB: setup here so ath5k_rate_update is happy */
693 if (test_bit(MODE_IEEE80211A, ah->ah_modes))
694 ath5k_setcurmode(sc, MODE_IEEE80211A);
696 ath5k_setcurmode(sc, MODE_IEEE80211B);
699 * Allocate tx+rx descriptors and populate the lists.
701 ret = ath5k_desc_alloc(sc, pdev);
703 ATH5K_ERR(sc, "can't allocate descriptors\n");
708 * Allocate hardware transmit queues: one queue for
709 * beacon frames and one data queue for each QoS
710 * priority. Note that hw functions handle reseting
711 * these queues at the needed time.
713 ret = ath5k_beaconq_setup(ah);
715 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
720 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
721 if (IS_ERR(sc->txq)) {
722 ATH5K_ERR(sc, "can't setup xmit queue\n");
723 ret = PTR_ERR(sc->txq);
727 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
728 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
729 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
730 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
731 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
733 sc->led_on = 0; /* low true */
735 * Auto-enable soft led processing for IBM cards and for
736 * 5211 minipci cards.
738 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
739 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
740 __set_bit(ATH_STAT_LEDSOFT, sc->status);
743 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
744 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
745 __set_bit(ATH_STAT_LEDSOFT, sc->status);
748 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
749 ath5k_hw_set_gpio_output(ah, sc->led_pin);
750 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
753 ath5k_hw_get_lladdr(ah, mac);
754 SET_IEEE80211_PERM_ADDR(hw, mac);
755 /* All MAC address bits matter for ACKs */
756 memset(sc->bssidmask, 0xff, ETH_ALEN);
757 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
759 ret = ieee80211_register_hw(hw);
761 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
767 ath5k_txq_release(sc);
769 ath5k_hw_release_tx_queue(ah, sc->bhalq);
771 ath5k_desc_free(sc, pdev);
777 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
779 struct ath5k_softc *sc = hw->priv;
782 * NB: the order of these is important:
783 * o call the 802.11 layer before detaching ath5k_hw to
784 * insure callbacks into the driver to delete global
785 * key cache entries can be handled
786 * o reclaim the tx queue data structures after calling
787 * the 802.11 layer as we'll get called back to reclaim
788 * node state and potentially want to use them
789 * o to cleanup the tx queues the hal is called, so detach
791 * XXX: ??? detach ath5k_hw ???
792 * Other than that, it's straightforward...
794 ieee80211_unregister_hw(hw);
795 ath5k_desc_free(sc, pdev);
796 ath5k_txq_release(sc);
797 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
800 * NB: can't reclaim these until after ieee80211_ifdetach
801 * returns because we'll get called back to reclaim node
802 * state and potentially want to use them.
809 /********************\
810 * Channel/mode setup *
811 \********************/
814 * Convert IEEE channel number to MHz frequency.
817 ath5k_ieee2mhz(short chan)
819 if (chan <= 14 || chan >= 27)
820 return ieee80211chan2mhz(chan);
822 return 2212 + chan * 20;
826 ath5k_copy_rates(struct ieee80211_rate *rates,
827 const struct ath5k_rate_table *rt,
830 unsigned int i, count;
835 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
836 if (!rt->rates[i].valid)
838 rates->rate = rt->rates[i].rate_kbps / 100;
839 rates->val = rt->rates[i].rate_code;
840 rates->flags = rt->rates[i].modulation;
850 ath5k_copy_channels(struct ath5k_hw *ah,
851 struct ieee80211_channel *channels,
855 static const struct { unsigned int mode, mask, chan; } map[] = {
856 [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A },
857 [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T },
858 [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B },
859 [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G },
860 [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG },
862 static const struct ath5k_regchannel chans_2ghz[] =
863 IEEE80211_CHANNELS_2GHZ;
864 static const struct ath5k_regchannel chans_5ghz[] =
865 IEEE80211_CHANNELS_5GHZ;
866 const struct ath5k_regchannel *chans;
867 enum ath5k_regdom dmn;
868 unsigned int i, count, size, chfreq, all, f, ch;
870 if (!test_bit(mode, ah->ah_modes))
873 all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1;
876 case MODE_IEEE80211A:
877 case MODE_ATHEROS_TURBO:
878 /* 1..220, but 2GHz frequencies are filtered by check_channel */
879 size = all ? 220 : ARRAY_SIZE(chans_5ghz);
881 dmn = ath5k_regdom2flag(ah->ah_regdomain,
882 IEEE80211_CHANNELS_5GHZ_MIN);
883 chfreq = CHANNEL_5GHZ;
885 case MODE_IEEE80211B:
886 case MODE_IEEE80211G:
887 case MODE_ATHEROS_TURBOG:
888 size = all ? 26 : ARRAY_SIZE(chans_2ghz);
890 dmn = ath5k_regdom2flag(ah->ah_regdomain,
891 IEEE80211_CHANNELS_2GHZ_MIN);
892 chfreq = CHANNEL_2GHZ;
895 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
899 for (i = 0, count = 0; i < size && max > 0; i++) {
900 ch = all ? i + 1 : chans[i].chan;
901 f = ath5k_ieee2mhz(ch);
902 /* Check if channel is supported by the chipset */
903 if (!ath5k_channel_ok(ah, f, chfreq))
906 /* Match regulation domain */
907 if (!all && !(IEEE80211_DMN(chans[i].domain) &
911 if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode)
914 /* Write channel and increment counter */
917 channels->val = map[mode].chan;
926 /* Only tries to register modes our EEPROM says it can support */
927 #define REGISTER_MODE(m) do { \
928 ret = ath5k_register_mode(hw, m); \
934 ath5k_register_mode(struct ieee80211_hw *hw, u8 m)
936 struct ath5k_softc *sc = hw->priv;
937 struct ieee80211_hw_mode *modes = sc->modes;
941 if (!test_bit(m, sc->ah->ah_capabilities.cap_mode))
944 for (i = 0; i < NUM_DRIVER_MODES; i++) {
945 if (modes[i].mode != m || !modes[i].num_channels)
947 ret = ieee80211_register_hwmode(hw, &modes[i]);
949 ATH5K_ERR(sc, "can't register hwmode %u\n", m);
958 ath5k_getchannels(struct ieee80211_hw *hw)
960 struct ath5k_softc *sc = hw->priv;
961 struct ath5k_hw *ah = sc->ah;
962 struct ieee80211_hw_mode *modes = sc->modes;
963 unsigned int i, max_r, max_c;
966 BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 3);
968 /* The order here does not matter */
969 modes[0].mode = MODE_IEEE80211G;
970 modes[1].mode = MODE_IEEE80211B;
971 modes[2].mode = MODE_IEEE80211A;
973 max_r = ARRAY_SIZE(sc->rates);
974 max_c = ARRAY_SIZE(sc->channels);
976 for (i = 0; i < NUM_DRIVER_MODES; i++) {
977 struct ieee80211_hw_mode *mode = &modes[i];
978 const struct ath5k_rate_table *hw_rates;
981 modes[0].rates = sc->rates;
982 modes->channels = sc->channels;
984 struct ieee80211_hw_mode *prev_mode = &modes[i-1];
985 int prev_num_r = prev_mode->num_rates;
986 int prev_num_c = prev_mode->num_channels;
987 mode->rates = &prev_mode->rates[prev_num_r];
988 mode->channels = &prev_mode->channels[prev_num_c];
991 hw_rates = ath5k_hw_get_rate_table(ah, mode->mode);
992 mode->num_rates = ath5k_copy_rates(mode->rates, hw_rates,
994 mode->num_channels = ath5k_copy_channels(ah, mode->channels,
996 max_r -= mode->num_rates;
997 max_c -= mode->num_channels;
1000 /* We try to register all modes this driver supports. We don't bother
1001 * with MODE_IEEE80211B for AR5212 as MODE_IEEE80211G already accounts
1002 * for that as per mac80211. Then, REGISTER_MODE() will will actually
1003 * check the eeprom reading for more reliable capability information.
1004 * Order matters here as per mac80211's latest preference. This will
1005 * all hopefullly soon go away. */
1007 REGISTER_MODE(MODE_IEEE80211G);
1008 if (ah->ah_version != AR5K_AR5212)
1009 REGISTER_MODE(MODE_IEEE80211B);
1010 REGISTER_MODE(MODE_IEEE80211A);
1012 ath5k_debug_dump_modes(sc, modes);
1018 * Set/change channels. If the channel is really being changed,
1019 * it's done by reseting the chip. To accomplish this we must
1020 * first cleanup any pending DMA, then restart stuff after a la
1024 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1026 struct ath5k_hw *ah = sc->ah;
1029 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "%u (%u MHz) -> %u (%u MHz)\n",
1030 sc->curchan->chan, sc->curchan->freq,
1031 chan->chan, chan->freq);
1033 if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) {
1035 * To switch channels clear any pending DMA operations;
1036 * wait long enough for the RX fifo to drain, reset the
1037 * hardware at the new frequency, and then re-enable
1038 * the relevant bits of the h/w.
1040 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1041 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1042 ath5k_rx_stop(sc); /* turn off frame recv */
1043 ret = ath5k_hw_reset(ah, sc->opmode, chan, true);
1045 ATH5K_ERR(sc, "%s: unable to reset channel %u "
1046 "(%u Mhz)\n", __func__, chan->chan, chan->freq);
1050 ath5k_hw_set_txpower_limit(sc->ah, 0);
1053 * Re-enable rx framework.
1055 ret = ath5k_rx_start(sc);
1057 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1063 * Change channels and update the h/w rate map
1064 * if we're switching; e.g. 11a to 11b/g.
1068 /* ath5k_chan_change(sc, chan); */
1070 ath5k_beacon_config(sc);
1072 * Re-enable interrupts.
1074 ath5k_hw_set_intr(ah, sc->imask);
1081 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1083 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1084 /* from Atheros NDIS driver, w/ permission */
1085 static const struct {
1086 u16 rate; /* tx/rx 802.11 rate */
1087 u16 timeOn; /* LED on time (ms) */
1088 u16 timeOff; /* LED off time (ms) */
1105 const struct ath5k_rate_table *rt =
1106 ath5k_hw_get_rate_table(sc->ah, mode);
1111 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1112 for (i = 0; i < 32; i++) {
1113 u8 ix = rt->rate_code_to_index[i];
1115 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1116 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1119 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1120 if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation ==
1121 IEEE80211_RATE_OFDM)
1122 sc->hwmap[i].txflags |=
1123 IEEE80211_RADIOTAP_F_SHORTPRE;
1124 /* receive frames include FCS */
1125 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1126 IEEE80211_RADIOTAP_F_FCS;
1127 /* setup blink rate table to avoid per-packet lookup */
1128 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1129 if (blinkrates[j].rate == /* XXX why 7f? */
1130 (rt->rates[ix].dot11_rate&0x7f))
1133 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1135 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1144 ath5k_mode_setup(struct ath5k_softc *sc)
1146 struct ath5k_hw *ah = sc->ah;
1149 /* configure rx filter */
1150 rfilt = sc->filter_flags;
1151 ath5k_hw_set_rx_filter(ah, rfilt);
1153 if (ath5k_hw_hasbssidmask(ah))
1154 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1156 /* configure operational mode */
1157 ath5k_hw_set_opmode(ah);
1159 ath5k_hw_set_mcast_filter(ah, 0, 0);
1160 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1171 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1173 struct ath5k_hw *ah = sc->ah;
1174 struct sk_buff *skb = bf->skb;
1175 struct ath5k_desc *ds;
1177 if (likely(skb == NULL)) {
1181 * Allocate buffer with headroom_needed space for the
1182 * fake physical layer header at the start.
1184 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1185 if (unlikely(skb == NULL)) {
1186 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1187 sc->rxbufsize + sc->cachelsz - 1);
1191 * Cache-line-align. This is important (for the
1192 * 5210 at least) as not doing so causes bogus data
1195 off = ((unsigned long)skb->data) % sc->cachelsz;
1197 skb_reserve(skb, sc->cachelsz - off);
1200 bf->skbaddr = pci_map_single(sc->pdev,
1201 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1202 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1203 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1211 * Setup descriptors. For receive we always terminate
1212 * the descriptor list with a self-linked entry so we'll
1213 * not get overrun under high load (as can happen with a
1214 * 5212 when ANI processing enables PHY error frames).
1216 * To insure the last descriptor is self-linked we create
1217 * each descriptor as self-linked and add it to the end. As
1218 * each additional descriptor is added the previous self-linked
1219 * entry is ``fixed'' naturally. This should be safe even
1220 * if DMA is happening. When processing RX interrupts we
1221 * never remove/process the last, self-linked, entry on the
1222 * descriptor list. This insures the hardware always has
1223 * someplace to write a new frame.
1226 ds->ds_link = bf->daddr; /* link to self */
1227 ds->ds_data = bf->skbaddr;
1228 ath5k_hw_setup_rx_desc(ah, ds,
1229 skb_tailroom(skb), /* buffer size */
1232 if (sc->rxlink != NULL)
1233 *sc->rxlink = bf->daddr;
1234 sc->rxlink = &ds->ds_link;
1239 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1240 struct ieee80211_tx_control *ctl)
1242 struct ath5k_hw *ah = sc->ah;
1243 struct ath5k_txq *txq = sc->txq;
1244 struct ath5k_desc *ds = bf->desc;
1245 struct sk_buff *skb = bf->skb;
1246 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1249 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1251 /* XXX endianness */
1252 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1255 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1256 flags |= AR5K_TXDESC_NOACK;
1258 pktlen = skb->len + FCS_LEN;
1260 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1261 keyidx = ctl->key_idx;
1262 pktlen += ctl->icv_len;
1265 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1266 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1267 (ctl->power_level * 2), ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0);
1272 ds->ds_data = bf->skbaddr;
1274 spin_lock_bh(&txq->lock);
1275 list_add_tail(&bf->list, &txq->q);
1276 sc->tx_stats.data[txq->qnum].len++;
1277 if (txq->link == NULL) /* is this first packet? */
1278 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1279 else /* no, so only link it */
1280 *txq->link = bf->daddr;
1282 txq->link = &ds->ds_link;
1283 ath5k_hw_tx_start(ah, txq->qnum);
1284 spin_unlock_bh(&txq->lock);
1288 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1292 /*******************\
1293 * Descriptors setup *
1294 \*******************/
1297 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1299 struct ath5k_desc *ds;
1300 struct ath5k_buf *bf;
1305 /* allocate descriptors */
1306 sc->desc_len = sizeof(struct ath5k_desc) *
1307 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1308 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1309 if (sc->desc == NULL) {
1310 ATH5K_ERR(sc, "can't allocate descriptors\n");
1315 da = sc->desc_daddr;
1316 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1317 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1319 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1320 sizeof(struct ath5k_buf), GFP_KERNEL);
1322 ATH5K_ERR(sc, "can't allocate bufptr\n");
1328 INIT_LIST_HEAD(&sc->rxbuf);
1329 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1332 list_add_tail(&bf->list, &sc->rxbuf);
1335 INIT_LIST_HEAD(&sc->txbuf);
1336 sc->txbuf_len = ATH_TXBUF;
1337 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1338 da += sizeof(*ds)) {
1341 list_add_tail(&bf->list, &sc->txbuf);
1351 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1358 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1360 struct ath5k_buf *bf;
1362 ath5k_txbuf_free(sc, sc->bbuf);
1363 list_for_each_entry(bf, &sc->txbuf, list)
1364 ath5k_txbuf_free(sc, bf);
1365 list_for_each_entry(bf, &sc->rxbuf, list)
1366 ath5k_txbuf_free(sc, bf);
1368 /* Free memory associated with all descriptors */
1369 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1383 static struct ath5k_txq *
1384 ath5k_txq_setup(struct ath5k_softc *sc,
1385 int qtype, int subtype)
1387 struct ath5k_hw *ah = sc->ah;
1388 struct ath5k_txq *txq;
1389 struct ath5k_txq_info qi = {
1390 .tqi_subtype = subtype,
1391 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1392 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1393 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1398 * Enable interrupts only for EOL and DESC conditions.
1399 * We mark tx descriptors to receive a DESC interrupt
1400 * when a tx queue gets deep; otherwise waiting for the
1401 * EOL to reap descriptors. Note that this is done to
1402 * reduce interrupt load and this only defers reaping
1403 * descriptors, never transmitting frames. Aside from
1404 * reducing interrupts this also permits more concurrency.
1405 * The only potential downside is if the tx queue backs
1406 * up in which case the top half of the kernel may backup
1407 * due to a lack of tx descriptors.
1409 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1410 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1411 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1414 * NB: don't print a message, this happens
1415 * normally on parts with too few tx queues
1417 return ERR_PTR(qnum);
1419 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1420 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1421 qnum, ARRAY_SIZE(sc->txqs));
1422 ath5k_hw_release_tx_queue(ah, qnum);
1423 return ERR_PTR(-EINVAL);
1425 txq = &sc->txqs[qnum];
1429 INIT_LIST_HEAD(&txq->q);
1430 spin_lock_init(&txq->lock);
1433 return &sc->txqs[qnum];
1437 ath5k_beaconq_setup(struct ath5k_hw *ah)
1439 struct ath5k_txq_info qi = {
1440 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1441 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1442 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1443 /* NB: for dynamic turbo, don't enable any other interrupts */
1444 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1447 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1451 ath5k_beaconq_config(struct ath5k_softc *sc)
1453 struct ath5k_hw *ah = sc->ah;
1454 struct ath5k_txq_info qi;
1457 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1460 if (sc->opmode == IEEE80211_IF_TYPE_AP ||
1461 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1463 * Always burst out beacon and CAB traffic
1464 * (aifs = cwmin = cwmax = 0)
1471 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1473 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1474 "hardware queue!\n", __func__);
1478 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1482 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1484 struct ath5k_buf *bf, *bf0;
1487 * NB: this assumes output has been stopped and
1488 * we do not need to block ath5k_tx_tasklet
1490 spin_lock_bh(&txq->lock);
1491 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1492 ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah,
1495 ath5k_txbuf_free(sc, bf);
1497 spin_lock_bh(&sc->txbuflock);
1498 sc->tx_stats.data[txq->qnum].len--;
1499 list_move_tail(&bf->list, &sc->txbuf);
1501 spin_unlock_bh(&sc->txbuflock);
1504 spin_unlock_bh(&txq->lock);
1508 * Drain the transmit queues and reclaim resources.
1511 ath5k_txq_cleanup(struct ath5k_softc *sc)
1513 struct ath5k_hw *ah = sc->ah;
1516 /* XXX return value */
1517 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1518 /* don't touch the hardware if marked invalid */
1519 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1520 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1521 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1522 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1523 if (sc->txqs[i].setup) {
1524 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1525 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1528 ath5k_hw_get_tx_buf(ah,
1533 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1535 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1536 if (sc->txqs[i].setup)
1537 ath5k_txq_drainq(sc, &sc->txqs[i]);
1541 ath5k_txq_release(struct ath5k_softc *sc)
1543 struct ath5k_txq *txq = sc->txqs;
1546 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1548 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1561 * Enable the receive h/w following a reset.
1564 ath5k_rx_start(struct ath5k_softc *sc)
1566 struct ath5k_hw *ah = sc->ah;
1567 struct ath5k_buf *bf;
1570 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1572 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1573 sc->cachelsz, sc->rxbufsize);
1577 spin_lock_bh(&sc->rxbuflock);
1578 list_for_each_entry(bf, &sc->rxbuf, list) {
1579 ret = ath5k_rxbuf_setup(sc, bf);
1581 spin_unlock_bh(&sc->rxbuflock);
1585 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1586 spin_unlock_bh(&sc->rxbuflock);
1588 ath5k_hw_put_rx_buf(ah, bf->daddr);
1589 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1590 ath5k_mode_setup(sc); /* set filters, etc. */
1591 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1599 * Disable the receive h/w in preparation for a reset.
1602 ath5k_rx_stop(struct ath5k_softc *sc)
1604 struct ath5k_hw *ah = sc->ah;
1606 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1607 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1608 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1609 mdelay(3); /* 3ms is long enough for 1 frame */
1611 ath5k_debug_printrxbuffs(sc, ah);
1613 sc->rxlink = NULL; /* just in case */
1617 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1618 struct sk_buff *skb)
1620 struct ieee80211_hdr *hdr = (void *)skb->data;
1621 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1623 if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1624 ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID)
1625 return RX_FLAG_DECRYPTED;
1627 /* Apparently when a default key is used to decrypt the packet
1628 the hw does not set the index used to decrypt. In such cases
1629 get the index from the packet. */
1630 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1631 !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1632 skb->len >= hlen + 4) {
1633 keyix = skb->data[hlen + 3] >> 6;
1635 if (test_bit(keyix, sc->keymap))
1636 return RX_FLAG_DECRYPTED;
1643 ath5k_tasklet_rx(unsigned long data)
1645 struct ieee80211_rx_status rxs = {};
1646 struct sk_buff *skb;
1647 struct ath5k_softc *sc = (void *)data;
1648 struct ath5k_buf *bf;
1649 struct ath5k_desc *ds;
1656 spin_lock(&sc->rxbuflock);
1658 if (unlikely(list_empty(&sc->rxbuf))) {
1659 ATH5K_WARN(sc, "empty rx buf pool\n");
1662 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1663 BUG_ON(bf->skb == NULL);
1667 /* TODO only one segment */
1668 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1669 sc->desc_len, PCI_DMA_FROMDEVICE);
1671 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1674 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds);
1675 if (unlikely(ret == -EINPROGRESS))
1677 else if (unlikely(ret)) {
1678 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1682 if (unlikely(ds->ds_rxstat.rs_more)) {
1683 ATH5K_WARN(sc, "unsupported jumbo\n");
1687 stat = ds->ds_rxstat.rs_status;
1688 if (unlikely(stat)) {
1689 if (stat & AR5K_RXERR_PHY)
1691 if (stat & AR5K_RXERR_DECRYPT) {
1693 * Decrypt error. If the error occurred
1694 * because there was no hardware key, then
1695 * let the frame through so the upper layers
1696 * can process it. This is necessary for 5210
1697 * parts which have no way to setup a ``clear''
1700 * XXX do key cache faulting
1702 if (ds->ds_rxstat.rs_keyix ==
1703 AR5K_RXKEYIX_INVALID &&
1704 !(stat & AR5K_RXERR_CRC))
1707 if (stat & AR5K_RXERR_MIC) {
1708 rxs.flag |= RX_FLAG_MMIC_ERROR;
1712 /* let crypto-error packets fall through in MNTR */
1713 if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1714 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1718 len = ds->ds_rxstat.rs_datalen;
1719 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len,
1720 PCI_DMA_FROMDEVICE);
1721 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1722 PCI_DMA_FROMDEVICE);
1728 * the hardware adds a padding to 4 byte boundaries between
1729 * the header and the payload data if the header length is
1730 * not multiples of 4 - remove it
1732 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1735 memmove(skb->data + pad, skb->data, hdrlen);
1739 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
1740 rxs.mactime = ath5k_extend_tsf(sc->ah,
1741 ds->ds_rxstat.rs_tstamp);
1743 rxs.mactime = ds->ds_rxstat.rs_tstamp;
1744 rxs.freq = sc->curchan->freq;
1745 rxs.channel = sc->curchan->chan;
1746 rxs.phymode = sc->curmode;
1750 * the names here are misleading and the usage of these
1751 * values by iwconfig makes it even worse
1753 /* noise floor in dBm, from the last noise calibration */
1754 rxs.noise = sc->ah->ah_noise_floor;
1755 /* signal level in dBm */
1756 rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi;
1758 * "signal" is actually displayed as Link Quality by iwconfig
1759 * we provide a percentage based on rssi (assuming max rssi 64)
1761 rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64;
1763 rxs.antenna = ds->ds_rxstat.rs_antenna;
1764 rxs.rate = ds->ds_rxstat.rs_rate;
1765 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb);
1767 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1769 __ieee80211_rx(sc->hw, skb, &rxs);
1770 sc->led_rxrate = ds->ds_rxstat.rs_rate;
1771 ath5k_led_event(sc, ATH_LED_RX);
1773 list_move_tail(&bf->list, &sc->rxbuf);
1774 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1775 spin_unlock(&sc->rxbuflock);
1786 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1788 struct ieee80211_tx_status txs = {};
1789 struct ath5k_buf *bf, *bf0;
1790 struct ath5k_desc *ds;
1791 struct sk_buff *skb;
1794 spin_lock(&txq->lock);
1795 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1798 /* TODO only one segment */
1799 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1800 sc->desc_len, PCI_DMA_FROMDEVICE);
1801 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds);
1802 if (unlikely(ret == -EINPROGRESS))
1804 else if (unlikely(ret)) {
1805 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1812 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1815 txs.control = bf->ctl;
1816 txs.retry_count = ds->ds_txstat.ts_shortretry +
1817 ds->ds_txstat.ts_longretry / 6;
1818 if (unlikely(ds->ds_txstat.ts_status)) {
1819 sc->ll_stats.dot11ACKFailureCount++;
1820 if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY)
1821 txs.excessive_retries = 1;
1822 else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT)
1823 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1825 txs.flags |= IEEE80211_TX_STATUS_ACK;
1826 txs.ack_signal = ds->ds_txstat.ts_rssi;
1829 ieee80211_tx_status(sc->hw, skb, &txs);
1830 sc->tx_stats.data[txq->qnum].count++;
1832 spin_lock(&sc->txbuflock);
1833 sc->tx_stats.data[txq->qnum].len--;
1834 list_move_tail(&bf->list, &sc->txbuf);
1836 spin_unlock(&sc->txbuflock);
1838 if (likely(list_empty(&txq->q)))
1840 spin_unlock(&txq->lock);
1841 if (sc->txbuf_len > ATH_TXBUF / 5)
1842 ieee80211_wake_queues(sc->hw);
1846 ath5k_tasklet_tx(unsigned long data)
1848 struct ath5k_softc *sc = (void *)data;
1850 ath5k_tx_processq(sc, sc->txq);
1852 ath5k_led_event(sc, ATH_LED_TX);
1863 * Setup the beacon frame for transmit.
1866 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1867 struct ieee80211_tx_control *ctl)
1869 struct sk_buff *skb = bf->skb;
1870 struct ath5k_hw *ah = sc->ah;
1871 struct ath5k_desc *ds;
1872 int ret, antenna = 0;
1875 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1877 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1878 "skbaddr %llx\n", skb, skb->data, skb->len,
1879 (unsigned long long)bf->skbaddr);
1880 if (pci_dma_mapping_error(bf->skbaddr)) {
1881 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1887 flags = AR5K_TXDESC_NOACK;
1888 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1889 ds->ds_link = bf->daddr; /* self-linked */
1890 flags |= AR5K_TXDESC_VEOL;
1892 * Let hardware handle antenna switching if txantenna is not set
1897 * Switch antenna every 4 beacons if txantenna is not set
1898 * XXX assumes two antennas
1901 antenna = sc->bsent & 4 ? 2 : 1;
1904 ds->ds_data = bf->skbaddr;
1905 ret = ah->ah_setup_tx_desc(ah, ds, skb->len + FCS_LEN,
1906 ieee80211_get_hdrlen_from_skb(skb),
1907 AR5K_PKT_TYPE_BEACON, (ctl->power_level * 2), ctl->tx_rate, 1,
1908 AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0);
1914 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1919 * Transmit a beacon frame at SWBA. Dynamic updates to the
1920 * frame contents are done as needed and the slot time is
1921 * also adjusted based on current state.
1923 * this is usually called from interrupt context (ath5k_intr())
1924 * but also from ath5k_beacon_config() in IBSS mode which in turn
1925 * can be called from a tasklet and user context
1928 ath5k_beacon_send(struct ath5k_softc *sc)
1930 struct ath5k_buf *bf = sc->bbuf;
1931 struct ath5k_hw *ah = sc->ah;
1933 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC, "in beacon_send\n");
1935 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1936 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1937 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1941 * Check if the previous beacon has gone out. If
1942 * not don't don't try to post another, skip this
1943 * period and wait for the next. Missed beacons
1944 * indicate a problem and should not occur. If we
1945 * miss too many consecutive beacons reset the device.
1947 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1949 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC,
1950 "missed %u consecutive beacons\n", sc->bmisscount);
1951 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
1952 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC,
1953 "stuck beacon time (%u missed)\n",
1955 tasklet_schedule(&sc->restq);
1959 if (unlikely(sc->bmisscount != 0)) {
1960 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC,
1961 "resume beacon xmit after %u misses\n",
1967 * Stop any current dma and put the new frame on the queue.
1968 * This should never fail since we check above that no frames
1969 * are still pending on the queue.
1971 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1972 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1973 /* NB: hw still stops DMA, so proceed */
1975 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
1978 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
1979 ath5k_hw_tx_start(ah, sc->bhalq);
1980 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON_PROC, "TXDP[%u] = %llx (%p)\n",
1981 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1988 ath5k_beacon_update_timers(struct ath5k_softc *sc)
1990 struct ath5k_hw *ah = sc->ah;
1991 u32 uninitialized_var(nexttbtt), intval, tsftu;
1994 intval = sc->bintval & AR5K_BEACON_PERIOD;
1995 if (WARN_ON(!intval))
1998 /* current TSF converted to TU */
1999 tsf = ath5k_hw_get_tsf64(ah);
2000 tsftu = TSF_TO_TU(tsf);
2003 * Pull nexttbtt forward to reflect the current
2004 * TSF. Add one intval otherwise the timespan
2005 * can be too short for ibss merges.
2007 nexttbtt = tsftu + 2 * intval;
2009 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2010 "hw tsftu %u nexttbtt %u intval %u\n", tsftu, nexttbtt, intval);
2012 intval |= AR5K_BEACON_ENA;
2014 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2019 * Configure the beacon timers and interrupts based on the operating mode
2021 * When operating in station mode we want to receive a BMISS interrupt when we
2022 * stop seeing beacons from the AP we've associated with so we can look for
2023 * another AP to associate with.
2025 * In IBSS mode we need to configure the beacon timers and use a self-linked tx
2026 * descriptor if possible. If the hardware cannot deal with that we enable SWBA
2027 * interrupts to send the beacons from the interrupt handler.
2030 ath5k_beacon_config(struct ath5k_softc *sc)
2032 struct ath5k_hw *ah = sc->ah;
2034 ath5k_hw_set_intr(ah, 0);
2037 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2038 sc->imask |= AR5K_INT_BMISS;
2039 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2041 * In IBSS mode enable the beacon timers but only enable SWBA
2042 * interrupts if we need to manually prepare beacon frames.
2043 * Otherwise we use a self-linked tx descriptor and let the
2044 * hardware deal with things. In that case we have to load it
2047 ath5k_beaconq_config(sc);
2048 ath5k_beacon_update_timers(sc);
2050 if (!ath5k_hw_hasveol(ah))
2051 sc->imask |= AR5K_INT_SWBA;
2053 ath5k_beacon_send(sc);
2057 ath5k_hw_set_intr(ah, sc->imask);
2061 /********************\
2062 * Interrupt handling *
2063 \********************/
2066 ath5k_init(struct ath5k_softc *sc)
2070 mutex_lock(&sc->lock);
2072 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2075 * Stop anything previously setup. This is safe
2076 * no matter this is the first time through or not.
2078 ath5k_stop_locked(sc);
2081 * The basic interface to setting the hardware in a good
2082 * state is ``reset''. On return the hardware is known to
2083 * be powered up and with interrupts disabled. This must
2084 * be followed by initialization of the appropriate bits
2085 * and then setup of the interrupt mask.
2087 sc->curchan = sc->hw->conf.chan;
2088 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2090 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2094 * This is needed only to setup initial state
2095 * but it's best done after a reset.
2097 ath5k_hw_set_txpower_limit(sc->ah, 0);
2100 * Setup the hardware after reset: the key cache
2101 * is filled as needed and the receive engine is
2102 * set going. Frame transmit is handled entirely
2103 * in the frame output path; there's nothing to do
2104 * here except setup the interrupt mask.
2106 ret = ath5k_rx_start(sc);
2111 * Enable interrupts.
2113 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2114 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2116 ath5k_hw_set_intr(sc->ah, sc->imask);
2117 /* Set ack to be sent at low bit-rates */
2118 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2120 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2121 msecs_to_jiffies(ath5k_calinterval * 1000)));
2125 mutex_unlock(&sc->lock);
2130 ath5k_stop_locked(struct ath5k_softc *sc)
2132 struct ath5k_hw *ah = sc->ah;
2134 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2135 test_bit(ATH_STAT_INVALID, sc->status));
2138 * Shutdown the hardware and driver:
2139 * stop output from above
2140 * disable interrupts
2142 * turn off the radio
2143 * clear transmit machinery
2144 * clear receive machinery
2145 * drain and release tx queues
2146 * reclaim beacon resources
2147 * power down hardware
2149 * Note that some of this work is not possible if the
2150 * hardware is gone (invalid).
2152 ieee80211_stop_queues(sc->hw);
2154 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2155 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2156 del_timer_sync(&sc->led_tim);
2157 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2158 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2160 ath5k_hw_set_intr(ah, 0);
2162 ath5k_txq_cleanup(sc);
2163 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2165 ath5k_hw_phy_disable(ah);
2173 * Stop the device, grabbing the top-level lock to protect
2174 * against concurrent entry through ath5k_init (which can happen
2175 * if another thread does a system call and the thread doing the
2176 * stop is preempted).
2179 ath5k_stop_hw(struct ath5k_softc *sc)
2183 mutex_lock(&sc->lock);
2184 ret = ath5k_stop_locked(sc);
2185 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2187 * Set the chip in full sleep mode. Note that we are
2188 * careful to do this only when bringing the interface
2189 * completely to a stop. When the chip is in this state
2190 * it must be carefully woken up or references to
2191 * registers in the PCI clock domain may freeze the bus
2192 * (and system). This varies by chip and is mostly an
2193 * issue with newer parts that go to sleep more quickly.
2195 if (sc->ah->ah_mac_srev >= 0x78) {
2198 * don't put newer MAC revisions > 7.8 to sleep because
2199 * of the above mentioned problems
2201 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2202 "not putting device to sleep\n");
2204 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2205 "putting device to full sleep\n");
2206 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2209 ath5k_txbuf_free(sc, sc->bbuf);
2210 mutex_unlock(&sc->lock);
2212 del_timer_sync(&sc->calib_tim);
2218 ath5k_intr(int irq, void *dev_id)
2220 struct ath5k_softc *sc = dev_id;
2221 struct ath5k_hw *ah = sc->ah;
2222 enum ath5k_int status;
2223 unsigned int counter = 1000;
2225 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2226 !ath5k_hw_is_intr_pending(ah)))
2231 * Figure out the reason(s) for the interrupt. Note
2232 * that get_isr returns a pseudo-ISR that may include
2233 * bits we haven't explicitly enabled so we mask the
2234 * value to insure we only process bits we requested.
2236 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2237 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2239 status &= sc->imask; /* discard unasked for bits */
2240 if (unlikely(status & AR5K_INT_FATAL)) {
2242 * Fatal errors are unrecoverable.
2243 * Typically these are caused by DMA errors.
2245 tasklet_schedule(&sc->restq);
2246 } else if (unlikely(status & AR5K_INT_RXORN)) {
2247 tasklet_schedule(&sc->restq);
2249 if (status & AR5K_INT_SWBA) {
2251 * Software beacon alert--time to send a beacon.
2252 * Handle beacon transmission directly; deferring
2253 * this is too slow to meet timing constraints
2256 ath5k_beacon_send(sc);
2258 if (status & AR5K_INT_RXEOL) {
2260 * NB: the hardware should re-read the link when
2261 * RXE bit is written, but it doesn't work at
2262 * least on older hardware revs.
2266 if (status & AR5K_INT_TXURN) {
2267 /* bump tx trigger level */
2268 ath5k_hw_update_tx_triglevel(ah, true);
2270 if (status & AR5K_INT_RX)
2271 tasklet_schedule(&sc->rxtq);
2272 if (status & AR5K_INT_TX)
2273 tasklet_schedule(&sc->txtq);
2274 if (status & AR5K_INT_BMISS) {
2276 if (status & AR5K_INT_MIB) {
2280 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2282 if (unlikely(!counter))
2283 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2289 ath5k_tasklet_reset(unsigned long data)
2291 struct ath5k_softc *sc = (void *)data;
2293 ath5k_reset(sc->hw);
2297 * Periodically recalibrate the PHY to account
2298 * for temperature/environment changes.
2301 ath5k_calibrate(unsigned long data)
2303 struct ath5k_softc *sc = (void *)data;
2304 struct ath5k_hw *ah = sc->ah;
2306 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2307 sc->curchan->chan, sc->curchan->val);
2309 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2311 * Rfgain is out of bounds, reset the chip
2312 * to load new gain values.
2314 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2315 ath5k_reset(sc->hw);
2317 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2318 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2321 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2322 msecs_to_jiffies(ath5k_calinterval * 1000)));
2332 ath5k_led_off(unsigned long data)
2334 struct ath5k_softc *sc = (void *)data;
2336 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2337 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2339 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2340 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2341 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2346 * Blink the LED according to the specified on/off times.
2349 ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2352 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2353 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2354 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2355 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2357 mod_timer(&sc->led_tim, jiffies + on);
2361 ath5k_led_event(struct ath5k_softc *sc, int event)
2363 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2365 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2366 return; /* don't interrupt active blink */
2369 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2370 sc->hwmap[sc->led_txrate].ledoff);
2373 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2374 sc->hwmap[sc->led_rxrate].ledoff);
2382 /********************\
2383 * Mac80211 functions *
2384 \********************/
2387 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2388 struct ieee80211_tx_control *ctl)
2390 struct ath5k_softc *sc = hw->priv;
2391 struct ath5k_buf *bf;
2392 unsigned long flags;
2396 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2398 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2399 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2402 * the hardware expects the header padded to 4 byte boundaries
2403 * if this is not the case we add the padding after the header
2405 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2408 if (skb_headroom(skb) < pad) {
2409 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2410 " headroom to pad %d\n", hdrlen, pad);
2414 memmove(skb->data, skb->data+pad, hdrlen);
2417 sc->led_txrate = ctl->tx_rate;
2419 spin_lock_irqsave(&sc->txbuflock, flags);
2420 if (list_empty(&sc->txbuf)) {
2421 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2422 spin_unlock_irqrestore(&sc->txbuflock, flags);
2423 ieee80211_stop_queue(hw, ctl->queue);
2426 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2427 list_del(&bf->list);
2429 if (list_empty(&sc->txbuf))
2430 ieee80211_stop_queues(hw);
2431 spin_unlock_irqrestore(&sc->txbuflock, flags);
2435 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2437 spin_lock_irqsave(&sc->txbuflock, flags);
2438 list_add_tail(&bf->list, &sc->txbuf);
2440 spin_unlock_irqrestore(&sc->txbuflock, flags);
2441 dev_kfree_skb_any(skb);
2449 ath5k_reset(struct ieee80211_hw *hw)
2451 struct ath5k_softc *sc = hw->priv;
2452 struct ath5k_hw *ah = sc->ah;
2455 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2457 * Convert to a hw channel description with the flags
2458 * constrained to reflect the current operating mode.
2460 sc->curchan = hw->conf.chan;
2462 ath5k_hw_set_intr(ah, 0);
2463 ath5k_txq_cleanup(sc);
2466 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2467 if (unlikely(ret)) {
2468 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2471 ath5k_hw_set_txpower_limit(sc->ah, 0);
2473 ret = ath5k_rx_start(sc);
2474 if (unlikely(ret)) {
2475 ATH5K_ERR(sc, "can't start recv logic\n");
2479 * We may be doing a reset in response to an ioctl
2480 * that changes the channel so update any state that
2481 * might change as a result.
2485 /* ath5k_chan_change(sc, c); */
2486 ath5k_beacon_config(sc);
2487 /* intrs are started by ath5k_beacon_config */
2489 ieee80211_wake_queues(hw);
2496 static int ath5k_start(struct ieee80211_hw *hw)
2498 return ath5k_init(hw->priv);
2501 static void ath5k_stop(struct ieee80211_hw *hw)
2503 ath5k_stop_hw(hw->priv);
2506 static int ath5k_add_interface(struct ieee80211_hw *hw,
2507 struct ieee80211_if_init_conf *conf)
2509 struct ath5k_softc *sc = hw->priv;
2512 mutex_lock(&sc->lock);
2518 sc->vif = conf->vif;
2520 switch (conf->type) {
2521 case IEEE80211_IF_TYPE_STA:
2522 case IEEE80211_IF_TYPE_IBSS:
2523 case IEEE80211_IF_TYPE_MNTR:
2524 sc->opmode = conf->type;
2532 mutex_unlock(&sc->lock);
2537 ath5k_remove_interface(struct ieee80211_hw *hw,
2538 struct ieee80211_if_init_conf *conf)
2540 struct ath5k_softc *sc = hw->priv;
2542 mutex_lock(&sc->lock);
2543 if (sc->vif != conf->vif)
2548 mutex_unlock(&sc->lock);
2552 ath5k_config(struct ieee80211_hw *hw,
2553 struct ieee80211_conf *conf)
2555 struct ath5k_softc *sc = hw->priv;
2557 sc->bintval = conf->beacon_int * 1000 / 1024;
2558 ath5k_setcurmode(sc, conf->phymode);
2560 return ath5k_chan_set(sc, conf->chan);
2564 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2565 struct ieee80211_if_conf *conf)
2567 struct ath5k_softc *sc = hw->priv;
2568 struct ath5k_hw *ah = sc->ah;
2571 /* Set to a reasonable value. Note that this will
2572 * be set to mac80211's value at ath5k_config(). */
2573 sc->bintval = 1000 * 1000 / 1024;
2574 mutex_lock(&sc->lock);
2575 if (sc->vif != vif) {
2580 /* Cache for later use during resets */
2581 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2582 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2583 * a clean way of letting us retrieve this yet. */
2584 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2586 mutex_unlock(&sc->lock);
2588 return ath5k_reset(hw);
2590 mutex_unlock(&sc->lock);
2594 #define SUPPORTED_FIF_FLAGS \
2595 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2596 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2597 FIF_BCN_PRBRESP_PROMISC
2599 * o always accept unicast, broadcast, and multicast traffic
2600 * o multicast traffic for all BSSIDs will be enabled if mac80211
2602 * o maintain current state of phy ofdm or phy cck error reception.
2603 * If the hardware detects any of these type of errors then
2604 * ath5k_hw_get_rx_filter() will pass to us the respective
2605 * hardware filters to be able to receive these type of frames.
2606 * o probe request frames are accepted only when operating in
2607 * hostap, adhoc, or monitor modes
2608 * o enable promiscuous mode according to the interface state
2610 * - when operating in adhoc mode so the 802.11 layer creates
2611 * node table entries for peers,
2612 * - when operating in station mode for collecting rssi data when
2613 * the station is otherwise quiet, or
2616 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2617 unsigned int changed_flags,
2618 unsigned int *new_flags,
2619 int mc_count, struct dev_mc_list *mclist)
2621 struct ath5k_softc *sc = hw->priv;
2622 struct ath5k_hw *ah = sc->ah;
2623 u32 mfilt[2], val, rfilt;
2630 /* Only deal with supported flags */
2631 changed_flags &= SUPPORTED_FIF_FLAGS;
2632 *new_flags &= SUPPORTED_FIF_FLAGS;
2634 /* If HW detects any phy or radar errors, leave those filters on.
2635 * Also, always enable Unicast, Broadcasts and Multicast
2636 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2637 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2638 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2639 AR5K_RX_FILTER_MCAST);
2641 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2642 if (*new_flags & FIF_PROMISC_IN_BSS) {
2643 rfilt |= AR5K_RX_FILTER_PROM;
2644 __set_bit(ATH_STAT_PROMISC, sc->status);
2647 __clear_bit(ATH_STAT_PROMISC, sc->status);
2650 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2651 if (*new_flags & FIF_ALLMULTI) {
2655 for (i = 0; i < mc_count; i++) {
2658 /* calculate XOR of eight 6-bit values */
2659 val = LE_READ_4(mclist->dmi_addr + 0);
2660 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2661 val = LE_READ_4(mclist->dmi_addr + 3);
2662 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2664 mfilt[pos / 32] |= (1 << (pos % 32));
2665 /* XXX: we might be able to just do this instead,
2666 * but not sure, needs testing, if we do use this we'd
2667 * neet to inform below to not reset the mcast */
2668 /* ath5k_hw_set_mcast_filterindex(ah,
2669 * mclist->dmi_addr[5]); */
2670 mclist = mclist->next;
2674 /* This is the best we can do */
2675 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2676 rfilt |= AR5K_RX_FILTER_PHYERR;
2678 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2679 * and probes for any BSSID, this needs testing */
2680 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2681 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2683 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2684 * set we should only pass on control frames for this
2685 * station. This needs testing. I believe right now this
2686 * enables *all* control frames, which is OK.. but
2687 * but we should see if we can improve on granularity */
2688 if (*new_flags & FIF_CONTROL)
2689 rfilt |= AR5K_RX_FILTER_CONTROL;
2691 /* Additional settings per mode -- this is per ath5k */
2693 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2695 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2696 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2697 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2698 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2699 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2700 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2701 test_bit(ATH_STAT_PROMISC, sc->status))
2702 rfilt |= AR5K_RX_FILTER_PROM;
2703 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2704 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2705 rfilt |= AR5K_RX_FILTER_BEACON;
2709 ath5k_hw_set_rx_filter(ah,rfilt);
2711 /* Set multicast bits */
2712 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2713 /* Set the cached hw filter flags, this will alter actually
2715 sc->filter_flags = rfilt;
2719 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2720 const u8 *local_addr, const u8 *addr,
2721 struct ieee80211_key_conf *key)
2723 struct ath5k_softc *sc = hw->priv;
2737 mutex_lock(&sc->lock);
2741 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2743 ATH5K_ERR(sc, "can't set the key\n");
2746 __set_bit(key->keyidx, sc->keymap);
2747 key->hw_key_idx = key->keyidx;
2750 ath5k_hw_reset_key(sc->ah, key->keyidx);
2751 __clear_bit(key->keyidx, sc->keymap);
2759 mutex_unlock(&sc->lock);
2764 ath5k_get_stats(struct ieee80211_hw *hw,
2765 struct ieee80211_low_level_stats *stats)
2767 struct ath5k_softc *sc = hw->priv;
2769 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2775 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2776 struct ieee80211_tx_queue_stats *stats)
2778 struct ath5k_softc *sc = hw->priv;
2780 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2786 ath5k_get_tsf(struct ieee80211_hw *hw)
2788 struct ath5k_softc *sc = hw->priv;
2790 return ath5k_hw_get_tsf64(sc->ah);
2794 ath5k_reset_tsf(struct ieee80211_hw *hw)
2796 struct ath5k_softc *sc = hw->priv;
2798 ath5k_hw_reset_tsf(sc->ah);
2802 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2803 struct ieee80211_tx_control *ctl)
2805 struct ath5k_softc *sc = hw->priv;
2808 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
2810 mutex_lock(&sc->lock);
2812 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
2817 ath5k_txbuf_free(sc, sc->bbuf);
2818 sc->bbuf->skb = skb;
2819 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
2821 sc->bbuf->skb = NULL;
2823 ath5k_beacon_config(sc);
2826 mutex_unlock(&sc->lock);