git.oblomov.eu Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 MODULE_AUTHOR("Qumranet");
  31 MODULE_LICENSE("GPL");
  32
  33 #define IOPM_ALLOC_ORDER 2
  34 #define MSRPM_ALLOC_ORDER 1
  35
  36 #define DB_VECTOR 1
  37 #define UD_VECTOR 6
  38 #define GP_VECTOR 13
  39
  40 #define DR7_GD_MASK (1 << 13)
  41 #define DR6_BD_MASK (1 << 13)
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_DEATURE_SVML (1 << 2)
  49
  50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  51
  52 /* enable NPT for AMD64 and X86 with PAE */
  53 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  54 static bool npt_enabled = true;
  55 #else
  56 static bool npt_enabled = false;
  57 #endif
  58 static int npt = 1;
  59
  60 module_param(npt, int, S_IRUGO);
  61
  62 static void kvm_reput_irq(struct vcpu_svm *svm);
  63
  64 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  65 {
  66         return container_of(vcpu, struct vcpu_svm, vcpu);
  67 }
  68
  69 unsigned long iopm_base;
  70
  71 struct kvm_ldttss_desc {
  72         u16 limit0;
  73         u16 base0;
  74         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  75         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  76         u32 base3;
  77         u32 zero1;
  78 } __attribute__((packed));
  79
  80 struct svm_cpu_data {
  81         int cpu;
  82
  83         u64 asid_generation;
  84         u32 max_asid;
  85         u32 next_asid;
  86         struct kvm_ldttss_desc *tss_desc;
  87
  88         struct page *save_area;
  89 };
  90
  91 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  92 static uint32_t svm_features;
  93
  94 struct svm_init_data {
  95         int cpu;
  96         int r;
  97 };
  98
  99 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 100
 101 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 102 #define MSRS_RANGE_SIZE 2048
 103 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 104
 105 #define MAX_INST_SIZE 15
 106
 107 static inline u32 svm_has(u32 feat)
 108 {
 109         return svm_features & feat;
 110 }
 111
 112 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 113 {
 114         int word_index = __ffs(vcpu->arch.irq_summary);
 115         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 116         int irq = word_index * BITS_PER_LONG + bit_index;
 117
 118         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 119         if (!vcpu->arch.irq_pending[word_index])
 120                 clear_bit(word_index, &vcpu->arch.irq_summary);
 121         return irq;
 122 }
 123
 124 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 125 {
 126         set_bit(irq, vcpu->arch.irq_pending);
 127         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 128 }
 129
 130 static inline void clgi(void)
 131 {
 132         asm volatile (SVM_CLGI);
 133 }
 134
 135 static inline void stgi(void)
 136 {
 137         asm volatile (SVM_STGI);
 138 }
 139
 140 static inline void invlpga(unsigned long addr, u32 asid)
 141 {
 142         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 143 }
 144
 145 static inline unsigned long kvm_read_cr2(void)
 146 {
 147         unsigned long cr2;
 148
 149         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 150         return cr2;
 151 }
 152
 153 static inline void kvm_write_cr2(unsigned long val)
 154 {
 155         asm volatile ("mov %0, %%cr2" :: "r" (val));
 156 }
 157
 158 static inline unsigned long read_dr6(void)
 159 {
 160         unsigned long dr6;
 161
 162         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 163         return dr6;
 164 }
 165
 166 static inline void write_dr6(unsigned long val)
 167 {
 168         asm volatile ("mov %0, %%dr6" :: "r" (val));
 169 }
 170
 171 static inline unsigned long read_dr7(void)
 172 {
 173         unsigned long dr7;
 174
 175         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 176         return dr7;
 177 }
 178
 179 static inline void write_dr7(unsigned long val)
 180 {
 181         asm volatile ("mov %0, %%dr7" :: "r" (val));
 182 }
 183
 184 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 185 {
 186         to_svm(vcpu)->asid_generation--;
 187 }
 188
 189 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 190 {
 191         force_new_asid(vcpu);
 192 }
 193
 194 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 195 {
 196         if (!npt_enabled && !(efer & EFER_LMA))
 197                 efer &= ~EFER_LME;
 198
 199         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 200         vcpu->arch.shadow_efer = efer;
 201 }
 202
 203 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 204                                 bool has_error_code, u32 error_code)
 205 {
 206         struct vcpu_svm *svm = to_svm(vcpu);
 207
 208         svm->vmcb->control.event_inj = nr
 209                 | SVM_EVTINJ_VALID
 210                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 211                 | SVM_EVTINJ_TYPE_EXEPT;
 212         svm->vmcb->control.event_inj_err = error_code;
 213 }
 214
 215 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 220 }
 221
 222 static int is_external_interrupt(u32 info)
 223 {
 224         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 225         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 226 }
 227
 228 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 229 {
 230         struct vcpu_svm *svm = to_svm(vcpu);
 231
 232         if (!svm->next_rip) {
 233                 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
 234                 return;
 235         }
 236         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 237                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 238                        __FUNCTION__,
 239                        svm->vmcb->save.rip,
 240                        svm->next_rip);
 241
 242         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 243         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 244
 245         vcpu->arch.interrupt_window_open = 1;
 246 }
 247
 248 static int has_svm(void)
 249 {
 250         uint32_t eax, ebx, ecx, edx;
 251
 252         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 253                 printk(KERN_INFO "has_svm: not amd\n");
 254                 return 0;
 255         }
 256
 257         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 258         if (eax < SVM_CPUID_FUNC) {
 259                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 260                 return 0;
 261         }
 262
 263         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 264         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 265                 printk(KERN_DEBUG "has_svm: svm not available\n");
 266                 return 0;
 267         }
 268         return 1;
 269 }
 270
 271 static void svm_hardware_disable(void *garbage)
 272 {
 273         struct svm_cpu_data *svm_data
 274                 = per_cpu(svm_data, raw_smp_processor_id());
 275
 276         if (svm_data) {
 277                 uint64_t efer;
 278
 279                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 280                 rdmsrl(MSR_EFER, efer);
 281                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 282                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 283                 __free_page(svm_data->save_area);
 284                 kfree(svm_data);
 285         }
 286 }
 287
 288 static void svm_hardware_enable(void *garbage)
 289 {
 290
 291         struct svm_cpu_data *svm_data;
 292         uint64_t efer;
 293 #ifdef CONFIG_X86_64
 294         struct desc_ptr gdt_descr;
 295 #else
 296         struct desc_ptr gdt_descr;
 297 #endif
 298         struct desc_struct *gdt;
 299         int me = raw_smp_processor_id();
 300
 301         if (!has_svm()) {
 302                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 303                 return;
 304         }
 305         svm_data = per_cpu(svm_data, me);
 306
 307         if (!svm_data) {
 308                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 309                        me);
 310                 return;
 311         }
 312
 313         svm_data->asid_generation = 1;
 314         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 315         svm_data->next_asid = svm_data->max_asid + 1;
 316
 317         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 318         gdt = (struct desc_struct *)gdt_descr.address;
 319         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 320
 321         rdmsrl(MSR_EFER, efer);
 322         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 323
 324         wrmsrl(MSR_VM_HSAVE_PA,
 325                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 326 }
 327
 328 static int svm_cpu_init(int cpu)
 329 {
 330         struct svm_cpu_data *svm_data;
 331         int r;
 332
 333         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 334         if (!svm_data)
 335                 return -ENOMEM;
 336         svm_data->cpu = cpu;
 337         svm_data->save_area = alloc_page(GFP_KERNEL);
 338         r = -ENOMEM;
 339         if (!svm_data->save_area)
 340                 goto err_1;
 341
 342         per_cpu(svm_data, cpu) = svm_data;
 343
 344         return 0;
 345
 346 err_1:
 347         kfree(svm_data);
 348         return r;
 349
 350 }
 351
 352 static void set_msr_interception(u32 *msrpm, unsigned msr,
 353                                  int read, int write)
 354 {
 355         int i;
 356
 357         for (i = 0; i < NUM_MSR_MAPS; i++) {
 358                 if (msr >= msrpm_ranges[i] &&
 359                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 360                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 361                                           msrpm_ranges[i]) * 2;
 362
 363                         u32 *base = msrpm + (msr_offset / 32);
 364                         u32 msr_shift = msr_offset % 32;
 365                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 366                         *base = (*base & ~(0x3 << msr_shift)) |
 367                                 (mask << msr_shift);
 368                         return;
 369                 }
 370         }
 371         BUG();
 372 }
 373
 374 static void svm_vcpu_init_msrpm(u32 *msrpm)
 375 {
 376         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 377
 378 #ifdef CONFIG_X86_64
 379         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 380         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 381         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 382         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 383         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 384         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 385 #endif
 386         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 387         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 388         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 389         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 390 }
 391
 392 static void svm_enable_lbrv(struct vcpu_svm *svm)
 393 {
 394         u32 *msrpm = svm->msrpm;
 395
 396         svm->vmcb->control.lbr_ctl = 1;
 397         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 398         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 399         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 400         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 401 }
 402
 403 static void svm_disable_lbrv(struct vcpu_svm *svm)
 404 {
 405         u32 *msrpm = svm->msrpm;
 406
 407         svm->vmcb->control.lbr_ctl = 0;
 408         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 409         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 410         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 411         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 412 }
 413
 414 static __init int svm_hardware_setup(void)
 415 {
 416         int cpu;
 417         struct page *iopm_pages;
 418         void *iopm_va;
 419         int r;
 420
 421         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 422
 423         if (!iopm_pages)
 424                 return -ENOMEM;
 425
 426         iopm_va = page_address(iopm_pages);
 427         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 428         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 429         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 430
 431         if (boot_cpu_has(X86_FEATURE_NX))
 432                 kvm_enable_efer_bits(EFER_NX);
 433
 434         for_each_online_cpu(cpu) {
 435                 r = svm_cpu_init(cpu);
 436                 if (r)
 437                         goto err;
 438         }
 439
 440         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 441
 442         if (!svm_has(SVM_FEATURE_NPT))
 443                 npt_enabled = false;
 444
 445         if (npt_enabled && !npt) {
 446                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 447                 npt_enabled = false;
 448         }
 449
 450         if (npt_enabled) {
 451                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 452                 kvm_enable_tdp();
 453         }
 454
 455         return 0;
 456
 457 err:
 458         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 459         iopm_base = 0;
 460         return r;
 461 }
 462
 463 static __exit void svm_hardware_unsetup(void)
 464 {
 465         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 466         iopm_base = 0;
 467 }
 468
 469 static void init_seg(struct vmcb_seg *seg)
 470 {
 471         seg->selector = 0;
 472         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 473                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 474         seg->limit = 0xffff;
 475         seg->base = 0;
 476 }
 477
 478 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 479 {
 480         seg->selector = 0;
 481         seg->attrib = SVM_SELECTOR_P_MASK | type;
 482         seg->limit = 0xffff;
 483         seg->base = 0;
 484 }
 485
 486 static void init_vmcb(struct vcpu_svm *svm)
 487 {
 488         struct vmcb_control_area *control = &svm->vmcb->control;
 489         struct vmcb_save_area *save = &svm->vmcb->save;
 490
 491         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 492                                         INTERCEPT_CR3_MASK |
 493                                         INTERCEPT_CR4_MASK |
 494                                         INTERCEPT_CR8_MASK;
 495
 496         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 497                                         INTERCEPT_CR3_MASK |
 498                                         INTERCEPT_CR4_MASK |
 499                                         INTERCEPT_CR8_MASK;
 500
 501         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 502                                         INTERCEPT_DR1_MASK |
 503                                         INTERCEPT_DR2_MASK |
 504                                         INTERCEPT_DR3_MASK;
 505
 506         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 507                                         INTERCEPT_DR1_MASK |
 508                                         INTERCEPT_DR2_MASK |
 509                                         INTERCEPT_DR3_MASK |
 510                                         INTERCEPT_DR5_MASK |
 511                                         INTERCEPT_DR7_MASK;
 512
 513         control->intercept_exceptions = (1 << PF_VECTOR) |
 514                                         (1 << UD_VECTOR);
 515
 516
 517         control->intercept =    (1ULL << INTERCEPT_INTR) |
 518                                 (1ULL << INTERCEPT_NMI) |
 519                                 (1ULL << INTERCEPT_SMI) |
 520                 /*
 521                  * selective cr0 intercept bug?
 522                  *      0:   0f 22 d8                mov    %eax,%cr3
 523                  *      3:   0f 20 c0                mov    %cr0,%eax
 524                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 525                  *      b:   0f 22 c0                mov    %eax,%cr0
 526                  * set cr3 ->interception
 527                  * get cr0 ->interception
 528                  * set cr0 -> no interception
 529                  */
 530                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 531                                 (1ULL << INTERCEPT_CPUID) |
 532                                 (1ULL << INTERCEPT_INVD) |
 533                                 (1ULL << INTERCEPT_HLT) |
 534                                 (1ULL << INTERCEPT_INVLPGA) |
 535                                 (1ULL << INTERCEPT_IOIO_PROT) |
 536                                 (1ULL << INTERCEPT_MSR_PROT) |
 537                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 538                                 (1ULL << INTERCEPT_SHUTDOWN) |
 539                                 (1ULL << INTERCEPT_VMRUN) |
 540                                 (1ULL << INTERCEPT_VMMCALL) |
 541                                 (1ULL << INTERCEPT_VMLOAD) |
 542                                 (1ULL << INTERCEPT_VMSAVE) |
 543                                 (1ULL << INTERCEPT_STGI) |
 544                                 (1ULL << INTERCEPT_CLGI) |
 545                                 (1ULL << INTERCEPT_SKINIT) |
 546                                 (1ULL << INTERCEPT_WBINVD) |
 547                                 (1ULL << INTERCEPT_MONITOR) |
 548                                 (1ULL << INTERCEPT_MWAIT);
 549
 550         control->iopm_base_pa = iopm_base;
 551         control->msrpm_base_pa = __pa(svm->msrpm);
 552         control->tsc_offset = 0;
 553         control->int_ctl = V_INTR_MASKING_MASK;
 554
 555         init_seg(&save->es);
 556         init_seg(&save->ss);
 557         init_seg(&save->ds);
 558         init_seg(&save->fs);
 559         init_seg(&save->gs);
 560
 561         save->cs.selector = 0xf000;
 562         /* Executable/Readable Code Segment */
 563         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 564                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 565         save->cs.limit = 0xffff;
 566         /*
 567          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 568          * be consistent with it.
 569          *
 570          * Replace when we have real mode working for vmx.
 571          */
 572         save->cs.base = 0xf0000;
 573
 574         save->gdtr.limit = 0xffff;
 575         save->idtr.limit = 0xffff;
 576
 577         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 578         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 579
 580         save->efer = MSR_EFER_SVME_MASK;
 581         save->dr6 = 0xffff0ff0;
 582         save->dr7 = 0x400;
 583         save->rflags = 2;
 584         save->rip = 0x0000fff0;
 585
 586         /*
 587          * cr0 val on cpu init should be 0x60000010, we enable cpu
 588          * cache by default. the orderly way is to enable cache in bios.
 589          */
 590         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 591         save->cr4 = X86_CR4_PAE;
 592         /* rdx = ?? */
 593
 594         if (npt_enabled) {
 595                 /* Setup VMCB for Nested Paging */
 596                 control->nested_ctl = 1;
 597                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 598                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 599                                                 INTERCEPT_CR3_MASK);
 600                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 601                                                  INTERCEPT_CR3_MASK);
 602                 save->g_pat = 0x0007040600070406ULL;
 603                 /* enable caching because the QEMU Bios doesn't enable it */
 604                 save->cr0 = X86_CR0_ET;
 605                 save->cr3 = 0;
 606                 save->cr4 = 0;
 607         }
 608
 609 }
 610
 611 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         init_vmcb(svm);
 616
 617         if (vcpu->vcpu_id != 0) {
 618                 svm->vmcb->save.rip = 0;
 619                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 620                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 627 {
 628         struct vcpu_svm *svm;
 629         struct page *page;
 630         struct page *msrpm_pages;
 631         int err;
 632
 633         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 634         if (!svm) {
 635                 err = -ENOMEM;
 636                 goto out;
 637         }
 638
 639         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 640         if (err)
 641                 goto free_svm;
 642
 643         page = alloc_page(GFP_KERNEL);
 644         if (!page) {
 645                 err = -ENOMEM;
 646                 goto uninit;
 647         }
 648
 649         err = -ENOMEM;
 650         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 651         if (!msrpm_pages)
 652                 goto uninit;
 653         svm->msrpm = page_address(msrpm_pages);
 654         svm_vcpu_init_msrpm(svm->msrpm);
 655
 656         svm->vmcb = page_address(page);
 657         clear_page(svm->vmcb);
 658         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 659         svm->asid_generation = 0;
 660         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 661         init_vmcb(svm);
 662
 663         fx_init(&svm->vcpu);
 664         svm->vcpu.fpu_active = 1;
 665         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 666         if (svm->vcpu.vcpu_id == 0)
 667                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 668
 669         return &svm->vcpu;
 670
 671 uninit:
 672         kvm_vcpu_uninit(&svm->vcpu);
 673 free_svm:
 674         kmem_cache_free(kvm_vcpu_cache, svm);
 675 out:
 676         return ERR_PTR(err);
 677 }
 678
 679 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 680 {
 681         struct vcpu_svm *svm = to_svm(vcpu);
 682
 683         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 684         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 685         kvm_vcpu_uninit(vcpu);
 686         kmem_cache_free(kvm_vcpu_cache, svm);
 687 }
 688
 689 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 690 {
 691         struct vcpu_svm *svm = to_svm(vcpu);
 692         int i;
 693
 694         if (unlikely(cpu != vcpu->cpu)) {
 695                 u64 tsc_this, delta;
 696
 697                 /*
 698                  * Make sure that the guest sees a monotonically
 699                  * increasing TSC.
 700                  */
 701                 rdtscll(tsc_this);
 702                 delta = vcpu->arch.host_tsc - tsc_this;
 703                 svm->vmcb->control.tsc_offset += delta;
 704                 vcpu->cpu = cpu;
 705                 kvm_migrate_apic_timer(vcpu);
 706         }
 707
 708         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 709                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 710 }
 711
 712 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 713 {
 714         struct vcpu_svm *svm = to_svm(vcpu);
 715         int i;
 716
 717         ++vcpu->stat.host_state_reload;
 718         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 719                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 720
 721         rdtscll(vcpu->arch.host_tsc);
 722 }
 723
 724 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 725 {
 726 }
 727
 728 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 729 {
 730         struct vcpu_svm *svm = to_svm(vcpu);
 731
 732         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 733         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 734         vcpu->arch.rip = svm->vmcb->save.rip;
 735 }
 736
 737 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 738 {
 739         struct vcpu_svm *svm = to_svm(vcpu);
 740         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 741         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 742         svm->vmcb->save.rip = vcpu->arch.rip;
 743 }
 744
 745 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 746 {
 747         return to_svm(vcpu)->vmcb->save.rflags;
 748 }
 749
 750 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 751 {
 752         to_svm(vcpu)->vmcb->save.rflags = rflags;
 753 }
 754
 755 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 756 {
 757         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 758
 759         switch (seg) {
 760         case VCPU_SREG_CS: return &save->cs;
 761         case VCPU_SREG_DS: return &save->ds;
 762         case VCPU_SREG_ES: return &save->es;
 763         case VCPU_SREG_FS: return &save->fs;
 764         case VCPU_SREG_GS: return &save->gs;
 765         case VCPU_SREG_SS: return &save->ss;
 766         case VCPU_SREG_TR: return &save->tr;
 767         case VCPU_SREG_LDTR: return &save->ldtr;
 768         }
 769         BUG();
 770         return NULL;
 771 }
 772
 773 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 774 {
 775         struct vmcb_seg *s = svm_seg(vcpu, seg);
 776
 777         return s->base;
 778 }
 779
 780 static void svm_get_segment(struct kvm_vcpu *vcpu,
 781                             struct kvm_segment *var, int seg)
 782 {
 783         struct vmcb_seg *s = svm_seg(vcpu, seg);
 784
 785         var->base = s->base;
 786         var->limit = s->limit;
 787         var->selector = s->selector;
 788         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 789         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 790         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 791         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 792         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 793         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 794         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 795         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 796         var->unusable = !var->present;
 797 }
 798
 799 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 800 {
 801         struct vcpu_svm *svm = to_svm(vcpu);
 802
 803         dt->limit = svm->vmcb->save.idtr.limit;
 804         dt->base = svm->vmcb->save.idtr.base;
 805 }
 806
 807 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 808 {
 809         struct vcpu_svm *svm = to_svm(vcpu);
 810
 811         svm->vmcb->save.idtr.limit = dt->limit;
 812         svm->vmcb->save.idtr.base = dt->base ;
 813 }
 814
 815 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 816 {
 817         struct vcpu_svm *svm = to_svm(vcpu);
 818
 819         dt->limit = svm->vmcb->save.gdtr.limit;
 820         dt->base = svm->vmcb->save.gdtr.base;
 821 }
 822
 823 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 824 {
 825         struct vcpu_svm *svm = to_svm(vcpu);
 826
 827         svm->vmcb->save.gdtr.limit = dt->limit;
 828         svm->vmcb->save.gdtr.base = dt->base ;
 829 }
 830
 831 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 832 {
 833 }
 834
 835 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 836 {
 837         struct vcpu_svm *svm = to_svm(vcpu);
 838
 839 #ifdef CONFIG_X86_64
 840         if (vcpu->arch.shadow_efer & EFER_LME) {
 841                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 842                         vcpu->arch.shadow_efer |= EFER_LMA;
 843                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 844                 }
 845
 846                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 847                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 848                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 849                 }
 850         }
 851 #endif
 852         if (npt_enabled)
 853                 goto set;
 854
 855         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 856                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 857                 vcpu->fpu_active = 1;
 858         }
 859
 860         vcpu->arch.cr0 = cr0;
 861         cr0 |= X86_CR0_PG | X86_CR0_WP;
 862         if (!vcpu->fpu_active) {
 863                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 864                 cr0 |= X86_CR0_TS;
 865         }
 866 set:
 867         /*
 868          * re-enable caching here because the QEMU bios
 869          * does not do it - this results in some delay at
 870          * reboot
 871          */
 872         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 873         svm->vmcb->save.cr0 = cr0;
 874 }
 875
 876 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 877 {
 878        vcpu->arch.cr4 = cr4;
 879        if (!npt_enabled)
 880                cr4 |= X86_CR4_PAE;
 881        to_svm(vcpu)->vmcb->save.cr4 = cr4;
 882 }
 883
 884 static void svm_set_segment(struct kvm_vcpu *vcpu,
 885                             struct kvm_segment *var, int seg)
 886 {
 887         struct vcpu_svm *svm = to_svm(vcpu);
 888         struct vmcb_seg *s = svm_seg(vcpu, seg);
 889
 890         s->base = var->base;
 891         s->limit = var->limit;
 892         s->selector = var->selector;
 893         if (var->unusable)
 894                 s->attrib = 0;
 895         else {
 896                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 897                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 898                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 899                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 900                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 901                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 902                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 903                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 904         }
 905         if (seg == VCPU_SREG_CS)
 906                 svm->vmcb->save.cpl
 907                         = (svm->vmcb->save.cs.attrib
 908                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 909
 910 }
 911
 912 /* FIXME:
 913
 914         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 915         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 916
 917 */
 918
 919 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 920 {
 921         return -EOPNOTSUPP;
 922 }
 923
 924 static int svm_get_irq(struct kvm_vcpu *vcpu)
 925 {
 926         struct vcpu_svm *svm = to_svm(vcpu);
 927         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 928
 929         if (is_external_interrupt(exit_int_info))
 930                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 931         return -1;
 932 }
 933
 934 static void load_host_msrs(struct kvm_vcpu *vcpu)
 935 {
 936 #ifdef CONFIG_X86_64
 937         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 938 #endif
 939 }
 940
 941 static void save_host_msrs(struct kvm_vcpu *vcpu)
 942 {
 943 #ifdef CONFIG_X86_64
 944         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 945 #endif
 946 }
 947
 948 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 949 {
 950         if (svm_data->next_asid > svm_data->max_asid) {
 951                 ++svm_data->asid_generation;
 952                 svm_data->next_asid = 1;
 953                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 954         }
 955
 956         svm->vcpu.cpu = svm_data->cpu;
 957         svm->asid_generation = svm_data->asid_generation;
 958         svm->vmcb->control.asid = svm_data->next_asid++;
 959 }
 960
 961 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 962 {
 963         return to_svm(vcpu)->db_regs[dr];
 964 }
 965
 966 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 967                        int *exception)
 968 {
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970
 971         *exception = 0;
 972
 973         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 974                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 975                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 976                 *exception = DB_VECTOR;
 977                 return;
 978         }
 979
 980         switch (dr) {
 981         case 0 ... 3:
 982                 svm->db_regs[dr] = value;
 983                 return;
 984         case 4 ... 5:
 985                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 986                         *exception = UD_VECTOR;
 987                         return;
 988                 }
 989         case 7: {
 990                 if (value & ~((1ULL << 32) - 1)) {
 991                         *exception = GP_VECTOR;
 992                         return;
 993                 }
 994                 svm->vmcb->save.dr7 = value;
 995                 return;
 996         }
 997         default:
 998                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 999                        __FUNCTION__, dr);
1000                 *exception = UD_VECTOR;
1001                 return;
1002         }
1003 }
1004
1005 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1006 {
1007         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1008         struct kvm *kvm = svm->vcpu.kvm;
1009         u64 fault_address;
1010         u32 error_code;
1011
1012         if (!irqchip_in_kernel(kvm) &&
1013                 is_external_interrupt(exit_int_info))
1014                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1015
1016         fault_address  = svm->vmcb->control.exit_info_2;
1017         error_code = svm->vmcb->control.exit_info_1;
1018         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1019 }
1020
1021 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1022 {
1023         int er;
1024
1025         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1026         if (er != EMULATE_DONE)
1027                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1028         return 1;
1029 }
1030
1031 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1032 {
1033         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1034         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1035                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1036         svm->vcpu.fpu_active = 1;
1037
1038         return 1;
1039 }
1040
1041 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1042 {
1043         /*
1044          * VMCB is undefined after a SHUTDOWN intercept
1045          * so reinitialize it.
1046          */
1047         clear_page(svm->vmcb);
1048         init_vmcb(svm);
1049
1050         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1051         return 0;
1052 }
1053
1054 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1055 {
1056         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1057         int size, down, in, string, rep;
1058         unsigned port;
1059
1060         ++svm->vcpu.stat.io_exits;
1061
1062         svm->next_rip = svm->vmcb->control.exit_info_2;
1063
1064         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1065
1066         if (string) {
1067                 if (emulate_instruction(&svm->vcpu,
1068                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1069                         return 0;
1070                 return 1;
1071         }
1072
1073         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1074         port = io_info >> 16;
1075         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1076         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1077         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1078
1079         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1080 }
1081
1082 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1083 {
1084         return 1;
1085 }
1086
1087 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1088 {
1089         svm->next_rip = svm->vmcb->save.rip + 1;
1090         skip_emulated_instruction(&svm->vcpu);
1091         return kvm_emulate_halt(&svm->vcpu);
1092 }
1093
1094 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1095 {
1096         svm->next_rip = svm->vmcb->save.rip + 3;
1097         skip_emulated_instruction(&svm->vcpu);
1098         kvm_emulate_hypercall(&svm->vcpu);
1099         return 1;
1100 }
1101
1102 static int invalid_op_interception(struct vcpu_svm *svm,
1103                                    struct kvm_run *kvm_run)
1104 {
1105         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1106         return 1;
1107 }
1108
1109 static int task_switch_interception(struct vcpu_svm *svm,
1110                                     struct kvm_run *kvm_run)
1111 {
1112         pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1113         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1114         return 0;
1115 }
1116
1117 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1118 {
1119         svm->next_rip = svm->vmcb->save.rip + 2;
1120         kvm_emulate_cpuid(&svm->vcpu);
1121         return 1;
1122 }
1123
1124 static int emulate_on_interception(struct vcpu_svm *svm,
1125                                    struct kvm_run *kvm_run)
1126 {
1127         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1128                 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1129         return 1;
1130 }
1131
1132 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1133 {
1134         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1135         if (irqchip_in_kernel(svm->vcpu.kvm))
1136                 return 1;
1137         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1138         return 0;
1139 }
1140
1141 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1142 {
1143         struct vcpu_svm *svm = to_svm(vcpu);
1144
1145         switch (ecx) {
1146         case MSR_IA32_TIME_STAMP_COUNTER: {
1147                 u64 tsc;
1148
1149                 rdtscll(tsc);
1150                 *data = svm->vmcb->control.tsc_offset + tsc;
1151                 break;
1152         }
1153         case MSR_K6_STAR:
1154                 *data = svm->vmcb->save.star;
1155                 break;
1156 #ifdef CONFIG_X86_64
1157         case MSR_LSTAR:
1158                 *data = svm->vmcb->save.lstar;
1159                 break;
1160         case MSR_CSTAR:
1161                 *data = svm->vmcb->save.cstar;
1162                 break;
1163         case MSR_KERNEL_GS_BASE:
1164                 *data = svm->vmcb->save.kernel_gs_base;
1165                 break;
1166         case MSR_SYSCALL_MASK:
1167                 *data = svm->vmcb->save.sfmask;
1168                 break;
1169 #endif
1170         case MSR_IA32_SYSENTER_CS:
1171                 *data = svm->vmcb->save.sysenter_cs;
1172                 break;
1173         case MSR_IA32_SYSENTER_EIP:
1174                 *data = svm->vmcb->save.sysenter_eip;
1175                 break;
1176         case MSR_IA32_SYSENTER_ESP:
1177                 *data = svm->vmcb->save.sysenter_esp;
1178                 break;
1179         /* Nobody will change the following 5 values in the VMCB so
1180            we can safely return them on rdmsr. They will always be 0
1181            until LBRV is implemented. */
1182         case MSR_IA32_DEBUGCTLMSR:
1183                 *data = svm->vmcb->save.dbgctl;
1184                 break;
1185         case MSR_IA32_LASTBRANCHFROMIP:
1186                 *data = svm->vmcb->save.br_from;
1187                 break;
1188         case MSR_IA32_LASTBRANCHTOIP:
1189                 *data = svm->vmcb->save.br_to;
1190                 break;
1191         case MSR_IA32_LASTINTFROMIP:
1192                 *data = svm->vmcb->save.last_excp_from;
1193                 break;
1194         case MSR_IA32_LASTINTTOIP:
1195                 *data = svm->vmcb->save.last_excp_to;
1196                 break;
1197         default:
1198                 return kvm_get_msr_common(vcpu, ecx, data);
1199         }
1200         return 0;
1201 }
1202
1203 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1204 {
1205         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1206         u64 data;
1207
1208         if (svm_get_msr(&svm->vcpu, ecx, &data))
1209                 kvm_inject_gp(&svm->vcpu, 0);
1210         else {
1211                 svm->vmcb->save.rax = data & 0xffffffff;
1212                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1213                 svm->next_rip = svm->vmcb->save.rip + 2;
1214                 skip_emulated_instruction(&svm->vcpu);
1215         }
1216         return 1;
1217 }
1218
1219 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1220 {
1221         struct vcpu_svm *svm = to_svm(vcpu);
1222
1223         switch (ecx) {
1224         case MSR_IA32_TIME_STAMP_COUNTER: {
1225                 u64 tsc;
1226
1227                 rdtscll(tsc);
1228                 svm->vmcb->control.tsc_offset = data - tsc;
1229                 break;
1230         }
1231         case MSR_K6_STAR:
1232                 svm->vmcb->save.star = data;
1233                 break;
1234 #ifdef CONFIG_X86_64
1235         case MSR_LSTAR:
1236                 svm->vmcb->save.lstar = data;
1237                 break;
1238         case MSR_CSTAR:
1239                 svm->vmcb->save.cstar = data;
1240                 break;
1241         case MSR_KERNEL_GS_BASE:
1242                 svm->vmcb->save.kernel_gs_base = data;
1243                 break;
1244         case MSR_SYSCALL_MASK:
1245                 svm->vmcb->save.sfmask = data;
1246                 break;
1247 #endif
1248         case MSR_IA32_SYSENTER_CS:
1249                 svm->vmcb->save.sysenter_cs = data;
1250                 break;
1251         case MSR_IA32_SYSENTER_EIP:
1252                 svm->vmcb->save.sysenter_eip = data;
1253                 break;
1254         case MSR_IA32_SYSENTER_ESP:
1255                 svm->vmcb->save.sysenter_esp = data;
1256                 break;
1257         case MSR_IA32_DEBUGCTLMSR:
1258                 if (!svm_has(SVM_FEATURE_LBRV)) {
1259                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1260                                         __FUNCTION__, data);
1261                         break;
1262                 }
1263                 if (data & DEBUGCTL_RESERVED_BITS)
1264                         return 1;
1265
1266                 svm->vmcb->save.dbgctl = data;
1267                 if (data & (1ULL<<0))
1268                         svm_enable_lbrv(svm);
1269                 else
1270                         svm_disable_lbrv(svm);
1271                 break;
1272         case MSR_K7_EVNTSEL0:
1273         case MSR_K7_EVNTSEL1:
1274         case MSR_K7_EVNTSEL2:
1275         case MSR_K7_EVNTSEL3:
1276                 /*
1277                  * only support writing 0 to the performance counters for now
1278                  * to make Windows happy. Should be replaced by a real
1279                  * performance counter emulation later.
1280                  */
1281                 if (data != 0)
1282                         goto unhandled;
1283                 break;
1284         default:
1285         unhandled:
1286                 return kvm_set_msr_common(vcpu, ecx, data);
1287         }
1288         return 0;
1289 }
1290
1291 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1292 {
1293         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1294         u64 data = (svm->vmcb->save.rax & -1u)
1295                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1296         svm->next_rip = svm->vmcb->save.rip + 2;
1297         if (svm_set_msr(&svm->vcpu, ecx, data))
1298                 kvm_inject_gp(&svm->vcpu, 0);
1299         else
1300                 skip_emulated_instruction(&svm->vcpu);
1301         return 1;
1302 }
1303
1304 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1305 {
1306         if (svm->vmcb->control.exit_info_1)
1307                 return wrmsr_interception(svm, kvm_run);
1308         else
1309                 return rdmsr_interception(svm, kvm_run);
1310 }
1311
1312 static int interrupt_window_interception(struct vcpu_svm *svm,
1313                                    struct kvm_run *kvm_run)
1314 {
1315         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1316         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1317         /*
1318          * If the user space waits to inject interrupts, exit as soon as
1319          * possible
1320          */
1321         if (kvm_run->request_interrupt_window &&
1322             !svm->vcpu.arch.irq_summary) {
1323                 ++svm->vcpu.stat.irq_window_exits;
1324                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1325                 return 0;
1326         }
1327
1328         return 1;
1329 }
1330
1331 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1332                                       struct kvm_run *kvm_run) = {
1333         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1334         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1335         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1336         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1337         /* for now: */
1338         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1339         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1340         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1341         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1342         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1343         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1344         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1345         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1346         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1347         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1348         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1349         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1350         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1351         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1352         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1353         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1354         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1355         [SVM_EXIT_INTR]                         = nop_on_interception,
1356         [SVM_EXIT_NMI]                          = nop_on_interception,
1357         [SVM_EXIT_SMI]                          = nop_on_interception,
1358         [SVM_EXIT_INIT]                         = nop_on_interception,
1359         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1360         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1361         [SVM_EXIT_CPUID]                        = cpuid_interception,
1362         [SVM_EXIT_INVD]                         = emulate_on_interception,
1363         [SVM_EXIT_HLT]                          = halt_interception,
1364         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1365         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1366         [SVM_EXIT_IOIO]                         = io_interception,
1367         [SVM_EXIT_MSR]                          = msr_interception,
1368         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1369         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1370         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1371         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1372         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1373         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1374         [SVM_EXIT_STGI]                         = invalid_op_interception,
1375         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1376         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1377         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1378         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1379         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1380         [SVM_EXIT_NPF]                          = pf_interception,
1381 };
1382
1383 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1384 {
1385         struct vcpu_svm *svm = to_svm(vcpu);
1386         u32 exit_code = svm->vmcb->control.exit_code;
1387
1388         if (npt_enabled) {
1389                 int mmu_reload = 0;
1390                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1391                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1392                         mmu_reload = 1;
1393                 }
1394                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1395                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1396                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1397                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1398                                 kvm_inject_gp(vcpu, 0);
1399                                 return 1;
1400                         }
1401                 }
1402                 if (mmu_reload) {
1403                         kvm_mmu_reset_context(vcpu);
1404                         kvm_mmu_load(vcpu);
1405                 }
1406         }
1407
1408         kvm_reput_irq(svm);
1409
1410         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1411                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1412                 kvm_run->fail_entry.hardware_entry_failure_reason
1413                         = svm->vmcb->control.exit_code;
1414                 return 0;
1415         }
1416
1417         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1418             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1419             exit_code != SVM_EXIT_NPF)
1420                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1421                        "exit_code 0x%x\n",
1422                        __FUNCTION__, svm->vmcb->control.exit_int_info,
1423                        exit_code);
1424
1425         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1426             || !svm_exit_handlers[exit_code]) {
1427                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1428                 kvm_run->hw.hardware_exit_reason = exit_code;
1429                 return 0;
1430         }
1431
1432         return svm_exit_handlers[exit_code](svm, kvm_run);
1433 }
1434
1435 static void reload_tss(struct kvm_vcpu *vcpu)
1436 {
1437         int cpu = raw_smp_processor_id();
1438
1439         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1440         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1441         load_TR_desc();
1442 }
1443
1444 static void pre_svm_run(struct vcpu_svm *svm)
1445 {
1446         int cpu = raw_smp_processor_id();
1447
1448         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1449
1450         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1451         if (svm->vcpu.cpu != cpu ||
1452             svm->asid_generation != svm_data->asid_generation)
1453                 new_asid(svm, svm_data);
1454 }
1455
1456
1457 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1458 {
1459         struct vmcb_control_area *control;
1460
1461         control = &svm->vmcb->control;
1462         control->int_vector = irq;
1463         control->int_ctl &= ~V_INTR_PRIO_MASK;
1464         control->int_ctl |= V_IRQ_MASK |
1465                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1466 }
1467
1468 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1469 {
1470         struct vcpu_svm *svm = to_svm(vcpu);
1471
1472         svm_inject_irq(svm, irq);
1473 }
1474
1475 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1476 {
1477         struct vcpu_svm *svm = to_svm(vcpu);
1478         struct vmcb *vmcb = svm->vmcb;
1479         int intr_vector = -1;
1480
1481         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1482             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1483                 intr_vector = vmcb->control.exit_int_info &
1484                               SVM_EVTINJ_VEC_MASK;
1485                 vmcb->control.exit_int_info = 0;
1486                 svm_inject_irq(svm, intr_vector);
1487                 return;
1488         }
1489
1490         if (vmcb->control.int_ctl & V_IRQ_MASK)
1491                 return;
1492
1493         if (!kvm_cpu_has_interrupt(vcpu))
1494                 return;
1495
1496         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1497             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1498             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1499                 /* unable to deliver irq, set pending irq */
1500                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1501                 svm_inject_irq(svm, 0x0);
1502                 return;
1503         }
1504         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1505         intr_vector = kvm_cpu_get_interrupt(vcpu);
1506         svm_inject_irq(svm, intr_vector);
1507         kvm_timer_intr_post(vcpu, intr_vector);
1508 }
1509
1510 static void kvm_reput_irq(struct vcpu_svm *svm)
1511 {
1512         struct vmcb_control_area *control = &svm->vmcb->control;
1513
1514         if ((control->int_ctl & V_IRQ_MASK)
1515             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1516                 control->int_ctl &= ~V_IRQ_MASK;
1517                 push_irq(&svm->vcpu, control->int_vector);
1518         }
1519
1520         svm->vcpu.arch.interrupt_window_open =
1521                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1522 }
1523
1524 static void svm_do_inject_vector(struct vcpu_svm *svm)
1525 {
1526         struct kvm_vcpu *vcpu = &svm->vcpu;
1527         int word_index = __ffs(vcpu->arch.irq_summary);
1528         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1529         int irq = word_index * BITS_PER_LONG + bit_index;
1530
1531         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1532         if (!vcpu->arch.irq_pending[word_index])
1533                 clear_bit(word_index, &vcpu->arch.irq_summary);
1534         svm_inject_irq(svm, irq);
1535 }
1536
1537 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1538                                        struct kvm_run *kvm_run)
1539 {
1540         struct vcpu_svm *svm = to_svm(vcpu);
1541         struct vmcb_control_area *control = &svm->vmcb->control;
1542
1543         svm->vcpu.arch.interrupt_window_open =
1544                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1545                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1546
1547         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1548                 /*
1549                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1550                  */
1551                 svm_do_inject_vector(svm);
1552
1553         /*
1554          * Interrupts blocked.  Wait for unblock.
1555          */
1556         if (!svm->vcpu.arch.interrupt_window_open &&
1557             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1558                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1559          else
1560                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1561 }
1562
1563 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1564 {
1565         return 0;
1566 }
1567
1568 static void save_db_regs(unsigned long *db_regs)
1569 {
1570         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1571         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1572         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1573         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1574 }
1575
1576 static void load_db_regs(unsigned long *db_regs)
1577 {
1578         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1579         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1580         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1581         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1582 }
1583
1584 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1585 {
1586         force_new_asid(vcpu);
1587 }
1588
1589 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1590 {
1591 }
1592
1593 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1594 {
1595         struct vcpu_svm *svm = to_svm(vcpu);
1596         u16 fs_selector;
1597         u16 gs_selector;
1598         u16 ldt_selector;
1599
1600         pre_svm_run(svm);
1601
1602         save_host_msrs(vcpu);
1603         fs_selector = read_fs();
1604         gs_selector = read_gs();
1605         ldt_selector = read_ldt();
1606         svm->host_cr2 = kvm_read_cr2();
1607         svm->host_dr6 = read_dr6();
1608         svm->host_dr7 = read_dr7();
1609         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1610         /* required for live migration with NPT */
1611         if (npt_enabled)
1612                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1613
1614         if (svm->vmcb->save.dr7 & 0xff) {
1615                 write_dr7(0);
1616                 save_db_regs(svm->host_db_regs);
1617                 load_db_regs(svm->db_regs);
1618         }
1619
1620         clgi();
1621
1622         local_irq_enable();
1623
1624         asm volatile (
1625 #ifdef CONFIG_X86_64
1626                 "push %%rbp; \n\t"
1627 #else
1628                 "push %%ebp; \n\t"
1629 #endif
1630
1631 #ifdef CONFIG_X86_64
1632                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1633                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1634                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1635                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1636                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1637                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1638                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1639                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1640                 "mov %c[r10](%[svm]), %%r10 \n\t"
1641                 "mov %c[r11](%[svm]), %%r11 \n\t"
1642                 "mov %c[r12](%[svm]), %%r12 \n\t"
1643                 "mov %c[r13](%[svm]), %%r13 \n\t"
1644                 "mov %c[r14](%[svm]), %%r14 \n\t"
1645                 "mov %c[r15](%[svm]), %%r15 \n\t"
1646 #else
1647                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1648                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1649                 "mov %c[rdx](%[svm]), %%edx \n\t"
1650                 "mov %c[rsi](%[svm]), %%esi \n\t"
1651                 "mov %c[rdi](%[svm]), %%edi \n\t"
1652                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1653 #endif
1654
1655 #ifdef CONFIG_X86_64
1656                 /* Enter guest mode */
1657                 "push %%rax \n\t"
1658                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1659                 SVM_VMLOAD "\n\t"
1660                 SVM_VMRUN "\n\t"
1661                 SVM_VMSAVE "\n\t"
1662                 "pop %%rax \n\t"
1663 #else
1664                 /* Enter guest mode */
1665                 "push %%eax \n\t"
1666                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1667                 SVM_VMLOAD "\n\t"
1668                 SVM_VMRUN "\n\t"
1669                 SVM_VMSAVE "\n\t"
1670                 "pop %%eax \n\t"
1671 #endif
1672
1673                 /* Save guest registers, load host registers */
1674 #ifdef CONFIG_X86_64
1675                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1676                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1677                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1678                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1679                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1680                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1681                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1682                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1683                 "mov %%r10, %c[r10](%[svm]) \n\t"
1684                 "mov %%r11, %c[r11](%[svm]) \n\t"
1685                 "mov %%r12, %c[r12](%[svm]) \n\t"
1686                 "mov %%r13, %c[r13](%[svm]) \n\t"
1687                 "mov %%r14, %c[r14](%[svm]) \n\t"
1688                 "mov %%r15, %c[r15](%[svm]) \n\t"
1689
1690                 "pop  %%rbp; \n\t"
1691 #else
1692                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1693                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1694                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1695                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1696                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1697                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1698
1699                 "pop  %%ebp; \n\t"
1700 #endif
1701                 :
1702                 : [svm]"a"(svm),
1703                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1704                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1705                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1706                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1707                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1708                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1709                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1710 #ifdef CONFIG_X86_64
1711                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1712                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1713                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1714                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1715                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1716                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1717                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1718                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1719 #endif
1720                 : "cc", "memory"
1721 #ifdef CONFIG_X86_64
1722                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1723                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1724 #else
1725                 , "ebx", "ecx", "edx" , "esi", "edi"
1726 #endif
1727                 );
1728
1729         if ((svm->vmcb->save.dr7 & 0xff))
1730                 load_db_regs(svm->host_db_regs);
1731
1732         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1733
1734         write_dr6(svm->host_dr6);
1735         write_dr7(svm->host_dr7);
1736         kvm_write_cr2(svm->host_cr2);
1737
1738         load_fs(fs_selector);
1739         load_gs(gs_selector);
1740         load_ldt(ldt_selector);
1741         load_host_msrs(vcpu);
1742
1743         reload_tss(vcpu);
1744
1745         local_irq_disable();
1746
1747         stgi();
1748
1749         svm->next_rip = 0;
1750 }
1751
1752 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1753 {
1754         struct vcpu_svm *svm = to_svm(vcpu);
1755
1756         if (npt_enabled) {
1757                 svm->vmcb->control.nested_cr3 = root;
1758                 force_new_asid(vcpu);
1759                 return;
1760         }
1761
1762         svm->vmcb->save.cr3 = root;
1763         force_new_asid(vcpu);
1764
1765         if (vcpu->fpu_active) {
1766                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1767                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1768                 vcpu->fpu_active = 0;
1769         }
1770 }
1771
1772 static int is_disabled(void)
1773 {
1774         u64 vm_cr;
1775
1776         rdmsrl(MSR_VM_CR, vm_cr);
1777         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1778                 return 1;
1779
1780         return 0;
1781 }
1782
1783 static void
1784 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1785 {
1786         /*
1787          * Patch in the VMMCALL instruction:
1788          */
1789         hypercall[0] = 0x0f;
1790         hypercall[1] = 0x01;
1791         hypercall[2] = 0xd9;
1792 }
1793
1794 static void svm_check_processor_compat(void *rtn)
1795 {
1796         *(int *)rtn = 0;
1797 }
1798
1799 static bool svm_cpu_has_accelerated_tpr(void)
1800 {
1801         return false;
1802 }
1803
1804 static struct kvm_x86_ops svm_x86_ops = {
1805         .cpu_has_kvm_support = has_svm,
1806         .disabled_by_bios = is_disabled,
1807         .hardware_setup = svm_hardware_setup,
1808         .hardware_unsetup = svm_hardware_unsetup,
1809         .check_processor_compatibility = svm_check_processor_compat,
1810         .hardware_enable = svm_hardware_enable,
1811         .hardware_disable = svm_hardware_disable,
1812         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1813
1814         .vcpu_create = svm_create_vcpu,
1815         .vcpu_free = svm_free_vcpu,
1816         .vcpu_reset = svm_vcpu_reset,
1817
1818         .prepare_guest_switch = svm_prepare_guest_switch,
1819         .vcpu_load = svm_vcpu_load,
1820         .vcpu_put = svm_vcpu_put,
1821         .vcpu_decache = svm_vcpu_decache,
1822
1823         .set_guest_debug = svm_guest_debug,
1824         .get_msr = svm_get_msr,
1825         .set_msr = svm_set_msr,
1826         .get_segment_base = svm_get_segment_base,
1827         .get_segment = svm_get_segment,
1828         .set_segment = svm_set_segment,
1829         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1830         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1831         .set_cr0 = svm_set_cr0,
1832         .set_cr3 = svm_set_cr3,
1833         .set_cr4 = svm_set_cr4,
1834         .set_efer = svm_set_efer,
1835         .get_idt = svm_get_idt,
1836         .set_idt = svm_set_idt,
1837         .get_gdt = svm_get_gdt,
1838         .set_gdt = svm_set_gdt,
1839         .get_dr = svm_get_dr,
1840         .set_dr = svm_set_dr,
1841         .cache_regs = svm_cache_regs,
1842         .decache_regs = svm_decache_regs,
1843         .get_rflags = svm_get_rflags,
1844         .set_rflags = svm_set_rflags,
1845
1846         .tlb_flush = svm_flush_tlb,
1847
1848         .run = svm_vcpu_run,
1849         .handle_exit = handle_exit,
1850         .skip_emulated_instruction = skip_emulated_instruction,
1851         .patch_hypercall = svm_patch_hypercall,
1852         .get_irq = svm_get_irq,
1853         .set_irq = svm_set_irq,
1854         .queue_exception = svm_queue_exception,
1855         .exception_injected = svm_exception_injected,
1856         .inject_pending_irq = svm_intr_assist,
1857         .inject_pending_vectors = do_interrupt_requests,
1858
1859         .set_tss_addr = svm_set_tss_addr,
1860 };
1861
1862 static int __init svm_init(void)
1863 {
1864         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1865                               THIS_MODULE);
1866 }
1867
1868 static void __exit svm_exit(void)
1869 {
1870         kvm_exit();
1871 }
1872
1873 module_init(svm_init)
1874 module_exit(svm_exit)