Merge nommu branch
[linux-2.6] / arch / arm / mach-ixp4xx / common.c
1 /*
2  * arch/arm/mach-ixp4xx/common.c
3  *
4  * Generic code shared across all IXP4XX platforms
5  *
6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7  *
8  * Copyright 2002 (c) Intel Corporation
9  * Copyright 2003-2004 (c) MontaVista, Software, Inc. 
10  * 
11  * This file is licensed under  the terms of the GNU General Public 
12  * License version 2. This program is licensed "as is" without any 
13  * warranty of any kind, whether express or implied.
14  */
15
16 #include <linux/kernel.h>
17 #include <linux/mm.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/sched.h>
21 #include <linux/tty.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial_core.h>
24 #include <linux/bootmem.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27 #include <linux/time.h>
28 #include <linux/timex.h>
29 #include <linux/clocksource.h>
30
31 #include <asm/hardware.h>
32 #include <asm/uaccess.h>
33 #include <asm/io.h>
34 #include <asm/pgtable.h>
35 #include <asm/page.h>
36 #include <asm/irq.h>
37
38 #include <asm/mach/map.h>
39 #include <asm/mach/irq.h>
40 #include <asm/mach/time.h>
41
42 /*************************************************************************
43  * IXP4xx chipset I/O mapping
44  *************************************************************************/
45 static struct map_desc ixp4xx_io_desc[] __initdata = {
46         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
47                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
48                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
49                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
50                 .type           = MT_DEVICE
51         }, {    /* Expansion Bus Config Registers */
52                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
53                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
54                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
55                 .type           = MT_DEVICE
56         }, {    /* PCI Registers */
57                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
58                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
59                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
60                 .type           = MT_DEVICE
61         },
62 #ifdef CONFIG_DEBUG_LL
63         {       /* Debug UART mapping */
64                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
65                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
66                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
67                 .type           = MT_DEVICE
68         }
69 #endif
70 };
71
72 void __init ixp4xx_map_io(void)
73 {
74         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
75 }
76
77
78 /*************************************************************************
79  * IXP4xx chipset IRQ handling
80  *
81  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
82  *       (be it PCI or something else) configures that GPIO line
83  *       as an IRQ.
84  **************************************************************************/
85 enum ixp4xx_irq_type {
86         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
87 };
88
89 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
90
91 /*
92  * IRQ -> GPIO mapping table
93  */
94 static signed char irq2gpio[32] = {
95         -1, -1, -1, -1, -1, -1,  0,  1,
96         -1, -1, -1, -1, -1, -1, -1, -1,
97         -1, -1, -1,  2,  3,  4,  5,  6,
98          7,  8,  9, 10, 11, 12, -1, -1,
99 };
100
101 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
102 {
103         int line = irq2gpio[irq];
104         u32 int_style;
105         enum ixp4xx_irq_type irq_type;
106         volatile u32 *int_reg;
107
108         /*
109          * Only for GPIO IRQs
110          */
111         if (line < 0)
112                 return -EINVAL;
113
114         switch (type){
115         case IRQT_BOTHEDGE:
116                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
117                 irq_type = IXP4XX_IRQ_EDGE;
118                 break;
119         case IRQT_RISING:
120                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
121                 irq_type = IXP4XX_IRQ_EDGE;
122                 break;
123         case IRQT_FALLING:
124                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
125                 irq_type = IXP4XX_IRQ_EDGE;
126                 break;
127         case IRQT_HIGH:
128                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
129                 irq_type = IXP4XX_IRQ_LEVEL;
130                 break;
131         case IRQT_LOW:
132                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
133                 irq_type = IXP4XX_IRQ_LEVEL;
134                 break;
135         default:
136                 return -EINVAL;
137         }
138         ixp4xx_config_irq(irq, irq_type);
139
140         if (line >= 8) {        /* pins 8-15 */
141                 line -= 8;
142                 int_reg = IXP4XX_GPIO_GPIT2R;
143         } else {                /* pins 0-7 */
144                 int_reg = IXP4XX_GPIO_GPIT1R;
145         }
146
147         /* Clear the style for the appropriate pin */
148         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
149                         (line * IXP4XX_GPIO_STYLE_SIZE));
150
151         *IXP4XX_GPIO_GPISR = (1 << line);
152
153         /* Set the new style */
154         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
155
156         /* Configure the line as an input */
157         gpio_line_config(line, IXP4XX_GPIO_IN);
158
159         return 0;
160 }
161
162 static void ixp4xx_irq_mask(unsigned int irq)
163 {
164         if (cpu_is_ixp46x() && irq >= 32)
165                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
166         else
167                 *IXP4XX_ICMR &= ~(1 << irq);
168 }
169
170 static void ixp4xx_irq_unmask(unsigned int irq)
171 {
172         if (cpu_is_ixp46x() && irq >= 32)
173                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
174         else
175                 *IXP4XX_ICMR |= (1 << irq);
176 }
177
178 static void ixp4xx_irq_ack(unsigned int irq)
179 {
180         int line = (irq < 32) ? irq2gpio[irq] : -1;
181
182         if (line >= 0)
183                 *IXP4XX_GPIO_GPISR = (1 << line);
184 }
185
186 /*
187  * Level triggered interrupts on GPIO lines can only be cleared when the
188  * interrupt condition disappears.
189  */
190 static void ixp4xx_irq_level_unmask(unsigned int irq)
191 {
192         ixp4xx_irq_ack(irq);
193         ixp4xx_irq_unmask(irq);
194 }
195
196 static struct irqchip ixp4xx_irq_level_chip = {
197         .ack            = ixp4xx_irq_mask,
198         .mask           = ixp4xx_irq_mask,
199         .unmask         = ixp4xx_irq_level_unmask,
200         .set_type       = ixp4xx_set_irq_type,
201 };
202
203 static struct irqchip ixp4xx_irq_edge_chip = {
204         .ack            = ixp4xx_irq_ack,
205         .mask           = ixp4xx_irq_mask,
206         .unmask         = ixp4xx_irq_unmask,
207         .set_type       = ixp4xx_set_irq_type,
208 };
209
210 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
211 {
212         switch (type) {
213         case IXP4XX_IRQ_LEVEL:
214                 set_irq_chip(irq, &ixp4xx_irq_level_chip);
215                 set_irq_handler(irq, do_level_IRQ);
216                 break;
217         case IXP4XX_IRQ_EDGE:
218                 set_irq_chip(irq, &ixp4xx_irq_edge_chip);
219                 set_irq_handler(irq, do_edge_IRQ);
220                 break;
221         }
222         set_irq_flags(irq, IRQF_VALID);
223 }
224
225 void __init ixp4xx_init_irq(void)
226 {
227         int i = 0;
228
229         /* Route all sources to IRQ instead of FIQ */
230         *IXP4XX_ICLR = 0x0;
231
232         /* Disable all interrupt */
233         *IXP4XX_ICMR = 0x0; 
234
235         if (cpu_is_ixp46x()) {
236                 /* Route upper 32 sources to IRQ instead of FIQ */
237                 *IXP4XX_ICLR2 = 0x00;
238
239                 /* Disable upper 32 interrupts */
240                 *IXP4XX_ICMR2 = 0x00;
241         }
242
243         /* Default to all level triggered */
244         for(i = 0; i < NR_IRQS; i++)
245                 ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL);
246 }
247
248
249 /*************************************************************************
250  * IXP4xx timer tick
251  * We use OS timer1 on the CPU for the timer tick and the timestamp 
252  * counter as a source of real clock ticks to account for missed jiffies.
253  *************************************************************************/
254
255 static unsigned volatile last_jiffy_time;
256
257 #define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
258
259 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
260 {
261         write_seqlock(&xtime_lock);
262
263         /* Clear Pending Interrupt by writing '1' to it */
264         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
265
266         /*
267          * Catch up with the real idea of time
268          */
269         while ((signed long)(*IXP4XX_OSTS - last_jiffy_time) >= LATCH) {
270                 timer_tick(regs);
271                 last_jiffy_time += LATCH;
272         }
273
274         write_sequnlock(&xtime_lock);
275
276         return IRQ_HANDLED;
277 }
278
279 static struct irqaction ixp4xx_timer_irq = {
280         .name           = "IXP4xx Timer Tick",
281         .flags          = IRQF_DISABLED | IRQF_TIMER,
282         .handler        = ixp4xx_timer_interrupt,
283 };
284
285 static void __init ixp4xx_timer_init(void)
286 {
287         /* Clear Pending Interrupt by writing '1' to it */
288         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
289
290         /* Setup the Timer counter value */
291         *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
292
293         /* Reset time-stamp counter */
294         *IXP4XX_OSTS = 0;
295         last_jiffy_time = 0;
296
297         /* Connect the interrupt handler and enable the interrupt */
298         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
299 }
300
301 struct sys_timer ixp4xx_timer = {
302         .init           = ixp4xx_timer_init,
303 };
304
305 static struct resource ixp46x_i2c_resources[] = {
306         [0] = {
307                 .start  = 0xc8011000,
308                 .end    = 0xc801101c,
309                 .flags  = IORESOURCE_MEM,
310         },
311         [1] = {
312                 .start  = IRQ_IXP4XX_I2C,
313                 .end    = IRQ_IXP4XX_I2C,
314                 .flags  = IORESOURCE_IRQ
315         }
316 };
317
318 /*
319  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
320  * we just use the same device name.
321  */
322 static struct platform_device ixp46x_i2c_controller = {
323         .name           = "IOP3xx-I2C",
324         .id             = 0,
325         .num_resources  = 2,
326         .resource       = ixp46x_i2c_resources
327 };
328
329 static struct platform_device *ixp46x_devices[] __initdata = {
330         &ixp46x_i2c_controller
331 };
332
333 unsigned long ixp4xx_exp_bus_size;
334 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
335
336 void __init ixp4xx_sys_init(void)
337 {
338         ixp4xx_exp_bus_size = SZ_16M;
339
340         if (cpu_is_ixp46x()) {
341                 int region;
342
343                 platform_add_devices(ixp46x_devices,
344                                 ARRAY_SIZE(ixp46x_devices));
345
346                 for (region = 0; region < 7; region++) {
347                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
348                                 ixp4xx_exp_bus_size = SZ_32M;
349                                 break;
350                         }
351                 }
352         }
353
354         printk("IXP4xx: Using %luMiB expansion bus window size\n",
355                         ixp4xx_exp_bus_size >> 20);
356 }
357
358 cycle_t ixp4xx_get_cycles(void)
359 {
360         return *IXP4XX_OSTS;
361 }
362
363 static struct clocksource clocksource_ixp4xx = {
364         .name           = "OSTS",
365         .rating         = 200,
366         .read           = ixp4xx_get_cycles,
367         .mask           = CLOCKSOURCE_MASK(32),
368         .shift          = 20,
369         .is_continuous  = 1,
370 };
371
372 unsigned long ixp4xx_timer_freq = FREQ;
373 static int __init ixp4xx_clocksource_init(void)
374 {
375         clocksource_ixp4xx.mult =
376                 clocksource_hz2mult(ixp4xx_timer_freq,
377                                     clocksource_ixp4xx.shift);
378         clocksource_register(&clocksource_ixp4xx);
379
380         return 0;
381 }
382
383 device_initcall(ixp4xx_clocksource_init);