2 * arch/arm/mach-ixp2000/core.c
4 * Common routines used by all IXP2400/2800 based platforms.
6 * Author: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2004 (C) MontaVista Software, Inc.
10 * Based on work Copyright (C) 2002-2003 Intel Corporation
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
17 #include <linux/config.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
21 #include <linux/sched.h>
22 #include <linux/interrupt.h>
23 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/bitops.h>
26 #include <linux/serial_8250.h>
29 #include <asm/types.h>
30 #include <asm/setup.h>
31 #include <asm/memory.h>
32 #include <asm/hardware.h>
34 #include <asm/system.h>
35 #include <asm/tlbflush.h>
36 #include <asm/pgtable.h>
38 #include <asm/mach/map.h>
39 #include <asm/mach/time.h>
40 #include <asm/mach/irq.h>
42 #include <asm/arch/gpio.h>
44 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
45 static unsigned long ixp2000_slowport_irq_flags;
47 /*************************************************************************
48 * Slowport access routines
49 *************************************************************************/
50 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
52 spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
54 old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
55 old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
56 old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
57 old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
58 old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
60 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
61 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
62 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
63 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
64 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
67 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
69 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
70 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
71 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
72 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
73 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
75 spin_unlock_irqrestore(&ixp2000_slowport_lock,
76 ixp2000_slowport_irq_flags);
79 /*************************************************************************
80 * Chip specific mappings shared by all IXP2000 systems
81 *************************************************************************/
82 static struct map_desc ixp2000_io_desc[] __initdata = {
84 .virtual = IXP2000_CAP_VIRT_BASE,
85 .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
86 .length = IXP2000_CAP_SIZE,
87 .type = MT_IXP2000_DEVICE,
89 .virtual = IXP2000_INTCTL_VIRT_BASE,
90 .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
91 .length = IXP2000_INTCTL_SIZE,
92 .type = MT_IXP2000_DEVICE,
94 .virtual = IXP2000_PCI_CREG_VIRT_BASE,
95 .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
96 .length = IXP2000_PCI_CREG_SIZE,
97 .type = MT_IXP2000_DEVICE,
99 .virtual = IXP2000_PCI_CSR_VIRT_BASE,
100 .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
101 .length = IXP2000_PCI_CSR_SIZE,
102 .type = MT_IXP2000_DEVICE,
104 .virtual = IXP2000_MSF_VIRT_BASE,
105 .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
106 .length = IXP2000_MSF_SIZE,
107 .type = MT_IXP2000_DEVICE,
109 .virtual = IXP2000_PCI_IO_VIRT_BASE,
110 .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
111 .length = IXP2000_PCI_IO_SIZE,
112 .type = MT_IXP2000_DEVICE,
114 .virtual = IXP2000_PCI_CFG0_VIRT_BASE,
115 .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
116 .length = IXP2000_PCI_CFG0_SIZE,
117 .type = MT_IXP2000_DEVICE,
119 .virtual = IXP2000_PCI_CFG1_VIRT_BASE,
120 .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
121 .length = IXP2000_PCI_CFG1_SIZE,
122 .type = MT_IXP2000_DEVICE,
126 void __init ixp2000_map_io(void)
129 * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE so that
130 * XCB=101 (to avoid triggering erratum #66), and given that
131 * this mode speeds up I/O accesses and we have write buffer
132 * flushes in the right places anyway, it doesn't hurt to use
133 * XCB=101 for all IXP2000s.
135 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
137 /* Set slowport to 8-bit mode. */
138 ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
142 /*************************************************************************
143 * Serial port support for IXP2000
144 *************************************************************************/
145 static struct plat_serial8250_port ixp2000_serial_port[] = {
147 .mapbase = IXP2000_UART_PHYS_BASE,
148 .membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
149 .irq = IRQ_IXP2000_UART,
150 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
158 static struct resource ixp2000_uart_resource = {
159 .start = IXP2000_UART_PHYS_BASE,
160 .end = IXP2000_UART_PHYS_BASE + 0x1f,
161 .flags = IORESOURCE_MEM,
164 static struct platform_device ixp2000_serial_device = {
165 .name = "serial8250",
166 .id = PLAT8250_DEV_PLATFORM,
168 .platform_data = ixp2000_serial_port,
171 .resource = &ixp2000_uart_resource,
174 void __init ixp2000_uart_init(void)
176 platform_device_register(&ixp2000_serial_device);
180 /*************************************************************************
181 * Timer-tick functions for IXP2000
182 *************************************************************************/
183 static unsigned ticks_per_jiffy;
184 static unsigned ticks_per_usec;
185 static unsigned next_jiffy_time;
186 static volatile unsigned long *missing_jiffy_timer_csr;
188 unsigned long ixp2000_gettimeoffset (void)
190 unsigned long offset;
192 offset = next_jiffy_time - *missing_jiffy_timer_csr;
194 return offset / ticks_per_usec;
197 static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
199 write_seqlock(&xtime_lock);
202 ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
204 while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
206 next_jiffy_time -= ticks_per_jiffy;
209 write_sequnlock(&xtime_lock);
214 static struct irqaction ixp2000_timer_irq = {
215 .name = "IXP2000 Timer Tick",
216 .flags = SA_INTERRUPT | SA_TIMER,
217 .handler = ixp2000_timer_interrupt,
220 void __init ixp2000_init_time(unsigned long tick_rate)
222 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
223 ticks_per_usec = tick_rate / 1000000;
226 * We use timer 1 as our timer interrupt.
228 ixp2000_reg_write(IXP2000_T1_CLR, 0);
229 ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
230 ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
233 * We use a second timer as a monotonic counter for tracking
234 * missed jiffies. The IXP2000 has four timers, but if we're
235 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
236 * chips we use timer 4. Timer 4 is the only timer that can
237 * be used for the watchdog, so we use timer 2 if we're on a
240 if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
241 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
243 ixp2000_reg_write(IXP2000_T4_CLR, 0);
244 ixp2000_reg_write(IXP2000_T4_CLD, -1);
245 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
246 missing_jiffy_timer_csr = IXP2000_T4_CSR;
248 ixp2000_reg_write(IXP2000_T2_CLR, 0);
249 ixp2000_reg_write(IXP2000_T2_CLD, -1);
250 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
251 missing_jiffy_timer_csr = IXP2000_T2_CSR;
253 next_jiffy_time = 0xffffffff;
255 /* register for interrupt */
256 setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
259 /*************************************************************************
261 *************************************************************************/
262 static unsigned long GPIO_IRQ_falling_edge;
263 static unsigned long GPIO_IRQ_rising_edge;
264 static unsigned long GPIO_IRQ_level_low;
265 static unsigned long GPIO_IRQ_level_high;
267 static void update_gpio_int_csrs(void)
269 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
270 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
271 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
272 ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
275 void gpio_line_config(int line, int direction)
279 local_irq_save(flags);
280 if (direction == GPIO_OUT) {
281 irq_desc[line + IRQ_IXP2000_GPIO0].valid = 0;
283 /* if it's an output, it ain't an interrupt anymore */
284 GPIO_IRQ_falling_edge &= ~(1 << line);
285 GPIO_IRQ_rising_edge &= ~(1 << line);
286 GPIO_IRQ_level_low &= ~(1 << line);
287 GPIO_IRQ_level_high &= ~(1 << line);
288 update_gpio_int_csrs();
290 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
291 } else if (direction == GPIO_IN) {
292 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
294 local_irq_restore(flags);
298 /*************************************************************************
299 * IRQ handling IXP2000
300 *************************************************************************/
301 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
304 unsigned long status = *IXP2000_GPIO_INST;
306 for (i = 0; i <= 7; i++) {
307 if (status & (1<<i)) {
308 desc = irq_desc + i + IRQ_IXP2000_GPIO0;
309 desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc, regs);
314 static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
316 int line = irq - IRQ_IXP2000_GPIO0;
319 * First, configure this GPIO line as an input.
321 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
324 * Then, set the proper trigger type.
326 if (type & IRQT_FALLING)
327 GPIO_IRQ_falling_edge |= 1 << line;
329 GPIO_IRQ_falling_edge &= ~(1 << line);
330 if (type & IRQT_RISING)
331 GPIO_IRQ_rising_edge |= 1 << line;
333 GPIO_IRQ_rising_edge &= ~(1 << line);
335 GPIO_IRQ_level_low |= 1 << line;
337 GPIO_IRQ_level_low &= ~(1 << line);
338 if (type & IRQT_HIGH)
339 GPIO_IRQ_level_high |= 1 << line;
341 GPIO_IRQ_level_high &= ~(1 << line);
342 update_gpio_int_csrs();
345 * Finally, mark the corresponding IRQ as valid.
347 irq_desc[irq].valid = 1;
352 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
354 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
356 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
357 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
358 ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
361 static void ixp2000_GPIO_irq_mask(unsigned int irq)
363 ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
366 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
368 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
371 static struct irqchip ixp2000_GPIO_irq_chip = {
372 .ack = ixp2000_GPIO_irq_mask_ack,
373 .mask = ixp2000_GPIO_irq_mask,
374 .unmask = ixp2000_GPIO_irq_unmask,
375 .set_type = ixp2000_GPIO_irq_type,
378 static void ixp2000_pci_irq_mask(unsigned int irq)
380 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
381 if (irq == IRQ_IXP2000_PCIA)
382 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
383 else if (irq == IRQ_IXP2000_PCIB)
384 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
387 static void ixp2000_pci_irq_unmask(unsigned int irq)
389 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
390 if (irq == IRQ_IXP2000_PCIA)
391 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
392 else if (irq == IRQ_IXP2000_PCIB)
393 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
397 * Error interrupts. These are used extensively by the microengine drivers
399 static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
402 unsigned long status = *IXP2000_IRQ_ERR_STATUS;
404 for(i = 31; i >= 0; i--) {
405 if(status & (1 << i)) {
406 desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
407 desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
412 static void ixp2000_err_irq_mask(unsigned int irq)
414 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
415 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
418 static void ixp2000_err_irq_unmask(unsigned int irq)
420 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
421 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
424 static struct irqchip ixp2000_err_irq_chip = {
425 .ack = ixp2000_err_irq_mask,
426 .mask = ixp2000_err_irq_mask,
427 .unmask = ixp2000_err_irq_unmask
430 static struct irqchip ixp2000_pci_irq_chip = {
431 .ack = ixp2000_pci_irq_mask,
432 .mask = ixp2000_pci_irq_mask,
433 .unmask = ixp2000_pci_irq_unmask
436 static void ixp2000_irq_mask(unsigned int irq)
438 ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
441 static void ixp2000_irq_unmask(unsigned int irq)
443 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
446 static struct irqchip ixp2000_irq_chip = {
447 .ack = ixp2000_irq_mask,
448 .mask = ixp2000_irq_mask,
449 .unmask = ixp2000_irq_unmask
452 void __init ixp2000_init_irq(void)
459 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
460 ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
462 /* clear all GPIO edge/level detects */
463 ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
464 ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
465 ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
466 ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
467 ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
469 /* clear PCI interrupt sources */
470 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
473 * Certain bits in the IRQ status register of the
474 * IXP2000 are reserved. Instead of trying to map
475 * things non 1:1 from bit position to IRQ number,
476 * we mark the reserved IRQs as invalid. This makes
477 * our mask/unmask code much simpler.
479 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
480 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
481 set_irq_chip(irq, &ixp2000_irq_chip);
482 set_irq_handler(irq, do_level_IRQ);
483 set_irq_flags(irq, IRQF_VALID);
484 } else set_irq_flags(irq, 0);
487 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
488 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
489 IXP2000_VALID_ERR_IRQ_MASK) {
490 set_irq_chip(irq, &ixp2000_err_irq_chip);
491 set_irq_handler(irq, do_level_IRQ);
492 set_irq_flags(irq, IRQF_VALID);
495 set_irq_flags(irq, 0);
497 set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
500 * GPIO IRQs are invalid until someone sets the interrupt mode
501 * by calling set_irq_type().
503 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
504 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
505 set_irq_handler(irq, do_level_IRQ);
506 set_irq_flags(irq, 0);
508 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
511 * Enable PCI irqs. The actual PCI[AB] decoding is done in
512 * entry-macro.S, so we don't need a chained handler for the
513 * PCI interrupt source.
515 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
516 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
517 set_irq_chip(irq, &ixp2000_pci_irq_chip);
518 set_irq_handler(irq, do_level_IRQ);
519 set_irq_flags(irq, IRQF_VALID);