git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/threads.h>
  12 #include <linux/cpumask.h>
  13 #include <linux/string.h>
  14 #include <linux/kernel.h>
  15 #include <linux/ctype.h>
  16 #include <linux/init.h>
  17 #include <linux/sched.h>
  18 #include <linux/bootmem.h>
  19 #include <linux/module.h>
  20 #include <asm/smp.h>
  21 #include <asm/ipi.h>
  22 #include <asm/genapic.h>
  23 #include <asm/uv/uv_mmrs.h>
  24 #include <asm/uv/uv_hub.h>
  25
  26 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  27 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  28
  29 struct uv_blade_info *uv_blade_info;
  30 EXPORT_SYMBOL_GPL(uv_blade_info);
  31
  32 short *uv_node_to_blade;
  33 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  34
  35 short *uv_cpu_to_blade;
  36 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  37
  38 short uv_possible_blades;
  39 EXPORT_SYMBOL_GPL(uv_possible_blades);
  40
  41 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  42
  43 static cpumask_t uv_target_cpus(void)
  44 {
  45         return cpumask_of_cpu(0);
  46 }
  47
  48 static cpumask_t uv_vector_allocation_domain(int cpu)
  49 {
  50         cpumask_t domain = CPU_MASK_NONE;
  51         cpu_set(cpu, domain);
  52         return domain;
  53 }
  54
  55 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  56 {
  57         unsigned long val;
  58         int pnode;
  59
  60         pnode = uv_apicid_to_pnode(phys_apicid);
  61         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  62             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  63             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
  64             APIC_DM_INIT;
  65         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  66         mdelay(10);
  67
  68         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  69             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  70             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
  71             APIC_DM_STARTUP;
  72         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  73         return 0;
  74 }
  75
  76 static void uv_send_IPI_one(int cpu, int vector)
  77 {
  78         unsigned long val, apicid, lapicid;
  79         int pnode;
  80
  81         apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
  82         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
  83         pnode = uv_apicid_to_pnode(apicid);
  84         val =
  85             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
  86                                               UVH_IPI_INT_APIC_ID_SHFT) |
  87             (vector << UVH_IPI_INT_VECTOR_SHFT);
  88         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  89 }
  90
  91 static void uv_send_IPI_mask(cpumask_t mask, int vector)
  92 {
  93         unsigned int cpu;
  94
  95         for (cpu = 0; cpu < NR_CPUS; ++cpu)
  96                 if (cpu_isset(cpu, mask))
  97                         uv_send_IPI_one(cpu, vector);
  98 }
  99
 100 static void uv_send_IPI_allbutself(int vector)
 101 {
 102         cpumask_t mask = cpu_online_map;
 103
 104         cpu_clear(smp_processor_id(), mask);
 105
 106         if (!cpus_empty(mask))
 107                 uv_send_IPI_mask(mask, vector);
 108 }
 109
 110 static void uv_send_IPI_all(int vector)
 111 {
 112         uv_send_IPI_mask(cpu_online_map, vector);
 113 }
 114
 115 static int uv_apic_id_registered(void)
 116 {
 117         return 1;
 118 }
 119
 120 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
 121 {
 122         int cpu;
 123
 124         /*
 125          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 126          * May as well be the first.
 127          */
 128         cpu = first_cpu(cpumask);
 129         if ((unsigned)cpu < NR_CPUS)
 130                 return per_cpu(x86_cpu_to_apicid, cpu);
 131         else
 132                 return BAD_APICID;
 133 }
 134
 135 static unsigned int phys_pkg_id(int index_msb)
 136 {
 137         return GET_APIC_ID(read_apic_id()) >> index_msb;
 138 }
 139
 140 #ifdef ZZZ              /* Needs x2apic patch */
 141 static void uv_send_IPI_self(int vector)
 142 {
 143         apic_write(APIC_SELF_IPI, vector);
 144 }
 145 #endif
 146
 147 struct genapic apic_x2apic_uv_x = {
 148         .name = "UV large system",
 149         .int_delivery_mode = dest_Fixed,
 150         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 151         .target_cpus = uv_target_cpus,
 152         .vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
 153         .apic_id_registered = uv_apic_id_registered,
 154         .send_IPI_all = uv_send_IPI_all,
 155         .send_IPI_allbutself = uv_send_IPI_allbutself,
 156         .send_IPI_mask = uv_send_IPI_mask,
 157         /* ZZZ.send_IPI_self = uv_send_IPI_self, */
 158         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 159         .phys_pkg_id = phys_pkg_id,     /* Fixme ZZZ */
 160 };
 161
 162 static __cpuinit void set_x2apic_extra_bits(int pnode)
 163 {
 164         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 165 }
 166
 167 /*
 168  * Called on boot cpu.
 169  */
 170 static __init int boot_pnode_to_blade(int pnode)
 171 {
 172         int blade;
 173
 174         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 175                 if (pnode == uv_blade_info[blade].pnode)
 176                         return blade;
 177         BUG();
 178 }
 179
 180 struct redir_addr {
 181         unsigned long redirect;
 182         unsigned long alias;
 183 };
 184
 185 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 186
 187 static __initdata struct redir_addr redir_addrs[] = {
 188         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 189         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 190         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 191 };
 192
 193 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 194 {
 195         union uvh_si_alias0_overlay_config_u alias;
 196         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 197         int i;
 198
 199         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 200                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 201                 if (alias.s.base == 0) {
 202                         *size = (1UL << alias.s.m_alias);
 203                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 204                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 205                         return;
 206                 }
 207         }
 208         BUG();
 209 }
 210
 211 static __init void uv_system_init(void)
 212 {
 213         union uvh_si_addr_map_config_u m_n_config;
 214         union uvh_node_id_u node_id;
 215         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 216         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 217         unsigned long mmr_base, present;
 218
 219         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 220         m_val = m_n_config.s.m_skt;
 221         n_val = m_n_config.s.n_skt;
 222         mmr_base =
 223             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 224             ~UV_MMR_ENABLE;
 225         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 226
 227         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 228                 uv_possible_blades +=
 229                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 230         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 231
 232         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 233         uv_blade_info = alloc_bootmem_pages(bytes);
 234
 235         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 236
 237         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 238         uv_node_to_blade = alloc_bootmem_pages(bytes);
 239         memset(uv_node_to_blade, 255, bytes);
 240
 241         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 242         uv_cpu_to_blade = alloc_bootmem_pages(bytes);
 243         memset(uv_cpu_to_blade, 255, bytes);
 244
 245         blade = 0;
 246         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 247                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 248                 for (j = 0; j < 64; j++) {
 249                         if (!test_bit(j, &present))
 250                                 continue;
 251                         uv_blade_info[blade].pnode = (i * 64 + j);
 252                         uv_blade_info[blade].nr_possible_cpus = 0;
 253                         uv_blade_info[blade].nr_online_cpus = 0;
 254                         blade++;
 255                 }
 256         }
 257
 258         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 259         gnode_upper = (((unsigned long)node_id.s.node_id) &
 260                        ~((1 << n_val) - 1)) << m_val;
 261
 262         for_each_present_cpu(cpu) {
 263                 nid = cpu_to_node(cpu);
 264                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 265                 blade = boot_pnode_to_blade(pnode);
 266                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 267                 uv_blade_info[blade].nr_possible_cpus++;
 268
 269                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 270                 uv_cpu_hub_info(cpu)->lowmem_remap_top =
 271                                         lowmem_redir_base + lowmem_redir_size;
 272                 uv_cpu_hub_info(cpu)->m_val = m_val;
 273                 uv_cpu_hub_info(cpu)->n_val = m_val;
 274                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 275                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 276                 uv_cpu_hub_info(cpu)->pnode = pnode;
 277                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 278                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 279                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 280                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 281                 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
 282                 uv_node_to_blade[nid] = blade;
 283                 uv_cpu_to_blade[cpu] = blade;
 284
 285                 printk(KERN_DEBUG "UV cpu %d, apicid 0x%x, pnode %d, nid %d, "
 286                         "lcpu %d, blade %d\n",
 287                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 288                         lcpu, blade);
 289         }
 290 }
 291
 292 /*
 293  * Called on each cpu to initialize the per_cpu UV data area.
 294  *      ZZZ hotplug not supported yet
 295  */
 296 void __cpuinit uv_cpu_init(void)
 297 {
 298         if (!uv_node_to_blade)
 299                 uv_system_init();
 300
 301         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 302
 303         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 304                 set_x2apic_extra_bits(uv_hub_info->pnode);
 305 }