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   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <scsi/fc/fc_fcoe.h>
  43
  44 #include "ixgbe.h"
  45 #include "ixgbe_common.h"
  46
  47 char ixgbe_driver_name[] = "ixgbe";
  48 static const char ixgbe_driver_string[] =
  49                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  50
  51 #define DRV_VERSION "2.0.24-k2"
  52 const char ixgbe_driver_version[] = DRV_VERSION;
  53 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  54
  55 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  56         [board_82598] = &ixgbe_82598_info,
  57         [board_82599] = &ixgbe_82599_info,
  58 };
  59
  60 /* ixgbe_pci_tbl - PCI Device ID Table
  61  *
  62  * Wildcard entries (PCI_ANY_ID) should come last
  63  * Last entry must be all 0s
  64  *
  65  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  66  *   Class, Class Mask, private data (not used) }
  67  */
  68 static struct pci_device_id ixgbe_pci_tbl[] = {
  69         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  70          board_82598 },
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  92          board_82599 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  94          board_82599 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  96          board_82599 },
  97
  98         /* required last entry */
  99         {0, }
 100 };
 101 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 102
 103 #ifdef CONFIG_IXGBE_DCA
 104 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 105                             void *p);
 106 static struct notifier_block dca_notifier = {
 107         .notifier_call = ixgbe_notify_dca,
 108         .next          = NULL,
 109         .priority      = 0
 110 };
 111 #endif
 112
 113 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 114 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 115 MODULE_LICENSE("GPL");
 116 MODULE_VERSION(DRV_VERSION);
 117
 118 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 119
 120 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 121 {
 122         u32 ctrl_ext;
 123
 124         /* Let firmware take over control of h/w */
 125         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 126         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 127                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 128 }
 129
 130 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 131 {
 132         u32 ctrl_ext;
 133
 134         /* Let firmware know the driver has taken over */
 135         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 136         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 137                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 138 }
 139
 140 /*
 141  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 142  * @adapter: pointer to adapter struct
 143  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 144  * @queue: queue to map the corresponding interrupt to
 145  * @msix_vector: the vector to map to the corresponding queue
 146  *
 147  */
 148 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 149                            u8 queue, u8 msix_vector)
 150 {
 151         u32 ivar, index;
 152         struct ixgbe_hw *hw = &adapter->hw;
 153         switch (hw->mac.type) {
 154         case ixgbe_mac_82598EB:
 155                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 156                 if (direction == -1)
 157                         direction = 0;
 158                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 159                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 160                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 161                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 162                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 163                 break;
 164         case ixgbe_mac_82599EB:
 165                 if (direction == -1) {
 166                         /* other causes */
 167                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 168                         index = ((queue & 1) * 8);
 169                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 170                         ivar &= ~(0xFF << index);
 171                         ivar |= (msix_vector << index);
 172                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 173                         break;
 174                 } else {
 175                         /* tx or rx causes */
 176                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 177                         index = ((16 * (queue & 1)) + (8 * direction));
 178                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 179                         ivar &= ~(0xFF << index);
 180                         ivar |= (msix_vector << index);
 181                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 182                         break;
 183                 }
 184         default:
 185                 break;
 186         }
 187 }
 188
 189 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 190                                              struct ixgbe_tx_buffer
 191                                              *tx_buffer_info)
 192 {
 193         tx_buffer_info->dma = 0;
 194         if (tx_buffer_info->skb) {
 195                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 196                               DMA_TO_DEVICE);
 197                 dev_kfree_skb_any(tx_buffer_info->skb);
 198                 tx_buffer_info->skb = NULL;
 199         }
 200         tx_buffer_info->time_stamp = 0;
 201         /* tx_buffer_info must be completely set up in the transmit path */
 202 }
 203
 204 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 205                                        struct ixgbe_ring *tx_ring,
 206                                        unsigned int eop)
 207 {
 208         struct ixgbe_hw *hw = &adapter->hw;
 209
 210         /* Detect a transmit hang in hardware, this serializes the
 211          * check with the clearing of time_stamp and movement of eop */
 212         adapter->detect_tx_hung = false;
 213         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 214             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 215             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 216                 /* detected Tx unit hang */
 217                 union ixgbe_adv_tx_desc *tx_desc;
 218                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 219                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 220                         "  Tx Queue             <%d>\n"
 221                         "  TDH, TDT             <%x>, <%x>\n"
 222                         "  next_to_use          <%x>\n"
 223                         "  next_to_clean        <%x>\n"
 224                         "tx_buffer_info[next_to_clean]\n"
 225                         "  time_stamp           <%lx>\n"
 226                         "  jiffies              <%lx>\n",
 227                         tx_ring->queue_index,
 228                         IXGBE_READ_REG(hw, tx_ring->head),
 229                         IXGBE_READ_REG(hw, tx_ring->tail),
 230                         tx_ring->next_to_use, eop,
 231                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 232                 return true;
 233         }
 234
 235         return false;
 236 }
 237
 238 #define IXGBE_MAX_TXD_PWR       14
 239 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 240
 241 /* Tx Descriptors needed, worst case */
 242 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 243                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 244 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 245         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 246
 247 static void ixgbe_tx_timeout(struct net_device *netdev);
 248
 249 /**
 250  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 251  * @adapter: board private structure
 252  * @tx_ring: tx ring to clean
 253  *
 254  * returns true if transmit work is done
 255  **/
 256 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
 257                                struct ixgbe_ring *tx_ring)
 258 {
 259         struct net_device *netdev = adapter->netdev;
 260         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 261         struct ixgbe_tx_buffer *tx_buffer_info;
 262         unsigned int i, eop, count = 0;
 263         unsigned int total_bytes = 0, total_packets = 0;
 264
 265         i = tx_ring->next_to_clean;
 266         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 267         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 268
 269         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 270                (count < tx_ring->work_limit)) {
 271                 bool cleaned = false;
 272                 for ( ; !cleaned; count++) {
 273                         struct sk_buff *skb;
 274                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 275                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 276                         cleaned = (i == eop);
 277                         skb = tx_buffer_info->skb;
 278
 279                         if (cleaned && skb) {
 280                                 unsigned int segs, bytecount;
 281
 282                                 /* gso_segs is currently only valid for tcp */
 283                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 284                                 /* multiply data chunks by size of headers */
 285                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
 286                                             skb->len;
 287                                 total_packets += segs;
 288                                 total_bytes += bytecount;
 289                         }
 290
 291                         ixgbe_unmap_and_free_tx_resource(adapter,
 292                                                          tx_buffer_info);
 293
 294                         tx_desc->wb.status = 0;
 295
 296                         i++;
 297                         if (i == tx_ring->count)
 298                                 i = 0;
 299                 }
 300
 301                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 302                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 303         }
 304
 305         tx_ring->next_to_clean = i;
 306
 307 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 308         if (unlikely(count && netif_carrier_ok(netdev) &&
 309                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 310                 /* Make sure that anybody stopping the queue after this
 311                  * sees the new next_to_clean.
 312                  */
 313                 smp_mb();
 314                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 315                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 316                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 317                         ++adapter->restart_queue;
 318                 }
 319         }
 320
 321         if (adapter->detect_tx_hung) {
 322                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 323                         /* schedule immediate reset if we believe we hung */
 324                         DPRINTK(PROBE, INFO,
 325                                 "tx hang %d detected, resetting adapter\n",
 326                                 adapter->tx_timeout_count + 1);
 327                         ixgbe_tx_timeout(adapter->netdev);
 328                 }
 329         }
 330
 331         /* re-arm the interrupt */
 332         if (count >= tx_ring->work_limit) {
 333                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 334                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
 335                                         tx_ring->v_idx);
 336                 else if (tx_ring->v_idx & 0xFFFFFFFF)
 337                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
 338                                         tx_ring->v_idx);
 339                 else
 340                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
 341                                         (tx_ring->v_idx >> 32));
 342         }
 343
 344
 345         tx_ring->total_bytes += total_bytes;
 346         tx_ring->total_packets += total_packets;
 347         tx_ring->stats.packets += total_packets;
 348         tx_ring->stats.bytes += total_bytes;
 349         adapter->net_stats.tx_bytes += total_bytes;
 350         adapter->net_stats.tx_packets += total_packets;
 351         return (count < tx_ring->work_limit);
 352 }
 353
 354 #ifdef CONFIG_IXGBE_DCA
 355 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 356                                 struct ixgbe_ring *rx_ring)
 357 {
 358         u32 rxctrl;
 359         int cpu = get_cpu();
 360         int q = rx_ring - adapter->rx_ring;
 361
 362         if (rx_ring->cpu != cpu) {
 363                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 364                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 365                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 366                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 367                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 368                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 369                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 370                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 371                 }
 372                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 373                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 374                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 375                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 376                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 377                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 378                 rx_ring->cpu = cpu;
 379         }
 380         put_cpu();
 381 }
 382
 383 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 384                                 struct ixgbe_ring *tx_ring)
 385 {
 386         u32 txctrl;
 387         int cpu = get_cpu();
 388         int q = tx_ring - adapter->tx_ring;
 389
 390         if (tx_ring->cpu != cpu) {
 391                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 392                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 393                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 394                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 395                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 396                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 397                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 398                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 399                 }
 400                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 401                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 402                 tx_ring->cpu = cpu;
 403         }
 404         put_cpu();
 405 }
 406
 407 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 408 {
 409         int i;
 410
 411         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 412                 return;
 413
 414         /* always use CB2 mode, difference is masked in the CB driver */
 415         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 416
 417         for (i = 0; i < adapter->num_tx_queues; i++) {
 418                 adapter->tx_ring[i].cpu = -1;
 419                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 420         }
 421         for (i = 0; i < adapter->num_rx_queues; i++) {
 422                 adapter->rx_ring[i].cpu = -1;
 423                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 424         }
 425 }
 426
 427 static int __ixgbe_notify_dca(struct device *dev, void *data)
 428 {
 429         struct net_device *netdev = dev_get_drvdata(dev);
 430         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 431         unsigned long event = *(unsigned long *)data;
 432
 433         switch (event) {
 434         case DCA_PROVIDER_ADD:
 435                 /* if we're already enabled, don't do it again */
 436                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 437                         break;
 438                 if (dca_add_requester(dev) == 0) {
 439                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 440                         ixgbe_setup_dca(adapter);
 441                         break;
 442                 }
 443                 /* Fall Through since DCA is disabled. */
 444         case DCA_PROVIDER_REMOVE:
 445                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 446                         dca_remove_requester(dev);
 447                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 448                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 449                 }
 450                 break;
 451         }
 452
 453         return 0;
 454 }
 455
 456 #endif /* CONFIG_IXGBE_DCA */
 457 /**
 458  * ixgbe_receive_skb - Send a completed packet up the stack
 459  * @adapter: board private structure
 460  * @skb: packet to send up
 461  * @status: hardware indication of status of receive
 462  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 463  * @rx_desc: rx descriptor
 464  **/
 465 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 466                               struct sk_buff *skb, u8 status,
 467                               struct ixgbe_ring *ring,
 468                               union ixgbe_adv_rx_desc *rx_desc)
 469 {
 470         struct ixgbe_adapter *adapter = q_vector->adapter;
 471         struct napi_struct *napi = &q_vector->napi;
 472         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 473         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 474
 475         skb_record_rx_queue(skb, ring->queue_index);
 476         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 477                 if (adapter->vlgrp && is_vlan && (tag != 0))
 478                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 479                 else
 480                         napi_gro_receive(napi, skb);
 481         } else {
 482                 if (adapter->vlgrp && is_vlan && (tag != 0))
 483                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 484                 else
 485                         netif_rx(skb);
 486         }
 487 }
 488
 489 /**
 490  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 491  * @adapter: address of board private structure
 492  * @status_err: hardware indication of status of receive
 493  * @skb: skb currently being received and modified
 494  **/
 495 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 496                                      u32 status_err, struct sk_buff *skb)
 497 {
 498         skb->ip_summed = CHECKSUM_NONE;
 499
 500         /* Rx csum disabled */
 501         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 502                 return;
 503
 504         /* if IP and error */
 505         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 506             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 507                 adapter->hw_csum_rx_error++;
 508                 return;
 509         }
 510
 511         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 512                 return;
 513
 514         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 515                 adapter->hw_csum_rx_error++;
 516                 return;
 517         }
 518
 519         /* It must be a TCP or UDP packet with a valid checksum */
 520         skb->ip_summed = CHECKSUM_UNNECESSARY;
 521         adapter->hw_csum_rx_good++;
 522 }
 523
 524 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 525                                          struct ixgbe_ring *rx_ring, u32 val)
 526 {
 527         /*
 528          * Force memory writes to complete before letting h/w
 529          * know there are new descriptors to fetch.  (Only
 530          * applicable for weak-ordered memory model archs,
 531          * such as IA-64).
 532          */
 533         wmb();
 534         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 535 }
 536
 537 /**
 538  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 539  * @adapter: address of board private structure
 540  **/
 541 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 542                                    struct ixgbe_ring *rx_ring,
 543                                    int cleaned_count)
 544 {
 545         struct pci_dev *pdev = adapter->pdev;
 546         union ixgbe_adv_rx_desc *rx_desc;
 547         struct ixgbe_rx_buffer *bi;
 548         unsigned int i;
 549         unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
 550
 551         i = rx_ring->next_to_use;
 552         bi = &rx_ring->rx_buffer_info[i];
 553
 554         while (cleaned_count--) {
 555                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 556
 557                 if (!bi->page_dma &&
 558                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 559                         if (!bi->page) {
 560                                 bi->page = alloc_page(GFP_ATOMIC);
 561                                 if (!bi->page) {
 562                                         adapter->alloc_rx_page_failed++;
 563                                         goto no_buffers;
 564                                 }
 565                                 bi->page_offset = 0;
 566                         } else {
 567                                 /* use a half page if we're re-using */
 568                                 bi->page_offset ^= (PAGE_SIZE / 2);
 569                         }
 570
 571                         bi->page_dma = pci_map_page(pdev, bi->page,
 572                                                     bi->page_offset,
 573                                                     (PAGE_SIZE / 2),
 574                                                     PCI_DMA_FROMDEVICE);
 575                 }
 576
 577                 if (!bi->skb) {
 578                         struct sk_buff *skb;
 579                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
 580
 581                         if (!skb) {
 582                                 adapter->alloc_rx_buff_failed++;
 583                                 goto no_buffers;
 584                         }
 585
 586                         /*
 587                          * Make buffer alignment 2 beyond a 16 byte boundary
 588                          * this will result in a 16 byte aligned IP header after
 589                          * the 14 byte MAC header is removed
 590                          */
 591                         skb_reserve(skb, NET_IP_ALIGN);
 592
 593                         bi->skb = skb;
 594                         bi->dma = pci_map_single(pdev, skb->data, bufsz,
 595                                                  PCI_DMA_FROMDEVICE);
 596                 }
 597                 /* Refresh the desc even if buffer_addrs didn't change because
 598                  * each write-back erases this info. */
 599                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 600                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 601                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 602                 } else {
 603                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 604                 }
 605
 606                 i++;
 607                 if (i == rx_ring->count)
 608                         i = 0;
 609                 bi = &rx_ring->rx_buffer_info[i];
 610         }
 611
 612 no_buffers:
 613         if (rx_ring->next_to_use != i) {
 614                 rx_ring->next_to_use = i;
 615                 if (i-- == 0)
 616                         i = (rx_ring->count - 1);
 617
 618                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 619         }
 620 }
 621
 622 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 623 {
 624         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 625 }
 626
 627 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 628 {
 629         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 630 }
 631
 632 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 633 {
 634         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 635                 IXGBE_RXDADV_RSCCNT_MASK) >>
 636                 IXGBE_RXDADV_RSCCNT_SHIFT;
 637 }
 638
 639 /**
 640  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 641  * @skb: pointer to the last skb in the rsc queue
 642  *
 643  * This function changes a queue full of hw rsc buffers into a completed
 644  * packet.  It uses the ->prev pointers to find the first packet and then
 645  * turns it into the frag list owner.
 646  **/
 647 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 648 {
 649         unsigned int frag_list_size = 0;
 650
 651         while (skb->prev) {
 652                 struct sk_buff *prev = skb->prev;
 653                 frag_list_size += skb->len;
 654                 skb->prev = NULL;
 655                 skb = prev;
 656         }
 657
 658         skb_shinfo(skb)->frag_list = skb->next;
 659         skb->next = NULL;
 660         skb->len += frag_list_size;
 661         skb->data_len += frag_list_size;
 662         skb->truesize += frag_list_size;
 663         return skb;
 664 }
 665
 666 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 667                                struct ixgbe_ring *rx_ring,
 668                                int *work_done, int work_to_do)
 669 {
 670         struct ixgbe_adapter *adapter = q_vector->adapter;
 671         struct pci_dev *pdev = adapter->pdev;
 672         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 673         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 674         struct sk_buff *skb;
 675         unsigned int i, rsc_count = 0;
 676         u32 len, staterr;
 677         u16 hdr_info;
 678         bool cleaned = false;
 679         int cleaned_count = 0;
 680         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 681
 682         i = rx_ring->next_to_clean;
 683         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 684         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 685         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 686
 687         while (staterr & IXGBE_RXD_STAT_DD) {
 688                 u32 upper_len = 0;
 689                 if (*work_done >= work_to_do)
 690                         break;
 691                 (*work_done)++;
 692
 693                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 694                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 695                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 696                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 697                         if (hdr_info & IXGBE_RXDADV_SPH)
 698                                 adapter->rx_hdr_split++;
 699                         if (len > IXGBE_RX_HDR_SIZE)
 700                                 len = IXGBE_RX_HDR_SIZE;
 701                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 702                 } else {
 703                         len = le16_to_cpu(rx_desc->wb.upper.length);
 704                 }
 705
 706                 cleaned = true;
 707                 skb = rx_buffer_info->skb;
 708                 prefetch(skb->data - NET_IP_ALIGN);
 709                 rx_buffer_info->skb = NULL;
 710
 711                 if (len && !skb_shinfo(skb)->nr_frags) {
 712                         pci_unmap_single(pdev, rx_buffer_info->dma,
 713                                          rx_ring->rx_buf_len,
 714                                          PCI_DMA_FROMDEVICE);
 715                         skb_put(skb, len);
 716                 }
 717
 718                 if (upper_len) {
 719                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 720                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 721                         rx_buffer_info->page_dma = 0;
 722                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 723                                            rx_buffer_info->page,
 724                                            rx_buffer_info->page_offset,
 725                                            upper_len);
 726
 727                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 728                             (page_count(rx_buffer_info->page) != 1))
 729                                 rx_buffer_info->page = NULL;
 730                         else
 731                                 get_page(rx_buffer_info->page);
 732
 733                         skb->len += upper_len;
 734                         skb->data_len += upper_len;
 735                         skb->truesize += upper_len;
 736                 }
 737
 738                 i++;
 739                 if (i == rx_ring->count)
 740                         i = 0;
 741
 742                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 743                 prefetch(next_rxd);
 744                 cleaned_count++;
 745
 746                 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
 747                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 748
 749                 if (rsc_count) {
 750                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 751                                      IXGBE_RXDADV_NEXTP_SHIFT;
 752                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 753                         rx_ring->rsc_count += (rsc_count - 1);
 754                 } else {
 755                         next_buffer = &rx_ring->rx_buffer_info[i];
 756                 }
 757
 758                 if (staterr & IXGBE_RXD_STAT_EOP) {
 759                         if (skb->prev)
 760                                 skb = ixgbe_transform_rsc_queue(skb);
 761                         rx_ring->stats.packets++;
 762                         rx_ring->stats.bytes += skb->len;
 763                 } else {
 764                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 765                                 rx_buffer_info->skb = next_buffer->skb;
 766                                 rx_buffer_info->dma = next_buffer->dma;
 767                                 next_buffer->skb = skb;
 768                                 next_buffer->dma = 0;
 769                         } else {
 770                                 skb->next = next_buffer->skb;
 771                                 skb->next->prev = skb;
 772                         }
 773                         adapter->non_eop_descs++;
 774                         goto next_desc;
 775                 }
 776
 777                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 778                         dev_kfree_skb_irq(skb);
 779                         goto next_desc;
 780                 }
 781
 782                 ixgbe_rx_checksum(adapter, staterr, skb);
 783
 784                 /* probably a little skewed due to removing CRC */
 785                 total_rx_bytes += skb->len;
 786                 total_rx_packets++;
 787
 788                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 789 #ifdef IXGBE_FCOE
 790                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 791                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 792                         if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb))
 793                                 goto next_desc;
 794 #endif /* IXGBE_FCOE */
 795                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 796
 797 next_desc:
 798                 rx_desc->wb.upper.status_error = 0;
 799
 800                 /* return some buffers to hardware, one at a time is too slow */
 801                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 802                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 803                         cleaned_count = 0;
 804                 }
 805
 806                 /* use prefetched values */
 807                 rx_desc = next_rxd;
 808                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 809
 810                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 811         }
 812
 813         rx_ring->next_to_clean = i;
 814         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 815
 816         if (cleaned_count)
 817                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 818
 819         rx_ring->total_packets += total_rx_packets;
 820         rx_ring->total_bytes += total_rx_bytes;
 821         adapter->net_stats.rx_bytes += total_rx_bytes;
 822         adapter->net_stats.rx_packets += total_rx_packets;
 823
 824         return cleaned;
 825 }
 826
 827 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 828 /**
 829  * ixgbe_configure_msix - Configure MSI-X hardware
 830  * @adapter: board private structure
 831  *
 832  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 833  * interrupts.
 834  **/
 835 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 836 {
 837         struct ixgbe_q_vector *q_vector;
 838         int i, j, q_vectors, v_idx, r_idx;
 839         u32 mask;
 840
 841         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 842
 843         /*
 844          * Populate the IVAR table and set the ITR values to the
 845          * corresponding register.
 846          */
 847         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 848                 q_vector = adapter->q_vector[v_idx];
 849                 /* XXX for_each_bit(...) */
 850                 r_idx = find_first_bit(q_vector->rxr_idx,
 851                                        adapter->num_rx_queues);
 852
 853                 for (i = 0; i < q_vector->rxr_count; i++) {
 854                         j = adapter->rx_ring[r_idx].reg_idx;
 855                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 856                         r_idx = find_next_bit(q_vector->rxr_idx,
 857                                               adapter->num_rx_queues,
 858                                               r_idx + 1);
 859                 }
 860                 r_idx = find_first_bit(q_vector->txr_idx,
 861                                        adapter->num_tx_queues);
 862
 863                 for (i = 0; i < q_vector->txr_count; i++) {
 864                         j = adapter->tx_ring[r_idx].reg_idx;
 865                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 866                         r_idx = find_next_bit(q_vector->txr_idx,
 867                                               adapter->num_tx_queues,
 868                                               r_idx + 1);
 869                 }
 870
 871                 /* if this is a tx only vector halve the interrupt rate */
 872                 if (q_vector->txr_count && !q_vector->rxr_count)
 873                         q_vector->eitr = (adapter->eitr_param >> 1);
 874                 else if (q_vector->rxr_count)
 875                         /* rx only */
 876                         q_vector->eitr = adapter->eitr_param;
 877
 878                 /*
 879                  * since this is initial set up don't need to call
 880                  * ixgbe_write_eitr helper
 881                  */
 882                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
 883                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
 884         }
 885
 886         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 887                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 888                                v_idx);
 889         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 890                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 891         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 892
 893         /* set up to autoclear timer, and the vectors */
 894         mask = IXGBE_EIMS_ENABLE_MASK;
 895         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 896         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 897 }
 898
 899 enum latency_range {
 900         lowest_latency = 0,
 901         low_latency = 1,
 902         bulk_latency = 2,
 903         latency_invalid = 255
 904 };
 905
 906 /**
 907  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 908  * @adapter: pointer to adapter
 909  * @eitr: eitr setting (ints per sec) to give last timeslice
 910  * @itr_setting: current throttle rate in ints/second
 911  * @packets: the number of packets during this measurement interval
 912  * @bytes: the number of bytes during this measurement interval
 913  *
 914  *      Stores a new ITR value based on packets and byte
 915  *      counts during the last interrupt.  The advantage of per interrupt
 916  *      computation is faster updates and more accurate ITR for the current
 917  *      traffic pattern.  Constants in this function were computed
 918  *      based on theoretical maximum wire speed and thresholds were set based
 919  *      on testing data as well as attempting to minimize response time
 920  *      while increasing bulk throughput.
 921  *      this functionality is controlled by the InterruptThrottleRate module
 922  *      parameter (see ixgbe_param.c)
 923  **/
 924 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 925                            u32 eitr, u8 itr_setting,
 926                            int packets, int bytes)
 927 {
 928         unsigned int retval = itr_setting;
 929         u32 timepassed_us;
 930         u64 bytes_perint;
 931
 932         if (packets == 0)
 933                 goto update_itr_done;
 934
 935
 936         /* simple throttlerate management
 937          *    0-20MB/s lowest (100000 ints/s)
 938          *   20-100MB/s low   (20000 ints/s)
 939          *  100-1249MB/s bulk (8000 ints/s)
 940          */
 941         /* what was last interrupt timeslice? */
 942         timepassed_us = 1000000/eitr;
 943         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 944
 945         switch (itr_setting) {
 946         case lowest_latency:
 947                 if (bytes_perint > adapter->eitr_low)
 948                         retval = low_latency;
 949                 break;
 950         case low_latency:
 951                 if (bytes_perint > adapter->eitr_high)
 952                         retval = bulk_latency;
 953                 else if (bytes_perint <= adapter->eitr_low)
 954                         retval = lowest_latency;
 955                 break;
 956         case bulk_latency:
 957                 if (bytes_perint <= adapter->eitr_high)
 958                         retval = low_latency;
 959                 break;
 960         }
 961
 962 update_itr_done:
 963         return retval;
 964 }
 965
 966 /**
 967  * ixgbe_write_eitr - write EITR register in hardware specific way
 968  * @adapter: pointer to adapter struct
 969  * @v_idx: vector index into q_vector array
 970  * @itr_reg: new value to be written in *register* format, not ints/s
 971  *
 972  * This function is made to be called by ethtool and by the driver
 973  * when it needs to update EITR registers at runtime.  Hardware
 974  * specific quirks/differences are taken care of here.
 975  */
 976 void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
 977 {
 978         struct ixgbe_hw *hw = &adapter->hw;
 979         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 980                 /* must write high and low 16 bits to reset counter */
 981                 itr_reg |= (itr_reg << 16);
 982         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 983                 /*
 984                  * set the WDIS bit to not clear the timer bits and cause an
 985                  * immediate assertion of the interrupt
 986                  */
 987                 itr_reg |= IXGBE_EITR_CNT_WDIS;
 988         }
 989         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
 990 }
 991
 992 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 993 {
 994         struct ixgbe_adapter *adapter = q_vector->adapter;
 995         u32 new_itr;
 996         u8 current_itr, ret_itr;
 997         int i, r_idx, v_idx = q_vector->v_idx;
 998         struct ixgbe_ring *rx_ring, *tx_ring;
 999
1000         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1001         for (i = 0; i < q_vector->txr_count; i++) {
1002                 tx_ring = &(adapter->tx_ring[r_idx]);
1003                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1004                                            q_vector->tx_itr,
1005                                            tx_ring->total_packets,
1006                                            tx_ring->total_bytes);
1007                 /* if the result for this queue would decrease interrupt
1008                  * rate for this vector then use that result */
1009                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1010                                     q_vector->tx_itr - 1 : ret_itr);
1011                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1012                                       r_idx + 1);
1013         }
1014
1015         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1016         for (i = 0; i < q_vector->rxr_count; i++) {
1017                 rx_ring = &(adapter->rx_ring[r_idx]);
1018                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1019                                            q_vector->rx_itr,
1020                                            rx_ring->total_packets,
1021                                            rx_ring->total_bytes);
1022                 /* if the result for this queue would decrease interrupt
1023                  * rate for this vector then use that result */
1024                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1025                                     q_vector->rx_itr - 1 : ret_itr);
1026                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1027                                       r_idx + 1);
1028         }
1029
1030         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1031
1032         switch (current_itr) {
1033         /* counts and packets in update_itr are dependent on these numbers */
1034         case lowest_latency:
1035                 new_itr = 100000;
1036                 break;
1037         case low_latency:
1038                 new_itr = 20000; /* aka hwitr = ~200 */
1039                 break;
1040         case bulk_latency:
1041         default:
1042                 new_itr = 8000;
1043                 break;
1044         }
1045
1046         if (new_itr != q_vector->eitr) {
1047                 u32 itr_reg;
1048
1049                 /* save the algorithm value here, not the smoothed one */
1050                 q_vector->eitr = new_itr;
1051                 /* do an exponential smoothing */
1052                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1053                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1054                 ixgbe_write_eitr(adapter, v_idx, itr_reg);
1055         }
1056
1057         return;
1058 }
1059
1060 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1061 {
1062         struct ixgbe_hw *hw = &adapter->hw;
1063
1064         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1065             (eicr & IXGBE_EICR_GPI_SDP1)) {
1066                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1067                 /* write to clear the interrupt */
1068                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1069         }
1070 }
1071
1072 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1073 {
1074         struct ixgbe_hw *hw = &adapter->hw;
1075
1076         if (eicr & IXGBE_EICR_GPI_SDP1) {
1077                 /* Clear the interrupt */
1078                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1079                 schedule_work(&adapter->multispeed_fiber_task);
1080         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1081                 /* Clear the interrupt */
1082                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1083                 schedule_work(&adapter->sfp_config_module_task);
1084         } else {
1085                 /* Interrupt isn't for us... */
1086                 return;
1087         }
1088 }
1089
1090 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1091 {
1092         struct ixgbe_hw *hw = &adapter->hw;
1093
1094         adapter->lsc_int++;
1095         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1096         adapter->link_check_timeout = jiffies;
1097         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1098                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1099                 schedule_work(&adapter->watchdog_task);
1100         }
1101 }
1102
1103 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1104 {
1105         struct net_device *netdev = data;
1106         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1107         struct ixgbe_hw *hw = &adapter->hw;
1108         u32 eicr;
1109
1110         /*
1111          * Workaround for Silicon errata.  Use clear-by-write instead
1112          * of clear-by-read.  Reading with EICS will return the
1113          * interrupt causes without clearing, which later be done
1114          * with the write to EICR.
1115          */
1116         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1117         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1118
1119         if (eicr & IXGBE_EICR_LSC)
1120                 ixgbe_check_lsc(adapter);
1121
1122         if (hw->mac.type == ixgbe_mac_82598EB)
1123                 ixgbe_check_fan_failure(adapter, eicr);
1124
1125         if (hw->mac.type == ixgbe_mac_82599EB)
1126                 ixgbe_check_sfp_event(adapter, eicr);
1127         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1128                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1129
1130         return IRQ_HANDLED;
1131 }
1132
1133 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1134 {
1135         struct ixgbe_q_vector *q_vector = data;
1136         struct ixgbe_adapter  *adapter = q_vector->adapter;
1137         struct ixgbe_ring     *tx_ring;
1138         int i, r_idx;
1139
1140         if (!q_vector->txr_count)
1141                 return IRQ_HANDLED;
1142
1143         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1144         for (i = 0; i < q_vector->txr_count; i++) {
1145                 tx_ring = &(adapter->tx_ring[r_idx]);
1146 #ifdef CONFIG_IXGBE_DCA
1147                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1148                         ixgbe_update_tx_dca(adapter, tx_ring);
1149 #endif
1150                 tx_ring->total_bytes = 0;
1151                 tx_ring->total_packets = 0;
1152                 ixgbe_clean_tx_irq(adapter, tx_ring);
1153                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1154                                       r_idx + 1);
1155         }
1156
1157         return IRQ_HANDLED;
1158 }
1159
1160 /**
1161  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1162  * @irq: unused
1163  * @data: pointer to our q_vector struct for this interrupt vector
1164  **/
1165 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1166 {
1167         struct ixgbe_q_vector *q_vector = data;
1168         struct ixgbe_adapter  *adapter = q_vector->adapter;
1169         struct ixgbe_ring  *rx_ring;
1170         int r_idx;
1171         int i;
1172
1173         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1174         for (i = 0;  i < q_vector->rxr_count; i++) {
1175                 rx_ring = &(adapter->rx_ring[r_idx]);
1176                 rx_ring->total_bytes = 0;
1177                 rx_ring->total_packets = 0;
1178                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1179                                       r_idx + 1);
1180         }
1181
1182         if (!q_vector->rxr_count)
1183                 return IRQ_HANDLED;
1184
1185         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1186         rx_ring = &(adapter->rx_ring[r_idx]);
1187         /* disable interrupts on this vector only */
1188         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1189                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1190         else if (rx_ring->v_idx & 0xFFFFFFFF)
1191                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1192         else
1193                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1194                                 (rx_ring->v_idx >> 32));
1195         napi_schedule(&q_vector->napi);
1196
1197         return IRQ_HANDLED;
1198 }
1199
1200 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1201 {
1202         ixgbe_msix_clean_rx(irq, data);
1203         ixgbe_msix_clean_tx(irq, data);
1204
1205         return IRQ_HANDLED;
1206 }
1207
1208 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1209                                            u64 qmask)
1210 {
1211         u32 mask;
1212
1213         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1214                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1215                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1216         } else {
1217                 mask = (qmask & 0xFFFFFFFF);
1218                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1219                 mask = (qmask >> 32);
1220                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1221         }
1222         /* skip the flush */
1223 }
1224
1225 /**
1226  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1227  * @napi: napi struct with our devices info in it
1228  * @budget: amount of work driver is allowed to do this pass, in packets
1229  *
1230  * This function is optimized for cleaning one queue only on a single
1231  * q_vector!!!
1232  **/
1233 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1234 {
1235         struct ixgbe_q_vector *q_vector =
1236                                container_of(napi, struct ixgbe_q_vector, napi);
1237         struct ixgbe_adapter *adapter = q_vector->adapter;
1238         struct ixgbe_ring *rx_ring = NULL;
1239         int work_done = 0;
1240         long r_idx;
1241
1242         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1243         rx_ring = &(adapter->rx_ring[r_idx]);
1244 #ifdef CONFIG_IXGBE_DCA
1245         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1246                 ixgbe_update_rx_dca(adapter, rx_ring);
1247 #endif
1248
1249         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1250
1251         /* If all Rx work done, exit the polling mode */
1252         if (work_done < budget) {
1253                 napi_complete(napi);
1254                 if (adapter->itr_setting & 1)
1255                         ixgbe_set_itr_msix(q_vector);
1256                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1257                         ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
1258         }
1259
1260         return work_done;
1261 }
1262
1263 /**
1264  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1265  * @napi: napi struct with our devices info in it
1266  * @budget: amount of work driver is allowed to do this pass, in packets
1267  *
1268  * This function will clean more than one rx queue associated with a
1269  * q_vector.
1270  **/
1271 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1272 {
1273         struct ixgbe_q_vector *q_vector =
1274                                container_of(napi, struct ixgbe_q_vector, napi);
1275         struct ixgbe_adapter *adapter = q_vector->adapter;
1276         struct ixgbe_ring *rx_ring = NULL;
1277         int work_done = 0, i;
1278         long r_idx;
1279         u64 enable_mask = 0;
1280
1281         /* attempt to distribute budget to each queue fairly, but don't allow
1282          * the budget to go below 1 because we'll exit polling */
1283         budget /= (q_vector->rxr_count ?: 1);
1284         budget = max(budget, 1);
1285         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1286         for (i = 0; i < q_vector->rxr_count; i++) {
1287                 rx_ring = &(adapter->rx_ring[r_idx]);
1288 #ifdef CONFIG_IXGBE_DCA
1289                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1290                         ixgbe_update_rx_dca(adapter, rx_ring);
1291 #endif
1292                 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1293                 enable_mask |= rx_ring->v_idx;
1294                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1295                                       r_idx + 1);
1296         }
1297
1298         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1299         rx_ring = &(adapter->rx_ring[r_idx]);
1300         /* If all Rx work done, exit the polling mode */
1301         if (work_done < budget) {
1302                 napi_complete(napi);
1303                 if (adapter->itr_setting & 1)
1304                         ixgbe_set_itr_msix(q_vector);
1305                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1306                         ixgbe_irq_enable_queues(adapter, enable_mask);
1307                 return 0;
1308         }
1309
1310         return work_done;
1311 }
1312 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1313                                      int r_idx)
1314 {
1315         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1316
1317         set_bit(r_idx, q_vector->rxr_idx);
1318         q_vector->rxr_count++;
1319         a->rx_ring[r_idx].v_idx = (u64)1 << v_idx;
1320 }
1321
1322 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1323                                      int t_idx)
1324 {
1325         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1326
1327         set_bit(t_idx, q_vector->txr_idx);
1328         q_vector->txr_count++;
1329         a->tx_ring[t_idx].v_idx = (u64)1 << v_idx;
1330 }
1331
1332 /**
1333  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1334  * @adapter: board private structure to initialize
1335  * @vectors: allotted vector count for descriptor rings
1336  *
1337  * This function maps descriptor rings to the queue-specific vectors
1338  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1339  * one vector per ring/queue, but on a constrained vector budget, we
1340  * group the rings as "efficiently" as possible.  You would add new
1341  * mapping configurations in here.
1342  **/
1343 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1344                                       int vectors)
1345 {
1346         int v_start = 0;
1347         int rxr_idx = 0, txr_idx = 0;
1348         int rxr_remaining = adapter->num_rx_queues;
1349         int txr_remaining = adapter->num_tx_queues;
1350         int i, j;
1351         int rqpv, tqpv;
1352         int err = 0;
1353
1354         /* No mapping required if MSI-X is disabled. */
1355         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1356                 goto out;
1357
1358         /*
1359          * The ideal configuration...
1360          * We have enough vectors to map one per queue.
1361          */
1362         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1363                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1364                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1365
1366                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1367                         map_vector_to_txq(adapter, v_start, txr_idx);
1368
1369                 goto out;
1370         }
1371
1372         /*
1373          * If we don't have enough vectors for a 1-to-1
1374          * mapping, we'll have to group them so there are
1375          * multiple queues per vector.
1376          */
1377         /* Re-adjusting *qpv takes care of the remainder. */
1378         for (i = v_start; i < vectors; i++) {
1379                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1380                 for (j = 0; j < rqpv; j++) {
1381                         map_vector_to_rxq(adapter, i, rxr_idx);
1382                         rxr_idx++;
1383                         rxr_remaining--;
1384                 }
1385         }
1386         for (i = v_start; i < vectors; i++) {
1387                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1388                 for (j = 0; j < tqpv; j++) {
1389                         map_vector_to_txq(adapter, i, txr_idx);
1390                         txr_idx++;
1391                         txr_remaining--;
1392                 }
1393         }
1394
1395 out:
1396         return err;
1397 }
1398
1399 /**
1400  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1401  * @adapter: board private structure
1402  *
1403  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1404  * interrupts from the kernel.
1405  **/
1406 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1407 {
1408         struct net_device *netdev = adapter->netdev;
1409         irqreturn_t (*handler)(int, void *);
1410         int i, vector, q_vectors, err;
1411         int ri=0, ti=0;
1412
1413         /* Decrement for Other and TCP Timer vectors */
1414         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1415
1416         /* Map the Tx/Rx rings to the vectors we were allotted. */
1417         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1418         if (err)
1419                 goto out;
1420
1421 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1422                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1423                          &ixgbe_msix_clean_many)
1424         for (vector = 0; vector < q_vectors; vector++) {
1425                 handler = SET_HANDLER(adapter->q_vector[vector]);
1426
1427                 if(handler == &ixgbe_msix_clean_rx) {
1428                         sprintf(adapter->name[vector], "%s-%s-%d",
1429                                 netdev->name, "rx", ri++);
1430                 }
1431                 else if(handler == &ixgbe_msix_clean_tx) {
1432                         sprintf(adapter->name[vector], "%s-%s-%d",
1433                                 netdev->name, "tx", ti++);
1434                 }
1435                 else
1436                         sprintf(adapter->name[vector], "%s-%s-%d",
1437                                 netdev->name, "TxRx", vector);
1438
1439                 err = request_irq(adapter->msix_entries[vector].vector,
1440                                   handler, 0, adapter->name[vector],
1441                                   adapter->q_vector[vector]);
1442                 if (err) {
1443                         DPRINTK(PROBE, ERR,
1444                                 "request_irq failed for MSIX interrupt "
1445                                 "Error: %d\n", err);
1446                         goto free_queue_irqs;
1447                 }
1448         }
1449
1450         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1451         err = request_irq(adapter->msix_entries[vector].vector,
1452                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1453         if (err) {
1454                 DPRINTK(PROBE, ERR,
1455                         "request_irq for msix_lsc failed: %d\n", err);
1456                 goto free_queue_irqs;
1457         }
1458
1459         return 0;
1460
1461 free_queue_irqs:
1462         for (i = vector - 1; i >= 0; i--)
1463                 free_irq(adapter->msix_entries[--vector].vector,
1464                          adapter->q_vector[i]);
1465         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1466         pci_disable_msix(adapter->pdev);
1467         kfree(adapter->msix_entries);
1468         adapter->msix_entries = NULL;
1469 out:
1470         return err;
1471 }
1472
1473 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1474 {
1475         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1476         u8 current_itr;
1477         u32 new_itr = q_vector->eitr;
1478         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1479         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1480
1481         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1482                                             q_vector->tx_itr,
1483                                             tx_ring->total_packets,
1484                                             tx_ring->total_bytes);
1485         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1486                                             q_vector->rx_itr,
1487                                             rx_ring->total_packets,
1488                                             rx_ring->total_bytes);
1489
1490         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1491
1492         switch (current_itr) {
1493         /* counts and packets in update_itr are dependent on these numbers */
1494         case lowest_latency:
1495                 new_itr = 100000;
1496                 break;
1497         case low_latency:
1498                 new_itr = 20000; /* aka hwitr = ~200 */
1499                 break;
1500         case bulk_latency:
1501                 new_itr = 8000;
1502                 break;
1503         default:
1504                 break;
1505         }
1506
1507         if (new_itr != q_vector->eitr) {
1508                 u32 itr_reg;
1509
1510                 /* save the algorithm value here, not the smoothed one */
1511                 q_vector->eitr = new_itr;
1512                 /* do an exponential smoothing */
1513                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1514                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1515                 ixgbe_write_eitr(adapter, 0, itr_reg);
1516         }
1517
1518         return;
1519 }
1520
1521 /**
1522  * ixgbe_irq_enable - Enable default interrupt generation settings
1523  * @adapter: board private structure
1524  **/
1525 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1526 {
1527         u32 mask;
1528
1529         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1530         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1531                 mask |= IXGBE_EIMS_GPI_SDP1;
1532         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1533                 mask |= IXGBE_EIMS_ECC;
1534                 mask |= IXGBE_EIMS_GPI_SDP1;
1535                 mask |= IXGBE_EIMS_GPI_SDP2;
1536         }
1537
1538         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1539         ixgbe_irq_enable_queues(adapter, ~0);
1540         IXGBE_WRITE_FLUSH(&adapter->hw);
1541 }
1542
1543 /**
1544  * ixgbe_intr - legacy mode Interrupt Handler
1545  * @irq: interrupt number
1546  * @data: pointer to a network interface device structure
1547  **/
1548 static irqreturn_t ixgbe_intr(int irq, void *data)
1549 {
1550         struct net_device *netdev = data;
1551         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1552         struct ixgbe_hw *hw = &adapter->hw;
1553         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1554         u32 eicr;
1555
1556         /*
1557          * Workaround for silicon errata.  Mask the interrupts
1558          * before the read of EICR.
1559          */
1560         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1561
1562         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1563          * therefore no explict interrupt disable is necessary */
1564         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1565         if (!eicr) {
1566                 /* shared interrupt alert!
1567                  * make sure interrupts are enabled because the read will
1568                  * have disabled interrupts due to EIAM */
1569                 ixgbe_irq_enable(adapter);
1570                 return IRQ_NONE;        /* Not our interrupt */
1571         }
1572
1573         if (eicr & IXGBE_EICR_LSC)
1574                 ixgbe_check_lsc(adapter);
1575
1576         if (hw->mac.type == ixgbe_mac_82599EB)
1577                 ixgbe_check_sfp_event(adapter, eicr);
1578
1579         ixgbe_check_fan_failure(adapter, eicr);
1580
1581         if (napi_schedule_prep(&(q_vector->napi))) {
1582                 adapter->tx_ring[0].total_packets = 0;
1583                 adapter->tx_ring[0].total_bytes = 0;
1584                 adapter->rx_ring[0].total_packets = 0;
1585                 adapter->rx_ring[0].total_bytes = 0;
1586                 /* would disable interrupts here but EIAM disabled it */
1587                 __napi_schedule(&(q_vector->napi));
1588         }
1589
1590         return IRQ_HANDLED;
1591 }
1592
1593 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1594 {
1595         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1596
1597         for (i = 0; i < q_vectors; i++) {
1598                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1599                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1600                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1601                 q_vector->rxr_count = 0;
1602                 q_vector->txr_count = 0;
1603         }
1604 }
1605
1606 /**
1607  * ixgbe_request_irq - initialize interrupts
1608  * @adapter: board private structure
1609  *
1610  * Attempts to configure interrupts using the best available
1611  * capabilities of the hardware and kernel.
1612  **/
1613 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1614 {
1615         struct net_device *netdev = adapter->netdev;
1616         int err;
1617
1618         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1619                 err = ixgbe_request_msix_irqs(adapter);
1620         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1621                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1622                                   netdev->name, netdev);
1623         } else {
1624                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1625                                   netdev->name, netdev);
1626         }
1627
1628         if (err)
1629                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1630
1631         return err;
1632 }
1633
1634 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1635 {
1636         struct net_device *netdev = adapter->netdev;
1637
1638         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1639                 int i, q_vectors;
1640
1641                 q_vectors = adapter->num_msix_vectors;
1642
1643                 i = q_vectors - 1;
1644                 free_irq(adapter->msix_entries[i].vector, netdev);
1645
1646                 i--;
1647                 for (; i >= 0; i--) {
1648                         free_irq(adapter->msix_entries[i].vector,
1649                                  adapter->q_vector[i]);
1650                 }
1651
1652                 ixgbe_reset_q_vectors(adapter);
1653         } else {
1654                 free_irq(adapter->pdev->irq, netdev);
1655         }
1656 }
1657
1658 /**
1659  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1660  * @adapter: board private structure
1661  **/
1662 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1663 {
1664         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1665                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1666         } else {
1667                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1668                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1669                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1670         }
1671         IXGBE_WRITE_FLUSH(&adapter->hw);
1672         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1673                 int i;
1674                 for (i = 0; i < adapter->num_msix_vectors; i++)
1675                         synchronize_irq(adapter->msix_entries[i].vector);
1676         } else {
1677                 synchronize_irq(adapter->pdev->irq);
1678         }
1679 }
1680
1681 /**
1682  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1683  *
1684  **/
1685 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1686 {
1687         struct ixgbe_hw *hw = &adapter->hw;
1688
1689         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1690                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1691
1692         ixgbe_set_ivar(adapter, 0, 0, 0);
1693         ixgbe_set_ivar(adapter, 1, 0, 0);
1694
1695         map_vector_to_rxq(adapter, 0, 0);
1696         map_vector_to_txq(adapter, 0, 0);
1697
1698         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1699 }
1700
1701 /**
1702  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1703  * @adapter: board private structure
1704  *
1705  * Configure the Tx unit of the MAC after a reset.
1706  **/
1707 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1708 {
1709         u64 tdba;
1710         struct ixgbe_hw *hw = &adapter->hw;
1711         u32 i, j, tdlen, txctrl;
1712
1713         /* Setup the HW Tx Head and Tail descriptor pointers */
1714         for (i = 0; i < adapter->num_tx_queues; i++) {
1715                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1716                 j = ring->reg_idx;
1717                 tdba = ring->dma;
1718                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1719                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1720                                 (tdba & DMA_BIT_MASK(32)));
1721                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1722                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1723                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1724                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1725                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1726                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1727                 /* Disable Tx Head Writeback RO bit, since this hoses
1728                  * bookkeeping if things aren't delivered in order.
1729                  */
1730                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1731                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1732                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1733         }
1734         if (hw->mac.type == ixgbe_mac_82599EB) {
1735                 /* We enable 8 traffic classes, DCB only */
1736                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1737                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1738                                         IXGBE_MTQC_8TC_8TQ));
1739         }
1740 }
1741
1742 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1743
1744 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1745 {
1746         struct ixgbe_ring *rx_ring;
1747         u32 srrctl;
1748         int queue0 = 0;
1749         unsigned long mask;
1750         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1751
1752         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1753                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1754                         int dcb_i = feature[RING_F_DCB].indices;
1755                         if (dcb_i == 8)
1756                                 queue0 = index >> 4;
1757                         else if (dcb_i == 4)
1758                                 queue0 = index >> 5;
1759                         else
1760                                 dev_err(&adapter->pdev->dev, "Invalid DCB "
1761                                         "configuration\n");
1762 #ifdef IXGBE_FCOE
1763                         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1764                                 struct ixgbe_ring_feature *f;
1765
1766                                 rx_ring = &adapter->rx_ring[queue0];
1767                                 f = &adapter->ring_feature[RING_F_FCOE];
1768                                 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1769                                         queue0 = f->mask + index -
1770                                                  rx_ring->reg_idx - 1;
1771                         }
1772 #endif /* IXGBE_FCOE */
1773                 } else {
1774                         queue0 = index;
1775                 }
1776         } else {
1777                 mask = (unsigned long) feature[RING_F_RSS].mask;
1778                 queue0 = index & mask;
1779                 index = index & mask;
1780         }
1781
1782         rx_ring = &adapter->rx_ring[queue0];
1783
1784         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1785
1786         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1787         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1788
1789         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1790                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1791
1792         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1793 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1794                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1795 #else
1796                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1797 #endif
1798                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1799         } else {
1800                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1801                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1802                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1803         }
1804
1805         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1806 }
1807
1808 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1809 {
1810         u32 mrqc = 0;
1811         int mask;
1812
1813         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1814                 return mrqc;
1815
1816         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1817 #ifdef CONFIG_IXGBE_DCB
1818                                  | IXGBE_FLAG_DCB_ENABLED
1819 #endif
1820                                 );
1821
1822         switch (mask) {
1823         case (IXGBE_FLAG_RSS_ENABLED):
1824                 mrqc = IXGBE_MRQC_RSSEN;
1825                 break;
1826 #ifdef CONFIG_IXGBE_DCB
1827         case (IXGBE_FLAG_DCB_ENABLED):
1828                 mrqc = IXGBE_MRQC_RT8TCEN;
1829                 break;
1830 #endif /* CONFIG_IXGBE_DCB */
1831         default:
1832                 break;
1833         }
1834
1835         return mrqc;
1836 }
1837
1838 /**
1839  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1840  * @adapter: board private structure
1841  *
1842  * Configure the Rx unit of the MAC after a reset.
1843  **/
1844 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1845 {
1846         u64 rdba;
1847         struct ixgbe_hw *hw = &adapter->hw;
1848         struct net_device *netdev = adapter->netdev;
1849         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1850         int i, j;
1851         u32 rdlen, rxctrl, rxcsum;
1852         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1853                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1854                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1855         u32 fctrl, hlreg0;
1856         u32 reta = 0, mrqc = 0;
1857         u32 rdrxctl;
1858         u32 rscctrl;
1859         int rx_buf_len;
1860
1861         /* Decide whether to use packet split mode or not */
1862         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1863
1864 #ifdef IXGBE_FCOE
1865         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1866                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1867 #endif /* IXGBE_FCOE */
1868
1869         /* Set the RX buffer length according to the mode */
1870         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1871                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1872                 if (hw->mac.type == ixgbe_mac_82599EB) {
1873                         /* PSRTYPE must be initialized in 82599 */
1874                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1875                                       IXGBE_PSRTYPE_UDPHDR |
1876                                       IXGBE_PSRTYPE_IPV4HDR |
1877                                       IXGBE_PSRTYPE_IPV6HDR |
1878                                       IXGBE_PSRTYPE_L2HDR;
1879                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1880                 }
1881         } else {
1882                 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1883                     (netdev->mtu <= ETH_DATA_LEN))
1884                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1885                 else
1886                         rx_buf_len = ALIGN(max_frame, 1024);
1887         }
1888
1889         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1890         fctrl |= IXGBE_FCTRL_BAM;
1891         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1892         fctrl |= IXGBE_FCTRL_PMCF;
1893         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1894
1895         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1896         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1897                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1898         else
1899                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1900 #ifdef IXGBE_FCOE
1901         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1902                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1903 #endif
1904         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1905
1906         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1907         /* disable receives while setting up the descriptors */
1908         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1909         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1910
1911         /*
1912          * Setup the HW Rx Head and Tail Descriptor Pointers and
1913          * the Base and Length of the Rx Descriptor Ring
1914          */
1915         for (i = 0; i < adapter->num_rx_queues; i++) {
1916                 rdba = adapter->rx_ring[i].dma;
1917                 j = adapter->rx_ring[i].reg_idx;
1918                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
1919                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1920                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1921                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1922                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1923                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1924                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1925                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1926
1927 #ifdef IXGBE_FCOE
1928                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1929                         struct ixgbe_ring_feature *f;
1930                         f = &adapter->ring_feature[RING_F_FCOE];
1931                         if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
1932                             (i >= f->mask) && (i < f->mask + f->indices))
1933                                 adapter->rx_ring[i].rx_buf_len =
1934                                         IXGBE_FCOE_JUMBO_FRAME_SIZE;
1935                 }
1936
1937 #endif /* IXGBE_FCOE */
1938                 ixgbe_configure_srrctl(adapter, j);
1939         }
1940
1941         if (hw->mac.type == ixgbe_mac_82598EB) {
1942                 /*
1943                  * For VMDq support of different descriptor types or
1944                  * buffer sizes through the use of multiple SRRCTL
1945                  * registers, RDRXCTL.MVMEN must be set to 1
1946                  *
1947                  * also, the manual doesn't mention it clearly but DCA hints
1948                  * will only use queue 0's tags unless this bit is set.  Side
1949                  * effects of setting this bit are only that SRRCTL must be
1950                  * fully programmed [0..15]
1951                  */
1952                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1953                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1954                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1955         }
1956
1957         /* Program MRQC for the distribution of queues */
1958         mrqc = ixgbe_setup_mrqc(adapter);
1959
1960         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1961                 /* Fill out redirection table */
1962                 for (i = 0, j = 0; i < 128; i++, j++) {
1963                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1964                                 j = 0;
1965                         /* reta = 4-byte sliding window of
1966                          * 0x00..(indices-1)(indices-1)00..etc. */
1967                         reta = (reta << 8) | (j * 0x11);
1968                         if ((i & 3) == 3)
1969                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1970                 }
1971
1972                 /* Fill out hash function seeds */
1973                 for (i = 0; i < 10; i++)
1974                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1975
1976                 if (hw->mac.type == ixgbe_mac_82598EB)
1977                         mrqc |= IXGBE_MRQC_RSSEN;
1978                     /* Perform hash on these packet types */
1979                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1980                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1981                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1982                       | IXGBE_MRQC_RSS_FIELD_IPV6
1983                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1984                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1985         }
1986         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1987
1988         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1989
1990         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1991             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1992                 /* Disable indicating checksum in descriptor, enables
1993                  * RSS hash */
1994                 rxcsum |= IXGBE_RXCSUM_PCSD;
1995         }
1996         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1997                 /* Enable IPv4 payload checksum for UDP fragments
1998                  * if PCSD is not set */
1999                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2000         }
2001
2002         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2003
2004         if (hw->mac.type == ixgbe_mac_82599EB) {
2005                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2006                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2007                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2008                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2009         }
2010
2011         if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
2012                 /* Enable 82599 HW-RSC */
2013                 for (i = 0; i < adapter->num_rx_queues; i++) {
2014                         j = adapter->rx_ring[i].reg_idx;
2015                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2016                         rscctrl |= IXGBE_RSCCTL_RSCEN;
2017                         /*
2018                          * we must limit the number of descriptors so that the
2019                          * total size of max desc * buf_len is not greater
2020                          * than 65535
2021                          */
2022                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2023 #if (MAX_SKB_FRAGS > 16)
2024                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2025 #elif (MAX_SKB_FRAGS > 8)
2026                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2027 #elif (MAX_SKB_FRAGS > 4)
2028                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2029 #else
2030                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2031 #endif
2032                         } else {
2033                                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2034                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2035                                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2036                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2037                                 else
2038                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2039                         }
2040                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2041                 }
2042                 /* Disable RSC for ACK packets */
2043                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2044                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2045         }
2046 }
2047
2048 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2049 {
2050         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2051         struct ixgbe_hw *hw = &adapter->hw;
2052
2053         /* add VID to filter table */
2054         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2055 }
2056
2057 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2058 {
2059         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2060         struct ixgbe_hw *hw = &adapter->hw;
2061
2062         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2063                 ixgbe_irq_disable(adapter);
2064
2065         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2066
2067         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2068                 ixgbe_irq_enable(adapter);
2069
2070         /* remove VID from filter table */
2071         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2072 }
2073
2074 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2075                                    struct vlan_group *grp)
2076 {
2077         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2078         u32 ctrl;
2079         int i, j;
2080
2081         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2082                 ixgbe_irq_disable(adapter);
2083         adapter->vlgrp = grp;
2084
2085         /*
2086          * For a DCB driver, always enable VLAN tag stripping so we can
2087          * still receive traffic from a DCB-enabled host even if we're
2088          * not in DCB mode.
2089          */
2090         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2091         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2092                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2093                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2094                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2095         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2096                 ctrl |= IXGBE_VLNCTRL_VFE;
2097                 /* enable VLAN tag insert/strip */
2098                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2099                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2100                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2101                 for (i = 0; i < adapter->num_rx_queues; i++) {
2102                         j = adapter->rx_ring[i].reg_idx;
2103                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2104                         ctrl |= IXGBE_RXDCTL_VME;
2105                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2106                 }
2107         }
2108         ixgbe_vlan_rx_add_vid(netdev, 0);
2109
2110         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2111                 ixgbe_irq_enable(adapter);
2112 }
2113
2114 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2115 {
2116         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2117
2118         if (adapter->vlgrp) {
2119                 u16 vid;
2120                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2121                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2122                                 continue;
2123                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2124                 }
2125         }
2126 }
2127
2128 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2129 {
2130         struct dev_mc_list *mc_ptr;
2131         u8 *addr = *mc_addr_ptr;
2132         *vmdq = 0;
2133
2134         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2135         if (mc_ptr->next)
2136                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2137         else
2138                 *mc_addr_ptr = NULL;
2139
2140         return addr;
2141 }
2142
2143 /**
2144  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2145  * @netdev: network interface device structure
2146  *
2147  * The set_rx_method entry point is called whenever the unicast/multicast
2148  * address list or the network interface flags are updated.  This routine is
2149  * responsible for configuring the hardware for proper unicast, multicast and
2150  * promiscuous mode.
2151  **/
2152 static void ixgbe_set_rx_mode(struct net_device *netdev)
2153 {
2154         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2155         struct ixgbe_hw *hw = &adapter->hw;
2156         u32 fctrl, vlnctrl;
2157         u8 *addr_list = NULL;
2158         int addr_count = 0;
2159
2160         /* Check for Promiscuous and All Multicast modes */
2161
2162         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2163         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2164
2165         if (netdev->flags & IFF_PROMISC) {
2166                 hw->addr_ctrl.user_set_promisc = 1;
2167                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2168                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2169         } else {
2170                 if (netdev->flags & IFF_ALLMULTI) {
2171                         fctrl |= IXGBE_FCTRL_MPE;
2172                         fctrl &= ~IXGBE_FCTRL_UPE;
2173                 } else {
2174                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2175                 }
2176                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2177                 hw->addr_ctrl.user_set_promisc = 0;
2178         }
2179
2180         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2181         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2182
2183         /* reprogram secondary unicast list */
2184         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc_list);
2185
2186         /* reprogram multicast list */
2187         addr_count = netdev->mc_count;
2188         if (addr_count)
2189                 addr_list = netdev->mc_list->dmi_addr;
2190         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2191                                         ixgbe_addr_list_itr);
2192 }
2193
2194 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2195 {
2196         int q_idx;
2197         struct ixgbe_q_vector *q_vector;
2198         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2199
2200         /* legacy and MSI only use one vector */
2201         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2202                 q_vectors = 1;
2203
2204         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2205                 struct napi_struct *napi;
2206                 q_vector = adapter->q_vector[q_idx];
2207                 if (!q_vector->rxr_count)
2208                         continue;
2209                 napi = &q_vector->napi;
2210                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2211                     (q_vector->rxr_count > 1))
2212                         napi->poll = &ixgbe_clean_rxonly_many;
2213
2214                 napi_enable(napi);
2215         }
2216 }
2217
2218 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2219 {
2220         int q_idx;
2221         struct ixgbe_q_vector *q_vector;
2222         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2223
2224         /* legacy and MSI only use one vector */
2225         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2226                 q_vectors = 1;
2227
2228         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2229                 q_vector = adapter->q_vector[q_idx];
2230                 if (!q_vector->rxr_count)
2231                         continue;
2232                 napi_disable(&q_vector->napi);
2233         }
2234 }
2235
2236 #ifdef CONFIG_IXGBE_DCB
2237 /*
2238  * ixgbe_configure_dcb - Configure DCB hardware
2239  * @adapter: ixgbe adapter struct
2240  *
2241  * This is called by the driver on open to configure the DCB hardware.
2242  * This is also called by the gennetlink interface when reconfiguring
2243  * the DCB state.
2244  */
2245 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2246 {
2247         struct ixgbe_hw *hw = &adapter->hw;
2248         u32 txdctl, vlnctrl;
2249         int i, j;
2250
2251         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2252         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2253         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2254
2255         /* reconfigure the hardware */
2256         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2257
2258         for (i = 0; i < adapter->num_tx_queues; i++) {
2259                 j = adapter->tx_ring[i].reg_idx;
2260                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2261                 /* PThresh workaround for Tx hang with DFP enabled. */
2262                 txdctl |= 32;
2263                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2264         }
2265         /* Enable VLAN tag insert/strip */
2266         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2267         if (hw->mac.type == ixgbe_mac_82598EB) {
2268                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2269                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2270                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2271         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2272                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2273                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2274                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2275                 for (i = 0; i < adapter->num_rx_queues; i++) {
2276                         j = adapter->rx_ring[i].reg_idx;
2277                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2278                         vlnctrl |= IXGBE_RXDCTL_VME;
2279                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2280                 }
2281         }
2282         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2283 }
2284
2285 #endif
2286 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2287 {
2288         struct net_device *netdev = adapter->netdev;
2289         int i;
2290
2291         ixgbe_set_rx_mode(netdev);
2292
2293         ixgbe_restore_vlan(adapter);
2294 #ifdef CONFIG_IXGBE_DCB
2295         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2296                 netif_set_gso_max_size(netdev, 32768);
2297                 ixgbe_configure_dcb(adapter);
2298         } else {
2299                 netif_set_gso_max_size(netdev, 65536);
2300         }
2301 #else
2302         netif_set_gso_max_size(netdev, 65536);
2303 #endif
2304
2305 #ifdef IXGBE_FCOE
2306         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2307                 ixgbe_configure_fcoe(adapter);
2308
2309 #endif /* IXGBE_FCOE */
2310         ixgbe_configure_tx(adapter);
2311         ixgbe_configure_rx(adapter);
2312         for (i = 0; i < adapter->num_rx_queues; i++)
2313                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2314                                        (adapter->rx_ring[i].count - 1));
2315 }
2316
2317 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2318 {
2319         switch (hw->phy.type) {
2320         case ixgbe_phy_sfp_avago:
2321         case ixgbe_phy_sfp_ftl:
2322         case ixgbe_phy_sfp_intel:
2323         case ixgbe_phy_sfp_unknown:
2324         case ixgbe_phy_tw_tyco:
2325         case ixgbe_phy_tw_unknown:
2326                 return true;
2327         default:
2328                 return false;
2329         }
2330 }
2331
2332 /**
2333  * ixgbe_sfp_link_config - set up SFP+ link
2334  * @adapter: pointer to private adapter struct
2335  **/
2336 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2337 {
2338         struct ixgbe_hw *hw = &adapter->hw;
2339
2340                 if (hw->phy.multispeed_fiber) {
2341                         /*
2342                          * In multispeed fiber setups, the device may not have
2343                          * had a physical connection when the driver loaded.
2344                          * If that's the case, the initial link configuration
2345                          * couldn't get the MAC into 10G or 1G mode, so we'll
2346                          * never have a link status change interrupt fire.
2347                          * We need to try and force an autonegotiation
2348                          * session, then bring up link.
2349                          */
2350                         hw->mac.ops.setup_sfp(hw);
2351                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2352                                 schedule_work(&adapter->multispeed_fiber_task);
2353                 } else {
2354                         /*
2355                          * Direct Attach Cu and non-multispeed fiber modules
2356                          * still need to be configured properly prior to
2357                          * attempting link.
2358                          */
2359                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2360                                 schedule_work(&adapter->sfp_config_module_task);
2361                 }
2362 }
2363
2364 /**
2365  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2366  * @hw: pointer to private hardware struct
2367  *
2368  * Returns 0 on success, negative on failure
2369  **/
2370 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2371 {
2372         u32 autoneg;
2373         bool link_up = false;
2374         u32 ret = IXGBE_ERR_LINK_SETUP;
2375
2376         if (hw->mac.ops.check_link)
2377                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2378
2379         if (ret)
2380                 goto link_cfg_out;
2381
2382         if (hw->mac.ops.get_link_capabilities)
2383                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2384                                                         &hw->mac.autoneg);
2385         if (ret)
2386                 goto link_cfg_out;
2387
2388         if (hw->mac.ops.setup_link_speed)
2389                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2390 link_cfg_out:
2391         return ret;
2392 }
2393
2394 #define IXGBE_MAX_RX_DESC_POLL 10
2395 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2396                                               int rxr)
2397 {
2398         int j = adapter->rx_ring[rxr].reg_idx;
2399         int k;
2400
2401         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2402                 if (IXGBE_READ_REG(&adapter->hw,
2403                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2404                         break;
2405                 else
2406                         msleep(1);
2407         }
2408         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2409                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2410                         "not set within the polling period\n", rxr);
2411         }
2412         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2413                               (adapter->rx_ring[rxr].count - 1));
2414 }
2415
2416 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2417 {
2418         struct net_device *netdev = adapter->netdev;
2419         struct ixgbe_hw *hw = &adapter->hw;
2420         int i, j = 0;
2421         int num_rx_rings = adapter->num_rx_queues;
2422         int err;
2423         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2424         u32 txdctl, rxdctl, mhadd;
2425         u32 dmatxctl;
2426         u32 gpie;
2427
2428         ixgbe_get_hw_control(adapter);
2429
2430         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2431             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2432                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2433                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2434                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2435                 } else {
2436                         /* MSI only */
2437                         gpie = 0;
2438                 }
2439                 /* XXX: to interrupt immediately for EICS writes, enable this */
2440                 /* gpie |= IXGBE_GPIE_EIMEN; */
2441                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2442         }
2443
2444         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2445                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2446                  * specifically only auto mask tx and rx interrupts */
2447                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2448         }
2449
2450         /* Enable fan failure interrupt if media type is copper */
2451         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2452                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2453                 gpie |= IXGBE_SDP1_GPIEN;
2454                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2455         }
2456
2457         if (hw->mac.type == ixgbe_mac_82599EB) {
2458                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2459                 gpie |= IXGBE_SDP1_GPIEN;
2460                 gpie |= IXGBE_SDP2_GPIEN;
2461                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2462         }
2463
2464 #ifdef IXGBE_FCOE
2465         /* adjust max frame to be able to do baby jumbo for FCoE */
2466         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2467             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2468                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2469
2470 #endif /* IXGBE_FCOE */
2471         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2472         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2473                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2474                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2475
2476                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2477         }
2478
2479         for (i = 0; i < adapter->num_tx_queues; i++) {
2480                 j = adapter->tx_ring[i].reg_idx;
2481                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2482                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2483                 txdctl |= (8 << 16);
2484                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2485         }
2486
2487         if (hw->mac.type == ixgbe_mac_82599EB) {
2488                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2489                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2490                 dmatxctl |= IXGBE_DMATXCTL_TE;
2491                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2492         }
2493         for (i = 0; i < adapter->num_tx_queues; i++) {
2494                 j = adapter->tx_ring[i].reg_idx;
2495                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2496                 txdctl |= IXGBE_TXDCTL_ENABLE;
2497                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2498         }
2499
2500         for (i = 0; i < num_rx_rings; i++) {
2501                 j = adapter->rx_ring[i].reg_idx;
2502                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2503                 /* enable PTHRESH=32 descriptors (half the internal cache)
2504                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2505                  * this also removes a pesky rx_no_buffer_count increment */
2506                 rxdctl |= 0x0020;
2507                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2508                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2509                 if (hw->mac.type == ixgbe_mac_82599EB)
2510                         ixgbe_rx_desc_queue_enable(adapter, i);
2511         }
2512         /* enable all receives */
2513         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2514         if (hw->mac.type == ixgbe_mac_82598EB)
2515                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2516         else
2517                 rxdctl |= IXGBE_RXCTRL_RXEN;
2518         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2519
2520         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2521                 ixgbe_configure_msix(adapter);
2522         else
2523                 ixgbe_configure_msi_and_legacy(adapter);
2524
2525         clear_bit(__IXGBE_DOWN, &adapter->state);
2526         ixgbe_napi_enable_all(adapter);
2527
2528         /* clear any pending interrupts, may auto mask */
2529         IXGBE_READ_REG(hw, IXGBE_EICR);
2530
2531         ixgbe_irq_enable(adapter);
2532
2533         /*
2534          * If this adapter has a fan, check to see if we had a failure
2535          * before we enabled the interrupt.
2536          */
2537         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2538                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2539                 if (esdp & IXGBE_ESDP_SDP1)
2540                         DPRINTK(DRV, CRIT,
2541                                 "Fan has stopped, replace the adapter\n");
2542         }
2543
2544         /*
2545          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2546          * arrived before interrupts were enabled.  We need to kick off
2547          * the SFP+ module setup first, then try to bring up link.
2548          * If we're not hot-pluggable SFP+, we just need to configure link
2549          * and bring it up.
2550          */
2551         err = hw->phy.ops.identify(hw);
2552         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2553                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2554                 ixgbe_down(adapter);
2555                 return err;
2556         }
2557
2558         if (ixgbe_is_sfp(hw)) {
2559                 ixgbe_sfp_link_config(adapter);
2560         } else {
2561                 err = ixgbe_non_sfp_link_config(hw);
2562                 if (err)
2563                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2564         }
2565
2566         /* enable transmits */
2567         netif_tx_start_all_queues(netdev);
2568
2569         /* bring the link up in the watchdog, this could race with our first
2570          * link up interrupt but shouldn't be a problem */
2571         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2572         adapter->link_check_timeout = jiffies;
2573         mod_timer(&adapter->watchdog_timer, jiffies);
2574         return 0;
2575 }
2576
2577 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2578 {
2579         WARN_ON(in_interrupt());
2580         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2581                 msleep(1);
2582         ixgbe_down(adapter);
2583         ixgbe_up(adapter);
2584         clear_bit(__IXGBE_RESETTING, &adapter->state);
2585 }
2586
2587 int ixgbe_up(struct ixgbe_adapter *adapter)
2588 {
2589         /* hardware has been reset, we need to reload some things */
2590         ixgbe_configure(adapter);
2591
2592         return ixgbe_up_complete(adapter);
2593 }
2594
2595 void ixgbe_reset(struct ixgbe_adapter *adapter)
2596 {
2597         struct ixgbe_hw *hw = &adapter->hw;
2598         int err;
2599
2600         err = hw->mac.ops.init_hw(hw);
2601         if (err && (err != IXGBE_ERR_SFP_NOT_PRESENT))
2602                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2603
2604         /* reprogram the RAR[0] in case user changed it. */
2605         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2606
2607 }
2608
2609 /**
2610  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2611  * @adapter: board private structure
2612  * @rx_ring: ring to free buffers from
2613  **/
2614 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2615                                 struct ixgbe_ring *rx_ring)
2616 {
2617         struct pci_dev *pdev = adapter->pdev;
2618         unsigned long size;
2619         unsigned int i;
2620
2621         /* Free all the Rx ring sk_buffs */
2622
2623         for (i = 0; i < rx_ring->count; i++) {
2624                 struct ixgbe_rx_buffer *rx_buffer_info;
2625
2626                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2627                 if (rx_buffer_info->dma) {
2628                         pci_unmap_single(pdev, rx_buffer_info->dma,
2629                                          rx_ring->rx_buf_len,
2630                                          PCI_DMA_FROMDEVICE);
2631                         rx_buffer_info->dma = 0;
2632                 }
2633                 if (rx_buffer_info->skb) {
2634                         struct sk_buff *skb = rx_buffer_info->skb;
2635                         rx_buffer_info->skb = NULL;
2636                         do {
2637                                 struct sk_buff *this = skb;
2638                                 skb = skb->prev;
2639                                 dev_kfree_skb(this);
2640                         } while (skb);
2641                 }
2642                 if (!rx_buffer_info->page)
2643                         continue;
2644                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2645                                PCI_DMA_FROMDEVICE);
2646                 rx_buffer_info->page_dma = 0;
2647                 put_page(rx_buffer_info->page);
2648                 rx_buffer_info->page = NULL;
2649                 rx_buffer_info->page_offset = 0;
2650         }
2651
2652         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2653         memset(rx_ring->rx_buffer_info, 0, size);
2654
2655         /* Zero out the descriptor ring */
2656         memset(rx_ring->desc, 0, rx_ring->size);
2657
2658         rx_ring->next_to_clean = 0;
2659         rx_ring->next_to_use = 0;
2660
2661         if (rx_ring->head)
2662                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2663         if (rx_ring->tail)
2664                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2665 }
2666
2667 /**
2668  * ixgbe_clean_tx_ring - Free Tx Buffers
2669  * @adapter: board private structure
2670  * @tx_ring: ring to be cleaned
2671  **/
2672 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2673                                 struct ixgbe_ring *tx_ring)
2674 {
2675         struct ixgbe_tx_buffer *tx_buffer_info;
2676         unsigned long size;
2677         unsigned int i;
2678
2679         /* Free all the Tx ring sk_buffs */
2680
2681         for (i = 0; i < tx_ring->count; i++) {
2682                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2683                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2684         }
2685
2686         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2687         memset(tx_ring->tx_buffer_info, 0, size);
2688
2689         /* Zero out the descriptor ring */
2690         memset(tx_ring->desc, 0, tx_ring->size);
2691
2692         tx_ring->next_to_use = 0;
2693         tx_ring->next_to_clean = 0;
2694
2695         if (tx_ring->head)
2696                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2697         if (tx_ring->tail)
2698                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2699 }
2700
2701 /**
2702  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2703  * @adapter: board private structure
2704  **/
2705 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2706 {
2707         int i;
2708
2709         for (i = 0; i < adapter->num_rx_queues; i++)
2710                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2711 }
2712
2713 /**
2714  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2715  * @adapter: board private structure
2716  **/
2717 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2718 {
2719         int i;
2720
2721         for (i = 0; i < adapter->num_tx_queues; i++)
2722                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2723 }
2724
2725 void ixgbe_down(struct ixgbe_adapter *adapter)
2726 {
2727         struct net_device *netdev = adapter->netdev;
2728         struct ixgbe_hw *hw = &adapter->hw;
2729         u32 rxctrl;
2730         u32 txdctl;
2731         int i, j;
2732
2733         /* signal that we are down to the interrupt handler */
2734         set_bit(__IXGBE_DOWN, &adapter->state);
2735
2736         /* disable receives */
2737         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2738         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2739
2740         netif_tx_disable(netdev);
2741
2742         IXGBE_WRITE_FLUSH(hw);
2743         msleep(10);
2744
2745         netif_tx_stop_all_queues(netdev);
2746
2747         ixgbe_irq_disable(adapter);
2748
2749         ixgbe_napi_disable_all(adapter);
2750
2751         del_timer_sync(&adapter->watchdog_timer);
2752         cancel_work_sync(&adapter->watchdog_task);
2753
2754         /* disable transmits in the hardware now that interrupts are off */
2755         for (i = 0; i < adapter->num_tx_queues; i++) {
2756                 j = adapter->tx_ring[i].reg_idx;
2757                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2758                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2759                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2760         }
2761         /* Disable the Tx DMA engine on 82599 */
2762         if (hw->mac.type == ixgbe_mac_82599EB)
2763                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2764                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2765                                  ~IXGBE_DMATXCTL_TE));
2766
2767         netif_carrier_off(netdev);
2768
2769         if (!pci_channel_offline(adapter->pdev))
2770                 ixgbe_reset(adapter);
2771         ixgbe_clean_all_tx_rings(adapter);
2772         ixgbe_clean_all_rx_rings(adapter);
2773
2774 #ifdef CONFIG_IXGBE_DCA
2775         /* since we reset the hardware DCA settings were cleared */
2776         ixgbe_setup_dca(adapter);
2777 #endif
2778 }
2779
2780 /**
2781  * ixgbe_poll - NAPI Rx polling callback
2782  * @napi: structure for representing this polling device
2783  * @budget: how many packets driver is allowed to clean
2784  *
2785  * This function is used for legacy and MSI, NAPI mode
2786  **/
2787 static int ixgbe_poll(struct napi_struct *napi, int budget)
2788 {
2789         struct ixgbe_q_vector *q_vector =
2790                                 container_of(napi, struct ixgbe_q_vector, napi);
2791         struct ixgbe_adapter *adapter = q_vector->adapter;
2792         int tx_clean_complete, work_done = 0;
2793
2794 #ifdef CONFIG_IXGBE_DCA
2795         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2796                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2797                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2798         }
2799 #endif
2800
2801         tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2802         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2803
2804         if (!tx_clean_complete)
2805                 work_done = budget;
2806
2807         /* If budget not fully consumed, exit the polling mode */
2808         if (work_done < budget) {
2809                 napi_complete(napi);
2810                 if (adapter->itr_setting & 1)
2811                         ixgbe_set_itr(adapter);
2812                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2813                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2814         }
2815         return work_done;
2816 }
2817
2818 /**
2819  * ixgbe_tx_timeout - Respond to a Tx Hang
2820  * @netdev: network interface device structure
2821  **/
2822 static void ixgbe_tx_timeout(struct net_device *netdev)
2823 {
2824         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2825
2826         /* Do the reset outside of interrupt context */
2827         schedule_work(&adapter->reset_task);
2828 }
2829
2830 static void ixgbe_reset_task(struct work_struct *work)
2831 {
2832         struct ixgbe_adapter *adapter;
2833         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2834
2835         /* If we're already down or resetting, just bail */
2836         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2837             test_bit(__IXGBE_RESETTING, &adapter->state))
2838                 return;
2839
2840         adapter->tx_timeout_count++;
2841
2842         ixgbe_reinit_locked(adapter);
2843 }
2844
2845 #ifdef CONFIG_IXGBE_DCB
2846 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2847 {
2848         bool ret = false;
2849         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
2850
2851         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2852                 return ret;
2853
2854         f->mask = 0x7 << 3;
2855         adapter->num_rx_queues = f->indices;
2856         adapter->num_tx_queues = f->indices;
2857         ret = true;
2858
2859         return ret;
2860 }
2861 #endif
2862
2863 /**
2864  * ixgbe_set_rss_queues: Allocate queues for RSS
2865  * @adapter: board private structure to initialize
2866  *
2867  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
2868  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2869  *
2870  **/
2871 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2872 {
2873         bool ret = false;
2874         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
2875
2876         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2877                 f->mask = 0xF;
2878                 adapter->num_rx_queues = f->indices;
2879                 adapter->num_tx_queues = f->indices;
2880                 ret = true;
2881         } else {
2882                 ret = false;
2883         }
2884
2885         return ret;
2886 }
2887
2888 #ifdef IXGBE_FCOE
2889 /**
2890  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
2891  * @adapter: board private structure to initialize
2892  *
2893  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
2894  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
2895  * rx queues out of the max number of rx queues, instead, it is used as the
2896  * index of the first rx queue used by FCoE.
2897  *
2898  **/
2899 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
2900 {
2901         bool ret = false;
2902         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
2903
2904         f->indices = min((int)num_online_cpus(), f->indices);
2905         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2906 #ifdef CONFIG_IXGBE_DCB
2907                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2908                         DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
2909                         ixgbe_set_dcb_queues(adapter);
2910                 }
2911 #endif
2912                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2913                         DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
2914                         ixgbe_set_rss_queues(adapter);
2915                 }
2916                 /* adding FCoE rx rings to the end */
2917                 f->mask = adapter->num_rx_queues;
2918                 adapter->num_rx_queues += f->indices;
2919                 if (adapter->num_tx_queues == 0)
2920                         adapter->num_tx_queues = f->indices;
2921
2922                 ret = true;
2923         }
2924
2925         return ret;
2926 }
2927
2928 #endif /* IXGBE_FCOE */
2929 /*
2930  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2931  * @adapter: board private structure to initialize
2932  *
2933  * This is the top level queue allocation routine.  The order here is very
2934  * important, starting with the "most" number of features turned on at once,
2935  * and ending with the smallest set of features.  This way large combinations
2936  * can be allocated if they're turned on, and smaller combinations are the
2937  * fallthrough conditions.
2938  *
2939  **/
2940 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2941 {
2942 #ifdef IXGBE_FCOE
2943         if (ixgbe_set_fcoe_queues(adapter))
2944                 goto done;
2945
2946 #endif /* IXGBE_FCOE */
2947 #ifdef CONFIG_IXGBE_DCB
2948         if (ixgbe_set_dcb_queues(adapter))
2949                 goto done;
2950
2951 #endif
2952         if (ixgbe_set_rss_queues(adapter))
2953                 goto done;
2954
2955         /* fallback to base case */
2956         adapter->num_rx_queues = 1;
2957         adapter->num_tx_queues = 1;
2958
2959 done:
2960         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2961         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2962 }
2963
2964 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2965                                        int vectors)
2966 {
2967         int err, vector_threshold;
2968
2969         /* We'll want at least 3 (vector_threshold):
2970          * 1) TxQ[0] Cleanup
2971          * 2) RxQ[0] Cleanup
2972          * 3) Other (Link Status Change, etc.)
2973          * 4) TCP Timer (optional)
2974          */
2975         vector_threshold = MIN_MSIX_COUNT;
2976
2977         /* The more we get, the more we will assign to Tx/Rx Cleanup
2978          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2979          * Right now, we simply care about how many we'll get; we'll
2980          * set them up later while requesting irq's.
2981          */
2982         while (vectors >= vector_threshold) {
2983                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2984                                       vectors);
2985                 if (!err) /* Success in acquiring all requested vectors. */
2986                         break;
2987                 else if (err < 0)
2988                         vectors = 0; /* Nasty failure, quit now */
2989                 else /* err == number of vectors we should try again with */
2990                         vectors = err;
2991         }
2992
2993         if (vectors < vector_threshold) {
2994                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2995                  * This just means we'll go with either a single MSI
2996                  * vector or fall back to legacy interrupts.
2997                  */
2998                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2999                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3000                 kfree(adapter->msix_entries);
3001                 adapter->msix_entries = NULL;
3002         } else {
3003                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3004                 /*
3005                  * Adjust for only the vectors we'll use, which is minimum
3006                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3007                  * vectors we were allocated.
3008                  */
3009                 adapter->num_msix_vectors = min(vectors,
3010                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3011         }
3012 }
3013
3014 /**
3015  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3016  * @adapter: board private structure to initialize
3017  *
3018  * Cache the descriptor ring offsets for RSS to the assigned rings.
3019  *
3020  **/
3021 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3022 {
3023         int i;
3024         bool ret = false;
3025
3026         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3027                 for (i = 0; i < adapter->num_rx_queues; i++)
3028                         adapter->rx_ring[i].reg_idx = i;
3029                 for (i = 0; i < adapter->num_tx_queues; i++)
3030                         adapter->tx_ring[i].reg_idx = i;
3031                 ret = true;
3032         } else {
3033                 ret = false;
3034         }
3035
3036         return ret;
3037 }
3038
3039 #ifdef CONFIG_IXGBE_DCB
3040 /**
3041  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3042  * @adapter: board private structure to initialize
3043  *
3044  * Cache the descriptor ring offsets for DCB to the assigned rings.
3045  *
3046  **/
3047 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3048 {
3049         int i;
3050         bool ret = false;
3051         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3052
3053         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3054                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3055                         /* the number of queues is assumed to be symmetric */
3056                         for (i = 0; i < dcb_i; i++) {
3057                                 adapter->rx_ring[i].reg_idx = i << 3;
3058                                 adapter->tx_ring[i].reg_idx = i << 2;
3059                         }
3060                         ret = true;
3061                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3062                         if (dcb_i == 8) {
3063                                 /*
3064                                  * Tx TC0 starts at: descriptor queue 0
3065                                  * Tx TC1 starts at: descriptor queue 32
3066                                  * Tx TC2 starts at: descriptor queue 64
3067                                  * Tx TC3 starts at: descriptor queue 80
3068                                  * Tx TC4 starts at: descriptor queue 96
3069                                  * Tx TC5 starts at: descriptor queue 104
3070                                  * Tx TC6 starts at: descriptor queue 112
3071                                  * Tx TC7 starts at: descriptor queue 120
3072                                  *
3073                                  * Rx TC0-TC7 are offset by 16 queues each
3074                                  */
3075                                 for (i = 0; i < 3; i++) {
3076                                         adapter->tx_ring[i].reg_idx = i << 5;
3077                                         adapter->rx_ring[i].reg_idx = i << 4;
3078                                 }
3079                                 for ( ; i < 5; i++) {
3080                                         adapter->tx_ring[i].reg_idx =
3081                                                                  ((i + 2) << 4);
3082                                         adapter->rx_ring[i].reg_idx = i << 4;
3083                                 }
3084                                 for ( ; i < dcb_i; i++) {
3085                                         adapter->tx_ring[i].reg_idx =
3086                                                                  ((i + 8) << 3);
3087                                         adapter->rx_ring[i].reg_idx = i << 4;
3088                                 }
3089
3090                                 ret = true;
3091                         } else if (dcb_i == 4) {
3092                                 /*
3093                                  * Tx TC0 starts at: descriptor queue 0
3094                                  * Tx TC1 starts at: descriptor queue 64
3095                                  * Tx TC2 starts at: descriptor queue 96
3096                                  * Tx TC3 starts at: descriptor queue 112
3097                                  *
3098                                  * Rx TC0-TC3 are offset by 32 queues each
3099                                  */
3100                                 adapter->tx_ring[0].reg_idx = 0;
3101                                 adapter->tx_ring[1].reg_idx = 64;
3102                                 adapter->tx_ring[2].reg_idx = 96;
3103                                 adapter->tx_ring[3].reg_idx = 112;
3104                                 for (i = 0 ; i < dcb_i; i++)
3105                                         adapter->rx_ring[i].reg_idx = i << 5;
3106
3107                                 ret = true;
3108                         } else {
3109                                 ret = false;
3110                         }
3111                 } else {
3112                         ret = false;
3113                 }
3114         } else {
3115                 ret = false;
3116         }
3117
3118         return ret;
3119 }
3120 #endif
3121
3122 #ifdef IXGBE_FCOE
3123 /**
3124  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3125  * @adapter: board private structure to initialize
3126  *
3127  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3128  *
3129  */
3130 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3131 {
3132         int i, fcoe_i = 0;
3133         bool ret = false;
3134         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3135
3136         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3137 #ifdef CONFIG_IXGBE_DCB
3138                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3139                         ixgbe_cache_ring_dcb(adapter);
3140                         fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3141                 }
3142 #endif /* CONFIG_IXGBE_DCB */
3143                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3144                         ixgbe_cache_ring_rss(adapter);
3145                         fcoe_i = f->mask;
3146                 }
3147                 for (i = 0; i < f->indices; i++, fcoe_i++)
3148                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3149                 ret = true;
3150         }
3151         return ret;
3152 }
3153
3154 #endif /* IXGBE_FCOE */
3155 /**
3156  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3157  * @adapter: board private structure to initialize
3158  *
3159  * Once we know the feature-set enabled for the device, we'll cache
3160  * the register offset the descriptor ring is assigned to.
3161  *
3162  * Note, the order the various feature calls is important.  It must start with
3163  * the "most" features enabled at the same time, then trickle down to the
3164  * least amount of features turned on at once.
3165  **/
3166 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3167 {
3168         /* start with default case */
3169         adapter->rx_ring[0].reg_idx = 0;
3170         adapter->tx_ring[0].reg_idx = 0;
3171
3172 #ifdef IXGBE_FCOE
3173         if (ixgbe_cache_ring_fcoe(adapter))
3174                 return;
3175
3176 #endif /* IXGBE_FCOE */
3177 #ifdef CONFIG_IXGBE_DCB
3178         if (ixgbe_cache_ring_dcb(adapter))
3179                 return;
3180
3181 #endif
3182         if (ixgbe_cache_ring_rss(adapter))
3183                 return;
3184 }
3185
3186 /**
3187  * ixgbe_alloc_queues - Allocate memory for all rings
3188  * @adapter: board private structure to initialize
3189  *
3190  * We allocate one ring per queue at run-time since we don't know the
3191  * number of queues at compile-time.  The polling_netdev array is
3192  * intended for Multiqueue, but should work fine with a single queue.
3193  **/
3194 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3195 {
3196         int i;
3197
3198         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3199                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3200         if (!adapter->tx_ring)
3201                 goto err_tx_ring_allocation;
3202
3203         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3204                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3205         if (!adapter->rx_ring)
3206                 goto err_rx_ring_allocation;
3207
3208         for (i = 0; i < adapter->num_tx_queues; i++) {
3209                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3210                 adapter->tx_ring[i].queue_index = i;
3211         }
3212
3213         for (i = 0; i < adapter->num_rx_queues; i++) {
3214                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3215                 adapter->rx_ring[i].queue_index = i;
3216         }
3217
3218         ixgbe_cache_ring_register(adapter);
3219
3220         return 0;
3221
3222 err_rx_ring_allocation:
3223         kfree(adapter->tx_ring);
3224 err_tx_ring_allocation:
3225         return -ENOMEM;
3226 }
3227
3228 /**
3229  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3230  * @adapter: board private structure to initialize
3231  *
3232  * Attempt to configure the interrupts using the best available
3233  * capabilities of the hardware and the kernel.
3234  **/
3235 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3236 {
3237         struct ixgbe_hw *hw = &adapter->hw;
3238         int err = 0;
3239         int vector, v_budget;
3240
3241         /*
3242          * It's easy to be greedy for MSI-X vectors, but it really
3243          * doesn't do us much good if we have a lot more vectors
3244          * than CPU's.  So let's be conservative and only ask for
3245          * (roughly) twice the number of vectors as there are CPU's.
3246          */
3247         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3248                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3249
3250         /*
3251          * At the same time, hardware can only support a maximum of
3252          * hw.mac->max_msix_vectors vectors.  With features
3253          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3254          * descriptor queues supported by our device.  Thus, we cap it off in
3255          * those rare cases where the cpu count also exceeds our vector limit.
3256          */
3257         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3258
3259         /* A failure in MSI-X entry allocation isn't fatal, but it does
3260          * mean we disable MSI-X capabilities of the adapter. */
3261         adapter->msix_entries = kcalloc(v_budget,
3262                                         sizeof(struct msix_entry), GFP_KERNEL);
3263         if (adapter->msix_entries) {
3264                 for (vector = 0; vector < v_budget; vector++)
3265                         adapter->msix_entries[vector].entry = vector;
3266
3267                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3268
3269                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3270                         goto out;
3271         }
3272
3273         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3274         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3275         ixgbe_set_num_queues(adapter);
3276
3277         err = pci_enable_msi(adapter->pdev);
3278         if (!err) {
3279                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3280         } else {
3281                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3282                         "falling back to legacy.  Error: %d\n", err);
3283                 /* reset err */
3284                 err = 0;
3285         }
3286
3287 out:
3288         return err;
3289 }
3290
3291 /**
3292  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3293  * @adapter: board private structure to initialize
3294  *
3295  * We allocate one q_vector per queue interrupt.  If allocation fails we
3296  * return -ENOMEM.
3297  **/
3298 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3299 {
3300         int q_idx, num_q_vectors;
3301         struct ixgbe_q_vector *q_vector;
3302         int napi_vectors;
3303         int (*poll)(struct napi_struct *, int);
3304
3305         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3306                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3307                 napi_vectors = adapter->num_rx_queues;
3308                 poll = &ixgbe_clean_rxonly;
3309         } else {
3310                 num_q_vectors = 1;
3311                 napi_vectors = 1;
3312                 poll = &ixgbe_poll;
3313         }
3314
3315         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3316                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3317                 if (!q_vector)
3318                         goto err_out;
3319                 q_vector->adapter = adapter;
3320                 q_vector->v_idx = q_idx;
3321                 q_vector->eitr = adapter->eitr_param;
3322                 if (q_idx < napi_vectors)
3323                         netif_napi_add(adapter->netdev, &q_vector->napi,
3324                                        (*poll), 64);
3325                 adapter->q_vector[q_idx] = q_vector;
3326         }
3327
3328         return 0;
3329
3330 err_out:
3331         while (q_idx) {
3332                 q_idx--;
3333                 q_vector = adapter->q_vector[q_idx];
3334                 netif_napi_del(&q_vector->napi);
3335                 kfree(q_vector);
3336                 adapter->q_vector[q_idx] = NULL;
3337         }
3338         return -ENOMEM;
3339 }
3340
3341 /**
3342  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3343  * @adapter: board private structure to initialize
3344  *
3345  * This function frees the memory allocated to the q_vectors.  In addition if
3346  * NAPI is enabled it will delete any references to the NAPI struct prior
3347  * to freeing the q_vector.
3348  **/
3349 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3350 {
3351         int q_idx, num_q_vectors;
3352         int napi_vectors;
3353
3354         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3355                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3356                 napi_vectors = adapter->num_rx_queues;
3357         } else {
3358                 num_q_vectors = 1;
3359                 napi_vectors = 1;
3360         }
3361
3362         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3363                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3364
3365                 adapter->q_vector[q_idx] = NULL;
3366                 if (q_idx < napi_vectors)
3367                         netif_napi_del(&q_vector->napi);
3368                 kfree(q_vector);
3369         }
3370 }
3371
3372 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3373 {
3374         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3375                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3376                 pci_disable_msix(adapter->pdev);
3377                 kfree(adapter->msix_entries);
3378                 adapter->msix_entries = NULL;
3379         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3380                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3381                 pci_disable_msi(adapter->pdev);
3382         }
3383         return;
3384 }
3385
3386 /**
3387  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3388  * @adapter: board private structure to initialize
3389  *
3390  * We determine which interrupt scheme to use based on...
3391  * - Kernel support (MSI, MSI-X)
3392  *   - which can be user-defined (via MODULE_PARAM)
3393  * - Hardware queue count (num_*_queues)
3394  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3395  **/
3396 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3397 {
3398         int err;
3399
3400         /* Number of supported queues */
3401         ixgbe_set_num_queues(adapter);
3402
3403         err = ixgbe_set_interrupt_capability(adapter);
3404         if (err) {
3405                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3406                 goto err_set_interrupt;
3407         }
3408
3409         err = ixgbe_alloc_q_vectors(adapter);
3410         if (err) {
3411                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3412                         "vectors\n");
3413                 goto err_alloc_q_vectors;
3414         }
3415
3416         err = ixgbe_alloc_queues(adapter);
3417         if (err) {
3418                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3419                 goto err_alloc_queues;
3420         }
3421
3422         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3423                 "Tx Queue count = %u\n",
3424                 (adapter->num_rx_queues > 1) ? "Enabled" :
3425                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3426
3427         set_bit(__IXGBE_DOWN, &adapter->state);
3428
3429         return 0;
3430
3431 err_alloc_queues:
3432         ixgbe_free_q_vectors(adapter);
3433 err_alloc_q_vectors:
3434         ixgbe_reset_interrupt_capability(adapter);
3435 err_set_interrupt:
3436         return err;
3437 }
3438
3439 /**
3440  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3441  * @adapter: board private structure to clear interrupt scheme on
3442  *
3443  * We go through and clear interrupt specific resources and reset the structure
3444  * to pre-load conditions
3445  **/
3446 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3447 {
3448         kfree(adapter->tx_ring);
3449         kfree(adapter->rx_ring);
3450         adapter->tx_ring = NULL;
3451         adapter->rx_ring = NULL;
3452
3453         ixgbe_free_q_vectors(adapter);
3454         ixgbe_reset_interrupt_capability(adapter);
3455 }
3456
3457 /**
3458  * ixgbe_sfp_timer - worker thread to find a missing module
3459  * @data: pointer to our adapter struct
3460  **/
3461 static void ixgbe_sfp_timer(unsigned long data)
3462 {
3463         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3464
3465         /*
3466          * Do the sfp_timer outside of interrupt context due to the
3467          * delays that sfp+ detection requires
3468          */
3469         schedule_work(&adapter->sfp_task);
3470 }
3471
3472 /**
3473  * ixgbe_sfp_task - worker thread to find a missing module
3474  * @work: pointer to work_struct containing our data
3475  **/
3476 static void ixgbe_sfp_task(struct work_struct *work)
3477 {
3478         struct ixgbe_adapter *adapter = container_of(work,
3479                                                      struct ixgbe_adapter,
3480                                                      sfp_task);
3481         struct ixgbe_hw *hw = &adapter->hw;
3482
3483         if ((hw->phy.type == ixgbe_phy_nl) &&
3484             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3485                 s32 ret = hw->phy.ops.identify_sfp(hw);
3486                 if (ret)
3487                         goto reschedule;
3488                 ret = hw->phy.ops.reset(hw);
3489                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3490                         DPRINTK(PROBE, ERR, "failed to initialize because an "
3491                                 "unsupported SFP+ module type was detected.\n"
3492                                 "Reload the driver after installing a "
3493                                 "supported module.\n");
3494                         unregister_netdev(adapter->netdev);
3495                 } else {
3496                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3497                                 hw->phy.sfp_type);
3498                 }
3499                 /* don't need this routine any more */
3500                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3501         }
3502         return;
3503 reschedule:
3504         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3505                 mod_timer(&adapter->sfp_timer,
3506                           round_jiffies(jiffies + (2 * HZ)));
3507 }
3508
3509 /**
3510  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3511  * @adapter: board private structure to initialize
3512  *
3513  * ixgbe_sw_init initializes the Adapter private data structure.
3514  * Fields are initialized based on PCI device information and
3515  * OS network device settings (MTU size).
3516  **/
3517 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3518 {
3519         struct ixgbe_hw *hw = &adapter->hw;
3520         struct pci_dev *pdev = adapter->pdev;
3521         unsigned int rss;
3522 #ifdef CONFIG_IXGBE_DCB
3523         int j;
3524         struct tc_configuration *tc;
3525 #endif
3526
3527         /* PCI config space info */
3528
3529         hw->vendor_id = pdev->vendor;
3530         hw->device_id = pdev->device;
3531         hw->revision_id = pdev->revision;
3532         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3533         hw->subsystem_device_id = pdev->subsystem_device;
3534
3535         /* Set capability flags */
3536         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3537         adapter->ring_feature[RING_F_RSS].indices = rss;
3538         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3539         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3540         if (hw->mac.type == ixgbe_mac_82598EB) {
3541                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3542                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3543                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3544         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3545                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3546                 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3547                 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3548 #ifdef IXGBE_FCOE
3549                 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
3550                 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
3551 #endif /* IXGBE_FCOE */
3552         }
3553
3554 #ifdef CONFIG_IXGBE_DCB
3555         /* Configure DCB traffic classes */
3556         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3557                 tc = &adapter->dcb_cfg.tc_config[j];
3558                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3559                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3560                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3561                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3562                 tc->dcb_pfc = pfc_disabled;
3563         }
3564         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3565         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3566         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3567         adapter->dcb_cfg.pfc_mode_enable = false;
3568         adapter->dcb_cfg.round_robin_enable = false;
3569         adapter->dcb_set_bitmap = 0x00;
3570         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3571                            adapter->ring_feature[RING_F_DCB].indices);
3572
3573 #endif
3574
3575         /* default flow control settings */
3576         hw->fc.requested_mode = ixgbe_fc_full;
3577         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3578 #ifdef CONFIG_DCB
3579         adapter->last_lfc_mode = hw->fc.current_mode;
3580 #endif
3581         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3582         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3583         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3584         hw->fc.send_xon = true;
3585         hw->fc.disable_fc_autoneg = false;
3586
3587         /* enable itr by default in dynamic mode */
3588         adapter->itr_setting = 1;
3589         adapter->eitr_param = 20000;
3590
3591         /* set defaults for eitr in MegaBytes */
3592         adapter->eitr_low = 10;
3593         adapter->eitr_high = 20;
3594
3595         /* set default ring sizes */
3596         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3597         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3598
3599         /* initialize eeprom parameters */
3600         if (ixgbe_init_eeprom_params_generic(hw)) {
3601                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3602                 return -EIO;
3603         }
3604
3605         /* enable rx csum by default */
3606         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3607
3608         set_bit(__IXGBE_DOWN, &adapter->state);
3609
3610         return 0;
3611 }
3612
3613 /**
3614  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3615  * @adapter: board private structure
3616  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3617  *
3618  * Return 0 on success, negative on failure
3619  **/
3620 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3621                              struct ixgbe_ring *tx_ring)
3622 {
3623         struct pci_dev *pdev = adapter->pdev;
3624         int size;
3625
3626         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3627         tx_ring->tx_buffer_info = vmalloc(size);
3628         if (!tx_ring->tx_buffer_info)
3629                 goto err;
3630         memset(tx_ring->tx_buffer_info, 0, size);
3631
3632         /* round up to nearest 4K */
3633         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3634         tx_ring->size = ALIGN(tx_ring->size, 4096);
3635
3636         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3637                                              &tx_ring->dma);
3638         if (!tx_ring->desc)
3639                 goto err;
3640
3641         tx_ring->next_to_use = 0;
3642         tx_ring->next_to_clean = 0;
3643         tx_ring->work_limit = tx_ring->count;
3644         return 0;
3645
3646 err:
3647         vfree(tx_ring->tx_buffer_info);
3648         tx_ring->tx_buffer_info = NULL;
3649         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3650                             "descriptor ring\n");
3651         return -ENOMEM;
3652 }
3653
3654 /**
3655  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3656  * @adapter: board private structure
3657  *
3658  * If this function returns with an error, then it's possible one or
3659  * more of the rings is populated (while the rest are not).  It is the
3660  * callers duty to clean those orphaned rings.
3661  *
3662  * Return 0 on success, negative on failure
3663  **/
3664 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3665 {
3666         int i, err = 0;
3667
3668         for (i = 0; i < adapter->num_tx_queues; i++) {
3669                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3670                 if (!err)
3671                         continue;
3672                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3673                 break;
3674         }
3675
3676         return err;
3677 }
3678
3679 /**
3680  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3681  * @adapter: board private structure
3682  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3683  *
3684  * Returns 0 on success, negative on failure
3685  **/
3686 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3687                              struct ixgbe_ring *rx_ring)
3688 {
3689         struct pci_dev *pdev = adapter->pdev;
3690         int size;
3691
3692         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3693         rx_ring->rx_buffer_info = vmalloc(size);
3694         if (!rx_ring->rx_buffer_info) {
3695                 DPRINTK(PROBE, ERR,
3696                         "vmalloc allocation failed for the rx desc ring\n");
3697                 goto alloc_failed;
3698         }
3699         memset(rx_ring->rx_buffer_info, 0, size);
3700
3701         /* Round up to nearest 4K */
3702         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3703         rx_ring->size = ALIGN(rx_ring->size, 4096);
3704
3705         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3706
3707         if (!rx_ring->desc) {
3708                 DPRINTK(PROBE, ERR,
3709                         "Memory allocation failed for the rx desc ring\n");
3710                 vfree(rx_ring->rx_buffer_info);
3711                 goto alloc_failed;
3712         }
3713
3714         rx_ring->next_to_clean = 0;
3715         rx_ring->next_to_use = 0;
3716
3717         return 0;
3718
3719 alloc_failed:
3720         return -ENOMEM;
3721 }
3722
3723 /**
3724  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3725  * @adapter: board private structure
3726  *
3727  * If this function returns with an error, then it's possible one or
3728  * more of the rings is populated (while the rest are not).  It is the
3729  * callers duty to clean those orphaned rings.
3730  *
3731  * Return 0 on success, negative on failure
3732  **/
3733
3734 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3735 {
3736         int i, err = 0;
3737
3738         for (i = 0; i < adapter->num_rx_queues; i++) {
3739                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3740                 if (!err)
3741                         continue;
3742                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3743                 break;
3744         }
3745
3746         return err;
3747 }
3748
3749 /**
3750  * ixgbe_free_tx_resources - Free Tx Resources per Queue
3751  * @adapter: board private structure
3752  * @tx_ring: Tx descriptor ring for a specific queue
3753  *
3754  * Free all transmit software resources
3755  **/
3756 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3757                              struct ixgbe_ring *tx_ring)
3758 {
3759         struct pci_dev *pdev = adapter->pdev;
3760
3761         ixgbe_clean_tx_ring(adapter, tx_ring);
3762
3763         vfree(tx_ring->tx_buffer_info);
3764         tx_ring->tx_buffer_info = NULL;
3765
3766         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3767
3768         tx_ring->desc = NULL;
3769 }
3770
3771 /**
3772  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3773  * @adapter: board private structure
3774  *
3775  * Free all transmit software resources
3776  **/
3777 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3778 {
3779         int i;
3780
3781         for (i = 0; i < adapter->num_tx_queues; i++)
3782                 if (adapter->tx_ring[i].desc)
3783                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3784 }
3785
3786 /**
3787  * ixgbe_free_rx_resources - Free Rx Resources
3788  * @adapter: board private structure
3789  * @rx_ring: ring to clean the resources from
3790  *
3791  * Free all receive software resources
3792  **/
3793 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3794                              struct ixgbe_ring *rx_ring)
3795 {
3796         struct pci_dev *pdev = adapter->pdev;
3797
3798         ixgbe_clean_rx_ring(adapter, rx_ring);
3799
3800         vfree(rx_ring->rx_buffer_info);
3801         rx_ring->rx_buffer_info = NULL;
3802
3803         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3804
3805         rx_ring->desc = NULL;
3806 }
3807
3808 /**
3809  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3810  * @adapter: board private structure
3811  *
3812  * Free all receive software resources
3813  **/
3814 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3815 {
3816         int i;
3817
3818         for (i = 0; i < adapter->num_rx_queues; i++)
3819                 if (adapter->rx_ring[i].desc)
3820                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3821 }
3822
3823 /**
3824  * ixgbe_change_mtu - Change the Maximum Transfer Unit
3825  * @netdev: network interface device structure
3826  * @new_mtu: new value for maximum frame size
3827  *
3828  * Returns 0 on success, negative on failure
3829  **/
3830 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3831 {
3832         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3833         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3834
3835         /* MTU < 68 is an error and causes problems on some kernels */
3836         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3837                 return -EINVAL;
3838
3839         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3840                 netdev->mtu, new_mtu);
3841         /* must set new MTU before calling down or up */
3842         netdev->mtu = new_mtu;
3843
3844         if (netif_running(netdev))
3845                 ixgbe_reinit_locked(adapter);
3846
3847         return 0;
3848 }
3849
3850 /**
3851  * ixgbe_open - Called when a network interface is made active
3852  * @netdev: network interface device structure
3853  *
3854  * Returns 0 on success, negative value on failure
3855  *
3856  * The open entry point is called when a network interface is made
3857  * active by the system (IFF_UP).  At this point all resources needed
3858  * for transmit and receive operations are allocated, the interrupt
3859  * handler is registered with the OS, the watchdog timer is started,
3860  * and the stack is notified that the interface is ready.
3861  **/
3862 static int ixgbe_open(struct net_device *netdev)
3863 {
3864         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3865         int err;
3866
3867         /* disallow open during test */
3868         if (test_bit(__IXGBE_TESTING, &adapter->state))
3869                 return -EBUSY;
3870
3871         netif_carrier_off(netdev);
3872
3873         /* allocate transmit descriptors */
3874         err = ixgbe_setup_all_tx_resources(adapter);
3875         if (err)
3876                 goto err_setup_tx;
3877
3878         /* allocate receive descriptors */
3879         err = ixgbe_setup_all_rx_resources(adapter);
3880         if (err)
3881                 goto err_setup_rx;
3882
3883         ixgbe_configure(adapter);
3884
3885         err = ixgbe_request_irq(adapter);
3886         if (err)
3887                 goto err_req_irq;
3888
3889         err = ixgbe_up_complete(adapter);
3890         if (err)
3891                 goto err_up;
3892
3893         netif_tx_start_all_queues(netdev);
3894
3895         return 0;
3896
3897 err_up:
3898         ixgbe_release_hw_control(adapter);
3899         ixgbe_free_irq(adapter);
3900 err_req_irq:
3901 err_setup_rx:
3902         ixgbe_free_all_rx_resources(adapter);
3903 err_setup_tx:
3904         ixgbe_free_all_tx_resources(adapter);
3905         ixgbe_reset(adapter);
3906
3907         return err;
3908 }
3909
3910 /**
3911  * ixgbe_close - Disables a network interface
3912  * @netdev: network interface device structure
3913  *
3914  * Returns 0, this is not allowed to fail
3915  *
3916  * The close entry point is called when an interface is de-activated
3917  * by the OS.  The hardware is still under the drivers control, but
3918  * needs to be disabled.  A global MAC reset is issued to stop the
3919  * hardware, and all transmit and receive resources are freed.
3920  **/
3921 static int ixgbe_close(struct net_device *netdev)
3922 {
3923         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3924
3925         ixgbe_down(adapter);
3926         ixgbe_free_irq(adapter);
3927
3928         ixgbe_free_all_tx_resources(adapter);
3929         ixgbe_free_all_rx_resources(adapter);
3930
3931         ixgbe_release_hw_control(adapter);
3932
3933         return 0;
3934 }
3935
3936 #ifdef CONFIG_PM
3937 static int ixgbe_resume(struct pci_dev *pdev)
3938 {
3939         struct net_device *netdev = pci_get_drvdata(pdev);
3940         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3941         u32 err;
3942
3943         pci_set_power_state(pdev, PCI_D0);
3944         pci_restore_state(pdev);
3945
3946         err = pci_enable_device_mem(pdev);
3947         if (err) {
3948                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3949                                 "suspend\n");
3950                 return err;
3951         }
3952         pci_set_master(pdev);
3953
3954         pci_wake_from_d3(pdev, false);
3955
3956         err = ixgbe_init_interrupt_scheme(adapter);
3957         if (err) {
3958                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3959                                 "device\n");
3960                 return err;
3961         }
3962
3963         ixgbe_reset(adapter);
3964
3965         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3966
3967         if (netif_running(netdev)) {
3968                 err = ixgbe_open(adapter->netdev);
3969                 if (err)
3970                         return err;
3971         }
3972
3973         netif_device_attach(netdev);
3974
3975         return 0;
3976 }
3977 #endif /* CONFIG_PM */
3978
3979 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
3980 {
3981         struct net_device *netdev = pci_get_drvdata(pdev);
3982         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3983         struct ixgbe_hw *hw = &adapter->hw;
3984         u32 ctrl, fctrl;
3985         u32 wufc = adapter->wol;
3986 #ifdef CONFIG_PM
3987         int retval = 0;
3988 #endif
3989
3990         netif_device_detach(netdev);
3991
3992         if (netif_running(netdev)) {
3993                 ixgbe_down(adapter);
3994                 ixgbe_free_irq(adapter);
3995                 ixgbe_free_all_tx_resources(adapter);
3996                 ixgbe_free_all_rx_resources(adapter);
3997         }
3998         ixgbe_clear_interrupt_scheme(adapter);
3999
4000 #ifdef CONFIG_PM
4001         retval = pci_save_state(pdev);
4002         if (retval)
4003                 return retval;
4004
4005 #endif
4006         if (wufc) {
4007                 ixgbe_set_rx_mode(netdev);
4008
4009                 /* turn on all-multi mode if wake on multicast is enabled */
4010                 if (wufc & IXGBE_WUFC_MC) {
4011                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4012                         fctrl |= IXGBE_FCTRL_MPE;
4013                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4014                 }
4015
4016                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4017                 ctrl |= IXGBE_CTRL_GIO_DIS;
4018                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4019
4020                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4021         } else {
4022                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4023                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4024         }
4025
4026         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4027                 pci_wake_from_d3(pdev, true);
4028         else
4029                 pci_wake_from_d3(pdev, false);
4030
4031         *enable_wake = !!wufc;
4032
4033         ixgbe_release_hw_control(adapter);
4034
4035         pci_disable_device(pdev);
4036
4037         return 0;
4038 }
4039
4040 #ifdef CONFIG_PM
4041 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4042 {
4043         int retval;
4044         bool wake;
4045
4046         retval = __ixgbe_shutdown(pdev, &wake);
4047         if (retval)
4048                 return retval;
4049
4050         if (wake) {
4051                 pci_prepare_to_sleep(pdev);
4052         } else {
4053                 pci_wake_from_d3(pdev, false);
4054                 pci_set_power_state(pdev, PCI_D3hot);
4055         }
4056
4057         return 0;
4058 }
4059 #endif /* CONFIG_PM */
4060
4061 static void ixgbe_shutdown(struct pci_dev *pdev)
4062 {
4063         bool wake;
4064
4065         __ixgbe_shutdown(pdev, &wake);
4066
4067         if (system_state == SYSTEM_POWER_OFF) {
4068                 pci_wake_from_d3(pdev, wake);
4069                 pci_set_power_state(pdev, PCI_D3hot);
4070         }
4071 }
4072
4073 /**
4074  * ixgbe_update_stats - Update the board statistics counters.
4075  * @adapter: board private structure
4076  **/
4077 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4078 {
4079         struct ixgbe_hw *hw = &adapter->hw;
4080         u64 total_mpc = 0;
4081         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4082
4083         if (hw->mac.type == ixgbe_mac_82599EB) {
4084                 u64 rsc_count = 0;
4085                 for (i = 0; i < 16; i++)
4086                         adapter->hw_rx_no_dma_resources +=
4087                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4088                 for (i = 0; i < adapter->num_rx_queues; i++)
4089                         rsc_count += adapter->rx_ring[i].rsc_count;
4090                 adapter->rsc_count = rsc_count;
4091         }
4092
4093         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4094         for (i = 0; i < 8; i++) {
4095                 /* for packet buffers not used, the register should read 0 */
4096                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4097                 missed_rx += mpc;
4098                 adapter->stats.mpc[i] += mpc;
4099                 total_mpc += adapter->stats.mpc[i];
4100                 if (hw->mac.type == ixgbe_mac_82598EB)
4101                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4102                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4103                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4104                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4105                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4106                 if (hw->mac.type == ixgbe_mac_82599EB) {
4107                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4108                                                             IXGBE_PXONRXCNT(i));
4109                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4110                                                            IXGBE_PXOFFRXCNT(i));
4111                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4112                 } else {
4113                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4114                                                               IXGBE_PXONRXC(i));
4115                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4116                                                              IXGBE_PXOFFRXC(i));
4117                 }
4118                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4119                                                             IXGBE_PXONTXC(i));
4120                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4121                                                              IXGBE_PXOFFTXC(i));
4122         }
4123         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4124         /* work around hardware counting issue */
4125         adapter->stats.gprc -= missed_rx;
4126
4127         /* 82598 hardware only has a 32 bit counter in the high register */
4128         if (hw->mac.type == ixgbe_mac_82599EB) {
4129                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4130                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4131                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4132                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4133                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4134                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4135                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4136                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4137 #ifdef IXGBE_FCOE
4138                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4139                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4140                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4141                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4142                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4143                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4144 #endif /* IXGBE_FCOE */
4145         } else {
4146                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4147                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4148                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4149                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4150                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4151         }
4152         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4153         adapter->stats.bprc += bprc;
4154         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4155         if (hw->mac.type == ixgbe_mac_82598EB)
4156                 adapter->stats.mprc -= bprc;
4157         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4158         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4159         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4160         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4161         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4162         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4163         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4164         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4165         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4166         adapter->stats.lxontxc += lxon;
4167         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4168         adapter->stats.lxofftxc += lxoff;
4169         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4170         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4171         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4172         /*
4173          * 82598 errata - tx of flow control packets is included in tx counters
4174          */
4175         xon_off_tot = lxon + lxoff;
4176         adapter->stats.gptc -= xon_off_tot;
4177         adapter->stats.mptc -= xon_off_tot;
4178         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4179         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4180         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4181         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4182         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4183         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4184         adapter->stats.ptc64 -= xon_off_tot;
4185         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4186         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4187         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4188         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4189         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4190         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4191
4192         /* Fill out the OS statistics structure */
4193         adapter->net_stats.multicast = adapter->stats.mprc;
4194
4195         /* Rx Errors */
4196         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4197                                        adapter->stats.rlec;
4198         adapter->net_stats.rx_dropped = 0;
4199         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4200         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4201         adapter->net_stats.rx_missed_errors = total_mpc;
4202 }
4203
4204 /**
4205  * ixgbe_watchdog - Timer Call-back
4206  * @data: pointer to adapter cast into an unsigned long
4207  **/
4208 static void ixgbe_watchdog(unsigned long data)
4209 {
4210         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4211         struct ixgbe_hw *hw = &adapter->hw;
4212
4213         /* Do the watchdog outside of interrupt context due to the lovely
4214          * delays that some of the newer hardware requires */
4215         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
4216                 u64 eics = 0;
4217                 int i;
4218
4219                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
4220                         eics |= ((u64)1 << i);
4221
4222                 /* Cause software interrupt to ensure rx rings are cleaned */
4223                 switch (hw->mac.type) {
4224                 case ixgbe_mac_82598EB:
4225                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4226                                 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4227                         } else {
4228                                 /*
4229                                  * for legacy and MSI interrupts don't set any
4230                                  * bits that are enabled for EIAM, because this
4231                                  * operation would set *both* EIMS and EICS for
4232                                  * any bit in EIAM
4233                                  */
4234                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4235                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4236                         }
4237                         break;
4238                 case ixgbe_mac_82599EB:
4239                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4240                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4241                                                 (u32)(eics & 0xFFFFFFFF));
4242                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
4243                                                 (u32)(eics >> 32));
4244                         } else {
4245                                 /*
4246                                  * for legacy and MSI interrupts don't set any
4247                                  * bits that are enabled for EIAM, because this
4248                                  * operation would set *both* EIMS and EICS for
4249                                  * any bit in EIAM
4250                                  */
4251                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4252                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4253                         }
4254                         break;
4255                 default:
4256                         break;
4257                 }
4258                 /* Reset the timer */
4259                 mod_timer(&adapter->watchdog_timer,
4260                           round_jiffies(jiffies + 2 * HZ));
4261         }
4262
4263         schedule_work(&adapter->watchdog_task);
4264 }
4265
4266 /**
4267  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4268  * @work: pointer to work_struct containing our data
4269  **/
4270 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4271 {
4272         struct ixgbe_adapter *adapter = container_of(work,
4273                                                      struct ixgbe_adapter,
4274                                                      multispeed_fiber_task);
4275         struct ixgbe_hw *hw = &adapter->hw;
4276         u32 autoneg;
4277
4278         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4279         if (hw->mac.ops.get_link_capabilities)
4280                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4281                                                   &hw->mac.autoneg);
4282         if (hw->mac.ops.setup_link_speed)
4283                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4284         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4285         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4286 }
4287
4288 /**
4289  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4290  * @work: pointer to work_struct containing our data
4291  **/
4292 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4293 {
4294         struct ixgbe_adapter *adapter = container_of(work,
4295                                                      struct ixgbe_adapter,
4296                                                      sfp_config_module_task);
4297         struct ixgbe_hw *hw = &adapter->hw;
4298         u32 err;
4299
4300         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4301         err = hw->phy.ops.identify_sfp(hw);
4302         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4303                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4304                 ixgbe_down(adapter);
4305                 return;
4306         }
4307         hw->mac.ops.setup_sfp(hw);
4308
4309         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4310                 /* This will also work for DA Twinax connections */
4311                 schedule_work(&adapter->multispeed_fiber_task);
4312         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4313 }
4314
4315 /**
4316  * ixgbe_watchdog_task - worker thread to bring link up
4317  * @work: pointer to work_struct containing our data
4318  **/
4319 static void ixgbe_watchdog_task(struct work_struct *work)
4320 {
4321         struct ixgbe_adapter *adapter = container_of(work,
4322                                                      struct ixgbe_adapter,
4323                                                      watchdog_task);
4324         struct net_device *netdev = adapter->netdev;
4325         struct ixgbe_hw *hw = &adapter->hw;
4326         u32 link_speed = adapter->link_speed;
4327         bool link_up = adapter->link_up;
4328         int i;
4329         struct ixgbe_ring *tx_ring;
4330         int some_tx_pending = 0;
4331
4332         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4333
4334         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4335                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4336                 if (link_up) {
4337 #ifdef CONFIG_DCB
4338                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4339                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4340                                         hw->mac.ops.setup_fc(hw, i);
4341                         } else {
4342                                 hw->mac.ops.setup_fc(hw, 0);
4343                         }
4344 #else
4345                         hw->mac.ops.setup_fc(hw, 0);
4346 #endif
4347                 }
4348
4349                 if (link_up ||
4350                     time_after(jiffies, (adapter->link_check_timeout +
4351                                          IXGBE_TRY_LINK_TIMEOUT))) {
4352                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4353                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4354                 }
4355                 adapter->link_up = link_up;
4356                 adapter->link_speed = link_speed;
4357         }
4358
4359         if (link_up) {
4360                 if (!netif_carrier_ok(netdev)) {
4361                         bool flow_rx, flow_tx;
4362
4363                         if (hw->mac.type == ixgbe_mac_82599EB) {
4364                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4365                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4366                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4367                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4368                         } else {
4369                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4370                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4371                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4372                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4373                         }
4374
4375                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4376                                "Flow Control: %s\n",
4377                                netdev->name,
4378                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4379                                 "10 Gbps" :
4380                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4381                                  "1 Gbps" : "unknown speed")),
4382                                ((flow_rx && flow_tx) ? "RX/TX" :
4383                                 (flow_rx ? "RX" :
4384                                 (flow_tx ? "TX" : "None"))));
4385
4386                         netif_carrier_on(netdev);
4387                 } else {
4388                         /* Force detection of hung controller */
4389                         adapter->detect_tx_hung = true;
4390                 }
4391         } else {
4392                 adapter->link_up = false;
4393                 adapter->link_speed = 0;
4394                 if (netif_carrier_ok(netdev)) {
4395                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4396                                netdev->name);
4397                         netif_carrier_off(netdev);
4398                 }
4399         }
4400
4401         if (!netif_carrier_ok(netdev)) {
4402                 for (i = 0; i < adapter->num_tx_queues; i++) {
4403                         tx_ring = &adapter->tx_ring[i];
4404                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4405                                 some_tx_pending = 1;
4406                                 break;
4407                         }
4408                 }
4409
4410                 if (some_tx_pending) {
4411                         /* We've lost link, so the controller stops DMA,
4412                          * but we've got queued Tx work that's never going
4413                          * to get done, so reset controller to flush Tx.
4414                          * (Do the reset outside of interrupt context).
4415                          */
4416                          schedule_work(&adapter->reset_task);
4417                 }
4418         }
4419
4420         ixgbe_update_stats(adapter);
4421         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4422 }
4423
4424 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4425                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4426                      u32 tx_flags, u8 *hdr_len)
4427 {
4428         struct ixgbe_adv_tx_context_desc *context_desc;
4429         unsigned int i;
4430         int err;
4431         struct ixgbe_tx_buffer *tx_buffer_info;
4432         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4433         u32 mss_l4len_idx, l4len;
4434
4435         if (skb_is_gso(skb)) {
4436                 if (skb_header_cloned(skb)) {
4437                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4438                         if (err)
4439                                 return err;
4440                 }
4441                 l4len = tcp_hdrlen(skb);
4442                 *hdr_len += l4len;
4443
4444                 if (skb->protocol == htons(ETH_P_IP)) {
4445                         struct iphdr *iph = ip_hdr(skb);
4446                         iph->tot_len = 0;
4447                         iph->check = 0;
4448                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4449                                                                  iph->daddr, 0,
4450                                                                  IPPROTO_TCP,
4451                                                                  0);
4452                         adapter->hw_tso_ctxt++;
4453                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4454                         ipv6_hdr(skb)->payload_len = 0;
4455                         tcp_hdr(skb)->check =
4456                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4457                                              &ipv6_hdr(skb)->daddr,
4458                                              0, IPPROTO_TCP, 0);
4459                         adapter->hw_tso6_ctxt++;
4460                 }
4461
4462                 i = tx_ring->next_to_use;
4463
4464                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4465                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4466
4467                 /* VLAN MACLEN IPLEN */
4468                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4469                         vlan_macip_lens |=
4470                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4471                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4472                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4473                 *hdr_len += skb_network_offset(skb);
4474                 vlan_macip_lens |=
4475                     (skb_transport_header(skb) - skb_network_header(skb));
4476                 *hdr_len +=
4477                     (skb_transport_header(skb) - skb_network_header(skb));
4478                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4479                 context_desc->seqnum_seed = 0;
4480
4481                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4482                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4483                                    IXGBE_ADVTXD_DTYP_CTXT);
4484
4485                 if (skb->protocol == htons(ETH_P_IP))
4486                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4487                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4488                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4489
4490                 /* MSS L4LEN IDX */
4491                 mss_l4len_idx =
4492                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4493                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4494                 /* use index 1 for TSO */
4495                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4496                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4497
4498                 tx_buffer_info->time_stamp = jiffies;
4499                 tx_buffer_info->next_to_watch = i;
4500
4501                 i++;
4502                 if (i == tx_ring->count)
4503                         i = 0;
4504                 tx_ring->next_to_use = i;
4505
4506                 return true;
4507         }
4508         return false;
4509 }
4510
4511 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4512                           struct ixgbe_ring *tx_ring,
4513                           struct sk_buff *skb, u32 tx_flags)
4514 {
4515         struct ixgbe_adv_tx_context_desc *context_desc;
4516         unsigned int i;
4517         struct ixgbe_tx_buffer *tx_buffer_info;
4518         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4519
4520         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4521             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4522                 i = tx_ring->next_to_use;
4523                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4524                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4525
4526                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4527                         vlan_macip_lens |=
4528                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4529                 vlan_macip_lens |= (skb_network_offset(skb) <<
4530                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4531                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4532                         vlan_macip_lens |= (skb_transport_header(skb) -
4533                                             skb_network_header(skb));
4534
4535                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4536                 context_desc->seqnum_seed = 0;
4537
4538                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4539                                     IXGBE_ADVTXD_DTYP_CTXT);
4540
4541                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4542                         switch (skb->protocol) {
4543                         case cpu_to_be16(ETH_P_IP):
4544                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4545                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4546                                         type_tucmd_mlhl |=
4547                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4548                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4549                                         type_tucmd_mlhl |=
4550                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4551                                 break;
4552                         case cpu_to_be16(ETH_P_IPV6):
4553                                 /* XXX what about other V6 headers?? */
4554                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4555                                         type_tucmd_mlhl |=
4556                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4557                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4558                                         type_tucmd_mlhl |=
4559                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4560                                 break;
4561                         default:
4562                                 if (unlikely(net_ratelimit())) {
4563                                         DPRINTK(PROBE, WARNING,
4564                                          "partial checksum but proto=%x!\n",
4565                                          skb->protocol);
4566                                 }
4567                                 break;
4568                         }
4569                 }
4570
4571                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4572                 /* use index zero for tx checksum offload */
4573                 context_desc->mss_l4len_idx = 0;
4574
4575                 tx_buffer_info->time_stamp = jiffies;
4576                 tx_buffer_info->next_to_watch = i;
4577
4578                 adapter->hw_csum_tx_good++;
4579                 i++;
4580                 if (i == tx_ring->count)
4581                         i = 0;
4582                 tx_ring->next_to_use = i;
4583
4584                 return true;
4585         }
4586
4587         return false;
4588 }
4589
4590 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4591                         struct ixgbe_ring *tx_ring,
4592                         struct sk_buff *skb, u32 tx_flags,
4593                         unsigned int first)
4594 {
4595         struct ixgbe_tx_buffer *tx_buffer_info;
4596         unsigned int len;
4597         unsigned int total = skb->len;
4598         unsigned int offset = 0, size, count = 0, i;
4599         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4600         unsigned int f;
4601         dma_addr_t *map;
4602
4603         i = tx_ring->next_to_use;
4604
4605         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4606                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4607                 return 0;
4608         }
4609
4610         map = skb_shinfo(skb)->dma_maps;
4611
4612         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4613                 /* excluding fcoe_crc_eof for FCoE */
4614                 total -= sizeof(struct fcoe_crc_eof);
4615
4616         len = min(skb_headlen(skb), total);
4617         while (len) {
4618                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4619                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4620
4621                 tx_buffer_info->length = size;
4622                 tx_buffer_info->dma = map[0] + offset;
4623                 tx_buffer_info->time_stamp = jiffies;
4624                 tx_buffer_info->next_to_watch = i;
4625
4626                 len -= size;
4627                 total -= size;
4628                 offset += size;
4629                 count++;
4630
4631                 if (len) {
4632                         i++;
4633                         if (i == tx_ring->count)
4634                                 i = 0;
4635                 }
4636         }
4637
4638         for (f = 0; f < nr_frags; f++) {
4639                 struct skb_frag_struct *frag;
4640
4641                 frag = &skb_shinfo(skb)->frags[f];
4642                 len = min((unsigned int)frag->size, total);
4643                 offset = 0;
4644
4645                 while (len) {
4646                         i++;
4647                         if (i == tx_ring->count)
4648                                 i = 0;
4649
4650                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4651                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4652
4653                         tx_buffer_info->length = size;
4654                         tx_buffer_info->dma = map[f + 1] + offset;
4655                         tx_buffer_info->time_stamp = jiffies;
4656                         tx_buffer_info->next_to_watch = i;
4657
4658                         len -= size;
4659                         total -= size;
4660                         offset += size;
4661                         count++;
4662                 }
4663                 if (total == 0)
4664                         break;
4665         }
4666
4667         tx_ring->tx_buffer_info[i].skb = skb;
4668         tx_ring->tx_buffer_info[first].next_to_watch = i;
4669
4670         return count;
4671 }
4672
4673 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4674                            struct ixgbe_ring *tx_ring,
4675                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4676 {
4677         union ixgbe_adv_tx_desc *tx_desc = NULL;
4678         struct ixgbe_tx_buffer *tx_buffer_info;
4679         u32 olinfo_status = 0, cmd_type_len = 0;
4680         unsigned int i;
4681         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4682
4683         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4684
4685         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4686
4687         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4688                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4689
4690         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4691                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4692
4693                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4694                                  IXGBE_ADVTXD_POPTS_SHIFT;
4695
4696                 /* use index 1 context for tso */
4697                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4698                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4699                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4700                                          IXGBE_ADVTXD_POPTS_SHIFT;
4701
4702         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4703                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4704                                  IXGBE_ADVTXD_POPTS_SHIFT;
4705
4706         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4707                 olinfo_status |= IXGBE_ADVTXD_CC;
4708                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4709                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4710                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4711         }
4712
4713         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4714
4715         i = tx_ring->next_to_use;
4716         while (count--) {
4717                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4718                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4719                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4720                 tx_desc->read.cmd_type_len =
4721                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4722                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4723                 i++;
4724                 if (i == tx_ring->count)
4725                         i = 0;
4726         }
4727
4728         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4729
4730         /*
4731          * Force memory writes to complete before letting h/w
4732          * know there are new descriptors to fetch.  (Only
4733          * applicable for weak-ordered memory model archs,
4734          * such as IA-64).
4735          */
4736         wmb();
4737
4738         tx_ring->next_to_use = i;
4739         writel(i, adapter->hw.hw_addr + tx_ring->tail);
4740 }
4741
4742 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4743                                  struct ixgbe_ring *tx_ring, int size)
4744 {
4745         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4746
4747         netif_stop_subqueue(netdev, tx_ring->queue_index);
4748         /* Herbert's original patch had:
4749          *  smp_mb__after_netif_stop_queue();
4750          * but since that doesn't exist yet, just open code it. */
4751         smp_mb();
4752
4753         /* We need to check again in a case another CPU has just
4754          * made room available. */
4755         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4756                 return -EBUSY;
4757
4758         /* A reprieve! - use start_queue because it doesn't call schedule */
4759         netif_start_subqueue(netdev, tx_ring->queue_index);
4760         ++adapter->restart_queue;
4761         return 0;
4762 }
4763
4764 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4765                               struct ixgbe_ring *tx_ring, int size)
4766 {
4767         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4768                 return 0;
4769         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4770 }
4771
4772 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4773 {
4774         struct ixgbe_adapter *adapter = netdev_priv(dev);
4775
4776         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4777                 return 0;  /* All traffic should default to class 0 */
4778
4779         return skb_tx_hash(dev, skb);
4780 }
4781
4782 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4783 {
4784         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4785         struct ixgbe_ring *tx_ring;
4786         unsigned int first;
4787         unsigned int tx_flags = 0;
4788         u8 hdr_len = 0;
4789         int r_idx = 0, tso;
4790         int count = 0;
4791         unsigned int f;
4792
4793         r_idx = skb->queue_mapping;
4794         tx_ring = &adapter->tx_ring[r_idx];
4795
4796         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4797                 tx_flags |= vlan_tx_tag_get(skb);
4798                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4799                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4800                         tx_flags |= (skb->queue_mapping << 13);
4801                 }
4802                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4803                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4804         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4805                 tx_flags |= (skb->queue_mapping << 13);
4806                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4807                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4808         }
4809
4810         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4811             (skb->protocol == htons(ETH_P_FCOE)))
4812                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
4813
4814         /* four things can cause us to need a context descriptor */
4815         if (skb_is_gso(skb) ||
4816             (skb->ip_summed == CHECKSUM_PARTIAL) ||
4817             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
4818             (tx_flags & IXGBE_TX_FLAGS_FCOE))
4819                 count++;
4820
4821         count += TXD_USE_COUNT(skb_headlen(skb));
4822         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4823                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4824
4825         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4826                 adapter->tx_busy++;
4827                 return NETDEV_TX_BUSY;
4828         }
4829
4830         first = tx_ring->next_to_use;
4831         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4832 #ifdef IXGBE_FCOE
4833                 /* setup tx offload for FCoE */
4834                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4835                 if (tso < 0) {
4836                         dev_kfree_skb_any(skb);
4837                         return NETDEV_TX_OK;
4838                 }
4839                 if (tso)
4840                         tx_flags |= IXGBE_TX_FLAGS_FSO;
4841 #endif /* IXGBE_FCOE */
4842         } else {
4843                 if (skb->protocol == htons(ETH_P_IP))
4844                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
4845                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4846                 if (tso < 0) {
4847                         dev_kfree_skb_any(skb);
4848                         return NETDEV_TX_OK;
4849                 }
4850
4851                 if (tso)
4852                         tx_flags |= IXGBE_TX_FLAGS_TSO;
4853                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4854                          (skb->ip_summed == CHECKSUM_PARTIAL))
4855                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
4856         }
4857
4858         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
4859         if (count) {
4860                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4861                                hdr_len);
4862                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4863
4864         } else {
4865                 dev_kfree_skb_any(skb);
4866                 tx_ring->tx_buffer_info[first].time_stamp = 0;
4867                 tx_ring->next_to_use = first;
4868         }
4869
4870         return NETDEV_TX_OK;
4871 }
4872
4873 /**
4874  * ixgbe_get_stats - Get System Network Statistics
4875  * @netdev: network interface device structure
4876  *
4877  * Returns the address of the device statistics structure.
4878  * The statistics are actually updated from the timer callback.
4879  **/
4880 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4881 {
4882         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4883
4884         /* only return the current stats */
4885         return &adapter->net_stats;
4886 }
4887
4888 /**
4889  * ixgbe_set_mac - Change the Ethernet Address of the NIC
4890  * @netdev: network interface device structure
4891  * @p: pointer to an address structure
4892  *
4893  * Returns 0 on success, negative on failure
4894  **/
4895 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4896 {
4897         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4898         struct ixgbe_hw *hw = &adapter->hw;
4899         struct sockaddr *addr = p;
4900
4901         if (!is_valid_ether_addr(addr->sa_data))
4902                 return -EADDRNOTAVAIL;
4903
4904         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4905         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4906
4907         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4908
4909         return 0;
4910 }
4911
4912 static int
4913 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4914 {
4915         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4916         struct ixgbe_hw *hw = &adapter->hw;
4917         u16 value;
4918         int rc;
4919
4920         if (prtad != hw->phy.mdio.prtad)
4921                 return -EINVAL;
4922         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4923         if (!rc)
4924                 rc = value;
4925         return rc;
4926 }
4927
4928 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4929                             u16 addr, u16 value)
4930 {
4931         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4932         struct ixgbe_hw *hw = &adapter->hw;
4933
4934         if (prtad != hw->phy.mdio.prtad)
4935                 return -EINVAL;
4936         return hw->phy.ops.write_reg(hw, addr, devad, value);
4937 }
4938
4939 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4940 {
4941         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4942
4943         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4944 }
4945
4946 /**
4947  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
4948  * netdev->dev_addr_list
4949  * @netdev: network interface device structure
4950  *
4951  * Returns non-zero on failure
4952  **/
4953 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
4954 {
4955         int err = 0;
4956         struct ixgbe_adapter *adapter = netdev_priv(dev);
4957         struct ixgbe_mac_info *mac = &adapter->hw.mac;
4958
4959         if (is_valid_ether_addr(mac->san_addr)) {
4960                 rtnl_lock();
4961                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4962                 rtnl_unlock();
4963         }
4964         return err;
4965 }
4966
4967 /**
4968  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
4969  * netdev->dev_addr_list
4970  * @netdev: network interface device structure
4971  *
4972  * Returns non-zero on failure
4973  **/
4974 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
4975 {
4976         int err = 0;
4977         struct ixgbe_adapter *adapter = netdev_priv(dev);
4978         struct ixgbe_mac_info *mac = &adapter->hw.mac;
4979
4980         if (is_valid_ether_addr(mac->san_addr)) {
4981                 rtnl_lock();
4982                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4983                 rtnl_unlock();
4984         }
4985         return err;
4986 }
4987
4988 #ifdef CONFIG_NET_POLL_CONTROLLER
4989 /*
4990  * Polling 'interrupt' - used by things like netconsole to send skbs
4991  * without having to re-enable interrupts. It's not called while
4992  * the interrupt routine is executing.
4993  */
4994 static void ixgbe_netpoll(struct net_device *netdev)
4995 {
4996         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4997
4998         disable_irq(adapter->pdev->irq);
4999         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5000         ixgbe_intr(adapter->pdev->irq, netdev);
5001         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5002         enable_irq(adapter->pdev->irq);
5003 }
5004 #endif
5005
5006 static const struct net_device_ops ixgbe_netdev_ops = {
5007         .ndo_open               = ixgbe_open,
5008         .ndo_stop               = ixgbe_close,
5009         .ndo_start_xmit         = ixgbe_xmit_frame,
5010         .ndo_select_queue       = ixgbe_select_queue,
5011         .ndo_get_stats          = ixgbe_get_stats,
5012         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5013         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5014         .ndo_validate_addr      = eth_validate_addr,
5015         .ndo_set_mac_address    = ixgbe_set_mac,
5016         .ndo_change_mtu         = ixgbe_change_mtu,
5017         .ndo_tx_timeout         = ixgbe_tx_timeout,
5018         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5019         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5020         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5021         .ndo_do_ioctl           = ixgbe_ioctl,
5022 #ifdef CONFIG_NET_POLL_CONTROLLER
5023         .ndo_poll_controller    = ixgbe_netpoll,
5024 #endif
5025 #ifdef IXGBE_FCOE
5026         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5027         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5028 #endif /* IXGBE_FCOE */
5029 };
5030
5031 /**
5032  * ixgbe_probe - Device Initialization Routine
5033  * @pdev: PCI device information struct
5034  * @ent: entry in ixgbe_pci_tbl
5035  *
5036  * Returns 0 on success, negative on failure
5037  *
5038  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5039  * The OS initialization, configuring of the adapter private structure,
5040  * and a hardware reset occur.
5041  **/
5042 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5043                                  const struct pci_device_id *ent)
5044 {
5045         struct net_device *netdev;
5046         struct ixgbe_adapter *adapter = NULL;
5047         struct ixgbe_hw *hw;
5048         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5049         static int cards_found;
5050         int i, err, pci_using_dac;
5051 #ifdef IXGBE_FCOE
5052         u16 device_caps;
5053 #endif
5054         u32 part_num, eec;
5055
5056         err = pci_enable_device_mem(pdev);
5057         if (err)
5058                 return err;
5059
5060         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5061             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5062                 pci_using_dac = 1;
5063         } else {
5064                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5065                 if (err) {
5066                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5067                         if (err) {
5068                                 dev_err(&pdev->dev, "No usable DMA "
5069                                         "configuration, aborting\n");
5070                                 goto err_dma;
5071                         }
5072                 }
5073                 pci_using_dac = 0;
5074         }
5075
5076         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5077                                            IORESOURCE_MEM), ixgbe_driver_name);
5078         if (err) {
5079                 dev_err(&pdev->dev,
5080                         "pci_request_selected_regions failed 0x%x\n", err);
5081                 goto err_pci_reg;
5082         }
5083
5084         err = pci_enable_pcie_error_reporting(pdev);
5085         if (err) {
5086                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5087                                     "0x%x\n", err);
5088                 /* non-fatal, continue */
5089         }
5090
5091         pci_set_master(pdev);
5092         pci_save_state(pdev);
5093
5094         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5095         if (!netdev) {
5096                 err = -ENOMEM;
5097                 goto err_alloc_etherdev;
5098         }
5099
5100         SET_NETDEV_DEV(netdev, &pdev->dev);
5101
5102         pci_set_drvdata(pdev, netdev);
5103         adapter = netdev_priv(netdev);
5104
5105         adapter->netdev = netdev;
5106         adapter->pdev = pdev;
5107         hw = &adapter->hw;
5108         hw->back = adapter;
5109         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5110
5111         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5112                               pci_resource_len(pdev, 0));
5113         if (!hw->hw_addr) {
5114                 err = -EIO;
5115                 goto err_ioremap;
5116         }
5117
5118         for (i = 1; i <= 5; i++) {
5119                 if (pci_resource_len(pdev, i) == 0)
5120                         continue;
5121         }
5122
5123         netdev->netdev_ops = &ixgbe_netdev_ops;
5124         ixgbe_set_ethtool_ops(netdev);
5125         netdev->watchdog_timeo = 5 * HZ;
5126         strcpy(netdev->name, pci_name(pdev));
5127
5128         adapter->bd_number = cards_found;
5129
5130         /* Setup hw api */
5131         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5132         hw->mac.type  = ii->mac;
5133
5134         /* EEPROM */
5135         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5136         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5137         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5138         if (!(eec & (1 << 8)))
5139                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5140
5141         /* PHY */
5142         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5143         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5144         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5145         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5146         hw->phy.mdio.mmds = 0;
5147         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5148         hw->phy.mdio.dev = netdev;
5149         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5150         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5151
5152         /* set up this timer and work struct before calling get_invariants
5153          * which might start the timer
5154          */
5155         init_timer(&adapter->sfp_timer);
5156         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5157         adapter->sfp_timer.data = (unsigned long) adapter;
5158
5159         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5160
5161         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5162         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5163
5164         /* a new SFP+ module arrival, called from GPI SDP2 context */
5165         INIT_WORK(&adapter->sfp_config_module_task,
5166                   ixgbe_sfp_config_module_task);
5167
5168         ii->get_invariants(hw);
5169
5170         /* setup the private structure */
5171         err = ixgbe_sw_init(adapter);
5172         if (err)
5173                 goto err_sw_init;
5174
5175         /*
5176          * If there is a fan on this device and it has failed log the
5177          * failure.
5178          */
5179         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5180                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5181                 if (esdp & IXGBE_ESDP_SDP1)
5182                         DPRINTK(PROBE, CRIT,
5183                                 "Fan has stopped, replace the adapter\n");
5184         }
5185
5186         /* reset_hw fills in the perm_addr as well */
5187         err = hw->mac.ops.reset_hw(hw);
5188         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5189             hw->mac.type == ixgbe_mac_82598EB) {
5190                 /*
5191                  * Start a kernel thread to watch for a module to arrive.
5192                  * Only do this for 82598, since 82599 will generate
5193                  * interrupts on module arrival.
5194                  */
5195                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5196                 mod_timer(&adapter->sfp_timer,
5197                           round_jiffies(jiffies + (2 * HZ)));
5198                 err = 0;
5199         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5200                 dev_err(&adapter->pdev->dev, "failed to load because an "
5201                         "unsupported SFP+ module type was detected.\n");
5202                 goto err_sw_init;
5203         } else if (err) {
5204                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5205                 goto err_sw_init;
5206         }
5207
5208         netdev->features = NETIF_F_SG |
5209                            NETIF_F_IP_CSUM |
5210                            NETIF_F_HW_VLAN_TX |
5211                            NETIF_F_HW_VLAN_RX |
5212                            NETIF_F_HW_VLAN_FILTER;
5213
5214         netdev->features |= NETIF_F_IPV6_CSUM;
5215         netdev->features |= NETIF_F_TSO;
5216         netdev->features |= NETIF_F_TSO6;
5217         netdev->features |= NETIF_F_GRO;
5218
5219         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5220                 netdev->features |= NETIF_F_SCTP_CSUM;
5221
5222         netdev->vlan_features |= NETIF_F_TSO;
5223         netdev->vlan_features |= NETIF_F_TSO6;
5224         netdev->vlan_features |= NETIF_F_IP_CSUM;
5225         netdev->vlan_features |= NETIF_F_SG;
5226
5227         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5228                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5229
5230 #ifdef CONFIG_IXGBE_DCB
5231         netdev->dcbnl_ops = &dcbnl_ops;
5232 #endif
5233
5234 #ifdef IXGBE_FCOE
5235         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5236                 if (hw->mac.ops.get_device_caps) {
5237                         hw->mac.ops.get_device_caps(hw, &device_caps);
5238                         if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5239                                 netdev->features |= NETIF_F_FCOE_CRC;
5240                                 netdev->features |= NETIF_F_FSO;
5241                                 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
5242                         } else {
5243                                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5244                         }
5245                 }
5246         }
5247 #endif /* IXGBE_FCOE */
5248         if (pci_using_dac)
5249                 netdev->features |= NETIF_F_HIGHDMA;
5250
5251         if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
5252                 netdev->features |= NETIF_F_LRO;
5253
5254         /* make sure the EEPROM is good */
5255         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5256                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5257                 err = -EIO;
5258                 goto err_eeprom;
5259         }
5260
5261         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5262         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5263
5264         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5265                 dev_err(&pdev->dev, "invalid MAC address\n");
5266                 err = -EIO;
5267                 goto err_eeprom;
5268         }
5269
5270         init_timer(&adapter->watchdog_timer);
5271         adapter->watchdog_timer.function = &ixgbe_watchdog;
5272         adapter->watchdog_timer.data = (unsigned long)adapter;
5273
5274         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5275         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5276
5277         err = ixgbe_init_interrupt_scheme(adapter);
5278         if (err)
5279                 goto err_sw_init;
5280
5281         switch (pdev->device) {
5282         case IXGBE_DEV_ID_82599_KX4:
5283                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5284                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5285                 break;
5286         default:
5287                 adapter->wol = 0;
5288                 break;
5289         }
5290         device_init_wakeup(&adapter->pdev->dev, true);
5291         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5292
5293         /* pick up the PCI bus settings for reporting later */
5294         hw->mac.ops.get_bus_info(hw);
5295
5296         /* print bus type/speed/width info */
5297         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5298                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5299                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5300                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5301                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5302                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5303                  "Unknown"),
5304                 netdev->dev_addr);
5305         ixgbe_read_pba_num_generic(hw, &part_num);
5306         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5307                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5308                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5309                          (part_num >> 8), (part_num & 0xff));
5310         else
5311                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5312                          hw->mac.type, hw->phy.type,
5313                          (part_num >> 8), (part_num & 0xff));
5314
5315         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5316                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5317                          "this card is not sufficient for optimal "
5318                          "performance.\n");
5319                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5320                          "PCI-Express slot is required.\n");
5321         }
5322
5323         /* save off EEPROM version number */
5324         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5325
5326         /* reset the hardware with the new settings */
5327         hw->mac.ops.start_hw(hw);
5328
5329         strcpy(netdev->name, "eth%d");
5330         err = register_netdev(netdev);
5331         if (err)
5332                 goto err_register;
5333
5334         /* carrier off reporting is important to ethtool even BEFORE open */
5335         netif_carrier_off(netdev);
5336
5337 #ifdef CONFIG_IXGBE_DCA
5338         if (dca_add_requester(&pdev->dev) == 0) {
5339                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5340                 ixgbe_setup_dca(adapter);
5341         }
5342 #endif
5343         /* add san mac addr to netdev */
5344         ixgbe_add_sanmac_netdev(netdev);
5345
5346         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5347         cards_found++;
5348         return 0;
5349
5350 err_register:
5351         ixgbe_release_hw_control(adapter);
5352         ixgbe_clear_interrupt_scheme(adapter);
5353 err_sw_init:
5354 err_eeprom:
5355         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5356         del_timer_sync(&adapter->sfp_timer);
5357         cancel_work_sync(&adapter->sfp_task);
5358         cancel_work_sync(&adapter->multispeed_fiber_task);
5359         cancel_work_sync(&adapter->sfp_config_module_task);
5360         iounmap(hw->hw_addr);
5361 err_ioremap:
5362         free_netdev(netdev);
5363 err_alloc_etherdev:
5364         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5365                                      IORESOURCE_MEM));
5366 err_pci_reg:
5367 err_dma:
5368         pci_disable_device(pdev);
5369         return err;
5370 }
5371
5372 /**
5373  * ixgbe_remove - Device Removal Routine
5374  * @pdev: PCI device information struct
5375  *
5376  * ixgbe_remove is called by the PCI subsystem to alert the driver
5377  * that it should release a PCI device.  The could be caused by a
5378  * Hot-Plug event, or because the driver is going to be removed from
5379  * memory.
5380  **/
5381 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5382 {
5383         struct net_device *netdev = pci_get_drvdata(pdev);
5384         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5385         int err;
5386
5387         set_bit(__IXGBE_DOWN, &adapter->state);
5388         /* clear the module not found bit to make sure the worker won't
5389          * reschedule
5390          */
5391         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5392         del_timer_sync(&adapter->watchdog_timer);
5393
5394         del_timer_sync(&adapter->sfp_timer);
5395         cancel_work_sync(&adapter->watchdog_task);
5396         cancel_work_sync(&adapter->sfp_task);
5397         cancel_work_sync(&adapter->multispeed_fiber_task);
5398         cancel_work_sync(&adapter->sfp_config_module_task);
5399         flush_scheduled_work();
5400
5401 #ifdef CONFIG_IXGBE_DCA
5402         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5403                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5404                 dca_remove_requester(&pdev->dev);
5405                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5406         }
5407
5408 #endif
5409 #ifdef IXGBE_FCOE
5410         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5411                 ixgbe_cleanup_fcoe(adapter);
5412
5413 #endif /* IXGBE_FCOE */
5414
5415         /* remove the added san mac */
5416         ixgbe_del_sanmac_netdev(netdev);
5417
5418         if (netdev->reg_state == NETREG_REGISTERED)
5419                 unregister_netdev(netdev);
5420
5421         ixgbe_clear_interrupt_scheme(adapter);
5422
5423         ixgbe_release_hw_control(adapter);
5424
5425         iounmap(adapter->hw.hw_addr);
5426         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5427                                      IORESOURCE_MEM));
5428
5429         DPRINTK(PROBE, INFO, "complete\n");
5430
5431         free_netdev(netdev);
5432
5433         err = pci_disable_pcie_error_reporting(pdev);
5434         if (err)
5435                 dev_err(&pdev->dev,
5436                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5437
5438         pci_disable_device(pdev);
5439 }
5440
5441 /**
5442  * ixgbe_io_error_detected - called when PCI error is detected
5443  * @pdev: Pointer to PCI device
5444  * @state: The current pci connection state
5445  *
5446  * This function is called after a PCI bus error affecting
5447  * this device has been detected.
5448  */
5449 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5450                                                 pci_channel_state_t state)
5451 {
5452         struct net_device *netdev = pci_get_drvdata(pdev);
5453         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5454
5455         netif_device_detach(netdev);
5456
5457         if (state == pci_channel_io_perm_failure)
5458                 return PCI_ERS_RESULT_DISCONNECT;
5459
5460         if (netif_running(netdev))
5461                 ixgbe_down(adapter);
5462         pci_disable_device(pdev);
5463
5464         /* Request a slot reset. */
5465         return PCI_ERS_RESULT_NEED_RESET;
5466 }
5467
5468 /**
5469  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5470  * @pdev: Pointer to PCI device
5471  *
5472  * Restart the card from scratch, as if from a cold-boot.
5473  */
5474 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5475 {
5476         struct net_device *netdev = pci_get_drvdata(pdev);
5477         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5478         pci_ers_result_t result;
5479         int err;
5480
5481         if (pci_enable_device_mem(pdev)) {
5482                 DPRINTK(PROBE, ERR,
5483                         "Cannot re-enable PCI device after reset.\n");
5484                 result = PCI_ERS_RESULT_DISCONNECT;
5485         } else {
5486                 pci_set_master(pdev);
5487                 pci_restore_state(pdev);
5488
5489                 pci_wake_from_d3(pdev, false);
5490
5491                 ixgbe_reset(adapter);
5492                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5493                 result = PCI_ERS_RESULT_RECOVERED;
5494         }
5495
5496         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5497         if (err) {
5498                 dev_err(&pdev->dev,
5499                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5500                 /* non-fatal, continue */
5501         }
5502
5503         return result;
5504 }
5505
5506 /**
5507  * ixgbe_io_resume - called when traffic can start flowing again.
5508  * @pdev: Pointer to PCI device
5509  *
5510  * This callback is called when the error recovery driver tells us that
5511  * its OK to resume normal operation.
5512  */
5513 static void ixgbe_io_resume(struct pci_dev *pdev)
5514 {
5515         struct net_device *netdev = pci_get_drvdata(pdev);
5516         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5517
5518         if (netif_running(netdev)) {
5519                 if (ixgbe_up(adapter)) {
5520                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5521                         return;
5522                 }
5523         }
5524
5525         netif_device_attach(netdev);
5526 }
5527
5528 static struct pci_error_handlers ixgbe_err_handler = {
5529         .error_detected = ixgbe_io_error_detected,
5530         .slot_reset = ixgbe_io_slot_reset,
5531         .resume = ixgbe_io_resume,
5532 };
5533
5534 static struct pci_driver ixgbe_driver = {
5535         .name     = ixgbe_driver_name,
5536         .id_table = ixgbe_pci_tbl,
5537         .probe    = ixgbe_probe,
5538         .remove   = __devexit_p(ixgbe_remove),
5539 #ifdef CONFIG_PM
5540         .suspend  = ixgbe_suspend,
5541         .resume   = ixgbe_resume,
5542 #endif
5543         .shutdown = ixgbe_shutdown,
5544         .err_handler = &ixgbe_err_handler
5545 };
5546
5547 /**
5548  * ixgbe_init_module - Driver Registration Routine
5549  *
5550  * ixgbe_init_module is the first routine called when the driver is
5551  * loaded. All it does is register with the PCI subsystem.
5552  **/
5553 static int __init ixgbe_init_module(void)
5554 {
5555         int ret;
5556         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5557                ixgbe_driver_string, ixgbe_driver_version);
5558
5559         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5560
5561 #ifdef CONFIG_IXGBE_DCA
5562         dca_register_notify(&dca_notifier);
5563 #endif
5564
5565         ret = pci_register_driver(&ixgbe_driver);
5566         return ret;
5567 }
5568
5569 module_init(ixgbe_init_module);
5570
5571 /**
5572  * ixgbe_exit_module - Driver Exit Cleanup Routine
5573  *
5574  * ixgbe_exit_module is called just before the driver is removed
5575  * from memory.
5576  **/
5577 static void __exit ixgbe_exit_module(void)
5578 {
5579 #ifdef CONFIG_IXGBE_DCA
5580         dca_unregister_notify(&dca_notifier);
5581 #endif
5582         pci_unregister_driver(&ixgbe_driver);
5583 }
5584
5585 #ifdef CONFIG_IXGBE_DCA
5586 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5587                             void *p)
5588 {
5589         int ret_val;
5590
5591         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5592                                          __ixgbe_notify_dca);
5593
5594         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5595 }
5596
5597 #endif /* CONFIG_IXGBE_DCA */
5598 #ifdef DEBUG
5599 /**
5600  * ixgbe_get_hw_dev_name - return device name string
5601  * used by hardware layer to print debugging information
5602  **/
5603 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5604 {
5605         struct ixgbe_adapter *adapter = hw->back;
5606         return adapter->netdev->name;
5607 }
5608
5609 #endif
5610 module_exit(ixgbe_exit_module);
5611
5612 /* ixgbe_main.c */