2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/dmapool.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/smp_lock.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
35 #include <linux/usb.h>
36 #include <linux/moduleparam.h>
37 #include <linux/dma-mapping.h>
39 #include "../core/hcd.h"
41 #include <asm/byteorder.h>
44 #include <asm/system.h>
45 #include <asm/unaligned.h>
48 /*-------------------------------------------------------------------------*/
51 * EHCI hc_driver implementation ... experimental, incomplete.
52 * Based on the final 1.0 register interface specification.
54 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
55 * First was PCMCIA, like ISA; then CardBus, which is PCI.
56 * Next comes "CardBay", using USB 2.0 signals.
58 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
59 * Special thanks to Intel and VIA for providing host controllers to
60 * test this driver on, and Cypress (including In-System Design) for
61 * providing early devices for those host controllers to talk to!
65 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
66 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
67 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
68 * <sojkam@centrum.cz>, updates by DB).
70 * 2002-11-29 Correct handling for hw async_next register.
71 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
72 * only scheduling is different, no arbitrary limitations.
73 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
74 * clean up HC run state handshaking.
75 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
76 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
77 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
78 * 2002-05-07 Some error path cleanups to report better errors; wmb();
79 * use non-CVS version id; better iso bandwidth claim.
80 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
81 * errors in submit path. Bugfixes to interrupt scheduling/processing.
82 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
83 * more checking to generic hcd framework (db). Make it work with
84 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
85 * 2002-01-14 Minor cleanup; version synch.
86 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
87 * 2002-01-04 Control/Bulk queuing behaves.
89 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
90 * 2001-June Works with usb-storage and NEC EHCI on 2.4
93 #define DRIVER_VERSION "10 Dec 2004"
94 #define DRIVER_AUTHOR "David Brownell"
95 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
97 static const char hcd_name [] = "ehci_hcd";
100 #undef EHCI_VERBOSE_DEBUG
101 #undef EHCI_URB_TRACE
107 /* magic numbers that can affect system performance */
108 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
109 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
110 #define EHCI_TUNE_RL_TT 0
111 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
112 #define EHCI_TUNE_MULT_TT 1
113 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
115 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
116 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
117 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
118 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
120 /* Initial IRQ latency: faster than hw default */
121 static int log2_irq_thresh = 0; // 0 to 6
122 module_param (log2_irq_thresh, int, S_IRUGO);
123 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
125 /* initial park setting: slower than hw default */
126 static unsigned park = 0;
127 module_param (park, uint, S_IRUGO);
128 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
130 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
132 /*-------------------------------------------------------------------------*/
135 #include "ehci-dbg.c"
137 /*-------------------------------------------------------------------------*/
140 * handshake - spin reading hc until handshake completes or fails
141 * @ptr: address of hc register to be read
142 * @mask: bits to look at in result of read
143 * @done: value of those bits when handshake succeeds
144 * @usec: timeout in microseconds
146 * Returns negative errno, or zero on success
148 * Success happens when the "mask" bits have the specified value (hardware
149 * handshake done). There are two failure modes: "usec" have passed (major
150 * hardware flakeout), or the register reads as all-ones (hardware removed).
152 * That last failure should_only happen in cases like physical cardbus eject
153 * before driver shutdown. But it also seems to be caused by bugs in cardbus
154 * bridge shutdown: shutting down the bridge before the devices using it.
156 static int handshake (void __iomem *ptr, u32 mask, u32 done, int usec)
161 result = readl (ptr);
162 if (result == ~(u32)0) /* card removed */
173 /* force HC to halt state from unknown (EHCI spec section 2.3) */
174 static int ehci_halt (struct ehci_hcd *ehci)
176 u32 temp = readl (&ehci->regs->status);
178 /* disable any irqs left enabled by previous code */
179 writel (0, &ehci->regs->intr_enable);
181 if ((temp & STS_HALT) != 0)
184 temp = readl (&ehci->regs->command);
186 writel (temp, &ehci->regs->command);
187 return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125);
190 /* put TDI/ARC silicon into EHCI mode */
191 static void tdi_reset (struct ehci_hcd *ehci)
193 u32 __iomem *reg_ptr;
196 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68);
197 tmp = readl (reg_ptr);
199 writel (tmp, reg_ptr);
202 /* reset a non-running (STS_HALT == 1) controller */
203 static int ehci_reset (struct ehci_hcd *ehci)
206 u32 command = readl (&ehci->regs->command);
208 command |= CMD_RESET;
209 dbg_cmd (ehci, "reset", command);
210 writel (command, &ehci->regs->command);
211 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
212 ehci->next_statechange = jiffies;
213 retval = handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000);
218 if (ehci_is_TDI(ehci))
224 /* idle the controller (from running) */
225 static void ehci_quiesce (struct ehci_hcd *ehci)
230 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
234 /* wait for any schedule enables/disables to take effect */
235 temp = readl (&ehci->regs->command) << 10;
236 temp &= STS_ASS | STS_PSS;
237 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
238 temp, 16 * 125) != 0) {
239 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
243 /* then disable anything that's still active */
244 temp = readl (&ehci->regs->command);
245 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
246 writel (temp, &ehci->regs->command);
248 /* hardware can take 16 microframes to turn off ... */
249 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
251 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
256 /*-------------------------------------------------------------------------*/
258 static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs);
260 #include "ehci-hub.c"
261 #include "ehci-mem.c"
263 #include "ehci-sched.c"
265 /*-------------------------------------------------------------------------*/
267 static void ehci_watchdog (unsigned long param)
269 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
272 spin_lock_irqsave (&ehci->lock, flags);
274 /* lost IAA irqs wedge things badly; seen with a vt8235 */
276 u32 status = readl (&ehci->regs->status);
278 if (status & STS_IAA) {
279 ehci_vdbg (ehci, "lost IAA\n");
280 COUNT (ehci->stats.lost_iaa);
281 writel (STS_IAA, &ehci->regs->status);
282 ehci->reclaim_ready = 1;
286 /* stop async processing after it's idled a bit */
287 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
288 start_unlink_async (ehci, ehci->async);
290 /* ehci could run by timer, without IRQs ... */
291 ehci_work (ehci, NULL);
293 spin_unlock_irqrestore (&ehci->lock, flags);
296 /* Reboot notifiers kick in for silicon on any bus (not just pci, etc).
297 * This forcibly disables dma and IRQs, helping kexec and other cases
298 * where the next system software may expect clean state.
301 ehci_reboot (struct notifier_block *self, unsigned long code, void *null)
303 struct ehci_hcd *ehci;
305 ehci = container_of (self, struct ehci_hcd, reboot_notifier);
306 (void) ehci_halt (ehci);
308 /* make BIOS/etc use companion controller during reboot */
309 writel (0, &ehci->regs->configured_flag);
313 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
317 if (!HCS_PPC (ehci->hcs_params))
320 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
321 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
322 (void) ehci_hub_control(ehci_to_hcd(ehci),
323 is_on ? SetPortFeature : ClearPortFeature,
329 /*-------------------------------------------------------------------------*/
332 * ehci_work is called from some interrupts, timers, and so on.
333 * it calls driver completion functions, after dropping ehci->lock.
335 static void ehci_work (struct ehci_hcd *ehci, struct pt_regs *regs)
337 timer_action_done (ehci, TIMER_IO_WATCHDOG);
338 if (ehci->reclaim_ready)
339 end_unlink_async (ehci, regs);
341 /* another CPU may drop ehci->lock during a schedule scan while
342 * it reports urb completions. this flag guards against bogus
343 * attempts at re-entrant schedule scanning.
348 scan_async (ehci, regs);
349 if (ehci->next_uframe != -1)
350 scan_periodic (ehci, regs);
353 /* the IO watchdog guards against hardware or driver bugs that
354 * misplace IRQs, and should let us run completely without IRQs.
355 * such lossage has been observed on both VT6202 and VT8235.
357 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
358 (ehci->async->qh_next.ptr != NULL ||
359 ehci->periodic_sched != 0))
360 timer_action (ehci, TIMER_IO_WATCHDOG);
363 static void ehci_stop (struct usb_hcd *hcd)
365 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
367 ehci_dbg (ehci, "stop\n");
369 /* Turn off port power on all root hub ports. */
370 ehci_port_power (ehci, 0);
372 /* no more interrupts ... */
373 del_timer_sync (&ehci->watchdog);
375 spin_lock_irq(&ehci->lock);
376 if (HC_IS_RUNNING (hcd->state))
380 writel (0, &ehci->regs->intr_enable);
381 spin_unlock_irq(&ehci->lock);
383 /* let companion controllers work when we aren't */
384 writel (0, &ehci->regs->configured_flag);
385 unregister_reboot_notifier (&ehci->reboot_notifier);
387 remove_debug_files (ehci);
389 /* root hub is shut down separately (first, when possible) */
390 spin_lock_irq (&ehci->lock);
392 ehci_work (ehci, NULL);
393 spin_unlock_irq (&ehci->lock);
394 ehci_mem_cleanup (ehci);
397 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
398 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
399 ehci->stats.lost_iaa);
400 ehci_dbg (ehci, "complete %ld unlink %ld\n",
401 ehci->stats.complete, ehci->stats.unlink);
404 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status));
407 /* one-time init, only for memory state */
408 static int ehci_init(struct usb_hcd *hcd)
410 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
415 spin_lock_init(&ehci->lock);
417 init_timer(&ehci->watchdog);
418 ehci->watchdog.function = ehci_watchdog;
419 ehci->watchdog.data = (unsigned long) ehci;
422 * hw default: 1K periodic list heads, one per frame.
423 * periodic_size can shrink by USBCMD update if hcc_params allows.
425 ehci->periodic_size = DEFAULT_I_TDPS;
426 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
429 /* controllers may cache some of the periodic schedule ... */
430 hcc_params = readl(&ehci->caps->hcc_params);
431 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
433 else // N microframes cached
434 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
436 ehci->reclaim = NULL;
437 ehci->reclaim_ready = 0;
438 ehci->next_uframe = -1;
441 * dedicate a qh for the async ring head, since we couldn't unlink
442 * a 'real' qh without stopping the async schedule [4.8]. use it
443 * as the 'reclamation list head' too.
444 * its dummy is used in hw_alt_next of many tds, to prevent the qh
445 * from automatically advancing to the next td after short reads.
447 ehci->async->qh_next.qh = NULL;
448 ehci->async->hw_next = QH_NEXT(ehci->async->qh_dma);
449 ehci->async->hw_info1 = cpu_to_le32(QH_HEAD);
450 ehci->async->hw_token = cpu_to_le32(QTD_STS_HALT);
451 ehci->async->hw_qtd_next = EHCI_LIST_END;
452 ehci->async->qh_state = QH_STATE_LINKED;
453 ehci->async->hw_alt_next = QTD_NEXT(ehci->async->dummy->qtd_dma);
455 /* clear interrupt enables, set irq latency */
456 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
458 temp = 1 << (16 + log2_irq_thresh);
459 if (HCC_CANPARK(hcc_params)) {
460 /* HW default park == 3, on hardware that supports it (like
461 * NVidia and ALI silicon), maximizes throughput on the async
462 * schedule by avoiding QH fetches between transfers.
464 * With fast usb storage devices and NForce2, "park" seems to
465 * make problems: throughput reduction (!), data errors...
468 park = min(park, (unsigned) 3);
472 ehci_dbg(ehci, "park %d\n", park);
474 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
475 /* periodic schedule size can be smaller than default */
477 temp |= (EHCI_TUNE_FLS << 2);
478 switch (EHCI_TUNE_FLS) {
479 case 0: ehci->periodic_size = 1024; break;
480 case 1: ehci->periodic_size = 512; break;
481 case 2: ehci->periodic_size = 256; break;
485 ehci->command = temp;
487 ehci->reboot_notifier.notifier_call = ehci_reboot;
488 register_reboot_notifier(&ehci->reboot_notifier);
493 /* start HC running; it's halted, ehci_init() has been run (once) */
494 static int ehci_run (struct usb_hcd *hcd)
496 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
501 /* EHCI spec section 4.1 */
502 if ((retval = ehci_reset(ehci)) != 0) {
503 unregister_reboot_notifier(&ehci->reboot_notifier);
504 ehci_mem_cleanup(ehci);
507 writel(ehci->periodic_dma, &ehci->regs->frame_list);
508 writel((u32)ehci->async->qh_dma, &ehci->regs->async_next);
511 * hcc_params controls whether ehci->regs->segment must (!!!)
512 * be used; it constrains QH/ITD/SITD and QTD locations.
513 * pci_pool consistent memory always uses segment zero.
514 * streaming mappings for I/O buffers, like pci_map_single(),
515 * can return segments above 4GB, if the device allows.
517 * NOTE: the dma mask is visible through dma_supported(), so
518 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
519 * Scsi_Host.highmem_io, and so forth. It's readonly to all
520 * host side drivers though.
522 hcc_params = readl(&ehci->caps->hcc_params);
523 if (HCC_64BIT_ADDR(hcc_params)) {
524 writel(0, &ehci->regs->segment);
526 // this is deeply broken on almost all architectures
527 if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK))
528 ehci_info(ehci, "enabled 64bit DMA\n");
533 // Philips, Intel, and maybe others need CMD_RUN before the
534 // root hub will detect new devices (why?); NEC doesn't
535 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
536 ehci->command |= CMD_RUN;
537 writel (ehci->command, &ehci->regs->command);
538 dbg_cmd (ehci, "init", ehci->command);
541 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
542 * are explicitly handed to companion controller(s), so no TT is
543 * involved with the root hub. (Except where one is integrated,
544 * and there's no companion controller unless maybe for USB OTG.)
546 hcd->state = HC_STATE_RUNNING;
547 writel (FLAG_CF, &ehci->regs->configured_flag);
548 readl (&ehci->regs->command); /* unblock posted writes */
550 temp = HC_VERSION(readl (&ehci->caps->hc_capbase));
552 "USB %x.%x started, EHCI %x.%02x, driver %s\n",
553 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
554 temp >> 8, temp & 0xff, DRIVER_VERSION);
556 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */
558 /* GRR this is run-once init(), being done every time the HC starts.
559 * So long as they're part of class devices, we can't do it init()
560 * since the class device isn't created that early.
562 create_debug_files(ehci);
567 /*-------------------------------------------------------------------------*/
569 static irqreturn_t ehci_irq (struct usb_hcd *hcd, struct pt_regs *regs)
571 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
575 spin_lock (&ehci->lock);
577 status = readl (&ehci->regs->status);
579 /* e.g. cardbus physical eject */
580 if (status == ~(u32) 0) {
581 ehci_dbg (ehci, "device removed\n");
586 if (!status) { /* irq sharing? */
587 spin_unlock(&ehci->lock);
591 /* clear (just) interrupts */
592 writel (status, &ehci->regs->status);
593 readl (&ehci->regs->command); /* unblock posted write */
596 #ifdef EHCI_VERBOSE_DEBUG
597 /* unrequested/ignored: Frame List Rollover */
598 dbg_status (ehci, "irq", status);
601 /* INT, ERR, and IAA interrupt rates can be throttled */
603 /* normal [4.15.1.2] or error [4.15.1.1] completion */
604 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
605 if (likely ((status & STS_ERR) == 0))
606 COUNT (ehci->stats.normal);
608 COUNT (ehci->stats.error);
612 /* complete the unlinking of some qh [4.15.2.3] */
613 if (status & STS_IAA) {
614 COUNT (ehci->stats.reclaim);
615 ehci->reclaim_ready = 1;
619 /* remote wakeup [4.3.1] */
620 if (status & STS_PCD) {
621 unsigned i = HCS_N_PORTS (ehci->hcs_params);
623 /* resume root hub? */
624 status = readl (&ehci->regs->command);
625 if (!(status & CMD_RUN))
626 writel (status | CMD_RUN, &ehci->regs->command);
629 status = readl (&ehci->regs->port_status [i]);
630 if (status & PORT_OWNER)
632 if (!(status & PORT_RESUME)
633 || ehci->reset_done [i] != 0)
636 /* start 20 msec resume signaling from this port,
637 * and make khubd collect PORT_STAT_C_SUSPEND to
638 * stop that signaling.
640 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
641 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
642 usb_hcd_resume_root_hub(hcd);
646 /* PCI errors [4.15.2.4] */
647 if (unlikely ((status & STS_FATAL) != 0)) {
648 /* bogus "fatal" IRQs appear on some chips... why? */
649 status = readl (&ehci->regs->status);
650 dbg_cmd (ehci, "fatal", readl (&ehci->regs->command));
651 dbg_status (ehci, "fatal", status);
652 if (status & STS_HALT) {
653 ehci_err (ehci, "fatal error\n");
656 writel (0, &ehci->regs->configured_flag);
657 /* generic layer kills/unlinks all urbs, then
658 * uses ehci_stop to clean up the rest
665 ehci_work (ehci, regs);
666 spin_unlock (&ehci->lock);
670 /*-------------------------------------------------------------------------*/
673 * non-error returns are a promise to giveback() the urb later
674 * we drop ownership so next owner (or urb unlink) can get it
676 * urb + dev is in hcd.self.controller.urb_list
677 * we're queueing TDs onto software and hardware lists
679 * hcd-specific init for hcpriv hasn't been done yet
681 * NOTE: control, bulk, and interrupt share the same code to append TDs
682 * to a (possibly active) QH, and the same QH scanning code.
684 static int ehci_urb_enqueue (
686 struct usb_host_endpoint *ep,
690 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
691 struct list_head qtd_list;
693 INIT_LIST_HEAD (&qtd_list);
695 switch (usb_pipetype (urb->pipe)) {
696 // case PIPE_CONTROL:
699 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
701 return submit_async (ehci, ep, urb, &qtd_list, mem_flags);
704 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
706 return intr_submit (ehci, ep, urb, &qtd_list, mem_flags);
708 case PIPE_ISOCHRONOUS:
709 if (urb->dev->speed == USB_SPEED_HIGH)
710 return itd_submit (ehci, urb, mem_flags);
712 return sitd_submit (ehci, urb, mem_flags);
716 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
718 /* if we need to use IAA and it's busy, defer */
719 if (qh->qh_state == QH_STATE_LINKED
721 && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) {
722 struct ehci_qh *last;
724 for (last = ehci->reclaim;
726 last = last->reclaim)
728 qh->qh_state = QH_STATE_UNLINK_WAIT;
731 /* bypass IAA if the hc can't care */
732 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim)
733 end_unlink_async (ehci, NULL);
735 /* something else might have unlinked the qh by now */
736 if (qh->qh_state == QH_STATE_LINKED)
737 start_unlink_async (ehci, qh);
740 /* remove from hardware lists
741 * completions normally happen asynchronously
744 static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
746 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
750 spin_lock_irqsave (&ehci->lock, flags);
751 switch (usb_pipetype (urb->pipe)) {
752 // case PIPE_CONTROL:
755 qh = (struct ehci_qh *) urb->hcpriv;
758 unlink_async (ehci, qh);
762 qh = (struct ehci_qh *) urb->hcpriv;
765 switch (qh->qh_state) {
766 case QH_STATE_LINKED:
767 intr_deschedule (ehci, qh);
770 qh_completions (ehci, qh, NULL);
773 ehci_dbg (ehci, "bogus qh %p state %d\n",
778 /* reschedule QH iff another request is queued */
779 if (!list_empty (&qh->qtd_list)
780 && HC_IS_RUNNING (hcd->state)) {
783 status = qh_schedule (ehci, qh);
784 spin_unlock_irqrestore (&ehci->lock, flags);
787 // shouldn't happen often, but ...
788 // FIXME kill those tds' urbs
789 err ("can't reschedule qh %p, err %d",
796 case PIPE_ISOCHRONOUS:
799 // wait till next completion, do it then.
800 // completion irqs can wait up to 1024 msec,
804 spin_unlock_irqrestore (&ehci->lock, flags);
808 /*-------------------------------------------------------------------------*/
810 // bulk qh holds the data toggle
813 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
815 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
817 struct ehci_qh *qh, *tmp;
819 /* ASSERT: any requests/urbs are being unlinked */
820 /* ASSERT: nobody can be submitting urbs for this any more */
823 spin_lock_irqsave (&ehci->lock, flags);
828 /* endpoints can be iso streams. for now, we don't
829 * accelerate iso completions ... so spin a while.
831 if (qh->hw_info1 == 0) {
832 ehci_vdbg (ehci, "iso delay\n");
836 if (!HC_IS_RUNNING (hcd->state))
837 qh->qh_state = QH_STATE_IDLE;
838 switch (qh->qh_state) {
839 case QH_STATE_LINKED:
840 for (tmp = ehci->async->qh_next.qh;
842 tmp = tmp->qh_next.qh)
844 /* periodic qh self-unlinks on empty */
847 unlink_async (ehci, qh);
849 case QH_STATE_UNLINK: /* wait for hw to finish? */
851 spin_unlock_irqrestore (&ehci->lock, flags);
852 schedule_timeout_uninterruptible(1);
854 case QH_STATE_IDLE: /* fully unlinked */
855 if (list_empty (&qh->qtd_list)) {
859 /* else FALL THROUGH */
862 /* caller was supposed to have unlinked any requests;
863 * that's not our job. just leak this memory.
865 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
866 qh, ep->desc.bEndpointAddress, qh->qh_state,
867 list_empty (&qh->qtd_list) ? "" : "(has tds)");
872 spin_unlock_irqrestore (&ehci->lock, flags);
876 static int ehci_get_frame (struct usb_hcd *hcd)
878 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
879 return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size;
882 /*-------------------------------------------------------------------------*/
884 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
886 MODULE_DESCRIPTION (DRIVER_INFO);
887 MODULE_AUTHOR (DRIVER_AUTHOR);
888 MODULE_LICENSE ("GPL");
891 #include "ehci-pci.c"
894 #if !defined(CONFIG_PCI)
895 #error "missing bus glue for ehci-hcd"