2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
61 udelay(REGISTER_BUSY_DELAY);
67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
73 * Wait until the BBP becomes ready.
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®, BBPCSR_VALUE, value);
86 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
99 * Wait until the BBP becomes ready.
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
118 * Wait until the BBP becomes ready.
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
143 udelay(REGISTER_BUSY_DELAY);
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®, RFCSR_VALUE, value);
152 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(®, RFCSR_BUSY, 1);
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
165 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
180 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, u32 *data)
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, u32 data)
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
234 #ifdef CONFIG_RT2400PCI_RFKILL
235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
243 #define rt2400pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2400PCI_RFKILL */
246 #ifdef CONFIG_RT2400PCI_LEDS
247 static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled && activity);
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
267 #define rt2400pci_led_brightness NULL
268 #endif /* CONFIG_RT2400PCI_LEDS */
271 * Configuration handlers.
273 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00_intf *intf,
275 struct rt2x00intf_conf *conf,
276 const unsigned int flags)
278 unsigned int bcn_preload;
281 if (flags & CONFIG_UPDATE_TYPE) {
282 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
285 * Enable beacon config
287 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
288 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
289 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
290 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
293 * Enable synchronisation.
295 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
296 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
297 rt2x00_set_field32(®, CSR14_TBCN,
298 (conf->sync == TSF_SYNC_BEACON));
299 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
300 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
301 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
304 if (flags & CONFIG_UPDATE_MAC)
305 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
306 conf->mac, sizeof(conf->mac));
308 if (flags & CONFIG_UPDATE_BSSID)
309 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
310 conf->bssid, sizeof(conf->bssid));
313 static int rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
314 const int short_preamble,
315 const int ack_timeout,
316 const int ack_consume_time)
322 * When short preamble is enabled, we should set bit 0x08
324 preamble_mask = short_preamble << 3;
326 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
327 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, ack_timeout);
328 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
329 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
331 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
332 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble_mask);
333 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
334 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
335 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
337 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
338 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
339 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
340 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
341 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
343 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
344 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
345 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
346 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
347 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
349 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
350 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
351 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
352 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
353 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
358 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
359 const int basic_rate_mask)
361 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
364 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
365 struct rf_channel *rf)
368 * Switch on tuning bits.
370 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
371 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
373 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
374 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
375 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
378 * RF2420 chipset don't need any additional actions.
380 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
384 * For the RT2421 chipsets we need to write an invalid
385 * reference clock rate to activate auto_tune.
386 * After that we set the value back to the correct channel.
388 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
389 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
390 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
394 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
395 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
396 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
401 * Switch off tuning bits.
403 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
404 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
406 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
407 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
410 * Clear false CRC during channel switch.
412 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
415 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
417 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
420 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
421 struct antenna_setup *ant)
426 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
427 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
430 * Configure the TX antenna.
433 case ANTENNA_HW_DIVERSITY:
434 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
437 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
439 case ANTENNA_SW_DIVERSITY:
441 * NOTE: We should never come here because rt2x00lib is
442 * supposed to catch this and send us the correct antenna
443 * explicitely. However we are nog going to bug about this.
444 * Instead, just default to antenna B.
447 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
452 * Configure the RX antenna.
455 case ANTENNA_HW_DIVERSITY:
456 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
459 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
461 case ANTENNA_SW_DIVERSITY:
463 * NOTE: We should never come here because rt2x00lib is
464 * supposed to catch this and send us the correct antenna
465 * explicitely. However we are nog going to bug about this.
466 * Instead, just default to antenna B.
469 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
473 rt2400pci_bbp_write(rt2x00dev, 4, r4);
474 rt2400pci_bbp_write(rt2x00dev, 1, r1);
477 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
478 struct rt2x00lib_conf *libconf)
482 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
483 rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
484 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
486 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
487 rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
488 rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
489 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
491 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
492 rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
493 rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
494 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
496 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
497 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
498 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
499 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
501 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
502 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
503 libconf->conf->beacon_int * 16);
504 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
505 libconf->conf->beacon_int * 16);
506 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
509 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
510 struct rt2x00lib_conf *libconf,
511 const unsigned int flags)
513 if (flags & CONFIG_UPDATE_PHYMODE)
514 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
515 if (flags & CONFIG_UPDATE_CHANNEL)
516 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
517 if (flags & CONFIG_UPDATE_TXPOWER)
518 rt2400pci_config_txpower(rt2x00dev,
519 libconf->conf->power_level);
520 if (flags & CONFIG_UPDATE_ANTENNA)
521 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
522 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
523 rt2400pci_config_duration(rt2x00dev, libconf);
526 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
527 const int cw_min, const int cw_max)
531 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
532 rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
533 rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
534 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
540 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
541 struct link_qual *qual)
547 * Update FCS error count from register.
549 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
550 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
553 * Update False CCA count from register.
555 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
556 qual->false_cca = bbp;
559 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
561 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
562 rt2x00dev->link.vgc_level = 0x08;
565 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
570 * The link tuner should not run longer then 60 seconds,
571 * and should run once every 2 seconds.
573 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
577 * Base r13 link tuning on the false cca count.
579 rt2400pci_bbp_read(rt2x00dev, 13, ®);
581 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
582 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
583 rt2x00dev->link.vgc_level = reg;
584 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
585 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
586 rt2x00dev->link.vgc_level = reg;
591 * Initialization functions.
593 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
594 struct queue_entry *entry)
596 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
599 rt2x00_desc_read(priv_rx->desc, 2, &word);
600 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->queue->data_size);
601 rt2x00_desc_write(priv_rx->desc, 2, word);
603 rt2x00_desc_read(priv_rx->desc, 1, &word);
604 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
605 rt2x00_desc_write(priv_rx->desc, 1, word);
607 rt2x00_desc_read(priv_rx->desc, 0, &word);
608 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
609 rt2x00_desc_write(priv_rx->desc, 0, word);
612 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
613 struct queue_entry *entry)
615 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
618 rt2x00_desc_read(priv_tx->desc, 1, &word);
619 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
620 rt2x00_desc_write(priv_tx->desc, 1, word);
622 rt2x00_desc_read(priv_tx->desc, 2, &word);
623 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
624 entry->queue->data_size);
625 rt2x00_desc_write(priv_tx->desc, 2, word);
627 rt2x00_desc_read(priv_tx->desc, 0, &word);
628 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
629 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
630 rt2x00_desc_write(priv_tx->desc, 0, word);
633 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
635 struct queue_entry_priv_pci_rx *priv_rx;
636 struct queue_entry_priv_pci_tx *priv_tx;
640 * Initialize registers.
642 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
643 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
644 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
645 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
646 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
647 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
649 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
650 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
651 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
652 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
654 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
655 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
656 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
657 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
659 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
660 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
661 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
662 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
664 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
665 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
666 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
667 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
669 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
670 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
671 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
672 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
674 priv_rx = rt2x00dev->rx->entries[0].priv_data;
675 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
676 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
677 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
682 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
686 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
687 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
688 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
689 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
691 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
692 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
693 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
694 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
695 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
697 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
698 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
699 (rt2x00dev->rx->data_size / 128));
700 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
702 rt2x00pci_register_read(rt2x00dev, LEDCSR, ®);
703 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, 70);
704 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, 30);
705 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
707 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
709 rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
710 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
711 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
712 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
713 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
714 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
716 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
717 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
718 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
719 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
720 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
721 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
722 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
723 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
725 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
727 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
730 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
731 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
733 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
734 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
735 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
737 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
738 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
739 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
740 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
741 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
742 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
744 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
745 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
746 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
747 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
748 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
750 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
751 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
752 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
753 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
756 * We must clear the FCS and FIFO error count.
757 * These registers are cleared on read,
758 * so we may pass a useless variable to store the value.
760 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
761 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
766 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
773 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
774 rt2400pci_bbp_read(rt2x00dev, 0, &value);
775 if ((value != 0xff) && (value != 0x00))
776 goto continue_csr_init;
777 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
778 udelay(REGISTER_BUSY_DELAY);
781 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
785 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
786 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
787 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
788 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
789 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
790 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
791 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
792 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
793 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
794 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
795 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
796 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
797 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
798 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
800 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
801 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
803 if (eeprom != 0xffff && eeprom != 0x0000) {
804 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
805 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
806 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
814 * Device state switch handlers.
816 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
817 enum dev_state state)
821 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
822 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
823 state == STATE_RADIO_RX_OFF);
824 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
827 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
828 enum dev_state state)
830 int mask = (state == STATE_RADIO_IRQ_OFF);
834 * When interrupts are being enabled, the interrupt registers
835 * should clear the register to assure a clean state.
837 if (state == STATE_RADIO_IRQ_ON) {
838 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
839 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
843 * Only toggle the interrupts bits we are going to use.
844 * Non-checked interrupt bits are disabled by default.
846 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
847 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
848 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
849 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
850 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
851 rt2x00_set_field32(®, CSR8_RXDONE, mask);
852 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
855 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
858 * Initialize all registers.
860 if (rt2400pci_init_queues(rt2x00dev) ||
861 rt2400pci_init_registers(rt2x00dev) ||
862 rt2400pci_init_bbp(rt2x00dev)) {
863 ERROR(rt2x00dev, "Register initialization failed.\n");
870 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
875 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
879 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
882 * Disable synchronisation.
884 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
889 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
890 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
891 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
894 * Disable interrupts.
896 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
899 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
900 enum dev_state state)
908 put_to_sleep = (state != STATE_AWAKE);
910 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
911 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
912 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
913 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
914 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
915 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
918 * Device is not guaranteed to be in the requested state yet.
919 * We must wait until the register indicates that the
920 * device has entered the correct state.
922 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
923 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
924 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
925 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
926 if (bbp_state == state && rf_state == state)
931 NOTICE(rt2x00dev, "Device failed to enter state %d, "
932 "current device state: bbp %d and rf %d.\n",
933 state, bbp_state, rf_state);
938 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
939 enum dev_state state)
945 retval = rt2400pci_enable_radio(rt2x00dev);
947 case STATE_RADIO_OFF:
948 rt2400pci_disable_radio(rt2x00dev);
950 case STATE_RADIO_RX_ON:
951 case STATE_RADIO_RX_ON_LINK:
952 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
954 case STATE_RADIO_RX_OFF:
955 case STATE_RADIO_RX_OFF_LINK:
956 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
958 case STATE_DEEP_SLEEP:
962 retval = rt2400pci_set_state(rt2x00dev, state);
973 * TX descriptor initialization
975 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
977 struct txentry_desc *txdesc,
978 struct ieee80211_tx_control *control)
980 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
981 __le32 *txd = skbdesc->desc;
985 * Start writing the descriptor words.
987 rt2x00_desc_read(txd, 2, &word);
988 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
989 rt2x00_desc_write(txd, 2, word);
991 rt2x00_desc_read(txd, 3, &word);
992 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
993 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
994 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
995 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
996 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
997 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
998 rt2x00_desc_write(txd, 3, word);
1000 rt2x00_desc_read(txd, 4, &word);
1001 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1002 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1003 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1004 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1005 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1006 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1007 rt2x00_desc_write(txd, 4, word);
1009 rt2x00_desc_read(txd, 0, &word);
1010 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1011 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1012 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1013 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1014 rt2x00_set_field32(&word, TXD_W0_ACK,
1015 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1016 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1017 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1018 rt2x00_set_field32(&word, TXD_W0_RTS,
1019 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1020 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1021 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1023 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1024 rt2x00_desc_write(txd, 0, word);
1028 * TX data initialization
1030 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1031 const unsigned int queue)
1035 if (queue == RT2X00_BCN_QUEUE_BEACON) {
1036 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1037 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1038 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1039 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1044 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1045 rt2x00_set_field32(®, TXCSR0_KICK_PRIO,
1046 (queue == IEEE80211_TX_QUEUE_DATA0));
1047 rt2x00_set_field32(®, TXCSR0_KICK_TX,
1048 (queue == IEEE80211_TX_QUEUE_DATA1));
1049 rt2x00_set_field32(®, TXCSR0_KICK_ATIM,
1050 (queue == RT2X00_BCN_QUEUE_ATIM));
1051 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1055 * RX control handlers
1057 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1058 struct rxdone_entry_desc *rxdesc)
1060 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1064 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1065 rt2x00_desc_read(priv_rx->desc, 2, &word2);
1068 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1069 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1070 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1071 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1074 * Obtain the status about this packet.
1076 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1077 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1078 entry->queue->rt2x00dev->rssi_offset;
1080 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1081 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1085 * Interrupt functions.
1087 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1088 const enum ieee80211_tx_queue queue_idx)
1090 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1091 struct queue_entry_priv_pci_tx *priv_tx;
1092 struct queue_entry *entry;
1093 struct txdone_entry_desc txdesc;
1096 while (!rt2x00queue_empty(queue)) {
1097 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1098 priv_tx = entry->priv_data;
1099 rt2x00_desc_read(priv_tx->desc, 0, &word);
1101 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1102 !rt2x00_get_field32(word, TXD_W0_VALID))
1106 * Obtain the status about this packet.
1108 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1109 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1111 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1115 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1117 struct rt2x00_dev *rt2x00dev = dev_instance;
1121 * Get the interrupt sources & saved to local variable.
1122 * Write register value back to clear pending interrupts.
1124 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1125 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1130 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1134 * Handle interrupts, walk through all bits
1135 * and run the tasks, the bits are checked in order of
1140 * 1 - Beacon timer expired interrupt.
1142 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1143 rt2x00lib_beacondone(rt2x00dev);
1146 * 2 - Rx ring done interrupt.
1148 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1149 rt2x00pci_rxdone(rt2x00dev);
1152 * 3 - Atim ring transmit done interrupt.
1154 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1155 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1158 * 4 - Priority ring transmit done interrupt.
1160 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1161 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1164 * 5 - Tx ring transmit done interrupt.
1166 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1167 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1173 * Device probe functions.
1175 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1177 struct eeprom_93cx6 eeprom;
1182 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1184 eeprom.data = rt2x00dev;
1185 eeprom.register_read = rt2400pci_eepromregister_read;
1186 eeprom.register_write = rt2400pci_eepromregister_write;
1187 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1188 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1189 eeprom.reg_data_in = 0;
1190 eeprom.reg_data_out = 0;
1191 eeprom.reg_data_clock = 0;
1192 eeprom.reg_chip_select = 0;
1194 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1195 EEPROM_SIZE / sizeof(u16));
1198 * Start validation of the data that has been read.
1200 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1201 if (!is_valid_ether_addr(mac)) {
1202 DECLARE_MAC_BUF(macbuf);
1204 random_ether_addr(mac);
1205 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1208 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1209 if (word == 0xffff) {
1210 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1217 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1224 * Read EEPROM word for configuration.
1226 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1229 * Identify RF chipset.
1231 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1232 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1233 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1235 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1236 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1237 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1242 * Identify default antenna configuration.
1244 rt2x00dev->default_ant.tx =
1245 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1246 rt2x00dev->default_ant.rx =
1247 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1250 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1251 * I am not 100% sure about this, but the legacy drivers do not
1252 * indicate antenna swapping in software is required when
1253 * diversity is enabled.
1255 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1256 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1257 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1258 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1261 * Store led mode, for correct led behaviour.
1263 #ifdef CONFIG_RT2400PCI_LEDS
1264 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1268 case LED_MODE_ALPHA:
1269 case LED_MODE_DEFAULT:
1270 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1272 case LED_MODE_TXRX_ACTIVITY:
1273 rt2x00dev->led_flags =
1274 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1276 case LED_MODE_SIGNAL_STRENGTH:
1277 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1280 #endif /* CONFIG_RT2400PCI_LEDS */
1283 * Detect if this device has an hardware controlled radio.
1285 #ifdef CONFIG_RT2400PCI_RFKILL
1286 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1287 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1288 #endif /* CONFIG_RT2400PCI_RFKILL */
1291 * Check if the BBP tuning should be enabled.
1293 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1294 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1300 * RF value list for RF2420 & RF2421
1303 static const struct rf_channel rf_vals_bg[] = {
1304 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1305 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1306 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1307 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1308 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1309 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1310 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1311 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1312 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1313 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1314 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1315 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1316 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1317 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1320 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1322 struct hw_mode_spec *spec = &rt2x00dev->spec;
1327 * Initialize all hw fields.
1329 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1330 rt2x00dev->hw->extra_tx_headroom = 0;
1331 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1332 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1333 rt2x00dev->hw->queues = 2;
1335 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1336 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1337 rt2x00_eeprom_addr(rt2x00dev,
1338 EEPROM_MAC_ADDR_0));
1341 * Convert tx_power array in eeprom.
1343 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1344 for (i = 0; i < 14; i++)
1345 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1348 * Initialize hw_mode information.
1350 spec->num_modes = 1;
1351 spec->num_rates = 4;
1352 spec->tx_power_a = NULL;
1353 spec->tx_power_bg = txpower;
1354 spec->tx_power_default = DEFAULT_TXPOWER;
1356 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1357 spec->channels = rf_vals_bg;
1360 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1365 * Allocate eeprom data.
1367 retval = rt2400pci_validate_eeprom(rt2x00dev);
1371 retval = rt2400pci_init_eeprom(rt2x00dev);
1376 * Initialize hw specifications.
1378 rt2400pci_probe_hw_mode(rt2x00dev);
1381 * This device requires the atim queue
1383 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1386 * Set the rssi offset.
1388 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1394 * IEEE80211 stack callback functions.
1396 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1397 unsigned int changed_flags,
1398 unsigned int *total_flags,
1400 struct dev_addr_list *mc_list)
1402 struct rt2x00_dev *rt2x00dev = hw->priv;
1406 * Mask off any flags we are going to ignore from
1407 * the total_flags field.
1418 * Apply some rules to the filters:
1419 * - Some filters imply different filters to be set.
1420 * - Some things we can't filter out at all.
1422 *total_flags |= FIF_ALLMULTI;
1423 if (*total_flags & FIF_OTHER_BSS ||
1424 *total_flags & FIF_PROMISC_IN_BSS)
1425 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1428 * Check if there is any work left for us.
1430 if (rt2x00dev->packet_filter == *total_flags)
1432 rt2x00dev->packet_filter = *total_flags;
1435 * Start configuration steps.
1436 * Note that the version error will always be dropped
1437 * since there is no filter for it at this time.
1439 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
1440 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
1441 !(*total_flags & FIF_FCSFAIL));
1442 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
1443 !(*total_flags & FIF_PLCPFAIL));
1444 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
1445 !(*total_flags & FIF_CONTROL));
1446 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
1447 !(*total_flags & FIF_PROMISC_IN_BSS));
1448 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
1449 !(*total_flags & FIF_PROMISC_IN_BSS));
1450 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
1451 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1454 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1455 u32 short_retry, u32 long_retry)
1457 struct rt2x00_dev *rt2x00dev = hw->priv;
1460 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
1461 rt2x00_set_field32(®, CSR11_LONG_RETRY, long_retry);
1462 rt2x00_set_field32(®, CSR11_SHORT_RETRY, short_retry);
1463 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1468 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1470 const struct ieee80211_tx_queue_params *params)
1472 struct rt2x00_dev *rt2x00dev = hw->priv;
1475 * We don't support variating cw_min and cw_max variables
1476 * per queue. So by default we only configure the TX queue,
1477 * and ignore all other configurations.
1479 if (queue != IEEE80211_TX_QUEUE_DATA0)
1482 if (rt2x00mac_conf_tx(hw, queue, params))
1486 * Write configuration to register.
1488 rt2400pci_config_cw(rt2x00dev,
1489 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1494 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1496 struct rt2x00_dev *rt2x00dev = hw->priv;
1500 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1501 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1502 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1503 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1508 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1510 struct rt2x00_dev *rt2x00dev = hw->priv;
1512 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1513 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1516 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1517 struct ieee80211_tx_control *control)
1519 struct rt2x00_dev *rt2x00dev = hw->priv;
1520 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1521 struct queue_entry_priv_pci_tx *priv_tx;
1522 struct skb_frame_desc *skbdesc;
1524 if (unlikely(!intf->beacon))
1527 priv_tx = intf->beacon->priv_data;
1530 * Fill in skb descriptor
1532 skbdesc = get_skb_frame_desc(skb);
1533 memset(skbdesc, 0, sizeof(*skbdesc));
1534 skbdesc->data = skb->data;
1535 skbdesc->data_len = skb->len;
1536 skbdesc->desc = priv_tx->desc;
1537 skbdesc->desc_len = intf->beacon->queue->desc_size;
1538 skbdesc->entry = intf->beacon;
1541 * mac80211 doesn't provide the control->queue variable
1542 * for beacons. Set our own queue identification so
1543 * it can be used during descriptor initialization.
1545 control->queue = RT2X00_BCN_QUEUE_BEACON;
1546 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1549 * Enable beacon generation.
1550 * Write entire beacon with descriptor to register,
1551 * and kick the beacon generator.
1553 memcpy(priv_tx->data, skb->data, skb->len);
1554 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1559 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1561 struct rt2x00_dev *rt2x00dev = hw->priv;
1564 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
1565 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1568 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1570 .start = rt2x00mac_start,
1571 .stop = rt2x00mac_stop,
1572 .add_interface = rt2x00mac_add_interface,
1573 .remove_interface = rt2x00mac_remove_interface,
1574 .config = rt2x00mac_config,
1575 .config_interface = rt2x00mac_config_interface,
1576 .configure_filter = rt2400pci_configure_filter,
1577 .get_stats = rt2x00mac_get_stats,
1578 .set_retry_limit = rt2400pci_set_retry_limit,
1579 .bss_info_changed = rt2x00mac_bss_info_changed,
1580 .conf_tx = rt2400pci_conf_tx,
1581 .get_tx_stats = rt2x00mac_get_tx_stats,
1582 .get_tsf = rt2400pci_get_tsf,
1583 .reset_tsf = rt2400pci_reset_tsf,
1584 .beacon_update = rt2400pci_beacon_update,
1585 .tx_last_beacon = rt2400pci_tx_last_beacon,
1588 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1589 .irq_handler = rt2400pci_interrupt,
1590 .probe_hw = rt2400pci_probe_hw,
1591 .initialize = rt2x00pci_initialize,
1592 .uninitialize = rt2x00pci_uninitialize,
1593 .init_rxentry = rt2400pci_init_rxentry,
1594 .init_txentry = rt2400pci_init_txentry,
1595 .set_device_state = rt2400pci_set_device_state,
1596 .rfkill_poll = rt2400pci_rfkill_poll,
1597 .link_stats = rt2400pci_link_stats,
1598 .reset_tuner = rt2400pci_reset_tuner,
1599 .link_tuner = rt2400pci_link_tuner,
1600 .led_brightness = rt2400pci_led_brightness,
1601 .write_tx_desc = rt2400pci_write_tx_desc,
1602 .write_tx_data = rt2x00pci_write_tx_data,
1603 .kick_tx_queue = rt2400pci_kick_tx_queue,
1604 .fill_rxdone = rt2400pci_fill_rxdone,
1605 .config_intf = rt2400pci_config_intf,
1606 .config_preamble = rt2400pci_config_preamble,
1607 .config = rt2400pci_config,
1610 static const struct data_queue_desc rt2400pci_queue_rx = {
1611 .entry_num = RX_ENTRIES,
1612 .data_size = DATA_FRAME_SIZE,
1613 .desc_size = RXD_DESC_SIZE,
1614 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1617 static const struct data_queue_desc rt2400pci_queue_tx = {
1618 .entry_num = TX_ENTRIES,
1619 .data_size = DATA_FRAME_SIZE,
1620 .desc_size = TXD_DESC_SIZE,
1621 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1624 static const struct data_queue_desc rt2400pci_queue_bcn = {
1625 .entry_num = BEACON_ENTRIES,
1626 .data_size = MGMT_FRAME_SIZE,
1627 .desc_size = TXD_DESC_SIZE,
1628 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1631 static const struct data_queue_desc rt2400pci_queue_atim = {
1632 .entry_num = ATIM_ENTRIES,
1633 .data_size = DATA_FRAME_SIZE,
1634 .desc_size = TXD_DESC_SIZE,
1635 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1638 static const struct rt2x00_ops rt2400pci_ops = {
1639 .name = KBUILD_MODNAME,
1642 .eeprom_size = EEPROM_SIZE,
1644 .rx = &rt2400pci_queue_rx,
1645 .tx = &rt2400pci_queue_tx,
1646 .bcn = &rt2400pci_queue_bcn,
1647 .atim = &rt2400pci_queue_atim,
1648 .lib = &rt2400pci_rt2x00_ops,
1649 .hw = &rt2400pci_mac80211_ops,
1650 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1651 .debugfs = &rt2400pci_rt2x00debug,
1652 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1656 * RT2400pci module information.
1658 static struct pci_device_id rt2400pci_device_table[] = {
1659 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1663 MODULE_AUTHOR(DRV_PROJECT);
1664 MODULE_VERSION(DRV_VERSION);
1665 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1666 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1667 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1668 MODULE_LICENSE("GPL");
1670 static struct pci_driver rt2400pci_driver = {
1671 .name = KBUILD_MODNAME,
1672 .id_table = rt2400pci_device_table,
1673 .probe = rt2x00pci_probe,
1674 .remove = __devexit_p(rt2x00pci_remove),
1675 .suspend = rt2x00pci_suspend,
1676 .resume = rt2x00pci_resume,
1679 static int __init rt2400pci_init(void)
1681 return pci_register_driver(&rt2400pci_driver);
1684 static void __exit rt2400pci_exit(void)
1686 pci_unregister_driver(&rt2400pci_driver);
1689 module_init(rt2400pci_init);
1690 module_exit(rt2400pci_exit);