2 driver for LSI L64781 COFDM demodulator
4 Copyright (C) 2001 Holger Waechtler for Convergence Integrated Media GmbH
5 Marko Kohtala <marko.kohtala@luukku.com>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/string.h>
28 #include <linux/slab.h>
29 #include "dvb_frontend.h"
34 struct i2c_adapter* i2c;
35 struct dvb_frontend_ops ops;
36 const struct l64781_config* config;
37 struct dvb_frontend frontend;
39 /* private demodulator data */
43 #define dprintk(args...) \
45 if (debug) printk(KERN_DEBUG "l64781: " args); \
50 module_param(debug, int, 0644);
51 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
54 static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data)
57 u8 buf [] = { reg, data };
58 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
60 if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
61 dprintk ("%s: write_reg error (reg == %02x) = %02x!\n",
62 __FUNCTION__, reg, ret);
64 return (ret != 1) ? -1 : 0;
67 static int l64781_readreg (struct l64781_state* state, u8 reg)
72 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
73 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
75 ret = i2c_transfer(state->i2c, msg, 2);
77 if (ret != 2) return ret;
82 static void apply_tps (struct l64781_state* state)
84 l64781_writereg (state, 0x2a, 0x00);
85 l64781_writereg (state, 0x2a, 0x01);
87 /* This here is a little bit questionable because it enables
88 the automatic update of TPS registers. I think we'd need to
89 handle the IRQ from FE to update some other registers as
90 well, or at least implement some magic to tuning to correct
91 to the TPS received from transmission. */
92 l64781_writereg (state, 0x2a, 0x02);
96 static void reset_afc (struct l64781_state* state)
98 /* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for
100 l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
101 l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */
102 l64781_writereg (state, 0x09, 0);
103 l64781_writereg (state, 0x0a, 0);
104 l64781_writereg (state, 0x07, 0x8e);
105 l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */
106 l64781_writereg (state, 0x11, 0x80); /* stall TIM */
107 l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */
108 l64781_writereg (state, 0x12, 0);
109 l64781_writereg (state, 0x13, 0);
110 l64781_writereg (state, 0x11, 0x00);
113 static int reset_and_configure (struct l64781_state* state)
115 u8 buf [] = { 0x06 };
116 struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };
117 // NOTE: this is correct in writing to address 0x00
119 return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;
122 static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_parameters *param)
124 struct l64781_state* state = fe->demodulator_priv;
125 /* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */
126 static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };
127 /* QPSK, QAM_16, QAM_64 */
128 static const u8 qam_tab [] = { 2, 4, 0, 6 };
129 static const u8 bw_tab [] = { 8, 7, 6 }; /* 8Mhz, 7MHz, 6MHz */
130 static const u8 guard_tab [] = { 1, 2, 4, 8 };
131 /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */
132 static const u32 ppm = 8000;
133 struct dvb_ofdm_parameters *p = ¶m->u.ofdm;
134 u32 ddfs_offset_fixed;
135 /* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */
136 /* bw_tab[p->bandWidth]<<10)/15625; */
142 int bw = p->bandwidth - BANDWIDTH_8_MHZ;
144 if (fe->ops->tuner_ops.set_params) {
145 fe->ops->tuner_ops.set_params(fe, param);
146 if (fe->ops->i2c_gate_ctrl) fe->ops->i2c_gate_ctrl(fe, 0);
149 if (param->inversion != INVERSION_ON &&
150 param->inversion != INVERSION_OFF)
153 if (bw < 0 || bw > 2)
156 if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
157 p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 &&
158 p->code_rate_HP != FEC_7_8)
161 if (p->hierarchy_information != HIERARCHY_NONE &&
162 (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 &&
163 p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 &&
164 p->code_rate_LP != FEC_7_8))
167 if (p->constellation != QPSK && p->constellation != QAM_16 &&
168 p->constellation != QAM_64)
171 if (p->transmission_mode != TRANSMISSION_MODE_2K &&
172 p->transmission_mode != TRANSMISSION_MODE_8K)
175 if (p->guard_interval < GUARD_INTERVAL_1_32 ||
176 p->guard_interval > GUARD_INTERVAL_1_4)
179 if (p->hierarchy_information < HIERARCHY_NONE ||
180 p->hierarchy_information > HIERARCHY_4)
183 ddfs_offset_fixed = 0x4000-(ppm<<16)/bw_tab[p->bandwidth]/1000000;
185 /* This works up to 20000 ppm, it overflows if too large ppm! */
186 init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) /
187 bw_tab[p->bandwidth] & 0xFFFFFF);
189 /* SPI bias calculation is slightly modified to fit in 32bit */
190 /* will work for high ppm only... */
191 spi_bias = 378 * (1 << 10);
193 spi_bias *= bw_tab[p->bandwidth];
194 spi_bias *= qam_tab[p->constellation];
195 spi_bias /= p->code_rate_HP + 1;
196 spi_bias /= (guard_tab[p->guard_interval] + 32);
198 spi_bias /= 1000ULL + ppm/1000;
199 spi_bias *= p->code_rate_HP;
201 val0x04 = (p->transmission_mode << 2) | p->guard_interval;
202 val0x05 = fec_tab[p->code_rate_HP];
204 if (p->hierarchy_information != HIERARCHY_NONE)
205 val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
207 val0x06 = (p->hierarchy_information << 2) | p->constellation;
209 l64781_writereg (state, 0x04, val0x04);
210 l64781_writereg (state, 0x05, val0x05);
211 l64781_writereg (state, 0x06, val0x06);
215 /* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */
216 l64781_writereg (state, 0x15,
217 p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3);
218 l64781_writereg (state, 0x16, init_freq & 0xff);
219 l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
220 l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
222 l64781_writereg (state, 0x1b, spi_bias & 0xff);
223 l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
224 l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
225 (param->inversion == INVERSION_ON ? 0x80 : 0x00));
227 l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
228 l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
230 l64781_readreg (state, 0x00); /* clear interrupt registers... */
231 l64781_readreg (state, 0x01); /* dto. */
238 static int get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters* param)
240 struct l64781_state* state = fe->demodulator_priv;
244 tmp = l64781_readreg(state, 0x04);
247 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
250 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
253 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
256 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
259 switch((tmp >> 2) & 3) {
261 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
264 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
267 printk("Unexpected value for transmission_mode\n");
272 tmp = l64781_readreg(state, 0x05);
275 param->u.ofdm.code_rate_HP = FEC_1_2;
278 param->u.ofdm.code_rate_HP = FEC_2_3;
281 param->u.ofdm.code_rate_HP = FEC_3_4;
284 param->u.ofdm.code_rate_HP = FEC_5_6;
287 param->u.ofdm.code_rate_HP = FEC_7_8;
290 printk("Unexpected value for code_rate_HP\n");
292 switch((tmp >> 3) & 7) {
294 param->u.ofdm.code_rate_LP = FEC_1_2;
297 param->u.ofdm.code_rate_LP = FEC_2_3;
300 param->u.ofdm.code_rate_LP = FEC_3_4;
303 param->u.ofdm.code_rate_LP = FEC_5_6;
306 param->u.ofdm.code_rate_LP = FEC_7_8;
309 printk("Unexpected value for code_rate_LP\n");
313 tmp = l64781_readreg(state, 0x06);
316 param->u.ofdm.constellation = QPSK;
319 param->u.ofdm.constellation = QAM_16;
322 param->u.ofdm.constellation = QAM_64;
325 printk("Unexpected value for constellation\n");
327 switch((tmp >> 2) & 7) {
329 param->u.ofdm.hierarchy_information = HIERARCHY_NONE;
332 param->u.ofdm.hierarchy_information = HIERARCHY_1;
335 param->u.ofdm.hierarchy_information = HIERARCHY_2;
338 param->u.ofdm.hierarchy_information = HIERARCHY_4;
341 printk("Unexpected value for hierarchy\n");
345 tmp = l64781_readreg (state, 0x1d);
346 param->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;
348 tmp = (int) (l64781_readreg (state, 0x08) |
349 (l64781_readreg (state, 0x09) << 8) |
350 (l64781_readreg (state, 0x0a) << 16));
351 param->frequency += tmp;
356 static int l64781_read_status(struct dvb_frontend* fe, fe_status_t* status)
358 struct l64781_state* state = fe->demodulator_priv;
359 int sync = l64781_readreg (state, 0x32);
360 int gain = l64781_readreg (state, 0x0e);
362 l64781_readreg (state, 0x00); /* clear interrupt registers... */
363 l64781_readreg (state, 0x01); /* dto. */
368 *status |= FE_HAS_SIGNAL;
370 if (sync & 0x02) /* VCXO locked, this criteria should be ok */
371 *status |= FE_HAS_CARRIER;
374 *status |= FE_HAS_VITERBI;
377 *status |= FE_HAS_SYNC;
380 *status |= FE_HAS_LOCK;
385 static int l64781_read_ber(struct dvb_frontend* fe, u32* ber)
387 struct l64781_state* state = fe->demodulator_priv;
389 /* XXX FIXME: set up counting period (reg 0x26...0x28)
391 *ber = l64781_readreg (state, 0x39)
392 | (l64781_readreg (state, 0x3a) << 8);
397 static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
399 struct l64781_state* state = fe->demodulator_priv;
401 u8 gain = l64781_readreg (state, 0x0e);
402 *signal_strength = (gain << 8) | gain;
407 static int l64781_read_snr(struct dvb_frontend* fe, u16* snr)
409 struct l64781_state* state = fe->demodulator_priv;
411 u8 avg_quality = 0xff - l64781_readreg (state, 0x33);
412 *snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/
417 static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
419 struct l64781_state* state = fe->demodulator_priv;
421 *ucblocks = l64781_readreg (state, 0x37)
422 | (l64781_readreg (state, 0x38) << 8);
427 static int l64781_sleep(struct dvb_frontend* fe)
429 struct l64781_state* state = fe->demodulator_priv;
432 return l64781_writereg (state, 0x3e, 0x5a);
435 static int l64781_init(struct dvb_frontend* fe)
437 struct l64781_state* state = fe->demodulator_priv;
439 reset_and_configure (state);
442 l64781_writereg (state, 0x3e, 0xa5);
445 l64781_writereg (state, 0x2a, 0x04);
446 l64781_writereg (state, 0x2a, 0x00);
448 /* Set tuner specific things */
449 /* AFC_POL, set also in reset_afc */
450 l64781_writereg (state, 0x07, 0x8e);
452 /* Use internal ADC */
453 l64781_writereg (state, 0x0b, 0x81);
455 /* AGC loop gain, and polarity is positive */
456 l64781_writereg (state, 0x0c, 0x84);
458 /* Internal ADC outputs two's complement */
459 l64781_writereg (state, 0x0d, 0x8c);
461 /* With ppm=8000, it seems the DTR_SENSITIVITY will result in
462 value of 2 with all possible bandwidths and guard
463 intervals, which is the initial value anyway. */
464 /*l64781_writereg (state, 0x19, 0x92);*/
466 /* Everything is two's complement, soft bit and CSI_OUT too */
467 l64781_writereg (state, 0x1e, 0x09);
469 /* delay a bit after first init attempt */
478 static int l64781_get_tune_settings(struct dvb_frontend* fe,
479 struct dvb_frontend_tune_settings* fesettings)
481 fesettings->min_delay_ms = 4000;
482 fesettings->step_size = 0;
483 fesettings->max_drift = 0;
487 static void l64781_release(struct dvb_frontend* fe)
489 struct l64781_state* state = fe->demodulator_priv;
493 static struct dvb_frontend_ops l64781_ops;
495 struct dvb_frontend* l64781_attach(const struct l64781_config* config,
496 struct i2c_adapter* i2c)
498 struct l64781_state* state = NULL;
502 struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 },
503 { .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
505 /* allocate memory for the internal state */
506 state = kmalloc(sizeof(struct l64781_state), GFP_KERNEL);
507 if (state == NULL) goto error;
509 /* setup the state */
510 state->config = config;
512 memcpy(&state->ops, &l64781_ops, sizeof(struct dvb_frontend_ops));
516 * the L64781 won't show up before we send the reset_and_configure()
517 * broadcast. If nothing responds there is no L64781 on the bus...
519 if (reset_and_configure(state) < 0) {
520 dprintk("No response to reset and configure broadcast...\n");
524 /* The chip always responds to reads */
525 if (i2c_transfer(state->i2c, msg, 2) != 2) {
526 dprintk("No response to read on I2C bus\n");
530 /* Save current register contents for bailout */
531 reg0x3e = l64781_readreg(state, 0x3e);
533 /* Reading the POWER_DOWN register always returns 0 */
535 dprintk("Device doesn't look like L64781\n");
539 /* Turn the chip off */
540 l64781_writereg (state, 0x3e, 0x5a);
542 /* Responds to all reads with 0 */
543 if (l64781_readreg(state, 0x1a) != 0) {
544 dprintk("Read 1 returned unexpcted value\n");
548 /* Turn the chip on */
549 l64781_writereg (state, 0x3e, 0xa5);
551 /* Responds with register default value */
552 if (l64781_readreg(state, 0x1a) != 0xa1) {
553 dprintk("Read 2 returned unexpcted value\n");
557 /* create dvb_frontend */
558 state->frontend.ops = &state->ops;
559 state->frontend.demodulator_priv = state;
560 return &state->frontend;
564 l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */
569 static struct dvb_frontend_ops l64781_ops = {
572 .name = "LSI L64781 DVB-T",
574 /* .frequency_min = ???,*/
575 /* .frequency_max = ???,*/
576 .frequency_stepsize = 166666,
577 /* .frequency_tolerance = ???,*/
578 /* .symbol_rate_tolerance = ???,*/
579 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
580 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
581 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
585 .release = l64781_release,
588 .sleep = l64781_sleep,
590 .set_frontend = apply_frontend_param,
591 .get_frontend = get_frontend,
592 .get_tune_settings = l64781_get_tune_settings,
594 .read_status = l64781_read_status,
595 .read_ber = l64781_read_ber,
596 .read_signal_strength = l64781_read_signal_strength,
597 .read_snr = l64781_read_snr,
598 .read_ucblocks = l64781_read_ucblocks,
601 MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver");
602 MODULE_AUTHOR("Holger Waechtler, Marko Kohtala");
603 MODULE_LICENSE("GPL");
605 EXPORT_SYMBOL(l64781_attach);