Merge branch 'w90x900' into devel
[linux-2.6] / drivers / net / ixgbe / ixgbe_82599.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES   128
38 #define IXGBE_82599_MC_TBL_SIZE   128
39 #define IXGBE_82599_VFT_TBL_SIZE  128
40
41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42                                       ixgbe_link_speed *speed,
43                                       bool *autoneg);
44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47                                      ixgbe_link_speed speed, bool autoneg,
48                                      bool autoneg_wait_to_complete);
49 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51                                ixgbe_link_speed *speed,
52                                bool *link_up, bool link_up_wait_to_complete);
53 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54                                      ixgbe_link_speed speed,
55                                      bool autoneg,
56                                      bool autoneg_wait_to_complete);
57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58                                              ixgbe_link_speed *speed,
59                                              bool *autoneg);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62                                                ixgbe_link_speed speed,
63                                                bool autoneg,
64                                                bool autoneg_wait_to_complete);
65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69                          u32 vind, bool vlan_on);
70 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
71 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
72 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
73 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
74 s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
75 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
76 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
77 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
78
79 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
80 {
81         struct ixgbe_mac_info *mac = &hw->mac;
82         if (hw->phy.multispeed_fiber) {
83                 /* Set up dual speed SFP+ support */
84                 mac->ops.setup_link =
85                           &ixgbe_setup_mac_link_multispeed_fiber;
86                 mac->ops.setup_link_speed =
87                           &ixgbe_setup_mac_link_speed_multispeed_fiber;
88         } else {
89                 mac->ops.setup_link =
90                           &ixgbe_setup_mac_link_82599;
91                 mac->ops.setup_link_speed =
92                           &ixgbe_setup_mac_link_speed_82599;
93         }
94 }
95
96 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97 {
98         s32 ret_val = 0;
99         u16 list_offset, data_offset, data_value;
100
101         if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
102                 ixgbe_init_mac_link_ops_82599(hw);
103                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
104                                                               &data_offset);
105
106                 if (ret_val != 0)
107                         goto setup_sfp_out;
108
109                 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
110                 while (data_value != 0xffff) {
111                         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
112                         IXGBE_WRITE_FLUSH(hw);
113                         hw->eeprom.ops.read(hw, ++data_offset, &data_value);
114                 }
115                 /* Now restart DSP */
116                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
117                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
118                 IXGBE_WRITE_FLUSH(hw);
119         }
120
121 setup_sfp_out:
122         return ret_val;
123 }
124
125 /**
126  *  ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
127  *  @hw: pointer to hardware structure
128  *
129  *  Read PCIe configuration space, and get the MSI-X vector count from
130  *  the capabilities table.
131  **/
132 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
133 {
134         struct ixgbe_adapter *adapter = hw->back;
135         u16 msix_count;
136         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
137                              &msix_count);
138         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
139
140         /* MSI-X count is zero-based in HW, so increment to give proper value */
141         msix_count++;
142
143         return msix_count;
144 }
145
146 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
147 {
148         struct ixgbe_mac_info *mac = &hw->mac;
149         struct ixgbe_phy_info *phy = &hw->phy;
150         s32 ret_val;
151
152         /* Set the bus information prior to PHY identification */
153         mac->ops.get_bus_info(hw);
154
155         /* Call PHY identify routine to get the Cu or SFI phy type */
156         ret_val = phy->ops.identify(hw);
157
158         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
159                 goto get_invariants_out;
160
161         ixgbe_init_mac_link_ops_82599(hw);
162
163         /* Setup SFP module if there is one present. */
164         ret_val = mac->ops.setup_sfp(hw);
165
166         /* If copper media, overwrite with copper function pointers */
167         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
168                 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
169                 mac->ops.setup_link_speed =
170                                   &ixgbe_setup_copper_link_speed_82599;
171                 mac->ops.get_link_capabilities =
172                                   &ixgbe_get_copper_link_capabilities_82599;
173         }
174
175         /* PHY Init */
176         switch (hw->phy.type) {
177         case ixgbe_phy_tn:
178                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
179                 phy->ops.get_firmware_version =
180                                   &ixgbe_get_phy_firmware_version_tnx;
181                 break;
182         default:
183                 break;
184         }
185
186         mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
187         mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
188         mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
189         mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
190         mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
191         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
192
193 get_invariants_out:
194         return ret_val;
195 }
196
197 /**
198  *  ixgbe_get_link_capabilities_82599 - Determines link capabilities
199  *  @hw: pointer to hardware structure
200  *  @speed: pointer to link speed
201  *  @negotiation: true when autoneg or autotry is enabled
202  *
203  *  Determines the link capabilities by reading the AUTOC register.
204  **/
205 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
206                                       ixgbe_link_speed *speed,
207                                       bool *negotiation)
208 {
209         s32 status = 0;
210
211         switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
212         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
213                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
214                 *negotiation = false;
215                 break;
216
217         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
218                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
219                 *negotiation = false;
220                 break;
221
222         case IXGBE_AUTOC_LMS_1G_AN:
223                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
224                 *negotiation = true;
225                 break;
226
227         case IXGBE_AUTOC_LMS_10G_SERIAL:
228                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
229                 *negotiation = false;
230                 break;
231
232         case IXGBE_AUTOC_LMS_KX4_KX_KR:
233         case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
234                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
235                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
236                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
237                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
238                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
239                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
240                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
241                 *negotiation = true;
242                 break;
243
244         case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
245                 *speed = IXGBE_LINK_SPEED_100_FULL;
246                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
247                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
248                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
249                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
250                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
251                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
252                 *negotiation = true;
253                 break;
254
255         case IXGBE_AUTOC_LMS_SGMII_1G_100M:
256                 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
257                 *negotiation = false;
258                 break;
259
260         default:
261                 status = IXGBE_ERR_LINK_SETUP;
262                 goto out;
263                 break;
264         }
265
266         if (hw->phy.multispeed_fiber) {
267                 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
268                           IXGBE_LINK_SPEED_1GB_FULL;
269                 *negotiation = true;
270         }
271
272 out:
273         return status;
274 }
275
276 /**
277  *  ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
278  *  @hw: pointer to hardware structure
279  *  @speed: pointer to link speed
280  *  @autoneg: boolean auto-negotiation value
281  *
282  *  Determines the link capabilities by reading the AUTOC register.
283  **/
284 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
285                                                     ixgbe_link_speed *speed,
286                                                     bool *autoneg)
287 {
288         s32 status = IXGBE_ERR_LINK_SETUP;
289         u16 speed_ability;
290
291         *speed = 0;
292         *autoneg = true;
293
294         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
295                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
296                                       &speed_ability);
297
298         if (status == 0) {
299                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
300                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
301                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
302                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
303         }
304
305         return status;
306 }
307
308 /**
309  *  ixgbe_get_media_type_82599 - Get media type
310  *  @hw: pointer to hardware structure
311  *
312  *  Returns the media type (fiber, copper, backplane)
313  **/
314 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
315 {
316         enum ixgbe_media_type media_type;
317
318         /* Detect if there is a copper PHY attached. */
319         if (hw->phy.type == ixgbe_phy_cu_unknown ||
320             hw->phy.type == ixgbe_phy_tn) {
321                 media_type = ixgbe_media_type_copper;
322                 goto out;
323         }
324
325         switch (hw->device_id) {
326         case IXGBE_DEV_ID_82599:
327         case IXGBE_DEV_ID_82599_KX4:
328                 /* Default device ID is mezzanine card KX/KX4 */
329                 media_type = ixgbe_media_type_backplane;
330                 break;
331         case IXGBE_DEV_ID_82599_SFP:
332                 media_type = ixgbe_media_type_fiber;
333                 break;
334         default:
335                 media_type = ixgbe_media_type_unknown;
336                 break;
337         }
338 out:
339         return media_type;
340 }
341
342 /**
343  *  ixgbe_setup_mac_link_82599 - Setup MAC link settings
344  *  @hw: pointer to hardware structure
345  *
346  *  Configures link settings based on values in the ixgbe_hw struct.
347  *  Restarts the link.  Performs autonegotiation if needed.
348  **/
349 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
350 {
351         u32 autoc_reg;
352         u32 links_reg;
353         u32 i;
354         s32 status = 0;
355
356         /* Restart link */
357         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
358         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
359         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
360
361         /* Only poll for autoneg to complete if specified to do so */
362         if (hw->phy.autoneg_wait_to_complete) {
363                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
364                      IXGBE_AUTOC_LMS_KX4_KX_KR ||
365                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
366                      IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
367                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
368                      IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
369                         links_reg = 0; /* Just in case Autoneg time = 0 */
370                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
371                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
372                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
373                                         break;
374                                 msleep(100);
375                         }
376                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
377                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
378                                 hw_dbg(hw, "Autoneg did not complete.\n");
379                         }
380                 }
381         }
382
383         /* Set up flow control */
384         status = ixgbe_setup_fc_generic(hw, 0);
385
386         /* Add delay to filter out noises during initial link setup */
387         msleep(50);
388
389         return status;
390 }
391
392 /**
393  *  ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
394  *  @hw: pointer to hardware structure
395  *
396  *  Configures link settings based on values in the ixgbe_hw struct.
397  *  Restarts the link for multi-speed fiber at 1G speed, if link
398  *  fails at 10G.
399  *  Performs autonegotiation if needed.
400  **/
401 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
402 {
403         s32 status = 0;
404         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
405         status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
406                                                              true, true);
407         return status;
408 }
409
410 /**
411  *  ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
412  *  @hw: pointer to hardware structure
413  *  @speed: new link speed
414  *  @autoneg: true if autonegotiation enabled
415  *  @autoneg_wait_to_complete: true when waiting for completion is needed
416  *
417  *  Set the link speed in the AUTOC register and restarts link.
418  **/
419 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
420                                                 ixgbe_link_speed speed,
421                                                 bool autoneg,
422                                                 bool autoneg_wait_to_complete)
423 {
424         s32 status = 0;
425         ixgbe_link_speed phy_link_speed;
426         ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
427         u32 speedcnt = 0;
428         u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
429         bool link_up = false;
430         bool negotiation;
431
432         /* Mask off requested but non-supported speeds */
433         hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
434         speed &= phy_link_speed;
435
436         /*
437          * Try each speed one by one, highest priority first.  We do this in
438          * software because 10gb fiber doesn't support speed autonegotiation.
439          */
440         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
441                 speedcnt++;
442                 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
443
444                 /* Set hardware SDP's */
445                 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
446                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
447
448                 ixgbe_setup_mac_link_speed_82599(hw,
449                                                  IXGBE_LINK_SPEED_10GB_FULL,
450                                                  autoneg,
451                                                  autoneg_wait_to_complete);
452
453                 msleep(50);
454
455                 /* If we have link, just jump out */
456                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
457                 if (link_up)
458                         goto out;
459         }
460
461         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
462                 speedcnt++;
463                 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
464                         highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
465
466                 /* Set hardware SDP's */
467                 esdp_reg &= ~IXGBE_ESDP_SDP5;
468                 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
469                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
470
471                 ixgbe_setup_mac_link_speed_82599(
472                         hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
473                         autoneg_wait_to_complete);
474
475                 msleep(50);
476
477                 /* If we have link, just jump out */
478                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
479                 if (link_up)
480                         goto out;
481         }
482
483         /*
484          * We didn't get link.  Configure back to the highest speed we tried,
485          * (if there was more than one).  We call ourselves back with just the
486          * single highest speed that the user requested.
487          */
488         if (speedcnt > 1)
489                 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
490                                                      highest_link_speed,
491                                                      autoneg,
492                                                      autoneg_wait_to_complete);
493
494 out:
495         return status;
496 }
497
498 /**
499  *  ixgbe_check_mac_link_82599 - Determine link and speed status
500  *  @hw: pointer to hardware structure
501  *  @speed: pointer to link speed
502  *  @link_up: true when link is up
503  *  @link_up_wait_to_complete: bool used to wait for link up or not
504  *
505  *  Reads the links register to determine if link is up and the current speed
506  **/
507 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
508                                bool *link_up, bool link_up_wait_to_complete)
509 {
510         u32 links_reg;
511         u32 i;
512
513         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
514         if (link_up_wait_to_complete) {
515                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
516                         if (links_reg & IXGBE_LINKS_UP) {
517                                 *link_up = true;
518                                 break;
519                         } else {
520                                 *link_up = false;
521                         }
522                         msleep(100);
523                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
524                 }
525         } else {
526                 if (links_reg & IXGBE_LINKS_UP)
527                         *link_up = true;
528                 else
529                         *link_up = false;
530         }
531
532         if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
533             IXGBE_LINKS_SPEED_10G_82599)
534                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
535         else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
536                  IXGBE_LINKS_SPEED_1G_82599)
537                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
538         else
539                 *speed = IXGBE_LINK_SPEED_100_FULL;
540
541
542         return 0;
543 }
544
545 /**
546  *  ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
547  *  @hw: pointer to hardware structure
548  *  @speed: new link speed
549  *  @autoneg: true if autonegotiation enabled
550  *  @autoneg_wait_to_complete: true when waiting for completion is needed
551  *
552  *  Set the link speed in the AUTOC register and restarts link.
553  **/
554 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
555                                      ixgbe_link_speed speed, bool autoneg,
556                                      bool autoneg_wait_to_complete)
557 {
558         s32 status = 0;
559         u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
560         u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
561         u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
562         u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
563         u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
564         u32 links_reg;
565         u32 i;
566         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
567
568         /* Check to see if speed passed in is supported. */
569         hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
570         speed &= link_capabilities;
571
572         if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
573                 status = IXGBE_ERR_LINK_SETUP;
574         } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
575                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
576                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
577                 /* Set KX4/KX/KR support according to speed requested */
578                 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
579                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
580                         if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
581                                 autoc |= IXGBE_AUTOC_KX4_SUPP;
582                         if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
583                                 autoc |= IXGBE_AUTOC_KR_SUPP;
584                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
585                         autoc |= IXGBE_AUTOC_KX_SUPP;
586         } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
587                    (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
588                     link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
589                 /* Switch from 1G SFI to 10G SFI if requested */
590                 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
591                     (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
592                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
593                         autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
594                 }
595         } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
596                    (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
597                 /* Switch from 10G SFI to 1G SFI if requested */
598                 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
599                     (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
600                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
601                         if (autoneg)
602                                 autoc |= IXGBE_AUTOC_LMS_1G_AN;
603                         else
604                                 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
605                 }
606         }
607
608         if (status == 0) {
609                 /* Restart link */
610                 autoc |= IXGBE_AUTOC_AN_RESTART;
611                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
612
613                 /* Only poll for autoneg to complete if specified to do so */
614                 if (autoneg_wait_to_complete) {
615                         if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
616                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
617                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
618                                 links_reg = 0; /*Just in case Autoneg time=0*/
619                                 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
620                                         links_reg =
621                                                IXGBE_READ_REG(hw, IXGBE_LINKS);
622                                         if (links_reg & IXGBE_LINKS_KX_AN_COMP)
623                                                 break;
624                                         msleep(100);
625                                 }
626                                 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
627                                         status =
628                                                 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
629                                         hw_dbg(hw, "Autoneg did not "
630                                                "complete.\n");
631                                 }
632                         }
633                 }
634
635                 /* Set up flow control */
636                 status = ixgbe_setup_fc_generic(hw, 0);
637
638                 /* Add delay to filter out noises during initial link setup */
639                 msleep(50);
640         }
641
642         return status;
643 }
644
645 /**
646  *  ixgbe_setup_copper_link_82599 - Setup copper link settings
647  *  @hw: pointer to hardware structure
648  *
649  *  Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
650  **/
651 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
652 {
653         s32 status;
654
655         /* Restart autonegotiation on PHY */
656         status = hw->phy.ops.setup_link(hw);
657
658         /* Set up MAC */
659         ixgbe_setup_mac_link_82599(hw);
660
661         return status;
662 }
663
664 /**
665  *  ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
666  *  @hw: pointer to hardware structure
667  *  @speed: new link speed
668  *  @autoneg: true if autonegotiation enabled
669  *  @autoneg_wait_to_complete: true if waiting is needed to complete
670  *
671  *  Restarts link on PHY and MAC based on settings passed in.
672  **/
673 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
674                                                ixgbe_link_speed speed,
675                                                bool autoneg,
676                                                bool autoneg_wait_to_complete)
677 {
678         s32 status;
679
680         /* Setup the PHY according to input speed */
681         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
682                                               autoneg_wait_to_complete);
683         /* Set up MAC */
684         ixgbe_setup_mac_link_82599(hw);
685
686         return status;
687 }
688
689 /**
690  *  ixgbe_reset_hw_82599 - Perform hardware reset
691  *  @hw: pointer to hardware structure
692  *
693  *  Resets the hardware by resetting the transmit and receive units, masks
694  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
695  *  reset.
696  **/
697 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
698 {
699         s32 status = 0;
700         u32 ctrl, ctrl_ext;
701         u32 i;
702         u32 autoc;
703         u32 autoc2;
704
705         /* Call adapter stop to disable tx/rx and clear interrupts */
706         hw->mac.ops.stop_adapter(hw);
707
708         /* Reset PHY */
709         hw->phy.ops.reset(hw);
710
711         /*
712          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
713          * access and verify no pending requests before reset
714          */
715         if (ixgbe_disable_pcie_master(hw) != 0) {
716                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
717                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
718         }
719
720         /*
721          * Issue global reset to the MAC.  This needs to be a SW reset.
722          * If link reset is used, it might reset the MAC when mng is using it
723          */
724         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
725         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
726         IXGBE_WRITE_FLUSH(hw);
727
728         /* Poll for reset bit to self-clear indicating reset is complete */
729         for (i = 0; i < 10; i++) {
730                 udelay(1);
731                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
732                 if (!(ctrl & IXGBE_CTRL_RST))
733                         break;
734         }
735         if (ctrl & IXGBE_CTRL_RST) {
736                 status = IXGBE_ERR_RESET_FAILED;
737                 hw_dbg(hw, "Reset polling failed to complete.\n");
738         }
739         /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
740         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
741         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
742         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
743
744         msleep(50);
745
746
747
748         /*
749          * Store the original AUTOC/AUTOC2 values if they have not been
750          * stored off yet.  Otherwise restore the stored original
751          * values since the reset operation sets back to defaults.
752          */
753         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
754         autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
755         if (hw->mac.orig_link_settings_stored == false) {
756                 hw->mac.orig_autoc = autoc;
757                 hw->mac.orig_autoc2 = autoc2;
758                 hw->mac.orig_link_settings_stored = true;
759         } else {
760                 if (autoc != hw->mac.orig_autoc)
761                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
762                                         IXGBE_AUTOC_AN_RESTART));
763
764                 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
765                     (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
766                         autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
767                         autoc2 |= (hw->mac.orig_autoc2 &
768                                    IXGBE_AUTOC2_UPPER_MASK);
769                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
770                 }
771         }
772
773         /* Store the permanent mac address */
774         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
775
776         return status;
777 }
778
779 /**
780  *  ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
781  *  @hw: pointer to hardware struct
782  *  @rar: receive address register index to disassociate
783  *  @vmdq: VMDq pool index to remove from the rar
784  **/
785 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
786 {
787         u32 mpsar_lo, mpsar_hi;
788         u32 rar_entries = hw->mac.num_rar_entries;
789
790         if (rar < rar_entries) {
791                 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
792                 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
793
794                 if (!mpsar_lo && !mpsar_hi)
795                         goto done;
796
797                 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
798                         if (mpsar_lo) {
799                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
800                                 mpsar_lo = 0;
801                         }
802                         if (mpsar_hi) {
803                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
804                                 mpsar_hi = 0;
805                         }
806                 } else if (vmdq < 32) {
807                         mpsar_lo &= ~(1 << vmdq);
808                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
809                 } else {
810                         mpsar_hi &= ~(1 << (vmdq - 32));
811                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
812                 }
813
814                 /* was that the last pool using this rar? */
815                 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
816                         hw->mac.ops.clear_rar(hw, rar);
817         } else {
818                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
819         }
820
821 done:
822         return 0;
823 }
824
825 /**
826  *  ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
827  *  @hw: pointer to hardware struct
828  *  @rar: receive address register index to associate with a VMDq index
829  *  @vmdq: VMDq pool index
830  **/
831 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
832 {
833         u32 mpsar;
834         u32 rar_entries = hw->mac.num_rar_entries;
835
836         if (rar < rar_entries) {
837                 if (vmdq < 32) {
838                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
839                         mpsar |= 1 << vmdq;
840                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
841                 } else {
842                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
843                         mpsar |= 1 << (vmdq - 32);
844                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
845                 }
846         } else {
847                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
848         }
849         return 0;
850 }
851
852 /**
853  *  ixgbe_set_vfta_82599 - Set VLAN filter table
854  *  @hw: pointer to hardware structure
855  *  @vlan: VLAN id to write to VLAN filter
856  *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
857  *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
858  *
859  *  Turn on/off specified VLAN in the VLAN filter table.
860  **/
861 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
862                          bool vlan_on)
863 {
864         u32 regindex;
865         u32 bitindex;
866         u32 bits;
867         u32 first_empty_slot;
868
869         if (vlan > 4095)
870                 return IXGBE_ERR_PARAM;
871
872         /*
873          * this is a 2 part operation - first the VFTA, then the
874          * VLVF and VLVFB if vind is set
875          */
876
877         /* Part 1
878          * The VFTA is a bitstring made up of 128 32-bit registers
879          * that enable the particular VLAN id, much like the MTA:
880          *    bits[11-5]: which register
881          *    bits[4-0]:  which bit in the register
882          */
883         regindex = (vlan >> 5) & 0x7F;
884         bitindex = vlan & 0x1F;
885         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
886         if (vlan_on)
887                 bits |= (1 << bitindex);
888         else
889                 bits &= ~(1 << bitindex);
890         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
891
892
893         /* Part 2
894          * If the vind is set
895          *   Either vlan_on
896          *     make sure the vlan is in VLVF
897          *     set the vind bit in the matching VLVFB
898          *   Or !vlan_on
899          *     clear the pool bit and possibly the vind
900          */
901         if (vind) {
902                 /* find the vlanid or the first empty slot */
903                 first_empty_slot = 0;
904
905                 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
906                         bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
907                         if (!bits && !first_empty_slot)
908                                 first_empty_slot = regindex;
909                         else if ((bits & 0x0FFF) == vlan)
910                                 break;
911                 }
912
913                 if (regindex >= IXGBE_VLVF_ENTRIES) {
914                         if (first_empty_slot)
915                                 regindex = first_empty_slot;
916                         else {
917                                 hw_dbg(hw, "No space in VLVF.\n");
918                                 goto out;
919                         }
920                 }
921
922                 if (vlan_on) {
923                         /* set the pool bit */
924                         if (vind < 32) {
925                                 bits = IXGBE_READ_REG(hw,
926                                                     IXGBE_VLVFB(regindex * 2));
927                                 bits |= (1 << vind);
928                                 IXGBE_WRITE_REG(hw,
929                                               IXGBE_VLVFB(regindex * 2), bits);
930                         } else {
931                                 bits = IXGBE_READ_REG(hw,
932                                               IXGBE_VLVFB((regindex * 2) + 1));
933                                 bits |= (1 << vind);
934                                 IXGBE_WRITE_REG(hw,
935                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
936                         }
937                 } else {
938                         /* clear the pool bit */
939                         if (vind < 32) {
940                                 bits = IXGBE_READ_REG(hw,
941                                      IXGBE_VLVFB(regindex * 2));
942                         bits &= ~(1 << vind);
943                                 IXGBE_WRITE_REG(hw,
944                                               IXGBE_VLVFB(regindex * 2), bits);
945                                 bits |= IXGBE_READ_REG(hw,
946                                               IXGBE_VLVFB((regindex * 2) + 1));
947                         } else {
948                                 bits = IXGBE_READ_REG(hw,
949                                               IXGBE_VLVFB((regindex * 2) + 1));
950                                 bits &= ~(1 << vind);
951                                 IXGBE_WRITE_REG(hw,
952                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
953                                 bits |= IXGBE_READ_REG(hw,
954                                                     IXGBE_VLVFB(regindex * 2));
955                         }
956                 }
957
958                 if (bits)
959                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
960                                         (IXGBE_VLVF_VIEN | vlan));
961                 else
962                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
963         }
964
965 out:
966         return 0;
967 }
968
969 /**
970  *  ixgbe_clear_vfta_82599 - Clear VLAN filter table
971  *  @hw: pointer to hardware structure
972  *
973  *  Clears the VLAN filer table, and the VMDq index associated with the filter
974  **/
975 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
976 {
977         u32 offset;
978
979         for (offset = 0; offset < hw->mac.vft_size; offset++)
980                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
981
982         for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
983                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
984                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
985                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
986         }
987
988         return 0;
989 }
990
991 /**
992  *  ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
993  *  @hw: pointer to hardware structure
994  **/
995 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
996 {
997         int i;
998         hw_dbg(hw, " Clearing UTA\n");
999
1000         for (i = 0; i < 128; i++)
1001                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1002
1003         return 0;
1004 }
1005
1006 /**
1007  *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1008  *  @hw: pointer to hardware structure
1009  *  @reg: analog register to read
1010  *  @val: read value
1011  *
1012  *  Performs read operation to Omer analog register specified.
1013  **/
1014 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1015 {
1016         u32  core_ctl;
1017
1018         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1019                         (reg << 8));
1020         IXGBE_WRITE_FLUSH(hw);
1021         udelay(10);
1022         core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1023         *val = (u8)core_ctl;
1024
1025         return 0;
1026 }
1027
1028 /**
1029  *  ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1030  *  @hw: pointer to hardware structure
1031  *  @reg: atlas register to write
1032  *  @val: value to write
1033  *
1034  *  Performs write operation to Omer analog register specified.
1035  **/
1036 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1037 {
1038         u32  core_ctl;
1039
1040         core_ctl = (reg << 8) | val;
1041         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1042         IXGBE_WRITE_FLUSH(hw);
1043         udelay(10);
1044
1045         return 0;
1046 }
1047
1048 /**
1049  *  ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1050  *  @hw: pointer to hardware structure
1051  *
1052  *  Starts the hardware using the generic start_hw function.
1053  *  Then performs device-specific:
1054  *  Clears the rate limiter registers.
1055  **/
1056 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1057 {
1058         u32 q_num;
1059
1060         ixgbe_start_hw_generic(hw);
1061
1062         /* Clear the rate limiters */
1063         for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1064                 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1065                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1066         }
1067         IXGBE_WRITE_FLUSH(hw);
1068
1069         return 0;
1070 }
1071
1072 /**
1073  *  ixgbe_identify_phy_82599 - Get physical layer module
1074  *  @hw: pointer to hardware structure
1075  *
1076  *  Determines the physical layer module found on the current adapter.
1077  **/
1078 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1079 {
1080         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1081         status = ixgbe_identify_phy_generic(hw);
1082         if (status != 0)
1083                 status = ixgbe_identify_sfp_module_generic(hw);
1084         return status;
1085 }
1086
1087 /**
1088  *  ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1089  *  @hw: pointer to hardware structure
1090  *
1091  *  Determines physical layer capabilities of the current configuration.
1092  **/
1093 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1094 {
1095         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1096         u8 comp_codes_10g = 0;
1097
1098         switch (hw->device_id) {
1099         case IXGBE_DEV_ID_82599:
1100         case IXGBE_DEV_ID_82599_KX4:
1101                 /* Default device ID is mezzanine card KX/KX4 */
1102                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1103                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1104                 break;
1105         case IXGBE_DEV_ID_82599_SFP:
1106                 hw->phy.ops.identify_sfp(hw);
1107
1108                 switch (hw->phy.sfp_type) {
1109                 case ixgbe_sfp_type_da_cu:
1110                 case ixgbe_sfp_type_da_cu_core0:
1111                 case ixgbe_sfp_type_da_cu_core1:
1112                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1113                         break;
1114                 case ixgbe_sfp_type_sr:
1115                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1116                         break;
1117                 case ixgbe_sfp_type_lr:
1118                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1119                         break;
1120                 case ixgbe_sfp_type_srlr_core0:
1121                 case ixgbe_sfp_type_srlr_core1:
1122                         hw->phy.ops.read_i2c_eeprom(hw,
1123                                                     IXGBE_SFF_10GBE_COMP_CODES,
1124                                                     &comp_codes_10g);
1125                         if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1126                                 physical_layer =
1127                                                 IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1128                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1129                                 physical_layer =
1130                                                 IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1131                         else
1132                                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1133                 default:
1134                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1135                         break;
1136                 }
1137                 break;
1138         default:
1139                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1140                 break;
1141         }
1142
1143         return physical_layer;
1144 }
1145
1146 /**
1147  *  ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1148  *  @hw: pointer to hardware structure
1149  *  @regval: register value to write to RXCTRL
1150  *
1151  *  Enables the Rx DMA unit for 82599
1152  **/
1153 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1154 {
1155 #define IXGBE_MAX_SECRX_POLL 30
1156         int i;
1157         int secrxreg;
1158
1159         /*
1160          * Workaround for 82599 silicon errata when enabling the Rx datapath.
1161          * If traffic is incoming before we enable the Rx unit, it could hang
1162          * the Rx DMA unit.  Therefore, make sure the security engine is
1163          * completely disabled prior to enabling the Rx unit.
1164          */
1165         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1166         secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1167         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1168         for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1169                 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1170                 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1171                         break;
1172                 else
1173                         udelay(10);
1174         }
1175
1176         /* For informational purposes only */
1177         if (i >= IXGBE_MAX_SECRX_POLL)
1178                 hw_dbg(hw, "Rx unit being enabled before security "
1179                        "path fully disabled.  Continuing with init.\n");
1180
1181         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1182         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1183         secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1184         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1185         IXGBE_WRITE_FLUSH(hw);
1186
1187         return 0;
1188 }
1189
1190 static struct ixgbe_mac_operations mac_ops_82599 = {
1191         .init_hw                = &ixgbe_init_hw_generic,
1192         .reset_hw               = &ixgbe_reset_hw_82599,
1193         .start_hw               = &ixgbe_start_hw_82599,
1194         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1195         .get_media_type         = &ixgbe_get_media_type_82599,
1196         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1197         .enable_rx_dma          = &ixgbe_enable_rx_dma_82599,
1198         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1199         .stop_adapter           = &ixgbe_stop_adapter_generic,
1200         .get_bus_info           = &ixgbe_get_bus_info_generic,
1201         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1202         .read_analog_reg8       = &ixgbe_read_analog_reg8_82599,
1203         .write_analog_reg8      = &ixgbe_write_analog_reg8_82599,
1204         .setup_link             = &ixgbe_setup_mac_link_82599,
1205         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82599,
1206         .check_link             = &ixgbe_check_mac_link_82599,
1207         .get_link_capabilities  = &ixgbe_get_link_capabilities_82599,
1208         .led_on                 = &ixgbe_led_on_generic,
1209         .led_off                = &ixgbe_led_off_generic,
1210         .blink_led_start        = &ixgbe_blink_led_start_generic,
1211         .blink_led_stop         = &ixgbe_blink_led_stop_generic,
1212         .set_rar                = &ixgbe_set_rar_generic,
1213         .clear_rar              = &ixgbe_clear_rar_generic,
1214         .set_vmdq               = &ixgbe_set_vmdq_82599,
1215         .clear_vmdq             = &ixgbe_clear_vmdq_82599,
1216         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1217         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1218         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1219         .enable_mc              = &ixgbe_enable_mc_generic,
1220         .disable_mc             = &ixgbe_disable_mc_generic,
1221         .clear_vfta             = &ixgbe_clear_vfta_82599,
1222         .set_vfta               = &ixgbe_set_vfta_82599,
1223         .setup_fc               = &ixgbe_setup_fc_generic,
1224         .init_uta_tables        = &ixgbe_init_uta_tables_82599,
1225         .setup_sfp              = &ixgbe_setup_sfp_modules_82599,
1226 };
1227
1228 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1229         .init_params            = &ixgbe_init_eeprom_params_generic,
1230         .read                   = &ixgbe_read_eeprom_generic,
1231         .write                  = &ixgbe_write_eeprom_generic,
1232         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1233         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1234 };
1235
1236 static struct ixgbe_phy_operations phy_ops_82599 = {
1237         .identify               = &ixgbe_identify_phy_82599,
1238         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1239         .reset                  = &ixgbe_reset_phy_generic,
1240         .read_reg               = &ixgbe_read_phy_reg_generic,
1241         .write_reg              = &ixgbe_write_phy_reg_generic,
1242         .setup_link             = &ixgbe_setup_phy_link_generic,
1243         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1244         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
1245         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
1246         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
1247         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
1248 };
1249
1250 struct ixgbe_info ixgbe_82599_info = {
1251         .mac                    = ixgbe_mac_82599EB,
1252         .get_invariants         = &ixgbe_get_invariants_82599,
1253         .mac_ops                = &mac_ops_82599,
1254         .eeprom_ops             = &eeprom_ops_82599,
1255         .phy_ops                = &phy_ops_82599,
1256 };