3 * Purpose: assembly portion of the IA64 MCA handling
5 * Mods by cfleck to integrate into kernel build
7 * 2000-03-15 David Mosberger-Tang <davidm@hpl.hp.com>
8 * Added various stop bits to get a clean compile
10 * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
11 * Added code to save INIT handoff state in pt_regs format,
12 * switch to temp kstack, switch modes, jump to C INIT handler
14 * 2002-01-04 J.Hall <jenna.s.hall@intel.com>
15 * Before entering virtual mode code:
16 * 1. Check for TLB CPU error
17 * 2. Restore current thread pointer to kr6
18 * 3. Move stack ptr 16 bytes to conform to C calling convention
20 * 2004-11-12 Russ Anderson <rja@sgi.com>
21 * Added per cpu MCA/INIT stack save areas.
23 * 2005-12-08 Keith Owens <kaos@sgi.com>
24 * Use per cpu MCA/INIT stacks for all data.
26 #include <linux/threads.h>
28 #include <asm/asmmacro.h>
29 #include <asm/pgtable.h>
30 #include <asm/processor.h>
31 #include <asm/mca_asm.h>
36 #define GET_IA64_MCA_DATA(reg) \
37 GET_THIS_PADDR(reg, ia64_mca_data) \
41 .global ia64_do_tlb_purge
42 .global ia64_os_mca_dispatch
43 .global ia64_os_init_dispatch_monarch
44 .global ia64_os_init_dispatch_slave
49 //StartMain////////////////////////////////////////////////////////////////////
52 * Just the TLB purge part is moved to a separate function
53 * so we can re-use the code for cpu hotplug code as well
54 * Caller should now setup b1, so we can branch once the
55 * tlb flush is complete.
59 #define O(member) IA64_CPUINFO_##member##_OFFSET
61 GET_THIS_PADDR(r2, cpu_info) // load phys addr of cpu_info into r2
63 addl r17=O(PTCE_STRIDE),r2
64 addl r2=O(PTCE_BASE),r2
66 ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
67 ld4 r19=[r2],4 // r19=ptce_count[0]
68 ld4 r21=[r17],4 // r21=ptce_stride[0]
70 ld4 r20=[r2] // r20=ptce_count[1]
71 ld4 r22=[r17] // r22=ptce_stride[1]
80 (p7) br.cond.dpnt.few 4f
93 srlz.i // srlz.i implies srlz.d
96 // Now purge addresses formerly mapped by TR registers
97 // 1. Purge ITR&DTR for kernel.
99 mov r18=KERNEL_TR_PAGE_SHIFT<<2
108 // 3. Purge ITR for PAL code.
109 GET_THIS_PADDR(r2, ia64_mca_pal_base)
112 mov r18=IA64_GRANULE_SHIFT<<2
118 // 4. Purge DTR for stack.
119 mov r16=IA64_KR(CURRENT_STACK)
121 shl r16=r16,IA64_GRANULE_SHIFT
125 mov r18=IA64_GRANULE_SHIFT<<2
131 // Now branch away to caller.
135 //EndMain//////////////////////////////////////////////////////////////////////
137 //StartMain////////////////////////////////////////////////////////////////////
139 ia64_os_mca_dispatch:
140 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
141 LOAD_PHYSICAL(p0,r2,1f) // return address
142 mov r19=1 // All MCA events are treated as monarch (for now)
143 br.sptk ia64_state_save // save the state that is not in minstate
146 GET_IA64_MCA_DATA(r2)
147 // Using MCA stack, struct ia64_sal_os_state, variable proc_state_param
149 add r3=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET+SOS(PROC_STATE_PARAM), r2
151 ld8 r18=[r3] // Get processor state parameter on existing PALE_CHECK.
154 (p7) br.spnt done_tlb_purge_and_reload
156 // The following code purges TC and TR entries. Then reload all TC entries.
157 // Purge percpu data TC entries.
158 begin_tlb_purge_and_reload:
159 movl r18=ia64_reload_tr;;
160 LOAD_PHYSICAL(p0,r18,ia64_reload_tr);;
162 br.sptk.many ia64_do_tlb_purge;;
165 // Finally reload the TR registers.
166 // 1. Reload DTR/ITR registers for kernel.
167 mov r18=KERNEL_TR_PAGE_SHIFT<<2
168 movl r17=KERNEL_START
172 mov r16=IA64_TR_KERNEL
176 dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT
187 // 3. Reload ITR for PAL code.
188 GET_THIS_PADDR(r2, ia64_mca_pal_pte)
190 ld8 r18=[r2] // load PAL PTE
192 GET_THIS_PADDR(r2, ia64_mca_pal_base)
194 ld8 r16=[r2] // load PAL vaddr
195 mov r19=IA64_GRANULE_SHIFT<<2
199 mov r20=IA64_TR_PALCODE
205 // 4. Reload DTR for stack.
206 mov r16=IA64_KR(CURRENT_STACK)
208 shl r16=r16,IA64_GRANULE_SHIFT
215 mov r19=IA64_GRANULE_SHIFT<<2
219 mov r20=IA64_TR_CURRENT_STACK
225 done_tlb_purge_and_reload:
227 // switch to per cpu MCA stack
228 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
229 LOAD_PHYSICAL(p0,r2,1f) // return address
230 br.sptk ia64_new_stack
233 // everything saved, now we can set the kernel registers
234 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
235 LOAD_PHYSICAL(p0,r2,1f) // return address
236 br.sptk ia64_set_kernel_registers
239 // This must be done in physical mode
240 GET_IA64_MCA_DATA(r2)
244 // Enter virtual mode from physical mode
245 VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
247 // This code returns to SAL via SOS r2, in general SAL has no unwind
248 // data. To get a clean termination when backtracing the C MCA/INIT
249 // handler, set a dummy return address of 0 in this routine. That
250 // requires that ia64_os_mca_virtual_begin be a global function.
251 ENTRY(ia64_os_mca_virtual_begin)
256 mov ar.rsc=3 // set eager mode for C handler
257 mov r2=r7 // see GET_IA64_MCA_DATA above
260 // Call virtual mode handler
261 alloc r14=ar.pfs,0,0,3,0
265 add out0=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2
266 add out1=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2
267 add out2=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET, r2
268 br.call.sptk.many b0=ia64_mca_handler
270 // Revert back to physical mode before going back to SAL
271 PHYSICAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_end, r4)
272 ia64_os_mca_virtual_end:
274 END(ia64_os_mca_virtual_begin)
276 // switch back to previous stack
277 alloc r14=ar.pfs,0,0,0,0 // remove the MCA handler frame
278 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
279 LOAD_PHYSICAL(p0,r2,1f) // return address
280 br.sptk ia64_old_stack
283 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
284 LOAD_PHYSICAL(p0,r2,1f) // return address
285 br.sptk ia64_state_restore // restore the SAL state
288 mov b0=r12 // SAL_CHECK return address
292 //EndMain//////////////////////////////////////////////////////////////////////
294 //StartMain////////////////////////////////////////////////////////////////////
297 // SAL to OS entry point for INIT on all processors. This has been defined for
298 // registration purposes with SAL as a part of ia64_mca_init. Monarch and
299 // slave INIT have identical processing, except for the value of the
300 // sos->monarch flag in r19.
303 ia64_os_init_dispatch_monarch:
304 mov r19=1 // Bow, bow, ye lower middle classes!
305 br.sptk ia64_os_init_dispatch
307 ia64_os_init_dispatch_slave:
308 mov r19=0 // <igor>yeth, mathter</igor>
310 ia64_os_init_dispatch:
312 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
313 LOAD_PHYSICAL(p0,r2,1f) // return address
314 br.sptk ia64_state_save // save the state that is not in minstate
317 // switch to per cpu INIT stack
318 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
319 LOAD_PHYSICAL(p0,r2,1f) // return address
320 br.sptk ia64_new_stack
323 // everything saved, now we can set the kernel registers
324 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
325 LOAD_PHYSICAL(p0,r2,1f) // return address
326 br.sptk ia64_set_kernel_registers
329 // This must be done in physical mode
330 GET_IA64_MCA_DATA(r2)
334 // Enter virtual mode from physical mode
335 VIRTUAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_begin, r4)
337 // This code returns to SAL via SOS r2, in general SAL has no unwind
338 // data. To get a clean termination when backtracing the C MCA/INIT
339 // handler, set a dummy return address of 0 in this routine. That
340 // requires that ia64_os_init_virtual_begin be a global function.
341 ENTRY(ia64_os_init_virtual_begin)
346 mov ar.rsc=3 // set eager mode for C handler
347 mov r2=r7 // see GET_IA64_MCA_DATA above
350 // Call virtual mode handler
351 alloc r14=ar.pfs,0,0,3,0
355 add out0=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2
356 add out1=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2
357 add out2=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SOS_OFFSET, r2
358 br.call.sptk.many b0=ia64_init_handler
360 // Revert back to physical mode before going back to SAL
361 PHYSICAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_end, r4)
362 ia64_os_init_virtual_end:
364 END(ia64_os_init_virtual_begin)
366 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
367 LOAD_PHYSICAL(p0,r2,1f) // return address
368 br.sptk ia64_state_restore // restore the SAL state
371 // switch back to previous stack
372 alloc r14=ar.pfs,0,0,0,0 // remove the INIT handler frame
373 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
374 LOAD_PHYSICAL(p0,r2,1f) // return address
375 br.sptk ia64_old_stack
378 mov b0=r12 // SAL_CHECK return address
381 //EndMain//////////////////////////////////////////////////////////////////////
383 // common defines for the stubs
386 #define temp1 r2 /* careful, it overlaps with input registers */
387 #define temp2 r3 /* careful, it overlaps with input registers */
398 // Save the state that is not in minstate. This is sensitive to the layout of
399 // struct ia64_sal_os_state in mca.h.
401 // r2 contains the return address, r3 contains either
402 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
404 // The OS to SAL section of struct ia64_sal_os_state is set to a default
405 // value of cold boot (MCA) or warm boot (INIT) and return to the same
406 // context. ia64_sal_os_state is also used to hold some registers that
407 // need to be saved and restored across the stack switches.
409 // Most input registers to this stub come from PAL/SAL
410 // r1 os gp, physical
411 // r8 pal_proc entry point
412 // r9 sal_proc entry point
414 // r11 MCA - rendevzous state, INIT - reason code
415 // r12 sal return address
417 // r18 processor state parameter
418 // r19 monarch flag, set by the caller of this routine
420 // In addition to the SAL to OS state, this routine saves all the
421 // registers that appear in struct pt_regs and struct switch_stack,
422 // excluding those that are already in the PAL minstate area. This
423 // results in a partial pt_regs and switch_stack, the C code copies the
424 // remaining registers from PAL minstate to pt_regs and switch_stack. The
425 // resulting structures contain all the state of the original process when
426 // MCA/INIT occurred.
431 add regs=MCA_SOS_OFFSET, r3
432 add ms=MCA_SOS_OFFSET+8, r3
433 mov b0=r2 // save return address
434 cmp.eq p1,p2=IA64_MCA_CPU_MCA_STACK_OFFSET, r3
436 GET_IA64_MCA_DATA(temp2)
438 add temp1=temp2, regs // struct ia64_sal_os_state on MCA or INIT stack
439 add temp2=temp2, ms // struct ia64_sal_os_state+8 on MCA or INIT stack
441 mov regs=temp1 // save the start of sos
442 st8 [temp1]=r1,16 // os_gp
443 st8 [temp2]=r8,16 // pal_proc
445 st8 [temp1]=r9,16 // sal_proc
446 st8 [temp2]=r11,16 // rv_rc
449 st8 [temp1]=r18 // proc_state_param
450 st8 [temp2]=r19 // monarch
451 mov r6=IA64_KR(CURRENT)
452 add temp1=SOS(SAL_RA), regs
453 add temp2=SOS(SAL_GP), regs
455 st8 [temp1]=r12,16 // sal_ra
456 st8 [temp2]=r10,16 // sal_gp
459 st8 [temp1]=r17,16 // pal_min_state
460 st8 [temp2]=r6,16 // prev_IA64_KR_CURRENT
461 mov r6=IA64_KR(CURRENT_STACK)
463 st8 [temp1]=r6,16 // prev_IA64_KR_CURRENT_STACK
464 st8 [temp2]=r0,16 // prev_task, starts off as NULL
467 st8 [temp1]=r12,16 // cr.isr
468 st8 [temp2]=r6,16 // cr.ifa
471 st8 [temp1]=r12,16 // cr.itir
472 st8 [temp2]=r11,16 // cr.iipa
475 st8 [temp1]=r12 // cr.iim
476 (p1) mov r12=IA64_MCA_COLD_BOOT
477 (p2) mov r12=IA64_INIT_WARM_BOOT
479 add temp1=SOS(OS_STATUS), regs
481 st8 [temp2]=r6 // cr.iha
482 add temp2=SOS(CONTEXT), regs
483 st8 [temp1]=r12 // os_status, default is cold boot
484 mov r6=IA64_MCA_SAME_CONTEXT
486 st8 [temp2]=r6 // context, default is same context
488 // Save the pt_regs data that is not in minstate. The previous code
490 add regs=MCA_PT_REGS_OFFSET-MCA_SOS_OFFSET, regs
492 add temp1=PT(B6), regs
495 add temp2=PT(B7), regs
497 st8 [temp1]=temp3,PT(AR_CSD)-PT(B6) // save b6
498 st8 [temp2]=temp4,PT(AR_SSD)-PT(B7) // save b7
501 cover // must be last in group
503 st8 [temp1]=temp3,PT(AR_UNAT)-PT(AR_CSD) // save ar.csd
504 st8 [temp2]=temp4,PT(AR_PFS)-PT(AR_SSD) // save ar.ssd
508 st8 [temp1]=temp3,PT(AR_RNAT)-PT(AR_UNAT) // save ar.unat
509 st8 [temp2]=temp4,PT(AR_BSPSTORE)-PT(AR_PFS) // save ar.pfs
511 mov temp4=ar.bspstore
513 st8 [temp1]=temp3,PT(LOADRS)-PT(AR_RNAT) // save ar.rnat
514 st8 [temp2]=temp4,PT(AR_FPSR)-PT(AR_BSPSTORE) // save ar.bspstore
517 sub temp3=temp3, temp4 // ar.bsp - ar.bspstore
520 shl temp3=temp3,16 // compute ar.rsc to be used for "loadrs"
522 st8 [temp1]=temp3,PT(AR_CCV)-PT(LOADRS) // save loadrs
523 st8 [temp2]=temp4,PT(F6)-PT(AR_FPSR) // save ar.fpsr
526 st8 [temp1]=temp3,PT(F7)-PT(AR_CCV) // save ar.ccv
527 stf.spill [temp2]=f6,PT(F8)-PT(F6)
529 stf.spill [temp1]=f7,PT(F9)-PT(F7)
530 stf.spill [temp2]=f8,PT(F10)-PT(F8)
532 stf.spill [temp1]=f9,PT(F11)-PT(F9)
533 stf.spill [temp2]=f10
535 stf.spill [temp1]=f11
537 // Save the switch_stack data that is not in minstate nor pt_regs. The
538 // previous code left regs at pt_regs.
539 add regs=MCA_SWITCH_STACK_OFFSET-MCA_PT_REGS_OFFSET, regs
541 add temp1=SW(F2), regs
542 add temp2=SW(F3), regs
544 stf.spill [temp1]=f2,32
545 stf.spill [temp2]=f3,32
547 stf.spill [temp1]=f4,32
548 stf.spill [temp2]=f5,32
550 stf.spill [temp1]=f12,32
551 stf.spill [temp2]=f13,32
553 stf.spill [temp1]=f14,32
554 stf.spill [temp2]=f15,32
556 stf.spill [temp1]=f16,32
557 stf.spill [temp2]=f17,32
559 stf.spill [temp1]=f18,32
560 stf.spill [temp2]=f19,32
562 stf.spill [temp1]=f20,32
563 stf.spill [temp2]=f21,32
565 stf.spill [temp1]=f22,32
566 stf.spill [temp2]=f23,32
568 stf.spill [temp1]=f24,32
569 stf.spill [temp2]=f25,32
571 stf.spill [temp1]=f26,32
572 stf.spill [temp2]=f27,32
574 stf.spill [temp1]=f28,32
575 stf.spill [temp2]=f29,32
577 stf.spill [temp1]=f30,SW(B2)-SW(F30)
578 stf.spill [temp2]=f31,SW(B3)-SW(F31)
582 st8 [temp1]=temp3,16 // save b2
583 st8 [temp2]=temp4,16 // save b3
587 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
588 st8 [temp2]=temp4 // save b5
591 st8 [temp1]=temp3 // save ar.lc
593 // FIXME: Some proms are incorrectly accessing the minstate area as
594 // cached data. The C code uses region 6, uncached virtual. Ensure
595 // that there is no cache data lying around for the first 1K of the
597 // Remove this code in September 2006, that gives platforms a year to
598 // fix their proms and get their customers updated.
670 //EndStub//////////////////////////////////////////////////////////////////////
675 // ia64_state_restore()
679 // Restore the SAL/OS state. This is sensitive to the layout of struct
680 // ia64_sal_os_state in mca.h.
682 // r2 contains the return address, r3 contains either
683 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
685 // In addition to the SAL to OS state, this routine restores all the
686 // registers that appear in struct pt_regs and struct switch_stack,
687 // excluding those in the PAL minstate area.
692 // Restore the switch_stack data that is not in minstate nor pt_regs.
693 add regs=MCA_SWITCH_STACK_OFFSET, r3
694 mov b0=r2 // save return address
696 GET_IA64_MCA_DATA(temp2)
700 add temp1=SW(F2), regs
701 add temp2=SW(F3), regs
703 ldf.fill f2=[temp1],32
704 ldf.fill f3=[temp2],32
706 ldf.fill f4=[temp1],32
707 ldf.fill f5=[temp2],32
709 ldf.fill f12=[temp1],32
710 ldf.fill f13=[temp2],32
712 ldf.fill f14=[temp1],32
713 ldf.fill f15=[temp2],32
715 ldf.fill f16=[temp1],32
716 ldf.fill f17=[temp2],32
718 ldf.fill f18=[temp1],32
719 ldf.fill f19=[temp2],32
721 ldf.fill f20=[temp1],32
722 ldf.fill f21=[temp2],32
724 ldf.fill f22=[temp1],32
725 ldf.fill f23=[temp2],32
727 ldf.fill f24=[temp1],32
728 ldf.fill f25=[temp2],32
730 ldf.fill f26=[temp1],32
731 ldf.fill f27=[temp2],32
733 ldf.fill f28=[temp1],32
734 ldf.fill f29=[temp2],32
736 ldf.fill f30=[temp1],SW(B2)-SW(F30)
737 ldf.fill f31=[temp2],SW(B3)-SW(F31)
739 ld8 temp3=[temp1],16 // restore b2
740 ld8 temp4=[temp2],16 // restore b3
744 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
745 ld8 temp4=[temp2] // restore b5
749 ld8 temp3=[temp1] // restore ar.lc
753 // Restore the pt_regs data that is not in minstate. The previous code
754 // left regs at switch_stack.
755 add regs=MCA_PT_REGS_OFFSET-MCA_SWITCH_STACK_OFFSET, regs
757 add temp1=PT(B6), regs
758 add temp2=PT(B7), regs
760 ld8 temp3=[temp1],PT(AR_CSD)-PT(B6) // restore b6
761 ld8 temp4=[temp2],PT(AR_SSD)-PT(B7) // restore b7
765 ld8 temp3=[temp1],PT(AR_UNAT)-PT(AR_CSD) // restore ar.csd
766 ld8 temp4=[temp2],PT(AR_PFS)-PT(AR_SSD) // restore ar.ssd
770 ld8 temp3=[temp1] // restore ar.unat
771 add temp1=PT(AR_CCV)-PT(AR_UNAT), temp1
772 ld8 temp4=[temp2],PT(AR_FPSR)-PT(AR_PFS) // restore ar.pfs
776 // ar.rnat, ar.bspstore, loadrs are restore in ia64_old_stack.
777 ld8 temp3=[temp1],PT(F6)-PT(AR_CCV) // restore ar.ccv
778 ld8 temp4=[temp2],PT(F7)-PT(AR_FPSR) // restore ar.fpsr
782 ldf.fill f6=[temp1],PT(F8)-PT(F6)
783 ldf.fill f7=[temp2],PT(F9)-PT(F7)
785 ldf.fill f8=[temp1],PT(F10)-PT(F8)
786 ldf.fill f9=[temp2],PT(F11)-PT(F9)
791 // Restore the SAL to OS state. The previous code left regs at pt_regs.
792 add regs=MCA_SOS_OFFSET-MCA_PT_REGS_OFFSET, regs
794 add temp1=SOS(SAL_RA), regs
795 add temp2=SOS(SAL_GP), regs
797 ld8 r12=[temp1],16 // sal_ra
798 ld8 r9=[temp2],16 // sal_gp
800 ld8 r22=[temp1],16 // pal_min_state, virtual
801 ld8 r13=[temp2],16 // prev_IA64_KR_CURRENT
803 ld8 r16=[temp1],16 // prev_IA64_KR_CURRENT_STACK
804 ld8 r20=[temp2],16 // prev_task
806 ld8 temp3=[temp1],16 // cr.isr
807 ld8 temp4=[temp2],16 // cr.ifa
811 ld8 temp3=[temp1],16 // cr.itir
812 ld8 temp4=[temp2],16 // cr.iipa
816 ld8 temp3=[temp1] // cr.iim
817 ld8 temp4=[temp2] // cr.iha
818 add temp1=SOS(OS_STATUS), regs
819 add temp2=SOS(CONTEXT), regs
823 dep r22=0,r22,62,1 // pal_min_state, physical, uncached
824 mov IA64_KR(CURRENT)=r13
825 ld8 r8=[temp1] // os_status
826 ld8 r10=[temp2] // context
828 /* Wire IA64_TR_CURRENT_STACK to the stack that we are resuming to. To
829 * avoid any dependencies on the algorithm in ia64_switch_to(), just
830 * purge any existing CURRENT_STACK mapping and insert the new one.
832 * r16 contains prev_IA64_KR_CURRENT_STACK, r13 contains
833 * prev_IA64_KR_CURRENT, these values may have been changed by the C
834 * code. Do not use r8, r9, r10, r22, they contain values ready for
838 mov r15=IA64_KR(CURRENT_STACK) // physical granule mapped by IA64_TR_CURRENT_STACK
840 shl r15=r15,IA64_GRANULE_SHIFT
842 dep r15=-1,r15,61,3 // virtual granule
843 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps
849 extr.u r19=r13,61,3 // r13 = prev_IA64_KR_CURRENT
850 shl r20=r16,IA64_GRANULE_SHIFT // r16 = prev_IA64_KR_CURRENT_STACK
851 movl r21=PAGE_KERNEL // page properties
853 mov IA64_KR(CURRENT_STACK)=r16
854 cmp.ne p6,p0=RGN_KERNEL,r19 // new stack is in the kernel region?
855 or r21=r20,r21 // construct PA | page properties
856 (p6) br.spnt 1f // the dreaded cpu 0 idle task in region 5:(
860 mov r20=IA64_TR_CURRENT_STACK
869 //EndStub//////////////////////////////////////////////////////////////////////
878 // Switch to the MCA/INIT stack.
880 // r2 contains the return address, r3 contains either
881 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
883 // On entry RBS is still on the original stack, this routine switches RBS
884 // to use the MCA/INIT stack.
886 // On entry, sos->pal_min_state is physical, on exit it is virtual.
891 add regs=MCA_PT_REGS_OFFSET, r3
892 add temp2=MCA_SOS_OFFSET+SOS(PAL_MIN_STATE), r3
893 mov b0=r2 // save return address
894 GET_IA64_MCA_DATA(temp1)
897 add temp2=temp2, temp1 // struct ia64_sal_os_state.pal_min_state on MCA or INIT stack
898 add regs=regs, temp1 // struct pt_regs on MCA or INIT stack
900 // Address of minstate area provided by PAL is physical, uncacheable.
901 // Convert to Linux virtual address in region 6 for C code.
902 ld8 ms=[temp2] // pal_min_state, physical
904 dep temp1=-1,ms,62,2 // set region 6
905 mov temp3=IA64_RBS_OFFSET-MCA_PT_REGS_OFFSET
907 st8 [temp2]=temp1 // pal_min_state, virtual
909 add temp4=temp3, regs // start of bspstore on new stack
911 mov ar.bspstore=temp4 // switch RBS to MCA/INIT stack
913 flushrs // must be first in group
916 //EndStub//////////////////////////////////////////////////////////////////////
925 // Switch to the old stack.
927 // r2 contains the return address, r3 contains either
928 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
930 // On entry, pal_min_state is virtual, on exit it is physical.
932 // On entry RBS is on the MCA/INIT stack, this routine switches RBS
933 // back to the previous stack.
935 // The psr is set to all zeroes. SAL return requires either all zeroes or
936 // just psr.mc set. Leaving psr.mc off allows INIT to be issued if this
937 // code does not perform correctly.
939 // The dirty registers at the time of the event were flushed to the
940 // MCA/INIT stack in ia64_pt_regs_save(). Restore the dirty registers
941 // before reverting to the previous bspstore.
945 add regs=MCA_PT_REGS_OFFSET, r3
946 mov b0=r2 // save return address
947 GET_IA64_MCA_DATA(temp2)
948 LOAD_PHYSICAL(p0,temp1,1f)
958 add regs=regs, temp2 // struct pt_regs on MCA or INIT stack
960 add temp1=PT(LOADRS), regs
962 ld8 temp2=[temp1],PT(AR_BSPSTORE)-PT(LOADRS) // restore loadrs
964 ld8 temp3=[temp1],PT(AR_RNAT)-PT(AR_BSPSTORE) // restore ar.bspstore
968 ld8 temp4=[temp1] // restore ar.rnat
970 mov ar.bspstore=temp3 // back to old stack
977 //EndStub//////////////////////////////////////////////////////////////////////
982 // ia64_set_kernel_registers()
986 // Set the registers that are required by the C code in order to run on an
989 // r2 contains the return address, r3 contains either
990 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
994 ia64_set_kernel_registers:
995 add temp3=MCA_SP_OFFSET, r3
996 mov b0=r2 // save return address
997 GET_IA64_MCA_DATA(temp1)
999 add r12=temp1, temp3 // kernel stack pointer on MCA/INIT stack
1000 add r13=temp1, r3 // set current to start of MCA/INIT stack
1001 add r20=temp1, r3 // physical start of MCA/INIT stack
1003 DATA_PA_TO_VA(r12,temp2)
1004 DATA_PA_TO_VA(r13,temp3)
1006 mov IA64_KR(CURRENT)=r13
1008 /* Wire IA64_TR_CURRENT_STACK to the MCA/INIT handler stack. To avoid
1009 * any dependencies on the algorithm in ia64_switch_to(), just purge
1010 * any existing CURRENT_STACK mapping and insert the new one.
1013 mov r16=IA64_KR(CURRENT_STACK) // physical granule mapped by IA64_TR_CURRENT_STACK
1015 shl r16=r16,IA64_GRANULE_SHIFT
1017 dep r16=-1,r16,61,3 // virtual granule
1018 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps
1024 shr.u r16=r20,IA64_GRANULE_SHIFT // r20 = physical start of MCA/INIT stack
1025 movl r21=PAGE_KERNEL // page properties
1027 mov IA64_KR(CURRENT_STACK)=r16
1028 or r21=r20,r21 // construct PA | page properties
1032 mov r20=IA64_TR_CURRENT_STACK
1034 movl r17=FPSR_DEFAULT
1036 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
1044 //EndStub//////////////////////////////////////////////////////////////////////
1054 // Support function for mca.c, it is here to avoid using inline asm. Given the
1055 // address of an rnat slot, if that address is below the current ar.bspstore
1056 // then return the contents of that slot, otherwise return the contents of
1058 GLOBAL_ENTRY(ia64_get_rnat)
1059 alloc r14=ar.pfs,1,0,0,0
1064 cmp.lt p6,p7=in0,r14