git.oblomov.eu Git - linux-2.6/blob - drivers/spi/mpc52xx_psc_spi.c

   1 /*
   2  * MPC52xx PSC in SPI mode driver.
   3  *
   4  * Maintainer: Dragos Carp
   5  *
   6  * Copyright (C) 2006 TOPTICA Photonics AG.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/errno.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/workqueue.h>
  20 #include <linux/completion.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/fsl_devices.h>
  25
  26 #include <asm/mpc52xx.h>
  27 #include <asm/mpc52xx_psc.h>
  28
  29 #define MCLK 20000000 /* PSC port MClk in hz */
  30
  31 struct mpc52xx_psc_spi {
  32         /* fsl_spi_platform data */
  33         void (*activate_cs)(u8, u8);
  34         void (*deactivate_cs)(u8, u8);
  35         u32 sysclk;
  36
  37         /* driver internal data */
  38         struct mpc52xx_psc __iomem *psc;
  39         struct mpc52xx_psc_fifo __iomem *fifo;
  40         unsigned int irq;
  41         u8 bits_per_word;
  42         u8 busy;
  43
  44         struct workqueue_struct *workqueue;
  45         struct work_struct work;
  46
  47         struct list_head queue;
  48         spinlock_t lock;
  49
  50         struct completion done;
  51 };
  52
  53 /* controller state */
  54 struct mpc52xx_psc_spi_cs {
  55         int bits_per_word;
  56         int speed_hz;
  57 };
  58
  59 /* set clock freq, clock ramp, bits per work
  60  * if t is NULL then reset the values to the default values
  61  */
  62 static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
  63                 struct spi_transfer *t)
  64 {
  65         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  66
  67         cs->speed_hz = (t && t->speed_hz)
  68                         ? t->speed_hz : spi->max_speed_hz;
  69         cs->bits_per_word = (t && t->bits_per_word)
  70                         ? t->bits_per_word : spi->bits_per_word;
  71         cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  72         return 0;
  73 }
  74
  75 static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
  76 {
  77         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  78         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  79         struct mpc52xx_psc __iomem *psc = mps->psc;
  80         u32 sicr;
  81         u16 ccr;
  82
  83         sicr = in_be32(&psc->sicr);
  84
  85         /* Set clock phase and polarity */
  86         if (spi->mode & SPI_CPHA)
  87                 sicr |= 0x00001000;
  88         else
  89                 sicr &= ~0x00001000;
  90         if (spi->mode & SPI_CPOL)
  91                 sicr |= 0x00002000;
  92         else
  93                 sicr &= ~0x00002000;
  94
  95         if (spi->mode & SPI_LSB_FIRST)
  96                 sicr |= 0x10000000;
  97         else
  98                 sicr &= ~0x10000000;
  99         out_be32(&psc->sicr, sicr);
 100
 101         /* Set clock frequency and bits per word
 102          * Because psc->ccr is defined as 16bit register instead of 32bit
 103          * just set the lower byte of BitClkDiv
 104          */
 105         ccr = in_be16((u16 __iomem *)&psc->ccr);
 106         ccr &= 0xFF00;
 107         if (cs->speed_hz)
 108                 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
 109         else /* by default SPI Clk 1MHz */
 110                 ccr |= (MCLK / 1000000 - 1) & 0xFF;
 111         out_be16((u16 __iomem *)&psc->ccr, ccr);
 112         mps->bits_per_word = cs->bits_per_word;
 113
 114         if (mps->activate_cs)
 115                 mps->activate_cs(spi->chip_select,
 116                                 (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 117 }
 118
 119 static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
 120 {
 121         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 122
 123         if (mps->deactivate_cs)
 124                 mps->deactivate_cs(spi->chip_select,
 125                                 (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 126 }
 127
 128 #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
 129 /* wake up when 80% fifo full */
 130 #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
 131
 132 static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
 133                                                 struct spi_transfer *t)
 134 {
 135         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 136         struct mpc52xx_psc __iomem *psc = mps->psc;
 137         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 138         unsigned rb = 0;        /* number of bytes receieved */
 139         unsigned sb = 0;        /* number of bytes sent */
 140         unsigned char *rx_buf = (unsigned char *)t->rx_buf;
 141         unsigned char *tx_buf = (unsigned char *)t->tx_buf;
 142         unsigned rfalarm;
 143         unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
 144         unsigned recv_at_once;
 145
 146         if (!t->tx_buf && !t->rx_buf && t->len)
 147                 return -EINVAL;
 148
 149         /* enable transmiter/receiver */
 150         out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
 151         while (rb < t->len) {
 152                 if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
 153                         rfalarm = MPC52xx_PSC_RFALARM;
 154                 } else {
 155                         send_at_once = t->len - sb;
 156                         rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
 157                 }
 158
 159                 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
 160                 for (; send_at_once; sb++, send_at_once--) {
 161                         /* set EOF flag before the last word is sent */
 162                         if (send_at_once == 1)
 163                                 out_8(&psc->ircr2, 0x01);
 164
 165                         if (tx_buf)
 166                                 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
 167                         else
 168                                 out_8(&psc->mpc52xx_psc_buffer_8, 0);
 169                 }
 170
 171
 172                 /* enable interrupts and wait for wake up
 173                  * if just one byte is expected the Rx FIFO genererates no
 174                  * FFULL interrupt, so activate the RxRDY interrupt
 175                  */
 176                 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 177                 if (t->len - rb == 1) {
 178                         out_8(&psc->mode, 0);
 179                 } else {
 180                         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 181                         out_be16(&fifo->rfalarm, rfalarm);
 182                 }
 183                 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
 184                 wait_for_completion(&mps->done);
 185                 recv_at_once = in_be16(&fifo->rfnum);
 186                 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
 187
 188                 send_at_once = recv_at_once;
 189                 if (rx_buf) {
 190                         for (; recv_at_once; rb++, recv_at_once--)
 191                                 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
 192                 } else {
 193                         for (; recv_at_once; rb++, recv_at_once--)
 194                                 in_8(&psc->mpc52xx_psc_buffer_8);
 195                 }
 196         }
 197         /* disable transmiter/receiver */
 198         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 199
 200         return 0;
 201 }
 202
 203 static void mpc52xx_psc_spi_work(struct work_struct *work)
 204 {
 205         struct mpc52xx_psc_spi *mps =
 206                 container_of(work, struct mpc52xx_psc_spi, work);
 207
 208         spin_lock_irq(&mps->lock);
 209         mps->busy = 1;
 210         while (!list_empty(&mps->queue)) {
 211                 struct spi_message *m;
 212                 struct spi_device *spi;
 213                 struct spi_transfer *t = NULL;
 214                 unsigned cs_change;
 215                 int status;
 216
 217                 m = container_of(mps->queue.next, struct spi_message, queue);
 218                 list_del_init(&m->queue);
 219                 spin_unlock_irq(&mps->lock);
 220
 221                 spi = m->spi;
 222                 cs_change = 1;
 223                 status = 0;
 224                 list_for_each_entry (t, &m->transfers, transfer_list) {
 225                         if (t->bits_per_word || t->speed_hz) {
 226                                 status = mpc52xx_psc_spi_transfer_setup(spi, t);
 227                                 if (status < 0)
 228                                         break;
 229                         }
 230
 231                         if (cs_change)
 232                                 mpc52xx_psc_spi_activate_cs(spi);
 233                         cs_change = t->cs_change;
 234
 235                         status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
 236                         if (status)
 237                                 break;
 238                         m->actual_length += t->len;
 239
 240                         if (t->delay_usecs)
 241                                 udelay(t->delay_usecs);
 242
 243                         if (cs_change)
 244                                 mpc52xx_psc_spi_deactivate_cs(spi);
 245                 }
 246
 247                 m->status = status;
 248                 m->complete(m->context);
 249
 250                 if (status || !cs_change)
 251                         mpc52xx_psc_spi_deactivate_cs(spi);
 252
 253                 mpc52xx_psc_spi_transfer_setup(spi, NULL);
 254
 255                 spin_lock_irq(&mps->lock);
 256         }
 257         mps->busy = 0;
 258         spin_unlock_irq(&mps->lock);
 259 }
 260
 261 /* the spi->mode bits understood by this driver: */
 262 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST)
 263
 264 static int mpc52xx_psc_spi_setup(struct spi_device *spi)
 265 {
 266         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 267         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
 268         unsigned long flags;
 269
 270         if (spi->bits_per_word%8)
 271                 return -EINVAL;
 272
 273         if (spi->mode & ~MODEBITS) {
 274                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 275                         spi->mode & ~MODEBITS);
 276                 return -EINVAL;
 277         }
 278
 279         if (!cs) {
 280                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 281                 if (!cs)
 282                         return -ENOMEM;
 283                 spi->controller_state = cs;
 284         }
 285
 286         cs->bits_per_word = spi->bits_per_word;
 287         cs->speed_hz = spi->max_speed_hz;
 288
 289         spin_lock_irqsave(&mps->lock, flags);
 290         if (!mps->busy)
 291                 mpc52xx_psc_spi_deactivate_cs(spi);
 292         spin_unlock_irqrestore(&mps->lock, flags);
 293
 294         return 0;
 295 }
 296
 297 static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
 298                 struct spi_message *m)
 299 {
 300         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 301         unsigned long flags;
 302
 303         m->actual_length = 0;
 304         m->status = -EINPROGRESS;
 305
 306         spin_lock_irqsave(&mps->lock, flags);
 307         list_add_tail(&m->queue, &mps->queue);
 308         queue_work(mps->workqueue, &mps->work);
 309         spin_unlock_irqrestore(&mps->lock, flags);
 310
 311         return 0;
 312 }
 313
 314 static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
 315 {
 316         kfree(spi->controller_state);
 317 }
 318
 319 static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
 320 {
 321         struct mpc52xx_psc __iomem *psc = mps->psc;
 322         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 323         u32 mclken_div;
 324         int ret = 0;
 325
 326         /* default sysclk is 512MHz */
 327         mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
 328         mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
 329
 330         /* Reset the PSC into a known state */
 331         out_8(&psc->command, MPC52xx_PSC_RST_RX);
 332         out_8(&psc->command, MPC52xx_PSC_RST_TX);
 333         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 334
 335         /* Disable interrupts, interrupts are based on alarm level */
 336         out_be16(&psc->mpc52xx_psc_imr, 0);
 337         out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 338         out_8(&fifo->rfcntl, 0);
 339         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 340
 341         /* Configure 8bit codec mode as a SPI master and use EOF flags */
 342         /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
 343         out_be32(&psc->sicr, 0x0180C800);
 344         out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
 345
 346         /* Set 2ms DTL delay */
 347         out_8(&psc->ctur, 0x00);
 348         out_8(&psc->ctlr, 0x84);
 349
 350         mps->bits_per_word = 8;
 351
 352         return ret;
 353 }
 354
 355 static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
 356 {
 357         struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
 358         struct mpc52xx_psc __iomem *psc = mps->psc;
 359
 360         /* disable interrupt and wake up the work queue */
 361         if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
 362                 out_be16(&psc->mpc52xx_psc_imr, 0);
 363                 complete(&mps->done);
 364                 return IRQ_HANDLED;
 365         }
 366         return IRQ_NONE;
 367 }
 368
 369 /* bus_num is used only for the case dev->platform_data == NULL */
 370 static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
 371                                 u32 size, unsigned int irq, s16 bus_num)
 372 {
 373         struct fsl_spi_platform_data *pdata = dev->platform_data;
 374         struct mpc52xx_psc_spi *mps;
 375         struct spi_master *master;
 376         int ret;
 377
 378         master = spi_alloc_master(dev, sizeof *mps);
 379         if (master == NULL)
 380                 return -ENOMEM;
 381
 382         dev_set_drvdata(dev, master);
 383         mps = spi_master_get_devdata(master);
 384
 385         mps->irq = irq;
 386         if (pdata == NULL) {
 387                 dev_warn(dev, "probe called without platform data, no "
 388                                 "(de)activate_cs function will be called\n");
 389                 mps->activate_cs = NULL;
 390                 mps->deactivate_cs = NULL;
 391                 mps->sysclk = 0;
 392                 master->bus_num = bus_num;
 393                 master->num_chipselect = 255;
 394         } else {
 395                 mps->activate_cs = pdata->activate_cs;
 396                 mps->deactivate_cs = pdata->deactivate_cs;
 397                 mps->sysclk = pdata->sysclk;
 398                 master->bus_num = pdata->bus_num;
 399                 master->num_chipselect = pdata->max_chipselect;
 400         }
 401         master->setup = mpc52xx_psc_spi_setup;
 402         master->transfer = mpc52xx_psc_spi_transfer;
 403         master->cleanup = mpc52xx_psc_spi_cleanup;
 404
 405         mps->psc = ioremap(regaddr, size);
 406         if (!mps->psc) {
 407                 dev_err(dev, "could not ioremap I/O port range\n");
 408                 ret = -EFAULT;
 409                 goto free_master;
 410         }
 411         /* On the 5200, fifo regs are immediately ajacent to the psc regs */
 412         mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
 413
 414         ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
 415                                 mps);
 416         if (ret)
 417                 goto free_master;
 418
 419         ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
 420         if (ret < 0)
 421                 goto free_irq;
 422
 423         spin_lock_init(&mps->lock);
 424         init_completion(&mps->done);
 425         INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
 426         INIT_LIST_HEAD(&mps->queue);
 427
 428         mps->workqueue = create_singlethread_workqueue(
 429                 master->dev.parent->bus_id);
 430         if (mps->workqueue == NULL) {
 431                 ret = -EBUSY;
 432                 goto free_irq;
 433         }
 434
 435         ret = spi_register_master(master);
 436         if (ret < 0)
 437                 goto unreg_master;
 438
 439         return ret;
 440
 441 unreg_master:
 442         destroy_workqueue(mps->workqueue);
 443 free_irq:
 444         free_irq(mps->irq, mps);
 445 free_master:
 446         if (mps->psc)
 447                 iounmap(mps->psc);
 448         spi_master_put(master);
 449
 450         return ret;
 451 }
 452
 453 static int __exit mpc52xx_psc_spi_do_remove(struct device *dev)
 454 {
 455         struct spi_master *master = dev_get_drvdata(dev);
 456         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
 457
 458         flush_workqueue(mps->workqueue);
 459         destroy_workqueue(mps->workqueue);
 460         spi_unregister_master(master);
 461         free_irq(mps->irq, mps);
 462         if (mps->psc)
 463                 iounmap(mps->psc);
 464
 465         return 0;
 466 }
 467
 468 static int __init mpc52xx_psc_spi_of_probe(struct of_device *op,
 469         const struct of_device_id *match)
 470 {
 471         const u32 *regaddr_p;
 472         u64 regaddr64, size64;
 473         s16 id = -1;
 474
 475         regaddr_p = of_get_address(op->node, 0, &size64, NULL);
 476         if (!regaddr_p) {
 477                 printk(KERN_ERR "Invalid PSC address\n");
 478                 return -EINVAL;
 479         }
 480         regaddr64 = of_translate_address(op->node, regaddr_p);
 481
 482         /* get PSC id (1..6, used by port_config) */
 483         if (op->dev.platform_data == NULL) {
 484                 const u32 *psc_nump;
 485
 486                 psc_nump = of_get_property(op->node, "cell-index", NULL);
 487                 if (!psc_nump || *psc_nump > 5) {
 488                         printk(KERN_ERR "mpc52xx_psc_spi: Device node %s has invalid "
 489                                         "cell-index property\n", op->node->full_name);
 490                         return -EINVAL;
 491                 }
 492                 id = *psc_nump + 1;
 493         }
 494
 495         return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
 496                                         irq_of_parse_and_map(op->node, 0), id);
 497 }
 498
 499 static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op)
 500 {
 501         return mpc52xx_psc_spi_do_remove(&op->dev);
 502 }
 503
 504 static struct of_device_id mpc52xx_psc_spi_of_match[] = {
 505         { .compatible = "fsl,mpc5200-psc-spi", },
 506         { .compatible = "mpc5200-psc-spi", }, /* old */
 507         {}
 508 };
 509
 510 MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
 511
 512 static struct of_platform_driver mpc52xx_psc_spi_of_driver = {
 513         .owner = THIS_MODULE,
 514         .name = "mpc52xx-psc-spi",
 515         .match_table = mpc52xx_psc_spi_of_match,
 516         .probe = mpc52xx_psc_spi_of_probe,
 517         .remove = __exit_p(mpc52xx_psc_spi_of_remove),
 518         .driver = {
 519                 .name = "mpc52xx-psc-spi",
 520                 .owner = THIS_MODULE,
 521         },
 522 };
 523
 524 static int __init mpc52xx_psc_spi_init(void)
 525 {
 526         return of_register_platform_driver(&mpc52xx_psc_spi_of_driver);
 527 }
 528 module_init(mpc52xx_psc_spi_init);
 529
 530 static void __exit mpc52xx_psc_spi_exit(void)
 531 {
 532         of_unregister_platform_driver(&mpc52xx_psc_spi_of_driver);
 533 }
 534 module_exit(mpc52xx_psc_spi_exit);
 535
 536 MODULE_AUTHOR("Dragos Carp");
 537 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
 538 MODULE_LICENSE("GPL");