2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 * This driver is designed for the Broadcom SiByte SOC built-in
20 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <asm/processor.h> /* Processor type for cache alignment. */
37 #include <asm/cache.h>
39 /* This is only here until the firmware is ready. In that case,
40 the firmware leaves the ethernet address in the register for us. */
41 #ifdef CONFIG_SIBYTE_STANDALONE
42 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
43 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
44 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
45 #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
49 /* These identify the driver base version and may not be removed. */
51 static char version1[] __devinitdata =
52 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
56 /* Operational parameters that usually are not changed. */
58 #define CONFIG_SBMAC_COALESCE
60 #define MAX_UNITS 4 /* More are supported, limit only on options */
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (2*HZ)
66 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
67 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
69 /* A few user-configurable values which may be modified when a driver
72 /* 1 normal messages, 0 quiet .. 7 verbose. */
74 module_param(debug, int, S_IRUGO);
75 MODULE_PARM_DESC(debug, "Debug messages");
78 static int noisy_mii = 1;
79 module_param(noisy_mii, int, S_IRUGO);
80 MODULE_PARM_DESC(noisy_mii, "MII status messages");
82 /* Used to pass the media type, etc.
83 Both 'options[]' and 'full_duplex[]' should exist for driver
85 The media type is usually passed in 'options[]'.
88 static int options[MAX_UNITS] = {-1, -1, -1, -1};
89 module_param_array(options, int, NULL, S_IRUGO);
90 MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
92 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
93 module_param_array(full_duplex, int, NULL, S_IRUGO);
94 MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
97 #ifdef CONFIG_SBMAC_COALESCE
98 static int int_pktcnt = 0;
99 module_param(int_pktcnt, int, S_IRUGO);
100 MODULE_PARM_DESC(int_pktcnt, "Packet count");
102 static int int_timeout = 0;
103 module_param(int_timeout, int, S_IRUGO);
104 MODULE_PARM_DESC(int_timeout, "Timeout value");
107 #include <asm/sibyte/sb1250.h>
108 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
109 #include <asm/sibyte/bcm1480_regs.h>
110 #include <asm/sibyte/bcm1480_int.h>
111 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
112 #include <asm/sibyte/sb1250_regs.h>
113 #include <asm/sibyte/sb1250_int.h>
115 #error invalid SiByte MAC configuation
117 #include <asm/sibyte/sb1250_scd.h>
118 #include <asm/sibyte/sb1250_mac.h>
119 #include <asm/sibyte/sb1250_dma.h>
121 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
122 #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
123 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
124 #define UNIT_INT(n) (K_INT_MAC_0 + (n))
126 #error invalid SiByte MAC configuation
129 /**********************************************************************
131 ********************************************************************* */
134 typedef enum { sbmac_speed_auto, sbmac_speed_10,
135 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
137 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
138 sbmac_duplex_full } sbmac_duplex_t;
140 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
141 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
143 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
144 sbmac_state_broken } sbmac_state_t;
147 /**********************************************************************
149 ********************************************************************* */
152 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
153 (d)->sbdma_dscrtable : (d)->f+1)
156 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
158 #define SBMAC_MAX_TXDESCR 32
159 #define SBMAC_MAX_RXDESCR 32
161 #define ETHER_ALIGN 2
162 #define ETHER_ADDR_LEN 6
163 #define ENET_PACKET_SIZE 1518
164 /*#define ENET_PACKET_SIZE 9216 */
166 /**********************************************************************
167 * DMA Descriptor structure
168 ********************************************************************* */
170 typedef struct sbdmadscr_s {
175 typedef unsigned long paddr_t;
177 /**********************************************************************
178 * DMA Controller structure
179 ********************************************************************* */
181 typedef struct sbmacdma_s {
184 * This stuff is used to identify the channel and the registers
185 * associated with it.
188 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */
189 int sbdma_channel; /* channel number */
190 int sbdma_txdir; /* direction (1=transmit) */
191 int sbdma_maxdescr; /* total # of descriptors in ring */
192 #ifdef CONFIG_SBMAC_COALESCE
193 int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/
194 int sbdma_int_timeout; /* # usec rx/tx interrupt */
197 volatile void __iomem *sbdma_config0; /* DMA config register 0 */
198 volatile void __iomem *sbdma_config1; /* DMA config register 1 */
199 volatile void __iomem *sbdma_dscrbase; /* Descriptor base address */
200 volatile void __iomem *sbdma_dscrcnt; /* Descriptor count register */
201 volatile void __iomem *sbdma_curdscr; /* current descriptor address */
204 * This stuff is for maintenance of the ring
207 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */
208 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */
210 struct sk_buff **sbdma_ctxtable; /* context table, one per descr */
212 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */
213 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */
214 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */
218 /**********************************************************************
219 * Ethernet softc structure
220 ********************************************************************* */
225 * Linux-specific things
228 struct net_device *sbm_dev; /* pointer to linux device */
229 spinlock_t sbm_lock; /* spin lock */
230 struct timer_list sbm_timer; /* for monitoring MII */
231 struct net_device_stats sbm_stats;
232 int sbm_devflags; /* current device flags */
235 int sbm_phy_oldanlpar;
236 int sbm_phy_oldk1stsr;
237 int sbm_phy_oldlinkstat;
240 unsigned char sbm_phys[2];
243 * Controller-specific things
246 void __iomem *sbm_base; /* MAC's base address */
247 sbmac_state_t sbm_state; /* current state */
249 volatile void __iomem *sbm_macenable; /* MAC Enable Register */
250 volatile void __iomem *sbm_maccfg; /* MAC Configuration Register */
251 volatile void __iomem *sbm_fifocfg; /* FIFO configuration register */
252 volatile void __iomem *sbm_framecfg; /* Frame configuration register */
253 volatile void __iomem *sbm_rxfilter; /* receive filter register */
254 volatile void __iomem *sbm_isr; /* Interrupt status register */
255 volatile void __iomem *sbm_imr; /* Interrupt mask register */
256 volatile void __iomem *sbm_mdio; /* MDIO register */
258 sbmac_speed_t sbm_speed; /* current speed */
259 sbmac_duplex_t sbm_duplex; /* current duplex */
260 sbmac_fc_t sbm_fc; /* current flow control setting */
262 unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
264 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */
265 sbmacdma_t sbm_rxdma;
271 /**********************************************************************
273 ********************************************************************* */
275 /**********************************************************************
277 ********************************************************************* */
279 static void sbdma_initctx(sbmacdma_t *d,
280 struct sbmac_softc *s,
284 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
285 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
286 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
287 static void sbdma_emptyring(sbmacdma_t *d);
288 static void sbdma_fillring(sbmacdma_t *d);
289 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
290 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
291 static int sbmac_initctx(struct sbmac_softc *s);
292 static void sbmac_channel_start(struct sbmac_softc *s);
293 static void sbmac_channel_stop(struct sbmac_softc *s);
294 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
295 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
296 static uint64_t sbmac_addr2reg(unsigned char *ptr);
297 static irqreturn_t sbmac_intr(int irq,void *dev_instance);
298 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
299 static void sbmac_setmulti(struct sbmac_softc *sc);
300 static int sbmac_init(struct net_device *dev, int idx);
301 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
302 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
304 static int sbmac_open(struct net_device *dev);
305 static void sbmac_timer(unsigned long data);
306 static void sbmac_tx_timeout (struct net_device *dev);
307 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
308 static void sbmac_set_rx_mode(struct net_device *dev);
309 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
310 static int sbmac_close(struct net_device *dev);
311 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
312 static int sbmac_mii_probe(struct net_device *dev);
314 static void sbmac_mii_sync(struct sbmac_softc *s);
315 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
316 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
317 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
318 unsigned int regval);
321 /**********************************************************************
323 ********************************************************************* */
325 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
328 /**********************************************************************
330 ********************************************************************* */
332 #define MII_COMMAND_START 0x01
333 #define MII_COMMAND_READ 0x02
334 #define MII_COMMAND_WRITE 0x01
335 #define MII_COMMAND_ACK 0x02
337 #define BMCR_RESET 0x8000
338 #define BMCR_LOOPBACK 0x4000
339 #define BMCR_SPEED0 0x2000
340 #define BMCR_ANENABLE 0x1000
341 #define BMCR_POWERDOWN 0x0800
342 #define BMCR_ISOLATE 0x0400
343 #define BMCR_RESTARTAN 0x0200
344 #define BMCR_DUPLEX 0x0100
345 #define BMCR_COLTEST 0x0080
346 #define BMCR_SPEED1 0x0040
347 #define BMCR_SPEED1000 BMCR_SPEED1
348 #define BMCR_SPEED100 BMCR_SPEED0
349 #define BMCR_SPEED10 0
351 #define BMSR_100BT4 0x8000
352 #define BMSR_100BT_FDX 0x4000
353 #define BMSR_100BT_HDX 0x2000
354 #define BMSR_10BT_FDX 0x1000
355 #define BMSR_10BT_HDX 0x0800
356 #define BMSR_100BT2_FDX 0x0400
357 #define BMSR_100BT2_HDX 0x0200
358 #define BMSR_1000BT_XSR 0x0100
359 #define BMSR_PRESUP 0x0040
360 #define BMSR_ANCOMPLT 0x0020
361 #define BMSR_REMFAULT 0x0010
362 #define BMSR_AUTONEG 0x0008
363 #define BMSR_LINKSTAT 0x0004
364 #define BMSR_JABDETECT 0x0002
365 #define BMSR_EXTCAPAB 0x0001
367 #define PHYIDR1 0x2000
368 #define PHYIDR2 0x5C60
370 #define ANAR_NP 0x8000
371 #define ANAR_RF 0x2000
372 #define ANAR_ASYPAUSE 0x0800
373 #define ANAR_PAUSE 0x0400
374 #define ANAR_T4 0x0200
375 #define ANAR_TXFD 0x0100
376 #define ANAR_TXHD 0x0080
377 #define ANAR_10FD 0x0040
378 #define ANAR_10HD 0x0020
379 #define ANAR_PSB 0x0001
381 #define ANLPAR_NP 0x8000
382 #define ANLPAR_ACK 0x4000
383 #define ANLPAR_RF 0x2000
384 #define ANLPAR_ASYPAUSE 0x0800
385 #define ANLPAR_PAUSE 0x0400
386 #define ANLPAR_T4 0x0200
387 #define ANLPAR_TXFD 0x0100
388 #define ANLPAR_TXHD 0x0080
389 #define ANLPAR_10FD 0x0040
390 #define ANLPAR_10HD 0x0020
391 #define ANLPAR_PSB 0x0001 /* 802.3 */
393 #define ANER_PDF 0x0010
394 #define ANER_LPNPABLE 0x0008
395 #define ANER_NPABLE 0x0004
396 #define ANER_PAGERX 0x0002
397 #define ANER_LPANABLE 0x0001
399 #define ANNPTR_NP 0x8000
400 #define ANNPTR_MP 0x2000
401 #define ANNPTR_ACK2 0x1000
402 #define ANNPTR_TOGTX 0x0800
403 #define ANNPTR_CODE 0x0008
405 #define ANNPRR_NP 0x8000
406 #define ANNPRR_MP 0x2000
407 #define ANNPRR_ACK3 0x1000
408 #define ANNPRR_TOGTX 0x0800
409 #define ANNPRR_CODE 0x0008
411 #define K1TCR_TESTMODE 0x0000
412 #define K1TCR_MSMCE 0x1000
413 #define K1TCR_MSCV 0x0800
414 #define K1TCR_RPTR 0x0400
415 #define K1TCR_1000BT_FDX 0x200
416 #define K1TCR_1000BT_HDX 0x100
418 #define K1STSR_MSMCFLT 0x8000
419 #define K1STSR_MSCFGRES 0x4000
420 #define K1STSR_LRSTAT 0x2000
421 #define K1STSR_RRSTAT 0x1000
422 #define K1STSR_LP1KFD 0x0800
423 #define K1STSR_LP1KHD 0x0400
424 #define K1STSR_LPASMDIR 0x0200
426 #define K1SCR_1KX_FDX 0x8000
427 #define K1SCR_1KX_HDX 0x4000
428 #define K1SCR_1KT_FDX 0x2000
429 #define K1SCR_1KT_HDX 0x1000
431 #define STRAP_PHY1 0x0800
432 #define STRAP_NCMODE 0x0400
433 #define STRAP_MANMSCFG 0x0200
434 #define STRAP_ANENABLE 0x0100
435 #define STRAP_MSVAL 0x0080
436 #define STRAP_1KHDXADV 0x0010
437 #define STRAP_1KFDXADV 0x0008
438 #define STRAP_100ADV 0x0004
439 #define STRAP_SPEEDSEL 0x0000
440 #define STRAP_SPEED100 0x0001
442 #define PHYSUP_SPEED1000 0x10
443 #define PHYSUP_SPEED100 0x08
444 #define PHYSUP_SPEED10 0x00
445 #define PHYSUP_LINKUP 0x04
446 #define PHYSUP_FDX 0x02
448 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
449 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
450 #define MII_PHYIDR1 0x02
451 #define MII_PHYIDR2 0x03
453 #define MII_K1STSR 0x0A /* 1K Status Register (ro) */
454 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
457 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
462 /**********************************************************************
465 * Synchronize with the MII - send a pattern of bits to the MII
466 * that will guarantee that it is ready to accept a command.
469 * s - sbmac structure
473 ********************************************************************* */
475 static void sbmac_mii_sync(struct sbmac_softc *s)
481 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
483 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
485 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
487 for (cnt = 0; cnt < 32; cnt++) {
488 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
489 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
493 /**********************************************************************
494 * SBMAC_MII_SENDDATA(s,data,bitcnt)
496 * Send some bits to the MII. The bits to be sent are right-
497 * justified in the 'data' parameter.
500 * s - sbmac structure
501 * data - data to send
502 * bitcnt - number of bits to send
503 ********************************************************************* */
505 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
509 unsigned int curmask;
512 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
514 bits = M_MAC_MDIO_DIR_OUTPUT;
515 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
517 curmask = 1 << (bitcnt - 1);
519 for (i = 0; i < bitcnt; i++) {
521 bits |= M_MAC_MDIO_OUT;
522 else bits &= ~M_MAC_MDIO_OUT;
523 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
524 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
525 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
532 /**********************************************************************
533 * SBMAC_MII_READ(s,phyaddr,regidx)
535 * Read a PHY register.
538 * s - sbmac structure
539 * phyaddr - PHY's address
540 * regidx = index of register to read
543 * value read, or 0 if an error occurred.
544 ********************************************************************* */
546 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
554 * Synchronize ourselves so that the PHY knows the next
555 * thing coming down is a command
561 * Send the data to the PHY. The sequence is
562 * a "start" command (2 bits)
563 * a "read" command (2 bits)
564 * the PHY addr (5 bits)
565 * the register index (5 bits)
568 sbmac_mii_senddata(s,MII_COMMAND_START, 2);
569 sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
570 sbmac_mii_senddata(s,phyaddr, 5);
571 sbmac_mii_senddata(s,regidx, 5);
573 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
576 * Switch the port around without a clock transition.
578 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
581 * Send out a clock pulse to signal we want the status
584 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
585 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
588 * If an error occurred, the PHY will signal '1' back
590 error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
593 * Issue an 'idle' clock pulse, but keep the direction
596 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
597 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
601 for (idx = 0; idx < 16; idx++) {
605 if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
609 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
610 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
613 /* Switch back to output */
614 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
622 /**********************************************************************
623 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
625 * Write a value to a PHY register.
628 * s - sbmac structure
629 * phyaddr - PHY to use
630 * regidx - register within the PHY
631 * regval - data to write to register
635 ********************************************************************* */
637 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
644 sbmac_mii_senddata(s,MII_COMMAND_START,2);
645 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
646 sbmac_mii_senddata(s,phyaddr, 5);
647 sbmac_mii_senddata(s,regidx, 5);
648 sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
649 sbmac_mii_senddata(s,regval,16);
651 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
653 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
658 /**********************************************************************
659 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
661 * Initialize a DMA channel context. Since there are potentially
662 * eight DMA channels per MAC, it's nice to do this in a standard
666 * d - sbmacdma_t structure (DMA channel context)
667 * s - sbmac_softc structure (pointer to a MAC)
668 * chan - channel number (0..1 right now)
669 * txrx - Identifies DMA_TX or DMA_RX for channel direction
670 * maxdescr - number of descriptors
674 ********************************************************************* */
676 static void sbdma_initctx(sbmacdma_t *d,
677 struct sbmac_softc *s,
683 * Save away interesting stuff in the structure
687 d->sbdma_channel = chan;
688 d->sbdma_txdir = txrx;
692 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
695 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
696 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
697 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
698 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
699 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
700 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
701 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
702 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
703 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
704 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
705 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
706 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
707 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
708 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
709 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
710 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
711 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
712 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
713 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
714 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
715 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
718 * initialize register pointers
722 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
724 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
726 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
728 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
730 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
733 * Allocate memory for the ring
736 d->sbdma_maxdescr = maxdescr;
738 d->sbdma_dscrtable = (sbdmadscr_t *)
739 kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
742 * The descriptor table must be aligned to at least 16 bytes or the
743 * MAC will corrupt it.
745 d->sbdma_dscrtable = (sbdmadscr_t *)
746 ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
748 memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
750 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
752 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
758 d->sbdma_ctxtable = (struct sk_buff **)
759 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
761 memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
763 #ifdef CONFIG_SBMAC_COALESCE
765 * Setup Rx/Tx DMA coalescing defaults
769 d->sbdma_int_pktcnt = int_pktcnt;
771 d->sbdma_int_pktcnt = 1;
775 d->sbdma_int_timeout = int_timeout;
777 d->sbdma_int_timeout = 0;
783 /**********************************************************************
784 * SBDMA_CHANNEL_START(d)
786 * Initialize the hardware registers for a DMA channel.
789 * d - DMA channel to init (context must be previously init'd
790 * rxtx - DMA_RX or DMA_TX depending on what type of channel
794 ********************************************************************* */
796 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
799 * Turn on the DMA channel
802 #ifdef CONFIG_SBMAC_COALESCE
803 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
804 0, d->sbdma_config1);
805 __raw_writeq(M_DMA_EOP_INT_EN |
806 V_DMA_RINGSZ(d->sbdma_maxdescr) |
807 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
808 0, d->sbdma_config0);
810 __raw_writeq(0, d->sbdma_config1);
811 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
812 0, d->sbdma_config0);
815 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
818 * Initialize ring pointers
821 d->sbdma_addptr = d->sbdma_dscrtable;
822 d->sbdma_remptr = d->sbdma_dscrtable;
825 /**********************************************************************
826 * SBDMA_CHANNEL_STOP(d)
828 * Initialize the hardware registers for a DMA channel.
831 * d - DMA channel to init (context must be previously init'd
835 ********************************************************************* */
837 static void sbdma_channel_stop(sbmacdma_t *d)
840 * Turn off the DMA channel
843 __raw_writeq(0, d->sbdma_config1);
845 __raw_writeq(0, d->sbdma_dscrbase);
847 __raw_writeq(0, d->sbdma_config0);
853 d->sbdma_addptr = NULL;
854 d->sbdma_remptr = NULL;
857 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
860 unsigned long newaddr;
862 addr = (unsigned long) skb->data;
864 newaddr = (addr + power2 - 1) & ~(power2 - 1);
866 skb_reserve(skb,newaddr-addr+offset);
870 /**********************************************************************
871 * SBDMA_ADD_RCVBUFFER(d,sb)
873 * Add a buffer to the specified DMA channel. For receive channels,
874 * this queues a buffer for inbound packets.
877 * d - DMA channel descriptor
878 * sb - sk_buff to add, or NULL if we should allocate one
881 * 0 if buffer could not be added (ring is full)
882 * 1 if buffer added successfully
883 ********************************************************************* */
886 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
889 sbdmadscr_t *nextdsc;
890 struct sk_buff *sb_new = NULL;
891 int pktsize = ENET_PACKET_SIZE;
893 /* get pointer to our current place in the ring */
895 dsc = d->sbdma_addptr;
896 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
899 * figure out if the ring is full - if the next descriptor
900 * is the same as the one that we're going to remove from
901 * the ring, the ring is full
904 if (nextdsc == d->sbdma_remptr) {
909 * Allocate a sk_buff if we don't already have one.
910 * If we do have an sk_buff, reset it so that it's empty.
912 * Note: sk_buffs don't seem to be guaranteed to have any sort
913 * of alignment when they are allocated. Therefore, allocate enough
914 * extra space to make sure that:
916 * 1. the data does not start in the middle of a cache line.
917 * 2. The data does not end in the middle of a cache line
918 * 3. The buffer can be aligned such that the IP addresses are
921 * Remember, the SOCs MAC writes whole cache lines at a time,
922 * without reading the old contents first. So, if the sk_buff's
923 * data portion starts in the middle of a cache line, the SOC
924 * DMA will trash the beginning (and ending) portions.
928 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
929 if (sb_new == NULL) {
930 printk(KERN_INFO "%s: sk_buff allocation failed\n",
931 d->sbdma_eth->sbm_dev->name);
935 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
940 * nothing special to reinit buffer, it's already aligned
941 * and sb->data already points to a good place.
946 * fill in the descriptor
949 #ifdef CONFIG_SBMAC_COALESCE
951 * Do not interrupt per DMA transfer.
953 dsc->dscr_a = virt_to_phys(sb_new->data) |
954 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
956 dsc->dscr_a = virt_to_phys(sb_new->data) |
957 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
958 M_DMA_DSCRA_INTERRUPT;
961 /* receiving: no options */
965 * fill in the context
968 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
971 * point at next packet
974 d->sbdma_addptr = nextdsc;
977 * Give the buffer to the DMA engine.
980 __raw_writeq(1, d->sbdma_dscrcnt);
982 return 0; /* we did it */
985 /**********************************************************************
986 * SBDMA_ADD_TXBUFFER(d,sb)
988 * Add a transmit buffer to the specified DMA channel, causing a
992 * d - DMA channel descriptor
993 * sb - sk_buff to add
996 * 0 transmit queued successfully
997 * otherwise error code
998 ********************************************************************* */
1001 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1004 sbdmadscr_t *nextdsc;
1009 /* get pointer to our current place in the ring */
1011 dsc = d->sbdma_addptr;
1012 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1015 * figure out if the ring is full - if the next descriptor
1016 * is the same as the one that we're going to remove from
1017 * the ring, the ring is full
1020 if (nextdsc == d->sbdma_remptr) {
1025 * Under Linux, it's not necessary to copy/coalesce buffers
1026 * like it is on NetBSD. We think they're all contiguous,
1027 * but that may not be true for GBE.
1033 * fill in the descriptor. Note that the number of cache
1034 * blocks in the descriptor is the number of blocks
1035 * *spanned*, so we need to add in the offset (if any)
1036 * while doing the calculation.
1039 phys = virt_to_phys(sb->data);
1040 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1042 dsc->dscr_a = phys |
1043 V_DMA_DSCRA_A_SIZE(ncb) |
1044 #ifndef CONFIG_SBMAC_COALESCE
1045 M_DMA_DSCRA_INTERRUPT |
1049 /* transmitting: set outbound options and length */
1051 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1052 V_DMA_DSCRB_PKT_SIZE(length);
1055 * fill in the context
1058 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1061 * point at next packet
1064 d->sbdma_addptr = nextdsc;
1067 * Give the buffer to the DMA engine.
1070 __raw_writeq(1, d->sbdma_dscrcnt);
1072 return 0; /* we did it */
1078 /**********************************************************************
1079 * SBDMA_EMPTYRING(d)
1081 * Free all allocated sk_buffs on the specified DMA channel;
1088 ********************************************************************* */
1090 static void sbdma_emptyring(sbmacdma_t *d)
1095 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1096 sb = d->sbdma_ctxtable[idx];
1099 d->sbdma_ctxtable[idx] = NULL;
1105 /**********************************************************************
1108 * Fill the specified DMA channel (must be receive channel)
1116 ********************************************************************* */
1118 static void sbdma_fillring(sbmacdma_t *d)
1122 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1123 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1128 #ifdef CONFIG_NET_POLL_CONTROLLER
1129 static void sbmac_netpoll(struct net_device *netdev)
1131 struct sbmac_softc *sc = netdev_priv(netdev);
1132 int irq = sc->sbm_dev->irq;
1134 __raw_writeq(0, sc->sbm_imr);
1136 sbmac_intr(irq, netdev, NULL);
1138 #ifdef CONFIG_SBMAC_COALESCE
1139 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1140 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1143 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1144 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1149 /**********************************************************************
1150 * SBDMA_RX_PROCESS(sc,d)
1152 * Process "completed" receive buffers on the specified DMA channel.
1153 * Note that this isn't really ideal for priority channels, since
1154 * it processes all of the packets on a given channel before
1158 * sc - softc structure
1159 * d - DMA channel context
1163 ********************************************************************* */
1165 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1175 * figure out where we are (as an index) and where
1176 * the hardware is (also as an index)
1178 * This could be done faster if (for example) the
1179 * descriptor table was page-aligned and contiguous in
1180 * both virtual and physical memory -- you could then
1181 * just compare the low-order bits of the virtual address
1182 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1185 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1186 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1187 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1190 * If they're the same, that means we've processed all
1191 * of the descriptors up to (but not including) the one that
1192 * the hardware is working on right now.
1195 if (curidx == hwidx)
1199 * Otherwise, get the packet's sk_buff ptr back
1202 dsc = &(d->sbdma_dscrtable[curidx]);
1203 sb = d->sbdma_ctxtable[curidx];
1204 d->sbdma_ctxtable[curidx] = NULL;
1206 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1209 * Check packet status. If good, process it.
1210 * If not, silently drop it and put it back on the
1214 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1217 * Add a new buffer to replace the old one. If we fail
1218 * to allocate a buffer, we're going to drop this
1219 * packet and put it right back on the receive ring.
1222 if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1223 sc->sbm_stats.rx_dropped++;
1224 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1227 * Set length into the packet
1232 * Buffer has been replaced on the
1233 * receive ring. Pass the buffer to
1236 sc->sbm_stats.rx_bytes += len;
1237 sc->sbm_stats.rx_packets++;
1238 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1239 /* Check hw IPv4/TCP checksum if supported */
1240 if (sc->rx_hw_checksum == ENABLE) {
1241 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1242 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1243 sb->ip_summed = CHECKSUM_UNNECESSARY;
1244 /* don't need to set sb->csum */
1246 sb->ip_summed = CHECKSUM_NONE;
1254 * Packet was mangled somehow. Just drop it and
1255 * put it back on the receive ring.
1257 sc->sbm_stats.rx_errors++;
1258 sbdma_add_rcvbuffer(d,sb);
1263 * .. and advance to the next buffer.
1266 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1273 /**********************************************************************
1274 * SBDMA_TX_PROCESS(sc,d)
1276 * Process "completed" transmit buffers on the specified DMA channel.
1277 * This is normally called within the interrupt service routine.
1278 * Note that this isn't really ideal for priority channels, since
1279 * it processes all of the packets on a given channel before
1283 * sc - softc structure
1284 * d - DMA channel context
1288 ********************************************************************* */
1290 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1296 unsigned long flags;
1298 spin_lock_irqsave(&(sc->sbm_lock), flags);
1302 * figure out where we are (as an index) and where
1303 * the hardware is (also as an index)
1305 * This could be done faster if (for example) the
1306 * descriptor table was page-aligned and contiguous in
1307 * both virtual and physical memory -- you could then
1308 * just compare the low-order bits of the virtual address
1309 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1312 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1313 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1314 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1317 * If they're the same, that means we've processed all
1318 * of the descriptors up to (but not including) the one that
1319 * the hardware is working on right now.
1322 if (curidx == hwidx)
1326 * Otherwise, get the packet's sk_buff ptr back
1329 dsc = &(d->sbdma_dscrtable[curidx]);
1330 sb = d->sbdma_ctxtable[curidx];
1331 d->sbdma_ctxtable[curidx] = NULL;
1337 sc->sbm_stats.tx_bytes += sb->len;
1338 sc->sbm_stats.tx_packets++;
1341 * for transmits, we just free buffers.
1344 dev_kfree_skb_irq(sb);
1347 * .. and advance to the next buffer.
1350 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1355 * Decide if we should wake up the protocol or not.
1356 * Other drivers seem to do this when we reach a low
1357 * watermark on the transmit queue.
1360 netif_wake_queue(d->sbdma_eth->sbm_dev);
1362 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1368 /**********************************************************************
1371 * Initialize an Ethernet context structure - this is called
1372 * once per MAC on the 1250. Memory is allocated here, so don't
1373 * call it again from inside the ioctl routines that bring the
1377 * s - sbmac context structure
1381 ********************************************************************* */
1383 static int sbmac_initctx(struct sbmac_softc *s)
1387 * figure out the addresses of some ports
1390 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1391 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1392 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
1393 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
1394 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
1395 s->sbm_isr = s->sbm_base + R_MAC_STATUS;
1396 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
1397 s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
1402 s->sbm_phy_oldbmsr = 0;
1403 s->sbm_phy_oldanlpar = 0;
1404 s->sbm_phy_oldk1stsr = 0;
1405 s->sbm_phy_oldlinkstat = 0;
1408 * Initialize the DMA channels. Right now, only one per MAC is used
1409 * Note: Only do this _once_, as it allocates memory from the kernel!
1412 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1413 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1416 * initial state is OFF
1419 s->sbm_state = sbmac_state_off;
1422 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1425 s->sbm_speed = sbmac_speed_10;
1426 s->sbm_duplex = sbmac_duplex_half;
1427 s->sbm_fc = sbmac_fc_disabled;
1433 static void sbdma_uninitctx(struct sbmacdma_s *d)
1435 if (d->sbdma_dscrtable) {
1436 kfree(d->sbdma_dscrtable);
1437 d->sbdma_dscrtable = NULL;
1440 if (d->sbdma_ctxtable) {
1441 kfree(d->sbdma_ctxtable);
1442 d->sbdma_ctxtable = NULL;
1447 static void sbmac_uninitctx(struct sbmac_softc *sc)
1449 sbdma_uninitctx(&(sc->sbm_txdma));
1450 sbdma_uninitctx(&(sc->sbm_rxdma));
1454 /**********************************************************************
1455 * SBMAC_CHANNEL_START(s)
1457 * Start packet processing on this MAC.
1460 * s - sbmac structure
1464 ********************************************************************* */
1466 static void sbmac_channel_start(struct sbmac_softc *s)
1469 volatile void __iomem *port;
1470 uint64_t cfg,fifo,framecfg;
1474 * Don't do this if running
1477 if (s->sbm_state == sbmac_state_on)
1481 * Bring the controller out of reset, but leave it off.
1484 __raw_writeq(0, s->sbm_macenable);
1487 * Ignore all received packets
1490 __raw_writeq(0, s->sbm_rxfilter);
1493 * Calculate values for various control registers.
1496 cfg = M_MAC_RETRY_EN |
1497 M_MAC_TX_HOLD_SOP_EN |
1498 V_MAC_TX_PAUSE_CNT_16K |
1505 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1506 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1507 * Use a larger RD_THRSH for gigabit
1509 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1514 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
1515 ((s->sbm_speed == sbmac_speed_1000)
1516 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1517 V_MAC_TX_RL_THRSH(4) |
1518 V_MAC_RX_PL_THRSH(4) |
1519 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
1520 V_MAC_RX_PL_THRSH(4) |
1521 V_MAC_RX_RL_THRSH(8) |
1524 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1525 V_MAC_MAX_FRAMESZ_DEFAULT |
1526 V_MAC_BACKOFF_SEL(1);
1529 * Clear out the hash address map
1532 port = s->sbm_base + R_MAC_HASH_BASE;
1533 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1534 __raw_writeq(0, port);
1535 port += sizeof(uint64_t);
1539 * Clear out the exact-match table
1542 port = s->sbm_base + R_MAC_ADDR_BASE;
1543 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1544 __raw_writeq(0, port);
1545 port += sizeof(uint64_t);
1549 * Clear out the DMA Channel mapping table registers
1552 port = s->sbm_base + R_MAC_CHUP0_BASE;
1553 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1554 __raw_writeq(0, port);
1555 port += sizeof(uint64_t);
1559 port = s->sbm_base + R_MAC_CHLO0_BASE;
1560 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1561 __raw_writeq(0, port);
1562 port += sizeof(uint64_t);
1566 * Program the hardware address. It goes into the hardware-address
1567 * register as well as the first filter register.
1570 reg = sbmac_addr2reg(s->sbm_hwaddr);
1572 port = s->sbm_base + R_MAC_ADDR_BASE;
1573 __raw_writeq(reg, port);
1574 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1576 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1578 * Pass1 SOCs do not receive packets addressed to the
1579 * destination address in the R_MAC_ETHERNET_ADDR register.
1580 * Set the value to zero.
1582 __raw_writeq(0, port);
1584 __raw_writeq(reg, port);
1588 * Set the receive filter for no packets, and write values
1589 * to the various config registers
1592 __raw_writeq(0, s->sbm_rxfilter);
1593 __raw_writeq(0, s->sbm_imr);
1594 __raw_writeq(framecfg, s->sbm_framecfg);
1595 __raw_writeq(fifo, s->sbm_fifocfg);
1596 __raw_writeq(cfg, s->sbm_maccfg);
1599 * Initialize DMA channels (rings should be ok now)
1602 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1603 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1606 * Configure the speed, duplex, and flow control
1609 sbmac_set_speed(s,s->sbm_speed);
1610 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1613 * Fill the receive ring
1616 sbdma_fillring(&(s->sbm_rxdma));
1619 * Turn on the rest of the bits in the enable register
1622 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1623 __raw_writeq(M_MAC_RXDMA_EN0 |
1624 M_MAC_TXDMA_EN0, s->sbm_macenable);
1625 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1626 __raw_writeq(M_MAC_RXDMA_EN0 |
1629 M_MAC_TX_ENABLE, s->sbm_macenable);
1631 #error invalid SiByte MAC configuation
1634 #ifdef CONFIG_SBMAC_COALESCE
1636 * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1638 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1639 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1642 * Accept any kind of interrupt on TX and RX DMA channel 0
1644 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1645 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1649 * Enable receiving unicasts and broadcasts
1652 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1655 * we're running now.
1658 s->sbm_state = sbmac_state_on;
1661 * Program multicast addresses
1667 * If channel was in promiscuous mode before, turn that on
1670 if (s->sbm_devflags & IFF_PROMISC) {
1671 sbmac_promiscuous_mode(s,1);
1677 /**********************************************************************
1678 * SBMAC_CHANNEL_STOP(s)
1680 * Stop packet processing on this MAC.
1683 * s - sbmac structure
1687 ********************************************************************* */
1689 static void sbmac_channel_stop(struct sbmac_softc *s)
1691 /* don't do this if already stopped */
1693 if (s->sbm_state == sbmac_state_off)
1696 /* don't accept any packets, disable all interrupts */
1698 __raw_writeq(0, s->sbm_rxfilter);
1699 __raw_writeq(0, s->sbm_imr);
1701 /* Turn off ticker */
1705 /* turn off receiver and transmitter */
1707 __raw_writeq(0, s->sbm_macenable);
1709 /* We're stopped now. */
1711 s->sbm_state = sbmac_state_off;
1714 * Stop DMA channels (rings should be ok now)
1717 sbdma_channel_stop(&(s->sbm_rxdma));
1718 sbdma_channel_stop(&(s->sbm_txdma));
1720 /* Empty the receive and transmit rings */
1722 sbdma_emptyring(&(s->sbm_rxdma));
1723 sbdma_emptyring(&(s->sbm_txdma));
1727 /**********************************************************************
1728 * SBMAC_SET_CHANNEL_STATE(state)
1730 * Set the channel's state ON or OFF
1737 ********************************************************************* */
1738 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1739 sbmac_state_t state)
1741 sbmac_state_t oldstate = sc->sbm_state;
1744 * If same as previous state, return
1747 if (state == oldstate) {
1752 * If new state is ON, turn channel on
1755 if (state == sbmac_state_on) {
1756 sbmac_channel_start(sc);
1759 sbmac_channel_stop(sc);
1763 * Return previous state
1770 /**********************************************************************
1771 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1773 * Turn on or off promiscuous mode
1777 * onoff - 1 to turn on, 0 to turn off
1781 ********************************************************************* */
1783 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1787 if (sc->sbm_state != sbmac_state_on)
1791 reg = __raw_readq(sc->sbm_rxfilter);
1792 reg |= M_MAC_ALLPKT_EN;
1793 __raw_writeq(reg, sc->sbm_rxfilter);
1796 reg = __raw_readq(sc->sbm_rxfilter);
1797 reg &= ~M_MAC_ALLPKT_EN;
1798 __raw_writeq(reg, sc->sbm_rxfilter);
1802 /**********************************************************************
1803 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1805 * Set the iphdr offset as 15 assuming ethernet encapsulation
1812 ********************************************************************* */
1814 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1818 /* Hard code the off set to 15 for now */
1819 reg = __raw_readq(sc->sbm_rxfilter);
1820 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1821 __raw_writeq(reg, sc->sbm_rxfilter);
1823 /* BCM1250 pass1 didn't have hardware checksum. Everything
1825 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1826 sc->rx_hw_checksum = DISABLE;
1828 sc->rx_hw_checksum = ENABLE;
1833 /**********************************************************************
1834 * SBMAC_ADDR2REG(ptr)
1836 * Convert six bytes into the 64-bit register value that
1837 * we typically write into the SBMAC's address/mcast registers
1840 * ptr - pointer to 6 bytes
1844 ********************************************************************* */
1846 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1852 reg |= (uint64_t) *(--ptr);
1854 reg |= (uint64_t) *(--ptr);
1856 reg |= (uint64_t) *(--ptr);
1858 reg |= (uint64_t) *(--ptr);
1860 reg |= (uint64_t) *(--ptr);
1862 reg |= (uint64_t) *(--ptr);
1868 /**********************************************************************
1869 * SBMAC_SET_SPEED(s,speed)
1871 * Configure LAN speed for the specified MAC.
1872 * Warning: must be called when MAC is off!
1875 * s - sbmac structure
1876 * speed - speed to set MAC to (see sbmac_speed_t enum)
1880 * 0 indicates invalid parameters
1881 ********************************************************************* */
1883 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1889 * Save new current values
1892 s->sbm_speed = speed;
1894 if (s->sbm_state == sbmac_state_on)
1895 return 0; /* save for next restart */
1898 * Read current register values
1901 cfg = __raw_readq(s->sbm_maccfg);
1902 framecfg = __raw_readq(s->sbm_framecfg);
1905 * Mask out the stuff we want to change
1908 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1909 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1913 * Now add in the new bits
1917 case sbmac_speed_10:
1918 framecfg |= V_MAC_IFG_RX_10 |
1920 K_MAC_IFG_THRSH_10 |
1922 cfg |= V_MAC_SPEED_SEL_10MBPS;
1925 case sbmac_speed_100:
1926 framecfg |= V_MAC_IFG_RX_100 |
1928 V_MAC_IFG_THRSH_100 |
1929 V_MAC_SLOT_SIZE_100;
1930 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1933 case sbmac_speed_1000:
1934 framecfg |= V_MAC_IFG_RX_1000 |
1936 V_MAC_IFG_THRSH_1000 |
1937 V_MAC_SLOT_SIZE_1000;
1938 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1941 case sbmac_speed_auto: /* XXX not implemented */
1948 * Send the bits back to the hardware
1951 __raw_writeq(framecfg, s->sbm_framecfg);
1952 __raw_writeq(cfg, s->sbm_maccfg);
1957 /**********************************************************************
1958 * SBMAC_SET_DUPLEX(s,duplex,fc)
1960 * Set Ethernet duplex and flow control options for this MAC
1961 * Warning: must be called when MAC is off!
1964 * s - sbmac structure
1965 * duplex - duplex setting (see sbmac_duplex_t)
1966 * fc - flow control setting (see sbmac_fc_t)
1970 * 0 if an invalid parameter combination was specified
1971 ********************************************************************* */
1973 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1978 * Save new current values
1981 s->sbm_duplex = duplex;
1984 if (s->sbm_state == sbmac_state_on)
1985 return 0; /* save for next restart */
1988 * Read current register values
1991 cfg = __raw_readq(s->sbm_maccfg);
1994 * Mask off the stuff we're about to change
1997 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
2001 case sbmac_duplex_half:
2003 case sbmac_fc_disabled:
2004 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2007 case sbmac_fc_collision:
2008 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2011 case sbmac_fc_carrier:
2012 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2015 case sbmac_fc_auto: /* XXX not implemented */
2017 case sbmac_fc_frame: /* not valid in half duplex */
2018 default: /* invalid selection */
2023 case sbmac_duplex_full:
2025 case sbmac_fc_disabled:
2026 cfg |= V_MAC_FC_CMD_DISABLED;
2029 case sbmac_fc_frame:
2030 cfg |= V_MAC_FC_CMD_ENABLED;
2033 case sbmac_fc_collision: /* not valid in full duplex */
2034 case sbmac_fc_carrier: /* not valid in full duplex */
2035 case sbmac_fc_auto: /* XXX not implemented */
2041 case sbmac_duplex_auto:
2042 /* XXX not implemented */
2047 * Send the bits back to the hardware
2050 __raw_writeq(cfg, s->sbm_maccfg);
2058 /**********************************************************************
2061 * Interrupt handler for MAC interrupts
2068 ********************************************************************* */
2069 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
2071 struct net_device *dev = (struct net_device *) dev_instance;
2072 struct sbmac_softc *sc = netdev_priv(dev);
2079 * Read the ISR (this clears the bits in the real
2080 * register, except for counter addr)
2083 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2091 * Transmits on channel 0
2094 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2095 sbdma_tx_process(sc,&(sc->sbm_txdma));
2099 * Receives on channel 0
2103 * It's important to test all the bits (or at least the
2104 * EOP_SEEN bit) when deciding to do the RX process
2105 * particularly when coalescing, to make sure we
2106 * take care of the following:
2108 * If you have some packets waiting (have been received
2109 * but no interrupt) and get a TX interrupt before
2110 * the RX timer or counter expires, reading the ISR
2111 * above will clear the timer and counter, and you
2112 * won't get another interrupt until a packet shows
2113 * up to start the timer again. Testing
2114 * EOP_SEEN here takes care of this case.
2115 * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2119 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2120 sbdma_rx_process(sc,&(sc->sbm_rxdma));
2123 return IRQ_RETVAL(handled);
2127 /**********************************************************************
2128 * SBMAC_START_TX(skb,dev)
2130 * Start output on the specified interface. Basically, we
2131 * queue as many buffers as we can until the ring fills up, or
2132 * we run off the end of the queue, whichever comes first.
2139 ********************************************************************* */
2140 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2142 struct sbmac_softc *sc = netdev_priv(dev);
2145 spin_lock_irq (&sc->sbm_lock);
2148 * Put the buffer on the transmit ring. If we
2149 * don't have room, stop the queue.
2152 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2153 /* XXX save skb that we could not send */
2154 netif_stop_queue(dev);
2155 spin_unlock_irq(&sc->sbm_lock);
2160 dev->trans_start = jiffies;
2162 spin_unlock_irq (&sc->sbm_lock);
2167 /**********************************************************************
2168 * SBMAC_SETMULTI(sc)
2170 * Reprogram the multicast table into the hardware, given
2171 * the list of multicasts associated with the interface
2179 ********************************************************************* */
2181 static void sbmac_setmulti(struct sbmac_softc *sc)
2184 volatile void __iomem *port;
2186 struct dev_mc_list *mclist;
2187 struct net_device *dev = sc->sbm_dev;
2190 * Clear out entire multicast table. We do this by nuking
2191 * the entire hash table and all the direct matches except
2192 * the first one, which is used for our station address
2195 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2196 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2197 __raw_writeq(0, port);
2200 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2201 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2202 __raw_writeq(0, port);
2206 * Clear the filter to say we don't want any multicasts.
2209 reg = __raw_readq(sc->sbm_rxfilter);
2210 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2211 __raw_writeq(reg, sc->sbm_rxfilter);
2213 if (dev->flags & IFF_ALLMULTI) {
2215 * Enable ALL multicasts. Do this by inverting the
2216 * multicast enable bit.
2218 reg = __raw_readq(sc->sbm_rxfilter);
2219 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2220 __raw_writeq(reg, sc->sbm_rxfilter);
2226 * Progam new multicast entries. For now, only use the
2227 * perfect filter. In the future we'll need to use the
2228 * hash filter if the perfect filter overflows
2231 /* XXX only using perfect filter for now, need to use hash
2232 * XXX if the table overflows */
2234 idx = 1; /* skip station address */
2235 mclist = dev->mc_list;
2236 while (mclist && (idx < MAC_ADDR_COUNT)) {
2237 reg = sbmac_addr2reg(mclist->dmi_addr);
2238 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2239 __raw_writeq(reg, port);
2241 mclist = mclist->next;
2245 * Enable the "accept multicast bits" if we programmed at least one
2250 reg = __raw_readq(sc->sbm_rxfilter);
2251 reg |= M_MAC_MCAST_EN;
2252 __raw_writeq(reg, sc->sbm_rxfilter);
2258 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2259 /**********************************************************************
2260 * SBMAC_PARSE_XDIGIT(str)
2262 * Parse a hex digit, returning its value
2268 * hex value, or -1 if invalid
2269 ********************************************************************* */
2271 static int sbmac_parse_xdigit(char str)
2275 if ((str >= '0') && (str <= '9'))
2277 else if ((str >= 'a') && (str <= 'f'))
2278 digit = str - 'a' + 10;
2279 else if ((str >= 'A') && (str <= 'F'))
2280 digit = str - 'A' + 10;
2287 /**********************************************************************
2288 * SBMAC_PARSE_HWADDR(str,hwaddr)
2290 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2295 * hwaddr - pointer to hardware address
2299 ********************************************************************* */
2301 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2306 while (*str && (idx > 0)) {
2307 digit1 = sbmac_parse_xdigit(*str);
2314 if ((*str == ':') || (*str == '-')) {
2319 digit2 = sbmac_parse_xdigit(*str);
2325 *hwaddr++ = (digit1 << 4) | digit2;
2337 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2339 if (new_mtu > ENET_PACKET_SIZE)
2341 _dev->mtu = new_mtu;
2342 printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2346 /**********************************************************************
2349 * Attach routine - init hardware and hook ourselves into linux
2352 * dev - net_device structure
2356 ********************************************************************* */
2358 static int sbmac_init(struct net_device *dev, int idx)
2360 struct sbmac_softc *sc;
2361 unsigned char *eaddr;
2366 sc = netdev_priv(dev);
2368 /* Determine controller base address */
2370 sc->sbm_base = IOADDR(dev->base_addr);
2374 eaddr = sc->sbm_hwaddr;
2377 * Read the ethernet address. The firwmare left this programmed
2378 * for us in the ethernet address register for each mac.
2381 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2382 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2383 for (i = 0; i < 6; i++) {
2384 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2388 for (i = 0; i < 6; i++) {
2389 dev->dev_addr[i] = eaddr[i];
2397 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2400 * Initialize context (get pointers to registers and stuff), then
2401 * allocate the memory for the descriptor tables.
2407 * Set up Linux device callins
2410 spin_lock_init(&(sc->sbm_lock));
2412 dev->open = sbmac_open;
2413 dev->hard_start_xmit = sbmac_start_tx;
2414 dev->stop = sbmac_close;
2415 dev->get_stats = sbmac_get_stats;
2416 dev->set_multicast_list = sbmac_set_rx_mode;
2417 dev->do_ioctl = sbmac_mii_ioctl;
2418 dev->tx_timeout = sbmac_tx_timeout;
2419 dev->watchdog_timeo = TX_TIMEOUT;
2421 dev->change_mtu = sb1250_change_mtu;
2422 #ifdef CONFIG_NET_POLL_CONTROLLER
2423 dev->poll_controller = sbmac_netpoll;
2426 /* This is needed for PASS2 for Rx H/W checksum feature */
2427 sbmac_set_iphdr_offset(sc);
2429 err = register_netdev(dev);
2433 if (sc->rx_hw_checksum == ENABLE) {
2434 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2439 * Display Ethernet address (this is called during the config
2440 * process so we need to finish off the config message that
2441 * was being displayed)
2444 "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2445 dev->name, dev->base_addr,
2446 eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2452 sbmac_uninitctx(sc);
2458 static int sbmac_open(struct net_device *dev)
2460 struct sbmac_softc *sc = netdev_priv(dev);
2463 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2467 * map/route interrupt (clear status first, in case something
2468 * weird is pending; we haven't initialized the mac registers
2472 __raw_readq(sc->sbm_isr);
2473 if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev))
2480 if(sbmac_mii_probe(dev) == -1) {
2481 printk("%s: failed to probe PHY.\n", dev->name);
2486 * Configure default speed
2489 sbmac_mii_poll(sc,noisy_mii);
2492 * Turn on the channel
2495 sbmac_set_channel_state(sc,sbmac_state_on);
2498 * XXX Station address is in dev->dev_addr
2501 if (dev->if_port == 0)
2504 netif_start_queue(dev);
2506 sbmac_set_rx_mode(dev);
2508 /* Set the timer to check for link beat. */
2509 init_timer(&sc->sbm_timer);
2510 sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2511 sc->sbm_timer.data = (unsigned long)dev;
2512 sc->sbm_timer.function = &sbmac_timer;
2513 add_timer(&sc->sbm_timer);
2518 static int sbmac_mii_probe(struct net_device *dev)
2521 struct sbmac_softc *s = netdev_priv(dev);
2525 for (i=1; i<31; i++) {
2526 bmsr = sbmac_mii_read(s, i, MII_BMSR);
2529 id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2530 id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2531 vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2532 device = (id2 >> 4) & 0x3f;
2534 printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2535 dev->name, i, vendor, device);
2543 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2545 int bmsr,bmcr,k1stsr,anlpar;
2550 /* Read the mode status and mode control registers. */
2551 bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2552 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2554 /* get the link partner status */
2555 anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2557 /* if supported, read the 1000baseT register */
2558 if (bmsr & BMSR_1000BT_XSR) {
2559 k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2567 if ((bmsr & BMSR_LINKSTAT) == 0) {
2569 * If link status is down, clear out old info so that when
2570 * it comes back up it will force us to reconfigure speed
2572 s->sbm_phy_oldbmsr = 0;
2573 s->sbm_phy_oldanlpar = 0;
2574 s->sbm_phy_oldk1stsr = 0;
2578 if ((s->sbm_phy_oldbmsr != bmsr) ||
2579 (s->sbm_phy_oldanlpar != anlpar) ||
2580 (s->sbm_phy_oldk1stsr != k1stsr)) {
2582 printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
2584 s->sbm_phy_oldbmsr,bmsr,
2585 s->sbm_phy_oldanlpar,anlpar,
2586 s->sbm_phy_oldk1stsr,k1stsr);
2588 s->sbm_phy_oldbmsr = bmsr;
2589 s->sbm_phy_oldanlpar = anlpar;
2590 s->sbm_phy_oldk1stsr = k1stsr;
2597 p += sprintf(p,"Link speed: ");
2599 if (k1stsr & K1STSR_LP1KFD) {
2600 s->sbm_speed = sbmac_speed_1000;
2601 s->sbm_duplex = sbmac_duplex_full;
2602 s->sbm_fc = sbmac_fc_frame;
2603 p += sprintf(p,"1000BaseT FDX");
2605 else if (k1stsr & K1STSR_LP1KHD) {
2606 s->sbm_speed = sbmac_speed_1000;
2607 s->sbm_duplex = sbmac_duplex_half;
2608 s->sbm_fc = sbmac_fc_disabled;
2609 p += sprintf(p,"1000BaseT HDX");
2611 else if (anlpar & ANLPAR_TXFD) {
2612 s->sbm_speed = sbmac_speed_100;
2613 s->sbm_duplex = sbmac_duplex_full;
2614 s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2615 p += sprintf(p,"100BaseT FDX");
2617 else if (anlpar & ANLPAR_TXHD) {
2618 s->sbm_speed = sbmac_speed_100;
2619 s->sbm_duplex = sbmac_duplex_half;
2620 s->sbm_fc = sbmac_fc_disabled;
2621 p += sprintf(p,"100BaseT HDX");
2623 else if (anlpar & ANLPAR_10FD) {
2624 s->sbm_speed = sbmac_speed_10;
2625 s->sbm_duplex = sbmac_duplex_full;
2626 s->sbm_fc = sbmac_fc_frame;
2627 p += sprintf(p,"10BaseT FDX");
2629 else if (anlpar & ANLPAR_10HD) {
2630 s->sbm_speed = sbmac_speed_10;
2631 s->sbm_duplex = sbmac_duplex_half;
2632 s->sbm_fc = sbmac_fc_collision;
2633 p += sprintf(p,"10BaseT HDX");
2636 p += sprintf(p,"Unknown");
2640 printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2647 static void sbmac_timer(unsigned long data)
2649 struct net_device *dev = (struct net_device *)data;
2650 struct sbmac_softc *sc = netdev_priv(dev);
2654 spin_lock_irq (&sc->sbm_lock);
2656 /* make IFF_RUNNING follow the MII status bit "Link established" */
2657 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2659 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2660 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2661 if (mii_status & BMSR_LINKSTAT) {
2662 netif_carrier_on(dev);
2665 netif_carrier_off(dev);
2670 * Poll the PHY to see what speed we should be running at
2673 if (sbmac_mii_poll(sc,noisy_mii)) {
2674 if (sc->sbm_state != sbmac_state_off) {
2676 * something changed, restart the channel
2679 printk("%s: restarting channel because speed changed\n",
2682 sbmac_channel_stop(sc);
2683 sbmac_channel_start(sc);
2687 spin_unlock_irq (&sc->sbm_lock);
2689 sc->sbm_timer.expires = jiffies + next_tick;
2690 add_timer(&sc->sbm_timer);
2694 static void sbmac_tx_timeout (struct net_device *dev)
2696 struct sbmac_softc *sc = netdev_priv(dev);
2698 spin_lock_irq (&sc->sbm_lock);
2701 dev->trans_start = jiffies;
2702 sc->sbm_stats.tx_errors++;
2704 spin_unlock_irq (&sc->sbm_lock);
2706 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2712 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2714 struct sbmac_softc *sc = netdev_priv(dev);
2715 unsigned long flags;
2717 spin_lock_irqsave(&sc->sbm_lock, flags);
2719 /* XXX update other stats here */
2721 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2723 return &sc->sbm_stats;
2728 static void sbmac_set_rx_mode(struct net_device *dev)
2730 unsigned long flags;
2731 struct sbmac_softc *sc = netdev_priv(dev);
2733 spin_lock_irqsave(&sc->sbm_lock, flags);
2734 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2736 * Promiscuous changed.
2739 if (dev->flags & IFF_PROMISC) {
2740 sbmac_promiscuous_mode(sc,1);
2743 sbmac_promiscuous_mode(sc,0);
2746 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2749 * Program the multicasts. Do this every time.
2756 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2758 struct sbmac_softc *sc = netdev_priv(dev);
2759 u16 *data = (u16 *)&rq->ifr_ifru;
2760 unsigned long flags;
2763 spin_lock_irqsave(&sc->sbm_lock, flags);
2767 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2768 data[0] = sc->sbm_phys[0] & 0x1f;
2770 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2771 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2773 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2774 if (!capable(CAP_NET_ADMIN)) {
2779 printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2780 data[0],data[1],data[2]);
2782 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2785 retval = -EOPNOTSUPP;
2788 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2792 static int sbmac_close(struct net_device *dev)
2794 struct sbmac_softc *sc = netdev_priv(dev);
2795 unsigned long flags;
2798 sbmac_set_channel_state(sc,sbmac_state_off);
2800 del_timer_sync(&sc->sbm_timer);
2802 spin_lock_irqsave(&sc->sbm_lock, flags);
2804 netif_stop_queue(dev);
2807 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2810 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2813 synchronize_irq(irq);
2816 sbdma_emptyring(&(sc->sbm_txdma));
2817 sbdma_emptyring(&(sc->sbm_rxdma));
2824 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2826 sbmac_setup_hwaddr(int chan,char *addr)
2832 port = A_MAC_CHANNEL_BASE(chan);
2833 sbmac_parse_hwaddr(addr,eaddr);
2834 val = sbmac_addr2reg(eaddr);
2835 __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
2836 val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2840 static struct net_device *dev_sbmac[MAX_UNITS];
2843 sbmac_init_module(void)
2846 struct net_device *dev;
2850 /* Set the number of available units based on the SOC type. */
2852 case K_SYS_SOC_TYPE_BCM1250:
2853 case K_SYS_SOC_TYPE_BCM1250_ALT:
2856 case K_SYS_SOC_TYPE_BCM1120:
2857 case K_SYS_SOC_TYPE_BCM1125:
2858 case K_SYS_SOC_TYPE_BCM1125H:
2859 case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2862 case K_SYS_SOC_TYPE_BCM1x55:
2863 case K_SYS_SOC_TYPE_BCM1x80:
2870 if (chip_max_units > MAX_UNITS)
2871 chip_max_units = MAX_UNITS;
2874 * For bringup when not using the firmware, we can pre-fill
2875 * the MAC addresses using the environment variables
2876 * specified in this file (or maybe from the config file?)
2878 #ifdef SBMAC_ETH0_HWADDR
2879 if (chip_max_units > 0)
2880 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2882 #ifdef SBMAC_ETH1_HWADDR
2883 if (chip_max_units > 1)
2884 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2886 #ifdef SBMAC_ETH2_HWADDR
2887 if (chip_max_units > 2)
2888 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2890 #ifdef SBMAC_ETH3_HWADDR
2891 if (chip_max_units > 3)
2892 sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
2896 * Walk through the Ethernet controllers and find
2897 * those who have their MAC addresses set.
2899 for (idx = 0; idx < chip_max_units; idx++) {
2902 * This is the base address of the MAC.
2905 port = A_MAC_CHANNEL_BASE(idx);
2908 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2909 * value for us by the firmware if we're going to use this MAC.
2910 * If we find a zero, skip this MAC.
2913 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2914 if (sbmac_orig_hwaddr[idx] == 0) {
2915 printk(KERN_DEBUG "sbmac: not configuring MAC at "
2921 * Okay, cool. Initialize this MAC.
2924 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2928 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2930 dev->irq = UNIT_INT(idx);
2931 dev->base_addr = port;
2933 if (sbmac_init(dev, idx)) {
2934 port = A_MAC_CHANNEL_BASE(idx);
2935 __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
2939 dev_sbmac[idx] = dev;
2946 sbmac_cleanup_module(void)
2948 struct net_device *dev;
2951 for (idx = 0; idx < MAX_UNITS; idx++) {
2952 struct sbmac_softc *sc;
2953 dev = dev_sbmac[idx];
2957 sc = netdev_priv(dev);
2958 unregister_netdev(dev);
2959 sbmac_uninitctx(sc);
2964 module_init(sbmac_init_module);
2965 module_exit(sbmac_cleanup_module);