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   1 /*
   2  *  linux/drivers/video/cyber2000fb.c
   3  *
   4  *  Copyright (C) 1998-2002 Russell King
   5  *
   6  *  MIPS and 50xx clock support
   7  *  Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com>
   8  *
   9  *  32 bit support, text color and panning fixes for modes != 8 bit
  10  *  Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device
  17  *
  18  * Based on cyberfb.c.
  19  *
  20  * Note that we now use the new fbcon fix, var and cmap scheme.  We do
  21  * still have to check which console is the currently displayed one
  22  * however, especially for the colourmap stuff.
  23  *
  24  * We also use the new hotplug PCI subsystem.  I'm not sure if there
  25  * are any such cards, but I'm erring on the side of caution.  We don't
  26  * want to go pop just because someone does have one.
  27  *
  28  * Note that this doesn't work fully in the case of multiple CyberPro
  29  * cards with grabbers.  We currently can only attach to the first
  30  * CyberPro card found.
  31  *
  32  * When we're in truecolour mode, we power down the LUT RAM as a power
  33  * saving feature.  Also, when we enter any of the powersaving modes
  34  * (except soft blanking) we power down the RAMDACs.  This saves about
  35  * 1W, which is roughly 8% of the power consumption of a NetWinder
  36  * (which, incidentally, is about the same saving as a 2.5in hard disk
  37  * entering standby mode.)
  38  */
  39 #include <linux/config.h>
  40 #include <linux/module.h>
  41 #include <linux/kernel.h>
  42 #include <linux/errno.h>
  43 #include <linux/string.h>
  44 #include <linux/mm.h>
  45 #include <linux/tty.h>
  46 #include <linux/slab.h>
  47 #include <linux/delay.h>
  48 #include <linux/fb.h>
  49 #include <linux/pci.h>
  50 #include <linux/init.h>
  51
  52 #include <asm/io.h>
  53 #include <asm/irq.h>
  54 #include <asm/pgtable.h>
  55 #include <asm/system.h>
  56 #include <asm/uaccess.h>
  57
  58 #ifdef __arm__
  59 #include <asm/mach-types.h>
  60 #endif
  61
  62 #include "cyber2000fb.h"
  63
  64 struct cfb_info {
  65         struct fb_info          fb;
  66         struct display_switch   *dispsw;
  67         struct display          *display;
  68         struct pci_dev          *dev;
  69         unsigned char           __iomem *region;
  70         unsigned char           __iomem *regs;
  71         u_int                   id;
  72         int                     func_use_count;
  73         u_long                  ref_ps;
  74
  75         /*
  76          * Clock divisors
  77          */
  78         u_int                   divisors[4];
  79
  80         struct {
  81                 u8 red, green, blue;
  82         } palette[NR_PALETTE];
  83
  84         u_char                  mem_ctl1;
  85         u_char                  mem_ctl2;
  86         u_char                  mclk_mult;
  87         u_char                  mclk_div;
  88         /*
  89          * RAMDAC control register is both of these or'ed together
  90          */
  91         u_char                  ramdac_ctrl;
  92         u_char                  ramdac_powerdown;
  93
  94         u32                     pseudo_palette[16];
  95 };
  96
  97 static char *default_font = "Acorn8x8";
  98 module_param(default_font, charp, 0);
  99 MODULE_PARM_DESC(default_font, "Default font name");
 100
 101 /*
 102  * Our access methods.
 103  */
 104 #define cyber2000fb_writel(val,reg,cfb) writel(val, (cfb)->regs + (reg))
 105 #define cyber2000fb_writew(val,reg,cfb) writew(val, (cfb)->regs + (reg))
 106 #define cyber2000fb_writeb(val,reg,cfb) writeb(val, (cfb)->regs + (reg))
 107
 108 #define cyber2000fb_readb(reg,cfb)      readb((cfb)->regs + (reg))
 109
 110 static inline void
 111 cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
 112 {
 113         cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb);
 114 }
 115
 116 static inline void
 117 cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
 118 {
 119         cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb);
 120 }
 121
 122 static inline unsigned int
 123 cyber2000_grphr(unsigned int reg, struct cfb_info *cfb)
 124 {
 125         cyber2000fb_writeb(reg, 0x3ce, cfb);
 126         return cyber2000fb_readb(0x3cf, cfb);
 127 }
 128
 129 static inline void
 130 cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
 131 {
 132         cyber2000fb_readb(0x3da, cfb);
 133         cyber2000fb_writeb(reg, 0x3c0, cfb);
 134         cyber2000fb_readb(0x3c1, cfb);
 135         cyber2000fb_writeb(val, 0x3c0, cfb);
 136 }
 137
 138 static inline void
 139 cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
 140 {
 141         cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb);
 142 }
 143
 144 /* -------------------- Hardware specific routines ------------------------- */
 145
 146 /*
 147  * Hardware Cyber2000 Acceleration
 148  */
 149 static void
 150 cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 151 {
 152         struct cfb_info *cfb = (struct cfb_info *)info;
 153         unsigned long dst, col;
 154
 155         if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
 156                 cfb_fillrect(info, rect);
 157                 return;
 158         }
 159
 160         cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
 161         cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb);
 162         cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb);
 163
 164         col = rect->color;
 165         if (cfb->fb.var.bits_per_pixel > 8)
 166                 col = ((u32 *)cfb->fb.pseudo_palette)[col];
 167         cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb);
 168
 169         dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual;
 170         if (cfb->fb.var.bits_per_pixel == 24) {
 171                 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
 172                 dst *= 3;
 173         }
 174
 175         cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
 176         cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
 177         cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb);
 178         cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb);
 179 }
 180
 181 static void
 182 cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
 183 {
 184         struct cfb_info *cfb = (struct cfb_info *)info;
 185         unsigned int cmd = CO_CMD_L_PATTERN_FGCOL;
 186         unsigned long src, dst;
 187
 188         if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
 189                 cfb_copyarea(info, region);
 190                 return;
 191         }
 192
 193         cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
 194         cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb);
 195         cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb);
 196
 197         src = region->sx + region->sy * cfb->fb.var.xres_virtual;
 198         dst = region->dx + region->dy * cfb->fb.var.xres_virtual;
 199
 200         if (region->sx < region->dx) {
 201                 src += region->width - 1;
 202                 dst += region->width - 1;
 203                 cmd |= CO_CMD_L_INC_LEFT;
 204         }
 205
 206         if (region->sy < region->dy) {
 207                 src += (region->height - 1) * cfb->fb.var.xres_virtual;
 208                 dst += (region->height - 1) * cfb->fb.var.xres_virtual;
 209                 cmd |= CO_CMD_L_INC_UP;
 210         }
 211
 212         if (cfb->fb.var.bits_per_pixel == 24) {
 213                 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
 214                 src *= 3;
 215                 dst *= 3;
 216         }
 217         cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb);
 218         cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
 219         cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
 220         cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb);
 221         cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER,
 222                            CO_REG_CMD_H, cfb);
 223 }
 224
 225 static void
 226 cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image)
 227 {
 228 //      struct cfb_info *cfb = (struct cfb_info *)info;
 229
 230 //      if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
 231                 cfb_imageblit(info, image);
 232                 return;
 233 //      }
 234 }
 235
 236 static int cyber2000fb_sync(struct fb_info *info)
 237 {
 238         struct cfb_info *cfb = (struct cfb_info *)info;
 239         int count = 100000;
 240
 241         if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT))
 242                 return 0;
 243
 244         while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) {
 245                 if (!count--) {
 246                         debug_printf("accel_wait timed out\n");
 247                         cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
 248                         break;
 249                 }
 250                 udelay(1);
 251         }
 252         return 0;
 253 }
 254
 255 /*
 256  * ===========================================================================
 257  */
 258
 259 static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf)
 260 {
 261         u_int mask = (1 << bf->length) - 1;
 262
 263         return (val >> (16 - bf->length) & mask) << bf->offset;
 264 }
 265
 266 /*
 267  *    Set a single color register. Return != 0 for invalid regno.
 268  */
 269 static int
 270 cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 271                       u_int transp, struct fb_info *info)
 272 {
 273         struct cfb_info *cfb = (struct cfb_info *)info;
 274         struct fb_var_screeninfo *var = &cfb->fb.var;
 275         u32 pseudo_val;
 276         int ret = 1;
 277
 278         switch (cfb->fb.fix.visual) {
 279         default:
 280                 return 1;
 281
 282         /*
 283          * Pseudocolour:
 284          *         8     8
 285          * pixel --/--+--/-->  red lut  --> red dac
 286          *            |  8
 287          *            +--/--> green lut --> green dac
 288          *            |  8
 289          *            +--/-->  blue lut --> blue dac
 290          */
 291         case FB_VISUAL_PSEUDOCOLOR:
 292                 if (regno >= NR_PALETTE)
 293                         return 1;
 294
 295                 red >>= 8;
 296                 green >>= 8;
 297                 blue >>= 8;
 298
 299                 cfb->palette[regno].red   = red;
 300                 cfb->palette[regno].green = green;
 301                 cfb->palette[regno].blue  = blue;
 302
 303                 cyber2000fb_writeb(regno, 0x3c8, cfb);
 304                 cyber2000fb_writeb(red, 0x3c9, cfb);
 305                 cyber2000fb_writeb(green, 0x3c9, cfb);
 306                 cyber2000fb_writeb(blue, 0x3c9, cfb);
 307                 return 0;
 308
 309         /*
 310          * Direct colour:
 311          *          n     rl
 312          *  pixel --/--+--/-->  red lut  --> red dac
 313          *             |  gl
 314          *             +--/--> green lut --> green dac
 315          *             |  bl
 316          *             +--/-->  blue lut --> blue dac
 317          * n = bpp, rl = red length, gl = green length, bl = blue length
 318          */
 319         case FB_VISUAL_DIRECTCOLOR:
 320                 red >>= 8;
 321                 green >>= 8;
 322                 blue >>= 8;
 323
 324                 if (var->green.length == 6 && regno < 64) {
 325                         cfb->palette[regno << 2].green = green;
 326
 327                         /*
 328                          * The 6 bits of the green component are applied
 329                          * to the high 6 bits of the LUT.
 330                          */
 331                         cyber2000fb_writeb(regno << 2, 0x3c8, cfb);
 332                         cyber2000fb_writeb(cfb->palette[regno >> 1].red, 0x3c9, cfb);
 333                         cyber2000fb_writeb(green, 0x3c9, cfb);
 334                         cyber2000fb_writeb(cfb->palette[regno >> 1].blue, 0x3c9, cfb);
 335
 336                         green = cfb->palette[regno << 3].green;
 337
 338                         ret = 0;
 339                 }
 340
 341                 if (var->green.length >= 5 && regno < 32) {
 342                         cfb->palette[regno << 3].red   = red;
 343                         cfb->palette[regno << 3].green = green;
 344                         cfb->palette[regno << 3].blue  = blue;
 345
 346                         /*
 347                          * The 5 bits of each colour component are
 348                          * applied to the high 5 bits of the LUT.
 349                          */
 350                         cyber2000fb_writeb(regno << 3, 0x3c8, cfb);
 351                         cyber2000fb_writeb(red, 0x3c9, cfb);
 352                         cyber2000fb_writeb(green, 0x3c9, cfb);
 353                         cyber2000fb_writeb(blue, 0x3c9, cfb);
 354                         ret = 0;
 355                 }
 356
 357                 if (var->green.length == 4 && regno < 16) {
 358                         cfb->palette[regno << 4].red   = red;
 359                         cfb->palette[regno << 4].green = green;
 360                         cfb->palette[regno << 4].blue  = blue;
 361
 362                         /*
 363                          * The 5 bits of each colour component are
 364                          * applied to the high 5 bits of the LUT.
 365                          */
 366                         cyber2000fb_writeb(regno << 4, 0x3c8, cfb);
 367                         cyber2000fb_writeb(red, 0x3c9, cfb);
 368                         cyber2000fb_writeb(green, 0x3c9, cfb);
 369                         cyber2000fb_writeb(blue, 0x3c9, cfb);
 370                         ret = 0;
 371                 }
 372
 373                 /*
 374                  * Since this is only used for the first 16 colours, we
 375                  * don't have to care about overflowing for regno >= 32
 376                  */
 377                 pseudo_val = regno << var->red.offset |
 378                              regno << var->green.offset |
 379                              regno << var->blue.offset;
 380                 break;
 381
 382         /*
 383          * True colour:
 384          *          n     rl
 385          *  pixel --/--+--/--> red dac
 386          *             |  gl
 387          *             +--/--> green dac
 388          *             |  bl
 389          *             +--/--> blue dac
 390          * n = bpp, rl = red length, gl = green length, bl = blue length
 391          */
 392         case FB_VISUAL_TRUECOLOR:
 393                 pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp);
 394                 pseudo_val |= convert_bitfield(red, &var->red);
 395                 pseudo_val |= convert_bitfield(green, &var->green);
 396                 pseudo_val |= convert_bitfield(blue, &var->blue);
 397                 break;
 398         }
 399
 400         /*
 401          * Now set our pseudo palette for the CFB16/24/32 drivers.
 402          */
 403         if (regno < 16)
 404                 ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val;
 405
 406         return ret;
 407 }
 408
 409 struct par_info {
 410         /*
 411          * Hardware
 412          */
 413         u_char  clock_mult;
 414         u_char  clock_div;
 415         u_char  extseqmisc;
 416         u_char  co_pixfmt;
 417         u_char  crtc_ofl;
 418         u_char  crtc[19];
 419         u_int   width;
 420         u_int   pitch;
 421         u_int   fetch;
 422
 423         /*
 424          * Other
 425          */
 426         u_char  ramdac;
 427 };
 428
 429 static const u_char crtc_idx[] = {
 430         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 431         0x08, 0x09,
 432         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18
 433 };
 434
 435 static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb)
 436 {
 437         unsigned int i;
 438         unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown;
 439
 440         cyber2000fb_writeb(0x56, 0x3ce, cfb);
 441         i = cyber2000fb_readb(0x3cf, cfb);
 442         cyber2000fb_writeb(i | 4, 0x3cf, cfb);
 443         cyber2000fb_writeb(val, 0x3c6, cfb);
 444         cyber2000fb_writeb(i, 0x3cf, cfb);
 445 }
 446
 447 static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
 448 {
 449         u_int i;
 450
 451         /*
 452          * Blank palette
 453          */
 454         for (i = 0; i < NR_PALETTE; i++) {
 455                 cyber2000fb_writeb(i, 0x3c8, cfb);
 456                 cyber2000fb_writeb(0, 0x3c9, cfb);
 457                 cyber2000fb_writeb(0, 0x3c9, cfb);
 458                 cyber2000fb_writeb(0, 0x3c9, cfb);
 459         }
 460
 461         cyber2000fb_writeb(0xef, 0x3c2, cfb);
 462         cyber2000_crtcw(0x11, 0x0b, cfb);
 463         cyber2000_attrw(0x11, 0x00, cfb);
 464
 465         cyber2000_seqw(0x00, 0x01, cfb);
 466         cyber2000_seqw(0x01, 0x01, cfb);
 467         cyber2000_seqw(0x02, 0x0f, cfb);
 468         cyber2000_seqw(0x03, 0x00, cfb);
 469         cyber2000_seqw(0x04, 0x0e, cfb);
 470         cyber2000_seqw(0x00, 0x03, cfb);
 471
 472         for (i = 0; i < sizeof(crtc_idx); i++)
 473                 cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb);
 474
 475         for (i = 0x0a; i < 0x10; i++)
 476                 cyber2000_crtcw(i, 0, cfb);
 477
 478         cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb);
 479         cyber2000_grphw(0x00, 0x00, cfb);
 480         cyber2000_grphw(0x01, 0x00, cfb);
 481         cyber2000_grphw(0x02, 0x00, cfb);
 482         cyber2000_grphw(0x03, 0x00, cfb);
 483         cyber2000_grphw(0x04, 0x00, cfb);
 484         cyber2000_grphw(0x05, 0x60, cfb);
 485         cyber2000_grphw(0x06, 0x05, cfb);
 486         cyber2000_grphw(0x07, 0x0f, cfb);
 487         cyber2000_grphw(0x08, 0xff, cfb);
 488
 489         /* Attribute controller registers */
 490         for (i = 0; i < 16; i++)
 491                 cyber2000_attrw(i, i, cfb);
 492
 493         cyber2000_attrw(0x10, 0x01, cfb);
 494         cyber2000_attrw(0x11, 0x00, cfb);
 495         cyber2000_attrw(0x12, 0x0f, cfb);
 496         cyber2000_attrw(0x13, 0x00, cfb);
 497         cyber2000_attrw(0x14, 0x00, cfb);
 498
 499         /* PLL registers */
 500         cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb);
 501         cyber2000_grphw(EXT_DCLK_DIV,  hw->clock_div, cfb);
 502         cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb);
 503         cyber2000_grphw(EXT_MCLK_DIV,  cfb->mclk_div, cfb);
 504         cyber2000_grphw(0x90, 0x01, cfb);
 505         cyber2000_grphw(0xb9, 0x80, cfb);
 506         cyber2000_grphw(0xb9, 0x00, cfb);
 507
 508         cfb->ramdac_ctrl = hw->ramdac;
 509         cyber2000fb_write_ramdac_ctrl(cfb);
 510
 511         cyber2000fb_writeb(0x20, 0x3c0, cfb);
 512         cyber2000fb_writeb(0xff, 0x3c6, cfb);
 513
 514         cyber2000_grphw(0x14, hw->fetch, cfb);
 515         cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) |
 516                               ((hw->pitch >> 4) & 0x30), cfb);
 517         cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb);
 518
 519         /*
 520          * Set up accelerator registers
 521          */
 522         cyber2000fb_writew(hw->width,     CO_REG_SRC_WIDTH,  cfb);
 523         cyber2000fb_writew(hw->width,     CO_REG_DEST_WIDTH, cfb);
 524         cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb);
 525 }
 526
 527 static inline int
 528 cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var)
 529 {
 530         u_int base = var->yoffset * var->xres_virtual + var->xoffset;
 531
 532         base *= var->bits_per_pixel;
 533
 534         /*
 535          * Convert to bytes and shift two extra bits because DAC
 536          * can only start on 4 byte aligned data.
 537          */
 538         base >>= 5;
 539
 540         if (base >= 1 << 20)
 541                 return -EINVAL;
 542
 543         cyber2000_grphw(0x10, base >> 16 | 0x10, cfb);
 544         cyber2000_crtcw(0x0c, base >> 8, cfb);
 545         cyber2000_crtcw(0x0d, base, cfb);
 546
 547         return 0;
 548 }
 549
 550 static int
 551 cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb,
 552                         struct fb_var_screeninfo *var)
 553 {
 554         u_int Htotal, Hblankend, Hsyncend;
 555         u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend;
 556 #define BIT(v,b1,m,b2) (((v >> b1) & m) << b2)
 557
 558         hw->crtc[13] = hw->pitch;
 559         hw->crtc[17] = 0xe3;
 560         hw->crtc[14] = 0;
 561         hw->crtc[8]  = 0;
 562
 563         Htotal      = var->xres + var->right_margin +
 564                       var->hsync_len + var->left_margin;
 565
 566         if (Htotal > 2080)
 567                 return -EINVAL;
 568
 569         hw->crtc[0] = (Htotal >> 3) - 5;
 570         hw->crtc[1] = (var->xres >> 3) - 1;
 571         hw->crtc[2] = var->xres >> 3;
 572         hw->crtc[4] = (var->xres + var->right_margin) >> 3;
 573
 574         Hblankend   = (Htotal - 4*8) >> 3;
 575
 576         hw->crtc[3] = BIT(Hblankend,  0, 0x1f,  0) |
 577                       BIT(1,          0, 0x01,  7);
 578
 579         Hsyncend    = (var->xres + var->right_margin + var->hsync_len) >> 3;
 580
 581         hw->crtc[5] = BIT(Hsyncend,   0, 0x1f,  0) |
 582                       BIT(Hblankend,  5, 0x01,  7);
 583
 584         Vdispend    = var->yres - 1;
 585         Vsyncstart  = var->yres + var->lower_margin;
 586         Vsyncend    = var->yres + var->lower_margin + var->vsync_len;
 587         Vtotal      = var->yres + var->lower_margin + var->vsync_len +
 588                       var->upper_margin - 2;
 589
 590         if (Vtotal > 2047)
 591                 return -EINVAL;
 592
 593         Vblankstart = var->yres + 6;
 594         Vblankend   = Vtotal - 10;
 595
 596         hw->crtc[6]  = Vtotal;
 597         hw->crtc[7]  = BIT(Vtotal,     8, 0x01,  0) |
 598                         BIT(Vdispend,   8, 0x01,  1) |
 599                         BIT(Vsyncstart, 8, 0x01,  2) |
 600                         BIT(Vblankstart,8, 0x01,  3) |
 601                         BIT(1,          0, 0x01,  4) |
 602                         BIT(Vtotal,     9, 0x01,  5) |
 603                         BIT(Vdispend,   9, 0x01,  6) |
 604                         BIT(Vsyncstart, 9, 0x01,  7);
 605         hw->crtc[9]  = BIT(0,          0, 0x1f,  0) |
 606                         BIT(Vblankstart,9, 0x01,  5) |
 607                         BIT(1,          0, 0x01,  6);
 608         hw->crtc[10] = Vsyncstart;
 609         hw->crtc[11] = BIT(Vsyncend,   0, 0x0f,  0) |
 610                        BIT(1,          0, 0x01,  7);
 611         hw->crtc[12] = Vdispend;
 612         hw->crtc[15] = Vblankstart;
 613         hw->crtc[16] = Vblankend;
 614         hw->crtc[18] = 0xff;
 615
 616         /*
 617          * overflow - graphics reg 0x11
 618          * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10
 619          * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT
 620          */
 621         hw->crtc_ofl =
 622                 BIT(Vtotal,     10, 0x01,  0) |
 623                 BIT(Vdispend,   10, 0x01,  1) |
 624                 BIT(Vsyncstart, 10, 0x01,  2) |
 625                 BIT(Vblankstart,10, 0x01,  3) |
 626                 EXT_CRT_VRTOFL_LINECOMP10;
 627
 628         /* woody: set the interlaced bit... */
 629         /* FIXME: what about doublescan? */
 630         if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
 631                 hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE;
 632
 633         return 0;
 634 }
 635
 636 /*
 637  * The following was discovered by a good monitor, bit twiddling, theorising
 638  * and but mostly luck.  Strangely, it looks like everyone elses' PLL!
 639  *
 640  * Clock registers:
 641  *   fclock = fpll / div2
 642  *   fpll   = fref * mult / div1
 643  * where:
 644  *   fref = 14.318MHz (69842ps)
 645  *   mult = reg0xb0.7:0
 646  *   div1 = (reg0xb1.5:0 + 1)
 647  *   div2 =  2^(reg0xb1.7:6)
 648  *   fpll should be between 115 and 260 MHz
 649  *  (8696ps and 3846ps)
 650  */
 651 static int
 652 cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb,
 653                          struct fb_var_screeninfo *var)
 654 {
 655         u_long pll_ps = var->pixclock;
 656         const u_long ref_ps = cfb->ref_ps;
 657         u_int div2, t_div1, best_div1, best_mult;
 658         int best_diff;
 659         int vco;
 660
 661         /*
 662          * Step 1:
 663          *   find div2 such that 115MHz < fpll < 260MHz
 664          *   and 0 <= div2 < 4
 665          */
 666         for (div2 = 0; div2 < 4; div2++) {
 667                 u_long new_pll;
 668
 669                 new_pll = pll_ps / cfb->divisors[div2];
 670                 if (8696 > new_pll && new_pll > 3846) {
 671                         pll_ps = new_pll;
 672                         break;
 673                 }
 674         }
 675
 676         if (div2 == 4)
 677                 return -EINVAL;
 678
 679         /*
 680          * Step 2:
 681          *  Given pll_ps and ref_ps, find:
 682          *    pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005
 683          *  where { 1 < best_div1 < 32, 1 < best_mult < 256 }
 684          *    pll_ps_calc = best_div1 / (ref_ps * best_mult)
 685          */
 686         best_diff = 0x7fffffff;
 687         best_mult = 32;
 688         best_div1 = 255;
 689         for (t_div1 = 32; t_div1 > 1; t_div1 -= 1) {
 690                 u_int rr, t_mult, t_pll_ps;
 691                 int diff;
 692
 693                 /*
 694                  * Find the multiplier for this divisor
 695                  */
 696                 rr = ref_ps * t_div1;
 697                 t_mult = (rr + pll_ps / 2) / pll_ps;
 698
 699                 /*
 700                  * Is the multiplier within the correct range?
 701                  */
 702                 if (t_mult > 256 || t_mult < 2)
 703                         continue;
 704
 705                 /*
 706                  * Calculate the actual clock period from this multiplier
 707                  * and divisor, and estimate the error.
 708                  */
 709                 t_pll_ps = (rr + t_mult / 2) / t_mult;
 710                 diff = pll_ps - t_pll_ps;
 711                 if (diff < 0)
 712                         diff = -diff;
 713
 714                 if (diff < best_diff) {
 715                         best_diff = diff;
 716                         best_mult = t_mult;
 717                         best_div1 = t_div1;
 718                 }
 719
 720                 /*
 721                  * If we hit an exact value, there is no point in continuing.
 722                  */
 723                 if (diff == 0)
 724                         break;
 725         }
 726
 727         /*
 728          * Step 3:
 729          *  combine values
 730          */
 731         hw->clock_mult = best_mult - 1;
 732         hw->clock_div  = div2 << 6 | (best_div1 - 1);
 733
 734         vco = ref_ps * best_div1 / best_mult;
 735         if ((ref_ps == 40690) && (vco < 5556))
 736                 /* Set VFSEL when VCO > 180MHz (5.556 ps). */
 737                 hw->clock_div |= EXT_DCLK_DIV_VFSEL;
 738
 739         return 0;
 740 }
 741
 742 /*
 743  *    Set the User Defined Part of the Display
 744  */
 745 static int
 746 cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 747 {
 748         struct cfb_info *cfb = (struct cfb_info *)info;
 749         struct par_info hw;
 750         unsigned int mem;
 751         int err;
 752
 753         var->transp.msb_right   = 0;
 754         var->red.msb_right      = 0;
 755         var->green.msb_right    = 0;
 756         var->blue.msb_right     = 0;
 757
 758         switch (var->bits_per_pixel) {
 759         case 8: /* PSEUDOCOLOUR, 256 */
 760                 var->transp.offset      = 0;
 761                 var->transp.length      = 0;
 762                 var->red.offset         = 0;
 763                 var->red.length         = 8;
 764                 var->green.offset       = 0;
 765                 var->green.length       = 8;
 766                 var->blue.offset        = 0;
 767                 var->blue.length        = 8;
 768                 break;
 769
 770         case 16:/* DIRECTCOLOUR, 64k or 32k */
 771                 switch (var->green.length) {
 772                 case 6: /* RGB565, 64k */
 773                         var->transp.offset      = 0;
 774                         var->transp.length      = 0;
 775                         var->red.offset         = 11;
 776                         var->red.length         = 5;
 777                         var->green.offset       = 5;
 778                         var->green.length       = 6;
 779                         var->blue.offset        = 0;
 780                         var->blue.length        = 5;
 781                         break;
 782
 783                 default:
 784                 case 5: /* RGB555, 32k */
 785                         var->transp.offset      = 0;
 786                         var->transp.length      = 0;
 787                         var->red.offset         = 10;
 788                         var->red.length         = 5;
 789                         var->green.offset       = 5;
 790                         var->green.length       = 5;
 791                         var->blue.offset        = 0;
 792                         var->blue.length        = 5;
 793                         break;
 794
 795                 case 4: /* RGB444, 4k + transparency? */
 796                         var->transp.offset      = 12;
 797                         var->transp.length      = 4;
 798                         var->red.offset         = 8;
 799                         var->red.length         = 4;
 800                         var->green.offset       = 4;
 801                         var->green.length       = 4;
 802                         var->blue.offset        = 0;
 803                         var->blue.length        = 4;
 804                         break;
 805                 }
 806                 break;
 807
 808         case 24:/* TRUECOLOUR, 16m */
 809                 var->transp.offset      = 0;
 810                 var->transp.length      = 0;
 811                 var->red.offset         = 16;
 812                 var->red.length         = 8;
 813                 var->green.offset       = 8;
 814                 var->green.length       = 8;
 815                 var->blue.offset        = 0;
 816                 var->blue.length        = 8;
 817                 break;
 818
 819         case 32:/* TRUECOLOUR, 16m */
 820                 var->transp.offset      = 24;
 821                 var->transp.length      = 8;
 822                 var->red.offset         = 16;
 823                 var->red.length         = 8;
 824                 var->green.offset       = 8;
 825                 var->green.length       = 8;
 826                 var->blue.offset        = 0;
 827                 var->blue.length        = 8;
 828                 break;
 829
 830         default:
 831                 return -EINVAL;
 832         }
 833
 834         mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8);
 835         if (mem > cfb->fb.fix.smem_len)
 836                 var->yres_virtual = cfb->fb.fix.smem_len * 8 /
 837                         (var->bits_per_pixel * var->xres_virtual);
 838
 839         if (var->yres > var->yres_virtual)
 840                 var->yres = var->yres_virtual;
 841         if (var->xres > var->xres_virtual)
 842                 var->xres = var->xres_virtual;
 843
 844         err = cyber2000fb_decode_clock(&hw, cfb, var);
 845         if (err)
 846                 return err;
 847
 848         err = cyber2000fb_decode_crtc(&hw, cfb, var);
 849         if (err)
 850                 return err;
 851
 852         return 0;
 853 }
 854
 855 static int cyber2000fb_set_par(struct fb_info *info)
 856 {
 857         struct cfb_info *cfb = (struct cfb_info *)info;
 858         struct fb_var_screeninfo *var = &cfb->fb.var;
 859         struct par_info hw;
 860         unsigned int mem;
 861
 862         hw.width = var->xres_virtual;
 863         hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT;
 864
 865         switch (var->bits_per_pixel) {
 866         case 8:
 867                 hw.co_pixfmt            = CO_PIXFMT_8BPP;
 868                 hw.pitch                = hw.width >> 3;
 869                 hw.extseqmisc           = EXT_SEQ_MISC_8;
 870                 break;
 871
 872         case 16:
 873                 hw.co_pixfmt            = CO_PIXFMT_16BPP;
 874                 hw.pitch                = hw.width >> 2;
 875
 876                 switch (var->green.length) {
 877                 case 6: /* RGB565, 64k */
 878                         hw.extseqmisc   = EXT_SEQ_MISC_16_RGB565;
 879                         break;
 880                 case 5: /* RGB555, 32k */
 881                         hw.extseqmisc   = EXT_SEQ_MISC_16_RGB555;
 882                         break;
 883                 case 4: /* RGB444, 4k + transparency? */
 884                         hw.extseqmisc   = EXT_SEQ_MISC_16_RGB444;
 885                         break;
 886                 default:
 887                         BUG();
 888                 }
 889         case 24:/* TRUECOLOUR, 16m */
 890                 hw.co_pixfmt            = CO_PIXFMT_24BPP;
 891                 hw.width                *= 3;
 892                 hw.pitch                = hw.width >> 3;
 893                 hw.ramdac               |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
 894                 hw.extseqmisc           = EXT_SEQ_MISC_24_RGB888;
 895                 break;
 896
 897         case 32:/* TRUECOLOUR, 16m */
 898                 hw.co_pixfmt            = CO_PIXFMT_32BPP;
 899                 hw.pitch                = hw.width >> 1;
 900                 hw.ramdac               |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
 901                 hw.extseqmisc           = EXT_SEQ_MISC_32;
 902                 break;
 903
 904         default:
 905                 BUG();
 906         }
 907
 908         /*
 909          * Sigh, this is absolutely disgusting, but caused by
 910          * the way the fbcon developers want to separate out
 911          * the "checking" and the "setting" of the video mode.
 912          *
 913          * If the mode is not suitable for the hardware here,
 914          * we can't prevent it being set by returning an error.
 915          *
 916          * In theory, since NetWinders contain just one VGA card,
 917          * we should never end up hitting this problem.
 918          */
 919         BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0);
 920         BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0);
 921
 922         hw.width -= 1;
 923         hw.fetch = hw.pitch;
 924         if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT))
 925                 hw.fetch <<= 1;
 926         hw.fetch += 1;
 927
 928         cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
 929
 930         /*
 931          * Same here - if the size of the video mode exceeds the
 932          * available RAM, we can't prevent this mode being set.
 933          *
 934          * In theory, since NetWinders contain just one VGA card,
 935          * we should never end up hitting this problem.
 936          */
 937         mem = cfb->fb.fix.line_length * var->yres_virtual;
 938         BUG_ON(mem > cfb->fb.fix.smem_len);
 939
 940         /*
 941          * 8bpp displays are always pseudo colour.  16bpp and above
 942          * are direct colour or true colour, depending on whether
 943          * the RAMDAC palettes are bypassed.  (Direct colour has
 944          * palettes, true colour does not.)
 945          */
 946         if (var->bits_per_pixel == 8)
 947                 cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
 948         else if (hw.ramdac & RAMDAC_BYPASS)
 949                 cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
 950         else
 951                 cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR;
 952
 953         cyber2000fb_set_timing(cfb, &hw);
 954         cyber2000fb_update_start(cfb, var);
 955
 956         return 0;
 957 }
 958
 959
 960 /*
 961  *    Pan or Wrap the Display
 962  */
 963 static int
 964 cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 965 {
 966         struct cfb_info *cfb = (struct cfb_info *)info;
 967
 968         if (cyber2000fb_update_start(cfb, var))
 969                 return -EINVAL;
 970
 971         cfb->fb.var.xoffset = var->xoffset;
 972         cfb->fb.var.yoffset = var->yoffset;
 973
 974         if (var->vmode & FB_VMODE_YWRAP) {
 975                 cfb->fb.var.vmode |= FB_VMODE_YWRAP;
 976         } else {
 977                 cfb->fb.var.vmode &= ~FB_VMODE_YWRAP;
 978         }
 979
 980         return 0;
 981 }
 982
 983 /*
 984  *    (Un)Blank the display.
 985  *
 986  *  Blank the screen if blank_mode != 0, else unblank. If
 987  *  blank == NULL then the caller blanks by setting the CLUT
 988  *  (Color Look Up Table) to all black. Return 0 if blanking
 989  *  succeeded, != 0 if un-/blanking failed due to e.g. a
 990  *  video mode which doesn't support it. Implements VESA
 991  *  suspend and powerdown modes on hardware that supports
 992  *  disabling hsync/vsync:
 993  *    blank_mode == 2: suspend vsync
 994  *    blank_mode == 3: suspend hsync
 995  *    blank_mode == 4: powerdown
 996  *
 997  *  wms...Enable VESA DMPS compatible powerdown mode
 998  *  run "setterm -powersave powerdown" to take advantage
 999  */
1000 static int cyber2000fb_blank(int blank, struct fb_info *info)
1001 {
1002         struct cfb_info *cfb = (struct cfb_info *)info;
1003         unsigned int sync = 0;
1004         int i;
1005
1006         switch (blank) {
1007         case FB_BLANK_POWERDOWN:        /* powerdown - both sync lines down */
1008                 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0;
1009                 break;
1010         case FB_BLANK_HSYNC_SUSPEND:    /* hsync off */
1011                 sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0;
1012                 break;
1013         case FB_BLANK_VSYNC_SUSPEND:    /* vsync off */
1014                 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL;
1015                 break;
1016         case FB_BLANK_NORMAL:           /* soft blank */
1017         default: /* unblank */
1018                 break;
1019         }
1020
1021         cyber2000_grphw(EXT_SYNC_CTL, sync, cfb);
1022
1023         if (blank <= 1) {
1024                 /* turn on ramdacs */
1025                 cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
1026                 cyber2000fb_write_ramdac_ctrl(cfb);
1027         }
1028
1029         /*
1030          * Soft blank/unblank the display.
1031          */
1032         if (blank) {    /* soft blank */
1033                 for (i = 0; i < NR_PALETTE; i++) {
1034                         cyber2000fb_writeb(i, 0x3c8, cfb);
1035                         cyber2000fb_writeb(0, 0x3c9, cfb);
1036                         cyber2000fb_writeb(0, 0x3c9, cfb);
1037                         cyber2000fb_writeb(0, 0x3c9, cfb);
1038                 }
1039         } else {        /* unblank */
1040                 for (i = 0; i < NR_PALETTE; i++) {
1041                         cyber2000fb_writeb(i, 0x3c8, cfb);
1042                         cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb);
1043                         cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb);
1044                         cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb);
1045                 }
1046         }
1047
1048         if (blank >= 2) {
1049                 /* turn off ramdacs */
1050                 cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN;
1051                 cyber2000fb_write_ramdac_ctrl(cfb);
1052         }
1053
1054         return 0;
1055 }
1056
1057 static struct fb_ops cyber2000fb_ops = {
1058         .owner          = THIS_MODULE,
1059         .fb_check_var   = cyber2000fb_check_var,
1060         .fb_set_par     = cyber2000fb_set_par,
1061         .fb_setcolreg   = cyber2000fb_setcolreg,
1062         .fb_blank       = cyber2000fb_blank,
1063         .fb_pan_display = cyber2000fb_pan_display,
1064         .fb_fillrect    = cyber2000fb_fillrect,
1065         .fb_copyarea    = cyber2000fb_copyarea,
1066         .fb_imageblit   = cyber2000fb_imageblit,
1067         .fb_sync        = cyber2000fb_sync,
1068 };
1069
1070 /*
1071  * This is the only "static" reference to the internal data structures
1072  * of this driver.  It is here solely at the moment to support the other
1073  * CyberPro modules external to this driver.
1074  */
1075 static struct cfb_info          *int_cfb_info;
1076
1077 /*
1078  * Enable access to the extended registers
1079  */
1080 void cyber2000fb_enable_extregs(struct cfb_info *cfb)
1081 {
1082         cfb->func_use_count += 1;
1083
1084         if (cfb->func_use_count == 1) {
1085                 int old;
1086
1087                 old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1088                 old |= EXT_FUNC_CTL_EXTREGENBL;
1089                 cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1090         }
1091 }
1092
1093 /*
1094  * Disable access to the extended registers
1095  */
1096 void cyber2000fb_disable_extregs(struct cfb_info *cfb)
1097 {
1098         if (cfb->func_use_count == 1) {
1099                 int old;
1100
1101                 old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1102                 old &= ~EXT_FUNC_CTL_EXTREGENBL;
1103                 cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1104         }
1105
1106         if (cfb->func_use_count == 0)
1107                 printk(KERN_ERR "disable_extregs: count = 0\n");
1108         else
1109                 cfb->func_use_count -= 1;
1110 }
1111
1112 void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var)
1113 {
1114         memcpy(var, &cfb->fb.var, sizeof(struct fb_var_screeninfo));
1115 }
1116
1117 /*
1118  * Attach a capture/tv driver to the core CyberX0X0 driver.
1119  */
1120 int cyber2000fb_attach(struct cyberpro_info *info, int idx)
1121 {
1122         if (int_cfb_info != NULL) {
1123                 info->dev             = int_cfb_info->dev;
1124                 info->regs            = int_cfb_info->regs;
1125                 info->fb              = int_cfb_info->fb.screen_base;
1126                 info->fb_size         = int_cfb_info->fb.fix.smem_len;
1127                 info->enable_extregs  = cyber2000fb_enable_extregs;
1128                 info->disable_extregs = cyber2000fb_disable_extregs;
1129                 info->info            = int_cfb_info;
1130
1131                 strlcpy(info->dev_name, int_cfb_info->fb.fix.id, sizeof(info->dev_name));
1132         }
1133
1134         return int_cfb_info != NULL;
1135 }
1136
1137 /*
1138  * Detach a capture/tv driver from the core CyberX0X0 driver.
1139  */
1140 void cyber2000fb_detach(int idx)
1141 {
1142 }
1143
1144 EXPORT_SYMBOL(cyber2000fb_attach);
1145 EXPORT_SYMBOL(cyber2000fb_detach);
1146 EXPORT_SYMBOL(cyber2000fb_enable_extregs);
1147 EXPORT_SYMBOL(cyber2000fb_disable_extregs);
1148 EXPORT_SYMBOL(cyber2000fb_get_fb_var);
1149
1150 /*
1151  * These parameters give
1152  * 640x480, hsync 31.5kHz, vsync 60Hz
1153  */
1154 static struct fb_videomode __devinitdata cyber2000fb_default_mode = {
1155         .refresh        = 60,
1156         .xres           = 640,
1157         .yres           = 480,
1158         .pixclock       = 39722,
1159         .left_margin    = 56,
1160         .right_margin   = 16,
1161         .upper_margin   = 34,
1162         .lower_margin   = 9,
1163         .hsync_len      = 88,
1164         .vsync_len      = 2,
1165         .sync           = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1166         .vmode          = FB_VMODE_NONINTERLACED
1167 };
1168
1169 static char igs_regs[] = {
1170         EXT_CRT_IRQ,            0,
1171         EXT_CRT_TEST,           0,
1172         EXT_SYNC_CTL,           0,
1173         EXT_SEG_WRITE_PTR,      0,
1174         EXT_SEG_READ_PTR,       0,
1175         EXT_BIU_MISC,           EXT_BIU_MISC_LIN_ENABLE |
1176                                 EXT_BIU_MISC_COP_ENABLE |
1177                                 EXT_BIU_MISC_COP_BFC,
1178         EXT_FUNC_CTL,           0,
1179         CURS_H_START,           0,
1180         CURS_H_START + 1,       0,
1181         CURS_H_PRESET,          0,
1182         CURS_V_START,           0,
1183         CURS_V_START + 1,       0,
1184         CURS_V_PRESET,          0,
1185         CURS_CTL,               0,
1186         EXT_ATTRIB_CTL,         EXT_ATTRIB_CTL_EXT,
1187         EXT_OVERSCAN_RED,       0,
1188         EXT_OVERSCAN_GREEN,     0,
1189         EXT_OVERSCAN_BLUE,      0,
1190
1191         /* some of these are questionable when we have a BIOS */
1192         EXT_MEM_CTL0,           EXT_MEM_CTL0_7CLK |
1193                                 EXT_MEM_CTL0_RAS_1 |
1194                                 EXT_MEM_CTL0_MULTCAS,
1195         EXT_HIDDEN_CTL1,        0x30,
1196         EXT_FIFO_CTL,           0x0b,
1197         EXT_FIFO_CTL + 1,       0x17,
1198         0x76,                   0x00,
1199         EXT_HIDDEN_CTL4,        0xc8
1200 };
1201
1202 /*
1203  * Initialise the CyberPro hardware.  On the CyberPro5XXXX,
1204  * ensure that we're using the correct PLL (5XXX's may be
1205  * programmed to use an additional set of PLLs.)
1206  */
1207 static void cyberpro_init_hw(struct cfb_info *cfb)
1208 {
1209         int i;
1210
1211         for (i = 0; i < sizeof(igs_regs); i += 2)
1212                 cyber2000_grphw(igs_regs[i], igs_regs[i+1], cfb);
1213
1214         if (cfb->id == ID_CYBERPRO_5000) {
1215                 unsigned char val;
1216                 cyber2000fb_writeb(0xba, 0x3ce, cfb);
1217                 val = cyber2000fb_readb(0x3cf, cfb) & 0x80;
1218                 cyber2000fb_writeb(val, 0x3cf, cfb);
1219         }
1220 }
1221
1222 static struct cfb_info * __devinit
1223 cyberpro_alloc_fb_info(unsigned int id, char *name)
1224 {
1225         struct cfb_info *cfb;
1226
1227         cfb = kmalloc(sizeof(struct cfb_info), GFP_KERNEL);
1228         if (!cfb)
1229                 return NULL;
1230
1231         memset(cfb, 0, sizeof(struct cfb_info));
1232
1233         cfb->id                 = id;
1234
1235         if (id == ID_CYBERPRO_5000)
1236                 cfb->ref_ps     = 40690; // 24.576 MHz
1237         else
1238                 cfb->ref_ps     = 69842; // 14.31818 MHz (69841?)
1239
1240         cfb->divisors[0]        = 1;
1241         cfb->divisors[1]        = 2;
1242         cfb->divisors[2]        = 4;
1243
1244         if (id == ID_CYBERPRO_2000)
1245                 cfb->divisors[3] = 8;
1246         else
1247                 cfb->divisors[3] = 6;
1248
1249         strcpy(cfb->fb.fix.id, name);
1250
1251         cfb->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1252         cfb->fb.fix.type_aux    = 0;
1253         cfb->fb.fix.xpanstep    = 0;
1254         cfb->fb.fix.ypanstep    = 1;
1255         cfb->fb.fix.ywrapstep   = 0;
1256
1257         switch (id) {
1258         case ID_IGA_1682:
1259                 cfb->fb.fix.accel = 0;
1260                 break;
1261
1262         case ID_CYBERPRO_2000:
1263                 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000;
1264                 break;
1265
1266         case ID_CYBERPRO_2010:
1267                 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010;
1268                 break;
1269
1270         case ID_CYBERPRO_5000:
1271                 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000;
1272                 break;
1273         }
1274
1275         cfb->fb.var.nonstd      = 0;
1276         cfb->fb.var.activate    = FB_ACTIVATE_NOW;
1277         cfb->fb.var.height      = -1;
1278         cfb->fb.var.width       = -1;
1279         cfb->fb.var.accel_flags = FB_ACCELF_TEXT;
1280
1281         cfb->fb.fbops           = &cyber2000fb_ops;
1282         cfb->fb.flags           = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1283         cfb->fb.pseudo_palette  = cfb->pseudo_palette;
1284
1285         fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0);
1286
1287         return cfb;
1288 }
1289
1290 static void
1291 cyberpro_free_fb_info(struct cfb_info *cfb)
1292 {
1293         if (cfb) {
1294                 /*
1295                  * Free the colourmap
1296                  */
1297                 fb_alloc_cmap(&cfb->fb.cmap, 0, 0);
1298
1299                 kfree(cfb);
1300         }
1301 }
1302
1303 /*
1304  * Parse Cyber2000fb options.  Usage:
1305  *  video=cyber2000:font:fontname
1306  */
1307 #ifndef MODULE
1308 static int
1309 cyber2000fb_setup(char *options)
1310 {
1311         char *opt;
1312
1313         if (!options || !*options)
1314                 return 0;
1315
1316         while ((opt = strsep(&options, ",")) != NULL) {
1317                 if (!*opt)
1318                         continue;
1319
1320                 if (strncmp(opt, "font:", 5) == 0) {
1321                         static char default_font_storage[40];
1322
1323                         strlcpy(default_font_storage, opt + 5, sizeof(default_font_storage));
1324                         default_font = default_font_storage;
1325                         continue;
1326                 }
1327
1328                 printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt);
1329         }
1330         return 0;
1331 }
1332 #endif  /*  MODULE  */
1333
1334 /*
1335  * The CyberPro chips can be placed on many different bus types.
1336  * This probe function is common to all bus types.  The bus-specific
1337  * probe function is expected to have:
1338  *  - enabled access to the linear memory region
1339  *  - memory mapped access to the registers
1340  *  - initialised mem_ctl1 and mem_ctl2 appropriately.
1341  */
1342 static int __devinit cyberpro_common_probe(struct cfb_info *cfb)
1343 {
1344         u_long smem_size;
1345         u_int h_sync, v_sync;
1346         int err;
1347
1348         cyberpro_init_hw(cfb);
1349
1350         /*
1351          * Get the video RAM size and width from the VGA register.
1352          * This should have been already initialised by the BIOS,
1353          * but if it's garbage, claim default 1MB VRAM (woody)
1354          */
1355         cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb);
1356         cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb);
1357
1358         /*
1359          * Determine the size of the memory.
1360          */
1361         switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) {
1362         case MEM_CTL2_SIZE_4MB: smem_size = 0x00400000; break;
1363         case MEM_CTL2_SIZE_2MB: smem_size = 0x00200000; break;
1364         case MEM_CTL2_SIZE_1MB: smem_size = 0x00100000; break;
1365         default:                smem_size = 0x00100000; break;
1366         }
1367
1368         cfb->fb.fix.smem_len   = smem_size;
1369         cfb->fb.fix.mmio_len   = MMIO_SIZE;
1370         cfb->fb.screen_base    = cfb->region;
1371
1372         err = -EINVAL;
1373         if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0,
1374                           &cyber2000fb_default_mode, 8)) {
1375                 printk("%s: no valid mode found\n", cfb->fb.fix.id);
1376                 goto failed;
1377         }
1378
1379         cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 /
1380                         (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual);
1381
1382         if (cfb->fb.var.yres_virtual < cfb->fb.var.yres)
1383                 cfb->fb.var.yres_virtual = cfb->fb.var.yres;
1384
1385 //      fb_set_var(&cfb->fb.var, -1, &cfb->fb);
1386
1387         /*
1388          * Calculate the hsync and vsync frequencies.  Note that
1389          * we split the 1e12 constant up so that we can preserve
1390          * the precision and fit the results into 32-bit registers.
1391          *  (1953125000 * 512 = 1e12)
1392          */
1393         h_sync = 1953125000 / cfb->fb.var.pixclock;
1394         h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin +
1395                  cfb->fb.var.right_margin + cfb->fb.var.hsync_len);
1396         v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin +
1397                  cfb->fb.var.lower_margin + cfb->fb.var.vsync_len);
1398
1399         printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
1400                 cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10,
1401                 cfb->fb.var.xres, cfb->fb.var.yres,
1402                 h_sync / 1000, h_sync % 1000, v_sync);
1403
1404         if (cfb->dev)
1405                 cfb->fb.device = &cfb->dev->dev;
1406         err = register_framebuffer(&cfb->fb);
1407
1408 failed:
1409         return err;
1410 }
1411
1412 static void cyberpro_common_resume(struct cfb_info *cfb)
1413 {
1414         cyberpro_init_hw(cfb);
1415
1416         /*
1417          * Reprogram the MEM_CTL1 and MEM_CTL2 registers
1418          */
1419         cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb);
1420         cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb);
1421
1422         /*
1423          * Restore the old video mode and the palette.
1424          * We also need to tell fbcon to redraw the console.
1425          */
1426         cyber2000fb_set_par(&cfb->fb);
1427 }
1428
1429 #ifdef CONFIG_ARCH_SHARK
1430
1431 #include <asm/arch/hardware.h>
1432
1433 static int __devinit
1434 cyberpro_vl_probe(void)
1435 {
1436         struct cfb_info *cfb;
1437         int err = -ENOMEM;
1438
1439         if (!request_mem_region(FB_START,FB_SIZE,"CyberPro2010")) return err;
1440
1441         cfb = cyberpro_alloc_fb_info(ID_CYBERPRO_2010, "CyberPro2010");
1442         if (!cfb)
1443                 goto failed_release;
1444
1445         cfb->dev = NULL;
1446         cfb->region = ioremap(FB_START,FB_SIZE);
1447         if (!cfb->region)
1448                 goto failed_ioremap;
1449
1450         cfb->regs = cfb->region + MMIO_OFFSET;
1451         cfb->fb.fix.mmio_start = FB_START + MMIO_OFFSET;
1452         cfb->fb.fix.smem_start = FB_START;
1453
1454         /*
1455          * Bring up the hardware.  This is expected to enable access
1456          * to the linear memory region, and allow access to the memory
1457          * mapped registers.  Also, mem_ctl1 and mem_ctl2 must be
1458          * initialised.
1459          */
1460         cyber2000fb_writeb(0x18, 0x46e8, cfb);
1461         cyber2000fb_writeb(0x01, 0x102, cfb);
1462         cyber2000fb_writeb(0x08, 0x46e8, cfb);
1463         cyber2000fb_writeb(EXT_BIU_MISC, 0x3ce, cfb);
1464         cyber2000fb_writeb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf, cfb);
1465
1466         cfb->mclk_mult = 0xdb;
1467         cfb->mclk_div  = 0x54;
1468
1469         err = cyberpro_common_probe(cfb);
1470         if (err)
1471                 goto failed;
1472
1473         if (int_cfb_info == NULL)
1474                 int_cfb_info = cfb;
1475
1476         return 0;
1477
1478 failed:
1479         iounmap(cfb->region);
1480 failed_ioremap:
1481         cyberpro_free_fb_info(cfb);
1482 failed_release:
1483         release_mem_region(FB_START,FB_SIZE);
1484
1485         return err;
1486 }
1487 #endif /* CONFIG_ARCH_SHARK */
1488
1489 /*
1490  * PCI specific support.
1491  */
1492 #ifdef CONFIG_PCI
1493 /*
1494  * We need to wake up the CyberPro, and make sure its in linear memory
1495  * mode.  Unfortunately, this is specific to the platform and card that
1496  * we are running on.
1497  *
1498  * On x86 and ARM, should we be initialising the CyberPro first via the
1499  * IO registers, and then the MMIO registers to catch all cases?  Can we
1500  * end up in the situation where the chip is in MMIO mode, but not awake
1501  * on an x86 system?
1502  */
1503 static int cyberpro_pci_enable_mmio(struct cfb_info *cfb)
1504 {
1505         unsigned char val;
1506
1507 #if defined(__sparc_v9__)
1508 #error "You lose, consult DaveM."
1509 #elif defined(__sparc__)
1510         /*
1511          * SPARC does not have an "outb" instruction, so we generate
1512          * I/O cycles storing into a reserved memory space at
1513          * physical address 0x3000000
1514          */
1515         unsigned char *iop;
1516
1517         iop = ioremap(0x3000000, 0x5000);
1518         if (iop == NULL) {
1519                 prom_printf("iga5000: cannot map I/O\n");
1520                 return -ENOMEM;
1521         }
1522
1523         writeb(0x18, iop + 0x46e8);
1524         writeb(0x01, iop + 0x102);
1525         writeb(0x08, iop + 0x46e8);
1526         writeb(EXT_BIU_MISC, iop + 0x3ce);
1527         writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf);
1528
1529         iounmap((void *)iop);
1530 #else
1531         /*
1532          * Most other machine types are "normal", so
1533          * we use the standard IO-based wakeup.
1534          */
1535         outb(0x18, 0x46e8);
1536         outb(0x01, 0x102);
1537         outb(0x08, 0x46e8);
1538         outb(EXT_BIU_MISC, 0x3ce);
1539         outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf);
1540 #endif
1541
1542         /*
1543          * Allow the CyberPro to accept PCI burst accesses
1544          */
1545         val = cyber2000_grphr(EXT_BUS_CTL, cfb);
1546         if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) {
1547                 printk(KERN_INFO "%s: enabling PCI bursts\n", cfb->fb.fix.id);
1548
1549                 val |= EXT_BUS_CTL_PCIBURST_WRITE;
1550
1551                 if (cfb->id == ID_CYBERPRO_5000)
1552                         val |= EXT_BUS_CTL_PCIBURST_READ;
1553
1554                 cyber2000_grphw(EXT_BUS_CTL, val, cfb);
1555         }
1556
1557         return 0;
1558 }
1559
1560 static int __devinit
1561 cyberpro_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1562 {
1563         struct cfb_info *cfb;
1564         char name[16];
1565         int err;
1566
1567         sprintf(name, "CyberPro%4X", id->device);
1568
1569         err = pci_enable_device(dev);
1570         if (err)
1571                 return err;
1572
1573         err = pci_request_regions(dev, name);
1574         if (err)
1575                 return err;
1576
1577         err = -ENOMEM;
1578         cfb = cyberpro_alloc_fb_info(id->driver_data, name);
1579         if (!cfb)
1580                 goto failed_release;
1581
1582         cfb->dev = dev;
1583         cfb->region = ioremap(pci_resource_start(dev, 0),
1584                               pci_resource_len(dev, 0));
1585         if (!cfb->region)
1586                 goto failed_ioremap;
1587
1588         cfb->regs = cfb->region + MMIO_OFFSET;
1589         cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET;
1590         cfb->fb.fix.smem_start = pci_resource_start(dev, 0);
1591
1592         /*
1593          * Bring up the hardware.  This is expected to enable access
1594          * to the linear memory region, and allow access to the memory
1595          * mapped registers.  Also, mem_ctl1 and mem_ctl2 must be
1596          * initialised.
1597          */
1598         err = cyberpro_pci_enable_mmio(cfb);
1599         if (err)
1600                 goto failed;
1601
1602         /*
1603          * Use MCLK from BIOS. FIXME: what about hotplug?
1604          */
1605         cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb);
1606         cfb->mclk_div  = cyber2000_grphr(EXT_MCLK_DIV, cfb);
1607
1608 #ifdef __arm__
1609         /*
1610          * MCLK on the NetWinder and the Shark is fixed at 75MHz
1611          */
1612         if (machine_is_netwinder()) {
1613                 cfb->mclk_mult = 0xdb;
1614                 cfb->mclk_div  = 0x54;
1615         }
1616 #endif
1617
1618         err = cyberpro_common_probe(cfb);
1619         if (err)
1620                 goto failed;
1621
1622         /*
1623          * Our driver data
1624          */
1625         pci_set_drvdata(dev, cfb);
1626         if (int_cfb_info == NULL)
1627                 int_cfb_info = cfb;
1628
1629         return 0;
1630
1631 failed:
1632         iounmap(cfb->region);
1633 failed_ioremap:
1634         cyberpro_free_fb_info(cfb);
1635 failed_release:
1636         pci_release_regions(dev);
1637
1638         return err;
1639 }
1640
1641 static void __devexit cyberpro_pci_remove(struct pci_dev *dev)
1642 {
1643         struct cfb_info *cfb = pci_get_drvdata(dev);
1644
1645         if (cfb) {
1646                 /*
1647                  * If unregister_framebuffer fails, then
1648                  * we will be leaving hooks that could cause
1649                  * oopsen laying around.
1650                  */
1651                 if (unregister_framebuffer(&cfb->fb))
1652                         printk(KERN_WARNING "%s: danger Will Robinson, "
1653                                 "danger danger!  Oopsen imminent!\n",
1654                                 cfb->fb.fix.id);
1655                 iounmap(cfb->region);
1656                 cyberpro_free_fb_info(cfb);
1657
1658                 /*
1659                  * Ensure that the driver data is no longer
1660                  * valid.
1661                  */
1662                 pci_set_drvdata(dev, NULL);
1663                 if (cfb == int_cfb_info)
1664                         int_cfb_info = NULL;
1665
1666                 pci_release_regions(dev);
1667         }
1668 }
1669
1670 static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state)
1671 {
1672         return 0;
1673 }
1674
1675 /*
1676  * Re-initialise the CyberPro hardware
1677  */
1678 static int cyberpro_pci_resume(struct pci_dev *dev)
1679 {
1680         struct cfb_info *cfb = pci_get_drvdata(dev);
1681
1682         if (cfb) {
1683                 cyberpro_pci_enable_mmio(cfb);
1684                 cyberpro_common_resume(cfb);
1685         }
1686
1687         return 0;
1688 }
1689
1690 static struct pci_device_id cyberpro_pci_table[] = {
1691 //      Not yet
1692 //      { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682,
1693 //              PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 },
1694         { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000,
1695                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 },
1696         { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010,
1697                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 },
1698         { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000,
1699                 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 },
1700         { 0, }
1701 };
1702
1703 MODULE_DEVICE_TABLE(pci,cyberpro_pci_table);
1704
1705 static struct pci_driver cyberpro_driver = {
1706         .name           = "CyberPro",
1707         .probe          = cyberpro_pci_probe,
1708         .remove         = __devexit_p(cyberpro_pci_remove),
1709         .suspend        = cyberpro_pci_suspend,
1710         .resume         = cyberpro_pci_resume,
1711         .id_table       = cyberpro_pci_table
1712 };
1713 #endif
1714
1715 /*
1716  * I don't think we can use the "module_init" stuff here because
1717  * the fbcon stuff may not be initialised yet.  Hence the #ifdef
1718  * around module_init.
1719  *
1720  * Tony: "module_init" is now required
1721  */
1722 static int __init cyber2000fb_init(void)
1723 {
1724         int ret = -1, err;
1725
1726 #ifndef MODULE
1727         char *option = NULL;
1728
1729         if (fb_get_options("cyber2000fb", &option))
1730                 return -ENODEV;
1731         cyber2000fb_setup(option);
1732 #endif
1733
1734 #ifdef CONFIG_ARCH_SHARK
1735         err = cyberpro_vl_probe();
1736         if (!err) {
1737                 ret = 0;
1738                 __module_get(THIS_MODULE);
1739         }
1740 #endif
1741 #ifdef CONFIG_PCI
1742         err = pci_register_driver(&cyberpro_driver);
1743         if (!err)
1744                 ret = 0;
1745 #endif
1746
1747         return ret ? err : 0;
1748 }
1749
1750 static void __exit cyberpro_exit(void)
1751 {
1752         pci_unregister_driver(&cyberpro_driver);
1753 }
1754
1755 module_init(cyber2000fb_init);
1756 module_exit(cyberpro_exit);
1757
1758 MODULE_AUTHOR("Russell King");
1759 MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver");
1760 MODULE_LICENSE("GPL");