2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
46 #define DRV_NAME "sata_nv"
47 #define DRV_VERSION "0.9"
54 NV_PORT0_SCR_REG_OFFSET = 0x00,
55 NV_PORT1_SCR_REG_OFFSET = 0x40,
57 /* INT_STATUS/ENABLE */
60 NV_INT_STATUS_CK804 = 0x440,
61 NV_INT_ENABLE_CK804 = 0x441,
63 /* INT_STATUS/ENABLE bits */
67 NV_INT_REMOVED = 0x08,
69 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
73 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
75 // For PCI config register 20
76 NV_MCP_SATA_CFG_20 = 0x50,
77 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
80 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
81 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
82 struct pt_regs *regs);
83 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
84 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
90 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
94 static const struct pci_device_id nv_pci_tbl[] = {
95 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
97 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
98 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
99 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
101 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
103 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
105 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
107 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
109 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
111 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
113 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
115 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
123 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
124 PCI_ANY_ID, PCI_ANY_ID,
125 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
126 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
127 PCI_ANY_ID, PCI_ANY_ID,
128 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
129 { 0, } /* terminate list */
132 static struct pci_driver nv_pci_driver = {
134 .id_table = nv_pci_tbl,
135 .probe = nv_init_one,
136 .remove = ata_pci_remove_one,
139 static struct scsi_host_template nv_sht = {
140 .module = THIS_MODULE,
142 .ioctl = ata_scsi_ioctl,
143 .queuecommand = ata_scsi_queuecmd,
144 .can_queue = ATA_DEF_QUEUE,
145 .this_id = ATA_SHT_THIS_ID,
146 .sg_tablesize = LIBATA_MAX_PRD,
147 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
148 .emulated = ATA_SHT_EMULATED,
149 .use_clustering = ATA_SHT_USE_CLUSTERING,
150 .proc_name = DRV_NAME,
151 .dma_boundary = ATA_DMA_BOUNDARY,
152 .slave_configure = ata_scsi_slave_config,
153 .slave_destroy = ata_scsi_slave_destroy,
154 .bios_param = ata_std_bios_param,
157 static const struct ata_port_operations nv_ops = {
158 .port_disable = ata_port_disable,
159 .tf_load = ata_tf_load,
160 .tf_read = ata_tf_read,
161 .exec_command = ata_exec_command,
162 .check_status = ata_check_status,
163 .dev_select = ata_std_dev_select,
164 .phy_reset = sata_phy_reset,
165 .bmdma_setup = ata_bmdma_setup,
166 .bmdma_start = ata_bmdma_start,
167 .bmdma_stop = ata_bmdma_stop,
168 .bmdma_status = ata_bmdma_status,
169 .qc_prep = ata_qc_prep,
170 .qc_issue = ata_qc_issue_prot,
171 .eng_timeout = ata_eng_timeout,
172 .data_xfer = ata_pio_data_xfer,
173 .irq_handler = nv_interrupt,
174 .irq_clear = ata_bmdma_irq_clear,
175 .scr_read = nv_scr_read,
176 .scr_write = nv_scr_write,
177 .port_start = ata_port_start,
178 .port_stop = ata_port_stop,
179 .host_stop = ata_pci_host_stop,
182 /* FIXME: The hardware provides the necessary SATA PHY controls
183 * to support ATA_FLAG_SATA_RESET. However, it is currently
184 * necessary to disable that flag, to solve misdetection problems.
185 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
187 * This problem really needs to be investigated further. But in the
188 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
190 static struct ata_port_info nv_port_info = {
192 .host_flags = ATA_FLAG_SATA |
193 /* ATA_FLAG_SATA_RESET | */
196 .pio_mask = NV_PIO_MASK,
197 .mwdma_mask = NV_MWDMA_MASK,
198 .udma_mask = NV_UDMA_MASK,
202 MODULE_AUTHOR("NVIDIA");
203 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
204 MODULE_LICENSE("GPL");
205 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
206 MODULE_VERSION(DRV_VERSION);
208 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
209 struct pt_regs *regs)
211 struct ata_host_set *host_set = dev_instance;
213 unsigned int handled = 0;
216 spin_lock_irqsave(&host_set->lock, flags);
218 for (i = 0; i < host_set->n_ports; i++) {
221 ap = host_set->ports[i];
223 !(ap->flags & ATA_FLAG_DISABLED)) {
224 struct ata_queued_cmd *qc;
226 qc = ata_qc_from_tag(ap, ap->active_tag);
227 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
228 handled += ata_host_intr(ap, qc);
230 // No request pending? Clear interrupt status
231 // anyway, in case there's one pending.
232 ap->ops->check_status(ap);
237 spin_unlock_irqrestore(&host_set->lock, flags);
239 return IRQ_RETVAL(handled);
242 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
244 if (sc_reg > SCR_CONTROL)
247 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
250 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
252 if (sc_reg > SCR_CONTROL)
255 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
258 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
260 static int printed_version = 0;
261 struct ata_port_info *ppi;
262 struct ata_probe_ent *probe_ent;
263 int pci_dev_busy = 0;
268 // Make sure this is a SATA controller by counting the number of bars
269 // (NVIDIA SATA controllers will always have six bars). Otherwise,
270 // it's an IDE controller and we ignore it.
271 for (bar=0; bar<6; bar++)
272 if (pci_resource_start(pdev, bar) == 0)
275 if (!printed_version++)
276 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
278 rc = pci_enable_device(pdev);
282 rc = pci_request_regions(pdev, DRV_NAME);
285 goto err_out_disable;
288 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
290 goto err_out_regions;
291 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
293 goto err_out_regions;
298 probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
300 goto err_out_regions;
302 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
303 if (!probe_ent->mmio_base) {
305 goto err_out_free_ent;
308 base = (unsigned long)probe_ent->mmio_base;
310 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
311 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
313 pci_set_master(pdev);
315 rc = ata_device_add(probe_ent);
317 goto err_out_iounmap;
324 pci_iounmap(pdev, probe_ent->mmio_base);
328 pci_release_regions(pdev);
331 pci_disable_device(pdev);
336 static int __init nv_init(void)
338 return pci_module_init(&nv_pci_driver);
341 static void __exit nv_exit(void)
343 pci_unregister_driver(&nv_pci_driver);
346 module_init(nv_init);
347 module_exit(nv_exit);