1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/skbuff.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/stddef.h>
70 #include <linux/ioctl.h>
71 #include <linux/timex.h>
72 #include <linux/ethtool.h>
73 #include <linux/workqueue.h>
74 #include <linux/if_vlan.h>
76 #include <linux/tcp.h>
79 #include <asm/system.h>
80 #include <asm/uaccess.h>
82 #include <asm/div64.h>
87 #include "s2io-regs.h"
89 #define DRV_VERSION "2.0.26.25"
91 /* S2io Driver name & version. */
92 static char s2io_driver_name[] = "Neterion";
93 static char s2io_driver_version[] = DRV_VERSION;
95 static int rxd_size[2] = {32,48};
96 static int rxd_count[2] = {127,85};
98 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
102 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
103 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
109 * Cards with following subsystem_id have a link state indication
110 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
111 * macro below identifies these cards given the subsystem_id.
113 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
114 (dev_type == XFRAME_I_DEVICE) ? \
115 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
116 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
118 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
119 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
121 static inline int is_s2io_card_up(const struct s2io_nic * sp)
123 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
135 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
137 {"tmac_data_octets"},
141 {"tmac_pause_ctrl_frms"},
145 {"tmac_any_err_frms"},
146 {"tmac_ttl_less_fb_octets"},
147 {"tmac_vld_ip_octets"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
161 {"rmac_out_rng_len_err_frms"},
163 {"rmac_pause_ctrl_frms"},
164 {"rmac_unsup_ctrl_frms"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
168 {"rmac_discarded_frms"},
169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
175 {"rmac_jabber_frms"},
176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
189 {"rmac_err_drp_udp"},
190 {"rmac_xgmii_err_sym"},
208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
210 {"rmac_accepted_ip"},
214 {"new_rd_req_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
219 {"new_wr_req_rtry_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
232 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
233 {"rmac_ttl_1519_4095_frms"},
234 {"rmac_ttl_4096_8191_frms"},
235 {"rmac_ttl_8192_max_frms"},
236 {"rmac_ttl_gt_max_frms"},
237 {"rmac_osized_alt_frms"},
238 {"rmac_jabber_alt_frms"},
239 {"rmac_gt_max_alt_frms"},
241 {"rmac_len_discard"},
242 {"rmac_fcs_discard"},
245 {"rmac_red_discard"},
246 {"rmac_rts_discard"},
247 {"rmac_ingm_full_discard"},
251 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
252 {"\n DRIVER STATISTICS"},
253 {"single_bit_ecc_errs"},
254 {"double_bit_ecc_errs"},
267 {"alarm_transceiver_temp_high"},
268 {"alarm_transceiver_temp_low"},
269 {"alarm_laser_bias_current_high"},
270 {"alarm_laser_bias_current_low"},
271 {"alarm_laser_output_power_high"},
272 {"alarm_laser_output_power_low"},
273 {"warn_transceiver_temp_high"},
274 {"warn_transceiver_temp_low"},
275 {"warn_laser_bias_current_high"},
276 {"warn_laser_bias_current_low"},
277 {"warn_laser_output_power_high"},
278 {"warn_laser_output_power_low"},
279 {"lro_aggregated_pkts"},
280 {"lro_flush_both_count"},
281 {"lro_out_of_sequence_pkts"},
282 {"lro_flush_due_to_max_pkts"},
283 {"lro_avg_aggr_pkts"},
284 {"mem_alloc_fail_cnt"},
285 {"pci_map_fail_cnt"},
286 {"watchdog_timer_cnt"},
293 {"tx_tcode_buf_abort_cnt"},
294 {"tx_tcode_desc_abort_cnt"},
295 {"tx_tcode_parity_err_cnt"},
296 {"tx_tcode_link_loss_cnt"},
297 {"tx_tcode_list_proc_err_cnt"},
298 {"rx_tcode_parity_err_cnt"},
299 {"rx_tcode_abort_cnt"},
300 {"rx_tcode_parity_abort_cnt"},
301 {"rx_tcode_rda_fail_cnt"},
302 {"rx_tcode_unkn_prot_cnt"},
303 {"rx_tcode_fcs_err_cnt"},
304 {"rx_tcode_buf_size_err_cnt"},
305 {"rx_tcode_rxd_corrupt_cnt"},
306 {"rx_tcode_unkn_err_cnt"},
314 {"mac_tmac_err_cnt"},
315 {"mac_rmac_err_cnt"},
316 {"xgxs_txgxs_err_cnt"},
317 {"xgxs_rxgxs_err_cnt"},
319 {"prc_pcix_err_cnt"},
326 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
327 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
328 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
330 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
331 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
333 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
334 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
336 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
337 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
339 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
340 init_timer(&timer); \
341 timer.function = handle; \
342 timer.data = (unsigned long) arg; \
343 mod_timer(&timer, (jiffies + exp)) \
345 /* copy mac addr to def_mac_addr array */
346 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
348 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
349 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
350 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
351 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
352 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
353 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
357 static void s2io_vlan_rx_register(struct net_device *dev,
358 struct vlan_group *grp)
361 struct s2io_nic *nic = netdev_priv(dev);
362 unsigned long flags[MAX_TX_FIFOS];
363 struct mac_info *mac_control = &nic->mac_control;
364 struct config_param *config = &nic->config;
366 for (i = 0; i < config->tx_fifo_num; i++)
367 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
370 for (i = config->tx_fifo_num - 1; i >= 0; i--)
371 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
375 /* Unregister the vlan */
376 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
379 struct s2io_nic *nic = netdev_priv(dev);
380 unsigned long flags[MAX_TX_FIFOS];
381 struct mac_info *mac_control = &nic->mac_control;
382 struct config_param *config = &nic->config;
384 for (i = 0; i < config->tx_fifo_num; i++)
385 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
388 vlan_group_set_device(nic->vlgrp, vid, NULL);
390 for (i = config->tx_fifo_num - 1; i >= 0; i--)
391 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
396 * Constants to be programmed into the Xena's registers, to configure
401 static const u64 herc_act_dtx_cfg[] = {
403 0x8000051536750000ULL, 0x80000515367500E0ULL,
405 0x8000051536750004ULL, 0x80000515367500E4ULL,
407 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
409 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
411 0x801205150D440000ULL, 0x801205150D4400E0ULL,
413 0x801205150D440004ULL, 0x801205150D4400E4ULL,
415 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
417 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
422 static const u64 xena_dtx_cfg[] = {
424 0x8000051500000000ULL, 0x80000515000000E0ULL,
426 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
428 0x8001051500000000ULL, 0x80010515000000E0ULL,
430 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
432 0x8002051500000000ULL, 0x80020515000000E0ULL,
434 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
439 * Constants for Fixing the MacAddress problem seen mostly on
442 static const u64 fix_mac[] = {
443 0x0060000000000000ULL, 0x0060600000000000ULL,
444 0x0040600000000000ULL, 0x0000600000000000ULL,
445 0x0020600000000000ULL, 0x0060600000000000ULL,
446 0x0020600000000000ULL, 0x0060600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0060600000000000ULL,
450 0x0020600000000000ULL, 0x0060600000000000ULL,
451 0x0020600000000000ULL, 0x0060600000000000ULL,
452 0x0020600000000000ULL, 0x0060600000000000ULL,
453 0x0020600000000000ULL, 0x0060600000000000ULL,
454 0x0020600000000000ULL, 0x0060600000000000ULL,
455 0x0020600000000000ULL, 0x0000600000000000ULL,
456 0x0040600000000000ULL, 0x0060600000000000ULL,
460 MODULE_LICENSE("GPL");
461 MODULE_VERSION(DRV_VERSION);
464 /* Module Loadable parameters. */
465 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
466 S2IO_PARM_INT(rx_ring_num, 1);
467 S2IO_PARM_INT(multiq, 0);
468 S2IO_PARM_INT(rx_ring_mode, 1);
469 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
470 S2IO_PARM_INT(rmac_pause_time, 0x100);
471 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
472 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
473 S2IO_PARM_INT(shared_splits, 0);
474 S2IO_PARM_INT(tmac_util_period, 5);
475 S2IO_PARM_INT(rmac_util_period, 5);
476 S2IO_PARM_INT(l3l4hdr_size, 128);
477 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
478 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
479 /* Frequency of Rx desc syncs expressed as power of 2 */
480 S2IO_PARM_INT(rxsync_frequency, 3);
481 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
482 S2IO_PARM_INT(intr_type, 2);
483 /* Large receive offload feature */
484 static unsigned int lro_enable;
485 module_param_named(lro, lro_enable, uint, 0);
487 /* Max pkts to be aggregated by LRO at one time. If not specified,
488 * aggregation happens until we hit max IP pkt size(64K)
490 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
491 S2IO_PARM_INT(indicate_max_pkts, 0);
493 S2IO_PARM_INT(napi, 1);
494 S2IO_PARM_INT(ufo, 0);
495 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
497 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
498 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
499 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
500 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
501 static unsigned int rts_frm_len[MAX_RX_RINGS] =
502 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
504 module_param_array(tx_fifo_len, uint, NULL, 0);
505 module_param_array(rx_ring_sz, uint, NULL, 0);
506 module_param_array(rts_frm_len, uint, NULL, 0);
510 * This table lists all the devices that this driver supports.
512 static struct pci_device_id s2io_tbl[] __devinitdata = {
513 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
514 PCI_ANY_ID, PCI_ANY_ID},
515 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
516 PCI_ANY_ID, PCI_ANY_ID},
517 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
518 PCI_ANY_ID, PCI_ANY_ID},
519 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
520 PCI_ANY_ID, PCI_ANY_ID},
524 MODULE_DEVICE_TABLE(pci, s2io_tbl);
526 static struct pci_error_handlers s2io_err_handler = {
527 .error_detected = s2io_io_error_detected,
528 .slot_reset = s2io_io_slot_reset,
529 .resume = s2io_io_resume,
532 static struct pci_driver s2io_driver = {
534 .id_table = s2io_tbl,
535 .probe = s2io_init_nic,
536 .remove = __devexit_p(s2io_rem_nic),
537 .err_handler = &s2io_err_handler,
540 /* A simplifier macro used both by init and free shared_mem Fns(). */
541 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
543 /* netqueue manipulation helper functions */
544 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
546 if (!sp->config.multiq) {
549 for (i = 0; i < sp->config.tx_fifo_num; i++)
550 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
552 netif_tx_stop_all_queues(sp->dev);
555 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
557 if (!sp->config.multiq)
558 sp->mac_control.fifos[fifo_no].queue_state =
561 netif_tx_stop_all_queues(sp->dev);
564 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
566 if (!sp->config.multiq) {
569 for (i = 0; i < sp->config.tx_fifo_num; i++)
570 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
572 netif_tx_start_all_queues(sp->dev);
575 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
577 if (!sp->config.multiq)
578 sp->mac_control.fifos[fifo_no].queue_state =
581 netif_tx_start_all_queues(sp->dev);
584 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
586 if (!sp->config.multiq) {
589 for (i = 0; i < sp->config.tx_fifo_num; i++)
590 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
592 netif_tx_wake_all_queues(sp->dev);
595 static inline void s2io_wake_tx_queue(
596 struct fifo_info *fifo, int cnt, u8 multiq)
600 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
601 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
602 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
603 if (netif_queue_stopped(fifo->dev)) {
604 fifo->queue_state = FIFO_QUEUE_START;
605 netif_wake_queue(fifo->dev);
611 * init_shared_mem - Allocation and Initialization of Memory
612 * @nic: Device private variable.
613 * Description: The function allocates all the memory areas shared
614 * between the NIC and the driver. This includes Tx descriptors,
615 * Rx descriptors and the statistics block.
618 static int init_shared_mem(struct s2io_nic *nic)
621 void *tmp_v_addr, *tmp_v_addr_next;
622 dma_addr_t tmp_p_addr, tmp_p_addr_next;
623 struct RxD_block *pre_rxd_blk = NULL;
625 int lst_size, lst_per_page;
626 struct net_device *dev = nic->dev;
630 struct mac_info *mac_control;
631 struct config_param *config;
632 unsigned long long mem_allocated = 0;
634 mac_control = &nic->mac_control;
635 config = &nic->config;
638 /* Allocation and initialization of TXDLs in FIOFs */
640 for (i = 0; i < config->tx_fifo_num; i++) {
641 size += config->tx_cfg[i].fifo_len;
643 if (size > MAX_AVAILABLE_TXDS) {
644 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
645 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
650 for (i = 0; i < config->tx_fifo_num; i++) {
651 size = config->tx_cfg[i].fifo_len;
653 * Legal values are from 2 to 8192
656 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
657 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
658 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
664 lst_size = (sizeof(struct TxD) * config->max_txds);
665 lst_per_page = PAGE_SIZE / lst_size;
667 for (i = 0; i < config->tx_fifo_num; i++) {
668 int fifo_len = config->tx_cfg[i].fifo_len;
669 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
670 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
672 if (!mac_control->fifos[i].list_info) {
674 "Malloc failed for list_info\n");
677 mem_allocated += list_holder_size;
679 for (i = 0; i < config->tx_fifo_num; i++) {
680 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
682 mac_control->fifos[i].tx_curr_put_info.offset = 0;
683 mac_control->fifos[i].tx_curr_put_info.fifo_len =
684 config->tx_cfg[i].fifo_len - 1;
685 mac_control->fifos[i].tx_curr_get_info.offset = 0;
686 mac_control->fifos[i].tx_curr_get_info.fifo_len =
687 config->tx_cfg[i].fifo_len - 1;
688 mac_control->fifos[i].fifo_no = i;
689 mac_control->fifos[i].nic = nic;
690 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
691 mac_control->fifos[i].dev = dev;
693 for (j = 0; j < page_num; j++) {
697 tmp_v = pci_alloc_consistent(nic->pdev,
701 "pci_alloc_consistent ");
702 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
705 /* If we got a zero DMA address(can happen on
706 * certain platforms like PPC), reallocate.
707 * Store virtual address of page we don't want,
711 mac_control->zerodma_virt_addr = tmp_v;
713 "%s: Zero DMA address for TxDL. ", dev->name);
715 "Virtual address %p\n", tmp_v);
716 tmp_v = pci_alloc_consistent(nic->pdev,
720 "pci_alloc_consistent ");
721 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
724 mem_allocated += PAGE_SIZE;
726 while (k < lst_per_page) {
727 int l = (j * lst_per_page) + k;
728 if (l == config->tx_cfg[i].fifo_len)
730 mac_control->fifos[i].list_info[l].list_virt_addr =
731 tmp_v + (k * lst_size);
732 mac_control->fifos[i].list_info[l].list_phy_addr =
733 tmp_p + (k * lst_size);
739 for (i = 0; i < config->tx_fifo_num; i++) {
740 size = config->tx_cfg[i].fifo_len;
741 mac_control->fifos[i].ufo_in_band_v
742 = kcalloc(size, sizeof(u64), GFP_KERNEL);
743 if (!mac_control->fifos[i].ufo_in_band_v)
745 mem_allocated += (size * sizeof(u64));
748 /* Allocation and initialization of RXDs in Rings */
750 for (i = 0; i < config->rx_ring_num; i++) {
751 if (config->rx_cfg[i].num_rxd %
752 (rxd_count[nic->rxd_mode] + 1)) {
753 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
754 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
756 DBG_PRINT(ERR_DBG, "RxDs per Block");
759 size += config->rx_cfg[i].num_rxd;
760 mac_control->rings[i].block_count =
761 config->rx_cfg[i].num_rxd /
762 (rxd_count[nic->rxd_mode] + 1 );
763 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
764 mac_control->rings[i].block_count;
766 if (nic->rxd_mode == RXD_MODE_1)
767 size = (size * (sizeof(struct RxD1)));
769 size = (size * (sizeof(struct RxD3)));
771 for (i = 0; i < config->rx_ring_num; i++) {
772 mac_control->rings[i].rx_curr_get_info.block_index = 0;
773 mac_control->rings[i].rx_curr_get_info.offset = 0;
774 mac_control->rings[i].rx_curr_get_info.ring_len =
775 config->rx_cfg[i].num_rxd - 1;
776 mac_control->rings[i].rx_curr_put_info.block_index = 0;
777 mac_control->rings[i].rx_curr_put_info.offset = 0;
778 mac_control->rings[i].rx_curr_put_info.ring_len =
779 config->rx_cfg[i].num_rxd - 1;
780 mac_control->rings[i].nic = nic;
781 mac_control->rings[i].ring_no = i;
782 mac_control->rings[i].lro = lro_enable;
784 blk_cnt = config->rx_cfg[i].num_rxd /
785 (rxd_count[nic->rxd_mode] + 1);
786 /* Allocating all the Rx blocks */
787 for (j = 0; j < blk_cnt; j++) {
788 struct rx_block_info *rx_blocks;
791 rx_blocks = &mac_control->rings[i].rx_blocks[j];
792 size = SIZE_OF_BLOCK; //size is always page size
793 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
795 if (tmp_v_addr == NULL) {
797 * In case of failure, free_shared_mem()
798 * is called, which should free any
799 * memory that was alloced till the
802 rx_blocks->block_virt_addr = tmp_v_addr;
805 mem_allocated += size;
806 memset(tmp_v_addr, 0, size);
807 rx_blocks->block_virt_addr = tmp_v_addr;
808 rx_blocks->block_dma_addr = tmp_p_addr;
809 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
810 rxd_count[nic->rxd_mode],
812 if (!rx_blocks->rxds)
815 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
816 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
817 rx_blocks->rxds[l].virt_addr =
818 rx_blocks->block_virt_addr +
819 (rxd_size[nic->rxd_mode] * l);
820 rx_blocks->rxds[l].dma_addr =
821 rx_blocks->block_dma_addr +
822 (rxd_size[nic->rxd_mode] * l);
825 /* Interlinking all Rx Blocks */
826 for (j = 0; j < blk_cnt; j++) {
828 mac_control->rings[i].rx_blocks[j].block_virt_addr;
830 mac_control->rings[i].rx_blocks[(j + 1) %
831 blk_cnt].block_virt_addr;
833 mac_control->rings[i].rx_blocks[j].block_dma_addr;
835 mac_control->rings[i].rx_blocks[(j + 1) %
836 blk_cnt].block_dma_addr;
838 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
839 pre_rxd_blk->reserved_2_pNext_RxD_block =
840 (unsigned long) tmp_v_addr_next;
841 pre_rxd_blk->pNext_RxD_Blk_physical =
842 (u64) tmp_p_addr_next;
845 if (nic->rxd_mode == RXD_MODE_3B) {
847 * Allocation of Storages for buffer addresses in 2BUFF mode
848 * and the buffers as well.
850 for (i = 0; i < config->rx_ring_num; i++) {
851 blk_cnt = config->rx_cfg[i].num_rxd /
852 (rxd_count[nic->rxd_mode]+ 1);
853 mac_control->rings[i].ba =
854 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
856 if (!mac_control->rings[i].ba)
858 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
859 for (j = 0; j < blk_cnt; j++) {
861 mac_control->rings[i].ba[j] =
862 kmalloc((sizeof(struct buffAdd) *
863 (rxd_count[nic->rxd_mode] + 1)),
865 if (!mac_control->rings[i].ba[j])
867 mem_allocated += (sizeof(struct buffAdd) * \
868 (rxd_count[nic->rxd_mode] + 1));
869 while (k != rxd_count[nic->rxd_mode]) {
870 ba = &mac_control->rings[i].ba[j][k];
872 ba->ba_0_org = (void *) kmalloc
873 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
877 (BUF0_LEN + ALIGN_SIZE);
878 tmp = (unsigned long)ba->ba_0_org;
880 tmp &= ~((unsigned long) ALIGN_SIZE);
881 ba->ba_0 = (void *) tmp;
883 ba->ba_1_org = (void *) kmalloc
884 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
888 += (BUF1_LEN + ALIGN_SIZE);
889 tmp = (unsigned long) ba->ba_1_org;
891 tmp &= ~((unsigned long) ALIGN_SIZE);
892 ba->ba_1 = (void *) tmp;
899 /* Allocation and initialization of Statistics block */
900 size = sizeof(struct stat_block);
901 mac_control->stats_mem = pci_alloc_consistent
902 (nic->pdev, size, &mac_control->stats_mem_phy);
904 if (!mac_control->stats_mem) {
906 * In case of failure, free_shared_mem() is called, which
907 * should free any memory that was alloced till the
912 mem_allocated += size;
913 mac_control->stats_mem_sz = size;
915 tmp_v_addr = mac_control->stats_mem;
916 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
917 memset(tmp_v_addr, 0, size);
918 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
919 (unsigned long long) tmp_p_addr);
920 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
925 * free_shared_mem - Free the allocated Memory
926 * @nic: Device private variable.
927 * Description: This function is to free all memory locations allocated by
928 * the init_shared_mem() function and return it to the kernel.
931 static void free_shared_mem(struct s2io_nic *nic)
933 int i, j, blk_cnt, size;
935 dma_addr_t tmp_p_addr;
936 struct mac_info *mac_control;
937 struct config_param *config;
938 int lst_size, lst_per_page;
939 struct net_device *dev;
947 mac_control = &nic->mac_control;
948 config = &nic->config;
950 lst_size = (sizeof(struct TxD) * config->max_txds);
951 lst_per_page = PAGE_SIZE / lst_size;
953 for (i = 0; i < config->tx_fifo_num; i++) {
954 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
956 for (j = 0; j < page_num; j++) {
957 int mem_blks = (j * lst_per_page);
958 if (!mac_control->fifos[i].list_info)
960 if (!mac_control->fifos[i].list_info[mem_blks].
963 pci_free_consistent(nic->pdev, PAGE_SIZE,
964 mac_control->fifos[i].
967 mac_control->fifos[i].
970 nic->mac_control.stats_info->sw_stat.mem_freed
973 /* If we got a zero DMA address during allocation,
976 if (mac_control->zerodma_virt_addr) {
977 pci_free_consistent(nic->pdev, PAGE_SIZE,
978 mac_control->zerodma_virt_addr,
981 "%s: Freeing TxDL with zero DMA addr. ",
983 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
984 mac_control->zerodma_virt_addr);
985 nic->mac_control.stats_info->sw_stat.mem_freed
988 kfree(mac_control->fifos[i].list_info);
989 nic->mac_control.stats_info->sw_stat.mem_freed +=
990 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
993 size = SIZE_OF_BLOCK;
994 for (i = 0; i < config->rx_ring_num; i++) {
995 blk_cnt = mac_control->rings[i].block_count;
996 for (j = 0; j < blk_cnt; j++) {
997 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
999 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1001 if (tmp_v_addr == NULL)
1003 pci_free_consistent(nic->pdev, size,
1004 tmp_v_addr, tmp_p_addr);
1005 nic->mac_control.stats_info->sw_stat.mem_freed += size;
1006 kfree(mac_control->rings[i].rx_blocks[j].rxds);
1007 nic->mac_control.stats_info->sw_stat.mem_freed +=
1008 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1012 if (nic->rxd_mode == RXD_MODE_3B) {
1013 /* Freeing buffer storage addresses in 2BUFF mode. */
1014 for (i = 0; i < config->rx_ring_num; i++) {
1015 blk_cnt = config->rx_cfg[i].num_rxd /
1016 (rxd_count[nic->rxd_mode] + 1);
1017 for (j = 0; j < blk_cnt; j++) {
1019 if (!mac_control->rings[i].ba[j])
1021 while (k != rxd_count[nic->rxd_mode]) {
1022 struct buffAdd *ba =
1023 &mac_control->rings[i].ba[j][k];
1024 kfree(ba->ba_0_org);
1025 nic->mac_control.stats_info->sw_stat.\
1026 mem_freed += (BUF0_LEN + ALIGN_SIZE);
1027 kfree(ba->ba_1_org);
1028 nic->mac_control.stats_info->sw_stat.\
1029 mem_freed += (BUF1_LEN + ALIGN_SIZE);
1032 kfree(mac_control->rings[i].ba[j]);
1033 nic->mac_control.stats_info->sw_stat.mem_freed +=
1034 (sizeof(struct buffAdd) *
1035 (rxd_count[nic->rxd_mode] + 1));
1037 kfree(mac_control->rings[i].ba);
1038 nic->mac_control.stats_info->sw_stat.mem_freed +=
1039 (sizeof(struct buffAdd *) * blk_cnt);
1043 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1044 if (mac_control->fifos[i].ufo_in_band_v) {
1045 nic->mac_control.stats_info->sw_stat.mem_freed
1046 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1047 kfree(mac_control->fifos[i].ufo_in_band_v);
1051 if (mac_control->stats_mem) {
1052 nic->mac_control.stats_info->sw_stat.mem_freed +=
1053 mac_control->stats_mem_sz;
1054 pci_free_consistent(nic->pdev,
1055 mac_control->stats_mem_sz,
1056 mac_control->stats_mem,
1057 mac_control->stats_mem_phy);
1062 * s2io_verify_pci_mode -
1065 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1067 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1068 register u64 val64 = 0;
1071 val64 = readq(&bar0->pci_mode);
1072 mode = (u8)GET_PCI_MODE(val64);
1074 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1075 return -1; /* Unknown PCI mode */
1079 #define NEC_VENID 0x1033
1080 #define NEC_DEVID 0x0125
1081 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1083 struct pci_dev *tdev = NULL;
1084 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1085 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1086 if (tdev->bus == s2io_pdev->bus->parent) {
1095 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1097 * s2io_print_pci_mode -
1099 static int s2io_print_pci_mode(struct s2io_nic *nic)
1101 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1102 register u64 val64 = 0;
1104 struct config_param *config = &nic->config;
1106 val64 = readq(&bar0->pci_mode);
1107 mode = (u8)GET_PCI_MODE(val64);
1109 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1110 return -1; /* Unknown PCI mode */
1112 config->bus_speed = bus_speed[mode];
1114 if (s2io_on_nec_bridge(nic->pdev)) {
1115 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1120 if (val64 & PCI_MODE_32_BITS) {
1121 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1123 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1127 case PCI_MODE_PCI_33:
1128 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1130 case PCI_MODE_PCI_66:
1131 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1133 case PCI_MODE_PCIX_M1_66:
1134 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1136 case PCI_MODE_PCIX_M1_100:
1137 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1139 case PCI_MODE_PCIX_M1_133:
1140 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1142 case PCI_MODE_PCIX_M2_66:
1143 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1145 case PCI_MODE_PCIX_M2_100:
1146 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1148 case PCI_MODE_PCIX_M2_133:
1149 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1152 return -1; /* Unsupported bus speed */
1159 * init_tti - Initialization transmit traffic interrupt scheme
1160 * @nic: device private variable
1161 * @link: link status (UP/DOWN) used to enable/disable continuous
1162 * transmit interrupts
1163 * Description: The function configures transmit traffic interrupts
1164 * Return Value: SUCCESS on success and
1168 static int init_tti(struct s2io_nic *nic, int link)
1170 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1171 register u64 val64 = 0;
1173 struct config_param *config;
1175 config = &nic->config;
1177 for (i = 0; i < config->tx_fifo_num; i++) {
1179 * TTI Initialization. Default Tx timer gets us about
1180 * 250 interrupts per sec. Continuous interrupts are enabled
1183 if (nic->device_type == XFRAME_II_DEVICE) {
1184 int count = (nic->config.bus_speed * 125)/2;
1185 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1187 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1189 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1190 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1191 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1192 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1194 if (use_continuous_tx_intrs && (link == LINK_UP))
1195 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1196 writeq(val64, &bar0->tti_data1_mem);
1198 if (nic->config.intr_type == MSI_X) {
1199 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1200 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1201 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1202 TTI_DATA2_MEM_TX_UFC_D(0x300);
1204 if ((nic->config.tx_steering_type ==
1205 TX_DEFAULT_STEERING) &&
1206 (config->tx_fifo_num > 1) &&
1207 (i >= nic->udp_fifo_idx) &&
1208 (i < (nic->udp_fifo_idx +
1209 nic->total_udp_fifos)))
1210 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1211 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1212 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1213 TTI_DATA2_MEM_TX_UFC_D(0x120);
1215 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1216 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1217 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1218 TTI_DATA2_MEM_TX_UFC_D(0x80);
1221 writeq(val64, &bar0->tti_data2_mem);
1223 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1224 TTI_CMD_MEM_OFFSET(i);
1225 writeq(val64, &bar0->tti_command_mem);
1227 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1228 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1236 * init_nic - Initialization of hardware
1237 * @nic: device private variable
1238 * Description: The function sequentially configures every block
1239 * of the H/W from their reset values.
1240 * Return Value: SUCCESS on success and
1241 * '-1' on failure (endian settings incorrect).
1244 static int init_nic(struct s2io_nic *nic)
1246 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1247 struct net_device *dev = nic->dev;
1248 register u64 val64 = 0;
1252 struct mac_info *mac_control;
1253 struct config_param *config;
1255 unsigned long long mem_share;
1258 mac_control = &nic->mac_control;
1259 config = &nic->config;
1261 /* to set the swapper controle on the card */
1262 if(s2io_set_swapper(nic)) {
1263 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1268 * Herc requires EOI to be removed from reset before XGXS, so..
1270 if (nic->device_type & XFRAME_II_DEVICE) {
1271 val64 = 0xA500000000ULL;
1272 writeq(val64, &bar0->sw_reset);
1274 val64 = readq(&bar0->sw_reset);
1277 /* Remove XGXS from reset state */
1279 writeq(val64, &bar0->sw_reset);
1281 val64 = readq(&bar0->sw_reset);
1283 /* Ensure that it's safe to access registers by checking
1284 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1286 if (nic->device_type == XFRAME_II_DEVICE) {
1287 for (i = 0; i < 50; i++) {
1288 val64 = readq(&bar0->adapter_status);
1289 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1297 /* Enable Receiving broadcasts */
1298 add = &bar0->mac_cfg;
1299 val64 = readq(&bar0->mac_cfg);
1300 val64 |= MAC_RMAC_BCAST_ENABLE;
1301 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1302 writel((u32) val64, add);
1303 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1304 writel((u32) (val64 >> 32), (add + 4));
1306 /* Read registers in all blocks */
1307 val64 = readq(&bar0->mac_int_mask);
1308 val64 = readq(&bar0->mc_int_mask);
1309 val64 = readq(&bar0->xgxs_int_mask);
1313 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1315 if (nic->device_type & XFRAME_II_DEVICE) {
1316 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1317 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1318 &bar0->dtx_control, UF);
1320 msleep(1); /* Necessary!! */
1324 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1325 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1326 &bar0->dtx_control, UF);
1327 val64 = readq(&bar0->dtx_control);
1332 /* Tx DMA Initialization */
1334 writeq(val64, &bar0->tx_fifo_partition_0);
1335 writeq(val64, &bar0->tx_fifo_partition_1);
1336 writeq(val64, &bar0->tx_fifo_partition_2);
1337 writeq(val64, &bar0->tx_fifo_partition_3);
1340 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1342 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1343 13) | vBIT(config->tx_cfg[i].fifo_priority,
1346 if (i == (config->tx_fifo_num - 1)) {
1353 writeq(val64, &bar0->tx_fifo_partition_0);
1358 writeq(val64, &bar0->tx_fifo_partition_1);
1363 writeq(val64, &bar0->tx_fifo_partition_2);
1368 writeq(val64, &bar0->tx_fifo_partition_3);
1379 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1380 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1382 if ((nic->device_type == XFRAME_I_DEVICE) &&
1383 (nic->pdev->revision < 4))
1384 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1386 val64 = readq(&bar0->tx_fifo_partition_0);
1387 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1388 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1391 * Initialization of Tx_PA_CONFIG register to ignore packet
1392 * integrity checking.
1394 val64 = readq(&bar0->tx_pa_cfg);
1395 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1396 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1397 writeq(val64, &bar0->tx_pa_cfg);
1399 /* Rx DMA intialization. */
1401 for (i = 0; i < config->rx_ring_num; i++) {
1403 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1406 writeq(val64, &bar0->rx_queue_priority);
1409 * Allocating equal share of memory to all the
1413 if (nic->device_type & XFRAME_II_DEVICE)
1418 for (i = 0; i < config->rx_ring_num; i++) {
1421 mem_share = (mem_size / config->rx_ring_num +
1422 mem_size % config->rx_ring_num);
1423 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1426 mem_share = (mem_size / config->rx_ring_num);
1427 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1430 mem_share = (mem_size / config->rx_ring_num);
1431 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1434 mem_share = (mem_size / config->rx_ring_num);
1435 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1438 mem_share = (mem_size / config->rx_ring_num);
1439 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1442 mem_share = (mem_size / config->rx_ring_num);
1443 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1446 mem_share = (mem_size / config->rx_ring_num);
1447 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1450 mem_share = (mem_size / config->rx_ring_num);
1451 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1455 writeq(val64, &bar0->rx_queue_cfg);
1458 * Filling Tx round robin registers
1459 * as per the number of FIFOs for equal scheduling priority
1461 switch (config->tx_fifo_num) {
1464 writeq(val64, &bar0->tx_w_round_robin_0);
1465 writeq(val64, &bar0->tx_w_round_robin_1);
1466 writeq(val64, &bar0->tx_w_round_robin_2);
1467 writeq(val64, &bar0->tx_w_round_robin_3);
1468 writeq(val64, &bar0->tx_w_round_robin_4);
1471 val64 = 0x0001000100010001ULL;
1472 writeq(val64, &bar0->tx_w_round_robin_0);
1473 writeq(val64, &bar0->tx_w_round_robin_1);
1474 writeq(val64, &bar0->tx_w_round_robin_2);
1475 writeq(val64, &bar0->tx_w_round_robin_3);
1476 val64 = 0x0001000100000000ULL;
1477 writeq(val64, &bar0->tx_w_round_robin_4);
1480 val64 = 0x0001020001020001ULL;
1481 writeq(val64, &bar0->tx_w_round_robin_0);
1482 val64 = 0x0200010200010200ULL;
1483 writeq(val64, &bar0->tx_w_round_robin_1);
1484 val64 = 0x0102000102000102ULL;
1485 writeq(val64, &bar0->tx_w_round_robin_2);
1486 val64 = 0x0001020001020001ULL;
1487 writeq(val64, &bar0->tx_w_round_robin_3);
1488 val64 = 0x0200010200000000ULL;
1489 writeq(val64, &bar0->tx_w_round_robin_4);
1492 val64 = 0x0001020300010203ULL;
1493 writeq(val64, &bar0->tx_w_round_robin_0);
1494 writeq(val64, &bar0->tx_w_round_robin_1);
1495 writeq(val64, &bar0->tx_w_round_robin_2);
1496 writeq(val64, &bar0->tx_w_round_robin_3);
1497 val64 = 0x0001020300000000ULL;
1498 writeq(val64, &bar0->tx_w_round_robin_4);
1501 val64 = 0x0001020304000102ULL;
1502 writeq(val64, &bar0->tx_w_round_robin_0);
1503 val64 = 0x0304000102030400ULL;
1504 writeq(val64, &bar0->tx_w_round_robin_1);
1505 val64 = 0x0102030400010203ULL;
1506 writeq(val64, &bar0->tx_w_round_robin_2);
1507 val64 = 0x0400010203040001ULL;
1508 writeq(val64, &bar0->tx_w_round_robin_3);
1509 val64 = 0x0203040000000000ULL;
1510 writeq(val64, &bar0->tx_w_round_robin_4);
1513 val64 = 0x0001020304050001ULL;
1514 writeq(val64, &bar0->tx_w_round_robin_0);
1515 val64 = 0x0203040500010203ULL;
1516 writeq(val64, &bar0->tx_w_round_robin_1);
1517 val64 = 0x0405000102030405ULL;
1518 writeq(val64, &bar0->tx_w_round_robin_2);
1519 val64 = 0x0001020304050001ULL;
1520 writeq(val64, &bar0->tx_w_round_robin_3);
1521 val64 = 0x0203040500000000ULL;
1522 writeq(val64, &bar0->tx_w_round_robin_4);
1525 val64 = 0x0001020304050600ULL;
1526 writeq(val64, &bar0->tx_w_round_robin_0);
1527 val64 = 0x0102030405060001ULL;
1528 writeq(val64, &bar0->tx_w_round_robin_1);
1529 val64 = 0x0203040506000102ULL;
1530 writeq(val64, &bar0->tx_w_round_robin_2);
1531 val64 = 0x0304050600010203ULL;
1532 writeq(val64, &bar0->tx_w_round_robin_3);
1533 val64 = 0x0405060000000000ULL;
1534 writeq(val64, &bar0->tx_w_round_robin_4);
1537 val64 = 0x0001020304050607ULL;
1538 writeq(val64, &bar0->tx_w_round_robin_0);
1539 writeq(val64, &bar0->tx_w_round_robin_1);
1540 writeq(val64, &bar0->tx_w_round_robin_2);
1541 writeq(val64, &bar0->tx_w_round_robin_3);
1542 val64 = 0x0001020300000000ULL;
1543 writeq(val64, &bar0->tx_w_round_robin_4);
1547 /* Enable all configured Tx FIFO partitions */
1548 val64 = readq(&bar0->tx_fifo_partition_0);
1549 val64 |= (TX_FIFO_PARTITION_EN);
1550 writeq(val64, &bar0->tx_fifo_partition_0);
1552 /* Filling the Rx round robin registers as per the
1553 * number of Rings and steering based on QoS with
1556 switch (config->rx_ring_num) {
1559 writeq(val64, &bar0->rx_w_round_robin_0);
1560 writeq(val64, &bar0->rx_w_round_robin_1);
1561 writeq(val64, &bar0->rx_w_round_robin_2);
1562 writeq(val64, &bar0->rx_w_round_robin_3);
1563 writeq(val64, &bar0->rx_w_round_robin_4);
1565 val64 = 0x8080808080808080ULL;
1566 writeq(val64, &bar0->rts_qos_steering);
1569 val64 = 0x0001000100010001ULL;
1570 writeq(val64, &bar0->rx_w_round_robin_0);
1571 writeq(val64, &bar0->rx_w_round_robin_1);
1572 writeq(val64, &bar0->rx_w_round_robin_2);
1573 writeq(val64, &bar0->rx_w_round_robin_3);
1574 val64 = 0x0001000100000000ULL;
1575 writeq(val64, &bar0->rx_w_round_robin_4);
1577 val64 = 0x8080808040404040ULL;
1578 writeq(val64, &bar0->rts_qos_steering);
1581 val64 = 0x0001020001020001ULL;
1582 writeq(val64, &bar0->rx_w_round_robin_0);
1583 val64 = 0x0200010200010200ULL;
1584 writeq(val64, &bar0->rx_w_round_robin_1);
1585 val64 = 0x0102000102000102ULL;
1586 writeq(val64, &bar0->rx_w_round_robin_2);
1587 val64 = 0x0001020001020001ULL;
1588 writeq(val64, &bar0->rx_w_round_robin_3);
1589 val64 = 0x0200010200000000ULL;
1590 writeq(val64, &bar0->rx_w_round_robin_4);
1592 val64 = 0x8080804040402020ULL;
1593 writeq(val64, &bar0->rts_qos_steering);
1596 val64 = 0x0001020300010203ULL;
1597 writeq(val64, &bar0->rx_w_round_robin_0);
1598 writeq(val64, &bar0->rx_w_round_robin_1);
1599 writeq(val64, &bar0->rx_w_round_robin_2);
1600 writeq(val64, &bar0->rx_w_round_robin_3);
1601 val64 = 0x0001020300000000ULL;
1602 writeq(val64, &bar0->rx_w_round_robin_4);
1604 val64 = 0x8080404020201010ULL;
1605 writeq(val64, &bar0->rts_qos_steering);
1608 val64 = 0x0001020304000102ULL;
1609 writeq(val64, &bar0->rx_w_round_robin_0);
1610 val64 = 0x0304000102030400ULL;
1611 writeq(val64, &bar0->rx_w_round_robin_1);
1612 val64 = 0x0102030400010203ULL;
1613 writeq(val64, &bar0->rx_w_round_robin_2);
1614 val64 = 0x0400010203040001ULL;
1615 writeq(val64, &bar0->rx_w_round_robin_3);
1616 val64 = 0x0203040000000000ULL;
1617 writeq(val64, &bar0->rx_w_round_robin_4);
1619 val64 = 0x8080404020201008ULL;
1620 writeq(val64, &bar0->rts_qos_steering);
1623 val64 = 0x0001020304050001ULL;
1624 writeq(val64, &bar0->rx_w_round_robin_0);
1625 val64 = 0x0203040500010203ULL;
1626 writeq(val64, &bar0->rx_w_round_robin_1);
1627 val64 = 0x0405000102030405ULL;
1628 writeq(val64, &bar0->rx_w_round_robin_2);
1629 val64 = 0x0001020304050001ULL;
1630 writeq(val64, &bar0->rx_w_round_robin_3);
1631 val64 = 0x0203040500000000ULL;
1632 writeq(val64, &bar0->rx_w_round_robin_4);
1634 val64 = 0x8080404020100804ULL;
1635 writeq(val64, &bar0->rts_qos_steering);
1638 val64 = 0x0001020304050600ULL;
1639 writeq(val64, &bar0->rx_w_round_robin_0);
1640 val64 = 0x0102030405060001ULL;
1641 writeq(val64, &bar0->rx_w_round_robin_1);
1642 val64 = 0x0203040506000102ULL;
1643 writeq(val64, &bar0->rx_w_round_robin_2);
1644 val64 = 0x0304050600010203ULL;
1645 writeq(val64, &bar0->rx_w_round_robin_3);
1646 val64 = 0x0405060000000000ULL;
1647 writeq(val64, &bar0->rx_w_round_robin_4);
1649 val64 = 0x8080402010080402ULL;
1650 writeq(val64, &bar0->rts_qos_steering);
1653 val64 = 0x0001020304050607ULL;
1654 writeq(val64, &bar0->rx_w_round_robin_0);
1655 writeq(val64, &bar0->rx_w_round_robin_1);
1656 writeq(val64, &bar0->rx_w_round_robin_2);
1657 writeq(val64, &bar0->rx_w_round_robin_3);
1658 val64 = 0x0001020300000000ULL;
1659 writeq(val64, &bar0->rx_w_round_robin_4);
1661 val64 = 0x8040201008040201ULL;
1662 writeq(val64, &bar0->rts_qos_steering);
1668 for (i = 0; i < 8; i++)
1669 writeq(val64, &bar0->rts_frm_len_n[i]);
1671 /* Set the default rts frame length for the rings configured */
1672 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1673 for (i = 0 ; i < config->rx_ring_num ; i++)
1674 writeq(val64, &bar0->rts_frm_len_n[i]);
1676 /* Set the frame length for the configured rings
1677 * desired by the user
1679 for (i = 0; i < config->rx_ring_num; i++) {
1680 /* If rts_frm_len[i] == 0 then it is assumed that user not
1681 * specified frame length steering.
1682 * If the user provides the frame length then program
1683 * the rts_frm_len register for those values or else
1684 * leave it as it is.
1686 if (rts_frm_len[i] != 0) {
1687 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1688 &bar0->rts_frm_len_n[i]);
1692 /* Disable differentiated services steering logic */
1693 for (i = 0; i < 64; i++) {
1694 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1695 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1697 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1702 /* Program statistics memory */
1703 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1705 if (nic->device_type == XFRAME_II_DEVICE) {
1706 val64 = STAT_BC(0x320);
1707 writeq(val64, &bar0->stat_byte_cnt);
1711 * Initializing the sampling rate for the device to calculate the
1712 * bandwidth utilization.
1714 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1715 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1716 writeq(val64, &bar0->mac_link_util);
1719 * Initializing the Transmit and Receive Traffic Interrupt
1723 /* Initialize TTI */
1724 if (SUCCESS != init_tti(nic, nic->last_link_state))
1727 /* RTI Initialization */
1728 if (nic->device_type == XFRAME_II_DEVICE) {
1730 * Programmed to generate Apprx 500 Intrs per
1733 int count = (nic->config.bus_speed * 125)/4;
1734 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1736 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1737 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1738 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1739 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1741 writeq(val64, &bar0->rti_data1_mem);
1743 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1744 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1745 if (nic->config.intr_type == MSI_X)
1746 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1747 RTI_DATA2_MEM_RX_UFC_D(0x40));
1749 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1750 RTI_DATA2_MEM_RX_UFC_D(0x80));
1751 writeq(val64, &bar0->rti_data2_mem);
1753 for (i = 0; i < config->rx_ring_num; i++) {
1754 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1755 | RTI_CMD_MEM_OFFSET(i);
1756 writeq(val64, &bar0->rti_command_mem);
1759 * Once the operation completes, the Strobe bit of the
1760 * command register will be reset. We poll for this
1761 * particular condition. We wait for a maximum of 500ms
1762 * for the operation to complete, if it's not complete
1763 * by then we return error.
1767 val64 = readq(&bar0->rti_command_mem);
1768 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1772 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1782 * Initializing proper values as Pause threshold into all
1783 * the 8 Queues on Rx side.
1785 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1786 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1788 /* Disable RMAC PAD STRIPPING */
1789 add = &bar0->mac_cfg;
1790 val64 = readq(&bar0->mac_cfg);
1791 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1792 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1793 writel((u32) (val64), add);
1794 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1795 writel((u32) (val64 >> 32), (add + 4));
1796 val64 = readq(&bar0->mac_cfg);
1798 /* Enable FCS stripping by adapter */
1799 add = &bar0->mac_cfg;
1800 val64 = readq(&bar0->mac_cfg);
1801 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1802 if (nic->device_type == XFRAME_II_DEVICE)
1803 writeq(val64, &bar0->mac_cfg);
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806 writel((u32) (val64), add);
1807 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1808 writel((u32) (val64 >> 32), (add + 4));
1812 * Set the time value to be inserted in the pause frame
1813 * generated by xena.
1815 val64 = readq(&bar0->rmac_pause_cfg);
1816 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1817 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1818 writeq(val64, &bar0->rmac_pause_cfg);
1821 * Set the Threshold Limit for Generating the pause frame
1822 * If the amount of data in any Queue exceeds ratio of
1823 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1824 * pause frame is generated
1827 for (i = 0; i < 4; i++) {
1829 (((u64) 0xFF00 | nic->mac_control.
1830 mc_pause_threshold_q0q3)
1833 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1836 for (i = 0; i < 4; i++) {
1838 (((u64) 0xFF00 | nic->mac_control.
1839 mc_pause_threshold_q4q7)
1842 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1845 * TxDMA will stop Read request if the number of read split has
1846 * exceeded the limit pointed by shared_splits
1848 val64 = readq(&bar0->pic_control);
1849 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1850 writeq(val64, &bar0->pic_control);
1852 if (nic->config.bus_speed == 266) {
1853 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1854 writeq(0x0, &bar0->read_retry_delay);
1855 writeq(0x0, &bar0->write_retry_delay);
1859 * Programming the Herc to split every write transaction
1860 * that does not start on an ADB to reduce disconnects.
1862 if (nic->device_type == XFRAME_II_DEVICE) {
1863 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1864 MISC_LINK_STABILITY_PRD(3);
1865 writeq(val64, &bar0->misc_control);
1866 val64 = readq(&bar0->pic_control2);
1867 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1868 writeq(val64, &bar0->pic_control2);
1870 if (strstr(nic->product_name, "CX4")) {
1871 val64 = TMAC_AVG_IPG(0x17);
1872 writeq(val64, &bar0->tmac_avg_ipg);
1877 #define LINK_UP_DOWN_INTERRUPT 1
1878 #define MAC_RMAC_ERR_TIMER 2
1880 static int s2io_link_fault_indication(struct s2io_nic *nic)
1882 if (nic->device_type == XFRAME_II_DEVICE)
1883 return LINK_UP_DOWN_INTERRUPT;
1885 return MAC_RMAC_ERR_TIMER;
1889 * do_s2io_write_bits - update alarm bits in alarm register
1890 * @value: alarm bits
1891 * @flag: interrupt status
1892 * @addr: address value
1893 * Description: update alarm bits in alarm register
1897 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1901 temp64 = readq(addr);
1903 if(flag == ENABLE_INTRS)
1904 temp64 &= ~((u64) value);
1906 temp64 |= ((u64) value);
1907 writeq(temp64, addr);
1910 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1912 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1913 register u64 gen_int_mask = 0;
1916 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1917 if (mask & TX_DMA_INTR) {
1919 gen_int_mask |= TXDMA_INT_M;
1921 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1922 TXDMA_PCC_INT | TXDMA_TTI_INT |
1923 TXDMA_LSO_INT | TXDMA_TPA_INT |
1924 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1926 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1927 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1928 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1929 &bar0->pfc_err_mask);
1931 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1932 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1933 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1935 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1936 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1937 PCC_N_SERR | PCC_6_COF_OV_ERR |
1938 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1939 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1940 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1942 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1943 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1945 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1946 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1947 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1948 flag, &bar0->lso_err_mask);
1950 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1951 flag, &bar0->tpa_err_mask);
1953 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1957 if (mask & TX_MAC_INTR) {
1958 gen_int_mask |= TXMAC_INT_M;
1959 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1960 &bar0->mac_int_mask);
1961 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1962 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1963 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1964 flag, &bar0->mac_tmac_err_mask);
1967 if (mask & TX_XGXS_INTR) {
1968 gen_int_mask |= TXXGXS_INT_M;
1969 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1970 &bar0->xgxs_int_mask);
1971 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1972 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1973 flag, &bar0->xgxs_txgxs_err_mask);
1976 if (mask & RX_DMA_INTR) {
1977 gen_int_mask |= RXDMA_INT_M;
1978 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1979 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1980 flag, &bar0->rxdma_int_mask);
1981 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1982 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1983 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1984 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1985 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1986 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1987 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1988 &bar0->prc_pcix_err_mask);
1989 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1990 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1991 &bar0->rpa_err_mask);
1992 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1993 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1994 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1995 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1996 flag, &bar0->rda_err_mask);
1997 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1998 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1999 flag, &bar0->rti_err_mask);
2002 if (mask & RX_MAC_INTR) {
2003 gen_int_mask |= RXMAC_INT_M;
2004 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2005 &bar0->mac_int_mask);
2006 interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2007 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2008 RMAC_DOUBLE_ECC_ERR;
2009 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2010 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2011 do_s2io_write_bits(interruptible,
2012 flag, &bar0->mac_rmac_err_mask);
2015 if (mask & RX_XGXS_INTR)
2017 gen_int_mask |= RXXGXS_INT_M;
2018 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2019 &bar0->xgxs_int_mask);
2020 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2021 &bar0->xgxs_rxgxs_err_mask);
2024 if (mask & MC_INTR) {
2025 gen_int_mask |= MC_INT_M;
2026 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2027 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2028 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2029 &bar0->mc_err_mask);
2031 nic->general_int_mask = gen_int_mask;
2033 /* Remove this line when alarm interrupts are enabled */
2034 nic->general_int_mask = 0;
2037 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2038 * @nic: device private variable,
2039 * @mask: A mask indicating which Intr block must be modified and,
2040 * @flag: A flag indicating whether to enable or disable the Intrs.
2041 * Description: This function will either disable or enable the interrupts
2042 * depending on the flag argument. The mask argument can be used to
2043 * enable/disable any Intr block.
2044 * Return Value: NONE.
2047 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2049 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2050 register u64 temp64 = 0, intr_mask = 0;
2052 intr_mask = nic->general_int_mask;
2054 /* Top level interrupt classification */
2055 /* PIC Interrupts */
2056 if (mask & TX_PIC_INTR) {
2057 /* Enable PIC Intrs in the general intr mask register */
2058 intr_mask |= TXPIC_INT_M;
2059 if (flag == ENABLE_INTRS) {
2061 * If Hercules adapter enable GPIO otherwise
2062 * disable all PCIX, Flash, MDIO, IIC and GPIO
2063 * interrupts for now.
2066 if (s2io_link_fault_indication(nic) ==
2067 LINK_UP_DOWN_INTERRUPT ) {
2068 do_s2io_write_bits(PIC_INT_GPIO, flag,
2069 &bar0->pic_int_mask);
2070 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2071 &bar0->gpio_int_mask);
2073 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2074 } else if (flag == DISABLE_INTRS) {
2076 * Disable PIC Intrs in the general
2077 * intr mask register
2079 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2083 /* Tx traffic interrupts */
2084 if (mask & TX_TRAFFIC_INTR) {
2085 intr_mask |= TXTRAFFIC_INT_M;
2086 if (flag == ENABLE_INTRS) {
2088 * Enable all the Tx side interrupts
2089 * writing 0 Enables all 64 TX interrupt levels
2091 writeq(0x0, &bar0->tx_traffic_mask);
2092 } else if (flag == DISABLE_INTRS) {
2094 * Disable Tx Traffic Intrs in the general intr mask
2097 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2101 /* Rx traffic interrupts */
2102 if (mask & RX_TRAFFIC_INTR) {
2103 intr_mask |= RXTRAFFIC_INT_M;
2104 if (flag == ENABLE_INTRS) {
2105 /* writing 0 Enables all 8 RX interrupt levels */
2106 writeq(0x0, &bar0->rx_traffic_mask);
2107 } else if (flag == DISABLE_INTRS) {
2109 * Disable Rx Traffic Intrs in the general intr mask
2112 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2116 temp64 = readq(&bar0->general_int_mask);
2117 if (flag == ENABLE_INTRS)
2118 temp64 &= ~((u64) intr_mask);
2120 temp64 = DISABLE_ALL_INTRS;
2121 writeq(temp64, &bar0->general_int_mask);
2123 nic->general_int_mask = readq(&bar0->general_int_mask);
2127 * verify_pcc_quiescent- Checks for PCC quiescent state
2128 * Return: 1 If PCC is quiescence
2129 * 0 If PCC is not quiescence
2131 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2134 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2135 u64 val64 = readq(&bar0->adapter_status);
2137 herc = (sp->device_type == XFRAME_II_DEVICE);
2139 if (flag == FALSE) {
2140 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2141 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2144 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2148 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2149 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2150 ADAPTER_STATUS_RMAC_PCC_IDLE))
2153 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2154 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2162 * verify_xena_quiescence - Checks whether the H/W is ready
2163 * Description: Returns whether the H/W is ready to go or not. Depending
2164 * on whether adapter enable bit was written or not the comparison
2165 * differs and the calling function passes the input argument flag to
2167 * Return: 1 If xena is quiescence
2168 * 0 If Xena is not quiescence
2171 static int verify_xena_quiescence(struct s2io_nic *sp)
2174 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2175 u64 val64 = readq(&bar0->adapter_status);
2176 mode = s2io_verify_pci_mode(sp);
2178 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2179 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2182 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2183 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2186 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2187 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2190 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2191 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2194 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2195 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2198 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2199 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2202 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2203 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2206 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2207 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2212 * In PCI 33 mode, the P_PLL is not used, and therefore,
2213 * the the P_PLL_LOCK bit in the adapter_status register will
2216 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2217 sp->device_type == XFRAME_II_DEVICE && mode !=
2219 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2222 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2223 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2224 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2231 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2232 * @sp: Pointer to device specifc structure
2234 * New procedure to clear mac address reading problems on Alpha platforms
2238 static void fix_mac_address(struct s2io_nic * sp)
2240 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2244 while (fix_mac[i] != END_SIGN) {
2245 writeq(fix_mac[i++], &bar0->gpio_control);
2247 val64 = readq(&bar0->gpio_control);
2252 * start_nic - Turns the device on
2253 * @nic : device private variable.
2255 * This function actually turns the device on. Before this function is
2256 * called,all Registers are configured from their reset states
2257 * and shared memory is allocated but the NIC is still quiescent. On
2258 * calling this function, the device interrupts are cleared and the NIC is
2259 * literally switched on by writing into the adapter control register.
2261 * SUCCESS on success and -1 on failure.
2264 static int start_nic(struct s2io_nic *nic)
2266 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2267 struct net_device *dev = nic->dev;
2268 register u64 val64 = 0;
2270 struct mac_info *mac_control;
2271 struct config_param *config;
2273 mac_control = &nic->mac_control;
2274 config = &nic->config;
2276 /* PRC Initialization and configuration */
2277 for (i = 0; i < config->rx_ring_num; i++) {
2278 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2279 &bar0->prc_rxd0_n[i]);
2281 val64 = readq(&bar0->prc_ctrl_n[i]);
2282 if (nic->rxd_mode == RXD_MODE_1)
2283 val64 |= PRC_CTRL_RC_ENABLED;
2285 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2286 if (nic->device_type == XFRAME_II_DEVICE)
2287 val64 |= PRC_CTRL_GROUP_READS;
2288 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2289 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2290 writeq(val64, &bar0->prc_ctrl_n[i]);
2293 if (nic->rxd_mode == RXD_MODE_3B) {
2294 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2295 val64 = readq(&bar0->rx_pa_cfg);
2296 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2297 writeq(val64, &bar0->rx_pa_cfg);
2300 if (vlan_tag_strip == 0) {
2301 val64 = readq(&bar0->rx_pa_cfg);
2302 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2303 writeq(val64, &bar0->rx_pa_cfg);
2304 nic->vlan_strip_flag = 0;
2308 * Enabling MC-RLDRAM. After enabling the device, we timeout
2309 * for around 100ms, which is approximately the time required
2310 * for the device to be ready for operation.
2312 val64 = readq(&bar0->mc_rldram_mrs);
2313 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2314 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2315 val64 = readq(&bar0->mc_rldram_mrs);
2317 msleep(100); /* Delay by around 100 ms. */
2319 /* Enabling ECC Protection. */
2320 val64 = readq(&bar0->adapter_control);
2321 val64 &= ~ADAPTER_ECC_EN;
2322 writeq(val64, &bar0->adapter_control);
2325 * Verify if the device is ready to be enabled, if so enable
2328 val64 = readq(&bar0->adapter_status);
2329 if (!verify_xena_quiescence(nic)) {
2330 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2331 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2332 (unsigned long long) val64);
2337 * With some switches, link might be already up at this point.
2338 * Because of this weird behavior, when we enable laser,
2339 * we may not get link. We need to handle this. We cannot
2340 * figure out which switch is misbehaving. So we are forced to
2341 * make a global change.
2344 /* Enabling Laser. */
2345 val64 = readq(&bar0->adapter_control);
2346 val64 |= ADAPTER_EOI_TX_ON;
2347 writeq(val64, &bar0->adapter_control);
2349 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2351 * Dont see link state interrupts initally on some switches,
2352 * so directly scheduling the link state task here.
2354 schedule_work(&nic->set_link_task);
2356 /* SXE-002: Initialize link and activity LED */
2357 subid = nic->pdev->subsystem_device;
2358 if (((subid & 0xFF) >= 0x07) &&
2359 (nic->device_type == XFRAME_I_DEVICE)) {
2360 val64 = readq(&bar0->gpio_control);
2361 val64 |= 0x0000800000000000ULL;
2362 writeq(val64, &bar0->gpio_control);
2363 val64 = 0x0411040400000000ULL;
2364 writeq(val64, (void __iomem *)bar0 + 0x2700);
2370 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2372 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2373 TxD *txdlp, int get_off)
2375 struct s2io_nic *nic = fifo_data->nic;
2376 struct sk_buff *skb;
2381 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2382 pci_unmap_single(nic->pdev, (dma_addr_t)
2383 txds->Buffer_Pointer, sizeof(u64),
2388 skb = (struct sk_buff *) ((unsigned long)
2389 txds->Host_Control);
2391 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2394 pci_unmap_single(nic->pdev, (dma_addr_t)
2395 txds->Buffer_Pointer,
2396 skb->len - skb->data_len,
2398 frg_cnt = skb_shinfo(skb)->nr_frags;
2401 for (j = 0; j < frg_cnt; j++, txds++) {
2402 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2403 if (!txds->Buffer_Pointer)
2405 pci_unmap_page(nic->pdev, (dma_addr_t)
2406 txds->Buffer_Pointer,
2407 frag->size, PCI_DMA_TODEVICE);
2410 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2415 * free_tx_buffers - Free all queued Tx buffers
2416 * @nic : device private variable.
2418 * Free all queued Tx buffers.
2419 * Return Value: void
2422 static void free_tx_buffers(struct s2io_nic *nic)
2424 struct net_device *dev = nic->dev;
2425 struct sk_buff *skb;
2428 struct mac_info *mac_control;
2429 struct config_param *config;
2432 mac_control = &nic->mac_control;
2433 config = &nic->config;
2435 for (i = 0; i < config->tx_fifo_num; i++) {
2436 unsigned long flags;
2437 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
2438 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
2439 txdp = (struct TxD *) \
2440 mac_control->fifos[i].list_info[j].list_virt_addr;
2441 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2443 nic->mac_control.stats_info->sw_stat.mem_freed
2450 "%s:forcibly freeing %d skbs on FIFO%d\n",
2452 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2453 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2454 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
2459 * stop_nic - To stop the nic
2460 * @nic ; device private variable.
2462 * This function does exactly the opposite of what the start_nic()
2463 * function does. This function is called to stop the device.
2468 static void stop_nic(struct s2io_nic *nic)
2470 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2471 register u64 val64 = 0;
2473 struct mac_info *mac_control;
2474 struct config_param *config;
2476 mac_control = &nic->mac_control;
2477 config = &nic->config;
2479 /* Disable all interrupts */
2480 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2481 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2482 interruptible |= TX_PIC_INTR;
2483 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2485 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2486 val64 = readq(&bar0->adapter_control);
2487 val64 &= ~(ADAPTER_CNTL_EN);
2488 writeq(val64, &bar0->adapter_control);
2492 * fill_rx_buffers - Allocates the Rx side skbs
2493 * @ring_info: per ring structure
2494 * @from_card_up: If this is true, we will map the buffer to get
2495 * the dma address for buf0 and buf1 to give it to the card.
2496 * Else we will sync the already mapped buffer to give it to the card.
2498 * The function allocates Rx side skbs and puts the physical
2499 * address of these buffers into the RxD buffer pointers, so that the NIC
2500 * can DMA the received frame into these locations.
2501 * The NIC supports 3 receive modes, viz
2503 * 2. three buffer and
2504 * 3. Five buffer modes.
2505 * Each mode defines how many fragments the received frame will be split
2506 * up into by the NIC. The frame is split into L3 header, L4 Header,
2507 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2508 * is split into 3 fragments. As of now only single buffer mode is
2511 * SUCCESS on success or an appropriate -ve value on failure.
2513 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2516 struct sk_buff *skb;
2518 int off, size, block_no, block_no1;
2523 struct RxD_t *first_rxdp = NULL;
2524 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2528 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
2530 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2532 block_no1 = ring->rx_curr_get_info.block_index;
2533 while (alloc_tab < alloc_cnt) {
2534 block_no = ring->rx_curr_put_info.block_index;
2536 off = ring->rx_curr_put_info.offset;
2538 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2540 rxd_index = off + 1;
2542 rxd_index += (block_no * ring->rxd_count);
2544 if ((block_no == block_no1) &&
2545 (off == ring->rx_curr_get_info.offset) &&
2546 (rxdp->Host_Control)) {
2547 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2549 DBG_PRINT(INTR_DBG, " info equated\n");
2552 if (off && (off == ring->rxd_count)) {
2553 ring->rx_curr_put_info.block_index++;
2554 if (ring->rx_curr_put_info.block_index ==
2556 ring->rx_curr_put_info.block_index = 0;
2557 block_no = ring->rx_curr_put_info.block_index;
2559 ring->rx_curr_put_info.offset = off;
2560 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2561 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2562 ring->dev->name, rxdp);
2566 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2567 ((ring->rxd_mode == RXD_MODE_3B) &&
2568 (rxdp->Control_2 & s2BIT(0)))) {
2569 ring->rx_curr_put_info.offset = off;
2572 /* calculate size of skb based on ring mode */
2573 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2574 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2575 if (ring->rxd_mode == RXD_MODE_1)
2576 size += NET_IP_ALIGN;
2578 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2581 skb = dev_alloc_skb(size);
2583 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
2584 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2587 first_rxdp->Control_1 |= RXD_OWN_XENA;
2589 stats->mem_alloc_fail_cnt++;
2593 stats->mem_allocated += skb->truesize;
2595 if (ring->rxd_mode == RXD_MODE_1) {
2596 /* 1 buffer mode - normal operation mode */
2597 rxdp1 = (struct RxD1*)rxdp;
2598 memset(rxdp, 0, sizeof(struct RxD1));
2599 skb_reserve(skb, NET_IP_ALIGN);
2600 rxdp1->Buffer0_ptr = pci_map_single
2601 (ring->pdev, skb->data, size - NET_IP_ALIGN,
2602 PCI_DMA_FROMDEVICE);
2603 if (pci_dma_mapping_error(nic->pdev,
2604 rxdp1->Buffer0_ptr))
2605 goto pci_map_failed;
2608 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2609 rxdp->Host_Control = (unsigned long) (skb);
2610 } else if (ring->rxd_mode == RXD_MODE_3B) {
2613 * 2 buffer mode provides 128
2614 * byte aligned receive buffers.
2617 rxdp3 = (struct RxD3*)rxdp;
2618 /* save buffer pointers to avoid frequent dma mapping */
2619 Buffer0_ptr = rxdp3->Buffer0_ptr;
2620 Buffer1_ptr = rxdp3->Buffer1_ptr;
2621 memset(rxdp, 0, sizeof(struct RxD3));
2622 /* restore the buffer pointers for dma sync*/
2623 rxdp3->Buffer0_ptr = Buffer0_ptr;
2624 rxdp3->Buffer1_ptr = Buffer1_ptr;
2626 ba = &ring->ba[block_no][off];
2627 skb_reserve(skb, BUF0_LEN);
2628 tmp = (u64)(unsigned long) skb->data;
2631 skb->data = (void *) (unsigned long)tmp;
2632 skb_reset_tail_pointer(skb);
2635 rxdp3->Buffer0_ptr =
2636 pci_map_single(ring->pdev, ba->ba_0,
2637 BUF0_LEN, PCI_DMA_FROMDEVICE);
2638 if (pci_dma_mapping_error(nic->pdev,
2639 rxdp3->Buffer0_ptr))
2640 goto pci_map_failed;
2642 pci_dma_sync_single_for_device(ring->pdev,
2643 (dma_addr_t) rxdp3->Buffer0_ptr,
2644 BUF0_LEN, PCI_DMA_FROMDEVICE);
2646 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2647 if (ring->rxd_mode == RXD_MODE_3B) {
2648 /* Two buffer mode */
2651 * Buffer2 will have L3/L4 header plus
2654 rxdp3->Buffer2_ptr = pci_map_single
2655 (ring->pdev, skb->data, ring->mtu + 4,
2656 PCI_DMA_FROMDEVICE);
2658 if (pci_dma_mapping_error(nic->pdev,
2659 rxdp3->Buffer2_ptr))
2660 goto pci_map_failed;
2663 rxdp3->Buffer1_ptr =
2664 pci_map_single(ring->pdev,
2666 PCI_DMA_FROMDEVICE);
2668 if (pci_dma_mapping_error(nic->pdev,
2669 rxdp3->Buffer1_ptr)) {
2672 (dma_addr_t)(unsigned long)
2675 PCI_DMA_FROMDEVICE);
2676 goto pci_map_failed;
2679 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2680 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2683 rxdp->Control_2 |= s2BIT(0);
2684 rxdp->Host_Control = (unsigned long) (skb);
2686 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2687 rxdp->Control_1 |= RXD_OWN_XENA;
2689 if (off == (ring->rxd_count + 1))
2691 ring->rx_curr_put_info.offset = off;
2693 rxdp->Control_2 |= SET_RXD_MARKER;
2694 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2697 first_rxdp->Control_1 |= RXD_OWN_XENA;
2701 ring->rx_bufs_left += 1;
2706 /* Transfer ownership of first descriptor to adapter just before
2707 * exiting. Before that, use memory barrier so that ownership
2708 * and other fields are seen by adapter correctly.
2712 first_rxdp->Control_1 |= RXD_OWN_XENA;
2717 stats->pci_map_fail_cnt++;
2718 stats->mem_freed += skb->truesize;
2719 dev_kfree_skb_irq(skb);
2723 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2725 struct net_device *dev = sp->dev;
2727 struct sk_buff *skb;
2729 struct mac_info *mac_control;
2734 mac_control = &sp->mac_control;
2735 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2736 rxdp = mac_control->rings[ring_no].
2737 rx_blocks[blk].rxds[j].virt_addr;
2738 skb = (struct sk_buff *)
2739 ((unsigned long) rxdp->Host_Control);
2743 if (sp->rxd_mode == RXD_MODE_1) {
2744 rxdp1 = (struct RxD1*)rxdp;
2745 pci_unmap_single(sp->pdev, (dma_addr_t)
2748 HEADER_ETHERNET_II_802_3_SIZE
2749 + HEADER_802_2_SIZE +
2751 PCI_DMA_FROMDEVICE);
2752 memset(rxdp, 0, sizeof(struct RxD1));
2753 } else if(sp->rxd_mode == RXD_MODE_3B) {
2754 rxdp3 = (struct RxD3*)rxdp;
2755 ba = &mac_control->rings[ring_no].
2757 pci_unmap_single(sp->pdev, (dma_addr_t)
2760 PCI_DMA_FROMDEVICE);
2761 pci_unmap_single(sp->pdev, (dma_addr_t)
2764 PCI_DMA_FROMDEVICE);
2765 pci_unmap_single(sp->pdev, (dma_addr_t)
2768 PCI_DMA_FROMDEVICE);
2769 memset(rxdp, 0, sizeof(struct RxD3));
2771 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2773 mac_control->rings[ring_no].rx_bufs_left -= 1;
2778 * free_rx_buffers - Frees all Rx buffers
2779 * @sp: device private variable.
2781 * This function will free all Rx buffers allocated by host.
2786 static void free_rx_buffers(struct s2io_nic *sp)
2788 struct net_device *dev = sp->dev;
2789 int i, blk = 0, buf_cnt = 0;
2790 struct mac_info *mac_control;
2791 struct config_param *config;
2793 mac_control = &sp->mac_control;
2794 config = &sp->config;
2796 for (i = 0; i < config->rx_ring_num; i++) {
2797 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2798 free_rxd_blk(sp,i,blk);
2800 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2801 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2802 mac_control->rings[i].rx_curr_put_info.offset = 0;
2803 mac_control->rings[i].rx_curr_get_info.offset = 0;
2804 mac_control->rings[i].rx_bufs_left = 0;
2805 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2806 dev->name, buf_cnt, i);
2810 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2812 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2813 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2814 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2820 * s2io_poll - Rx interrupt handler for NAPI support
2821 * @napi : pointer to the napi structure.
2822 * @budget : The number of packets that were budgeted to be processed
2823 * during one pass through the 'Poll" function.
2825 * Comes into picture only if NAPI support has been incorporated. It does
2826 * the same thing that rx_intr_handler does, but not in a interrupt context
2827 * also It will process only a given number of packets.
2829 * 0 on success and 1 if there are No Rx packets to be processed.
2832 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2834 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2835 struct net_device *dev = ring->dev;
2836 struct config_param *config;
2837 struct mac_info *mac_control;
2838 int pkts_processed = 0;
2839 u8 __iomem *addr = NULL;
2841 struct s2io_nic *nic = netdev_priv(dev);
2842 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2843 int budget_org = budget;
2845 config = &nic->config;
2846 mac_control = &nic->mac_control;
2848 if (unlikely(!is_s2io_card_up(nic)))
2851 pkts_processed = rx_intr_handler(ring, budget);
2852 s2io_chk_rx_buffers(nic, ring);
2854 if (pkts_processed < budget_org) {
2855 napi_complete(napi);
2856 /*Re Enable MSI-Rx Vector*/
2857 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2858 addr += 7 - ring->ring_no;
2859 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2863 return pkts_processed;
2865 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2867 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2868 struct ring_info *ring;
2869 struct config_param *config;
2870 struct mac_info *mac_control;
2871 int pkts_processed = 0;
2872 int ring_pkts_processed, i;
2873 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2874 int budget_org = budget;
2876 config = &nic->config;
2877 mac_control = &nic->mac_control;
2879 if (unlikely(!is_s2io_card_up(nic)))
2882 for (i = 0; i < config->rx_ring_num; i++) {
2883 ring = &mac_control->rings[i];
2884 ring_pkts_processed = rx_intr_handler(ring, budget);
2885 s2io_chk_rx_buffers(nic, ring);
2886 pkts_processed += ring_pkts_processed;
2887 budget -= ring_pkts_processed;
2891 if (pkts_processed < budget_org) {
2892 napi_complete(napi);
2893 /* Re enable the Rx interrupts for the ring */
2894 writeq(0, &bar0->rx_traffic_mask);
2895 readl(&bar0->rx_traffic_mask);
2897 return pkts_processed;
2900 #ifdef CONFIG_NET_POLL_CONTROLLER
2902 * s2io_netpoll - netpoll event handler entry point
2903 * @dev : pointer to the device structure.
2905 * This function will be called by upper layer to check for events on the
2906 * interface in situations where interrupts are disabled. It is used for
2907 * specific in-kernel networking tasks, such as remote consoles and kernel
2908 * debugging over the network (example netdump in RedHat).
2910 static void s2io_netpoll(struct net_device *dev)
2912 struct s2io_nic *nic = netdev_priv(dev);
2913 struct mac_info *mac_control;
2914 struct config_param *config;
2915 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2916 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2919 if (pci_channel_offline(nic->pdev))
2922 disable_irq(dev->irq);
2924 mac_control = &nic->mac_control;
2925 config = &nic->config;
2927 writeq(val64, &bar0->rx_traffic_int);
2928 writeq(val64, &bar0->tx_traffic_int);
2930 /* we need to free up the transmitted skbufs or else netpoll will
2931 * run out of skbs and will fail and eventually netpoll application such
2932 * as netdump will fail.
2934 for (i = 0; i < config->tx_fifo_num; i++)
2935 tx_intr_handler(&mac_control->fifos[i]);
2937 /* check for received packet and indicate up to network */
2938 for (i = 0; i < config->rx_ring_num; i++)
2939 rx_intr_handler(&mac_control->rings[i], 0);
2941 for (i = 0; i < config->rx_ring_num; i++) {
2942 if (fill_rx_buffers(nic, &mac_control->rings[i], 0) ==
2944 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2945 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2949 enable_irq(dev->irq);
2955 * rx_intr_handler - Rx interrupt handler
2956 * @ring_info: per ring structure.
2957 * @budget: budget for napi processing.
2959 * If the interrupt is because of a received frame or if the
2960 * receive ring contains fresh as yet un-processed frames,this function is
2961 * called. It picks out the RxD at which place the last Rx processing had
2962 * stopped and sends the skb to the OSM's Rx handler and then increments
2965 * No. of napi packets processed.
2967 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2969 int get_block, put_block;
2970 struct rx_curr_get_info get_info, put_info;
2972 struct sk_buff *skb;
2973 int pkt_cnt = 0, napi_pkts = 0;
2978 get_info = ring_data->rx_curr_get_info;
2979 get_block = get_info.block_index;
2980 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2981 put_block = put_info.block_index;
2982 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2984 while (RXD_IS_UP2DT(rxdp)) {
2986 * If your are next to put index then it's
2987 * FIFO full condition
2989 if ((get_block == put_block) &&
2990 (get_info.offset + 1) == put_info.offset) {
2991 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2992 ring_data->dev->name);
2995 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2997 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2998 ring_data->dev->name);
2999 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
3002 if (ring_data->rxd_mode == RXD_MODE_1) {
3003 rxdp1 = (struct RxD1*)rxdp;
3004 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3007 HEADER_ETHERNET_II_802_3_SIZE +
3010 PCI_DMA_FROMDEVICE);
3011 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3012 rxdp3 = (struct RxD3*)rxdp;
3013 pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
3015 BUF0_LEN, PCI_DMA_FROMDEVICE);
3016 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3019 PCI_DMA_FROMDEVICE);
3021 prefetch(skb->data);
3022 rx_osm_handler(ring_data, rxdp);
3024 ring_data->rx_curr_get_info.offset = get_info.offset;
3025 rxdp = ring_data->rx_blocks[get_block].
3026 rxds[get_info.offset].virt_addr;
3027 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3028 get_info.offset = 0;
3029 ring_data->rx_curr_get_info.offset = get_info.offset;
3031 if (get_block == ring_data->block_count)
3033 ring_data->rx_curr_get_info.block_index = get_block;
3034 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3037 if (ring_data->nic->config.napi) {
3044 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3047 if (ring_data->lro) {
3048 /* Clear all LRO sessions before exiting */
3049 for (i=0; i<MAX_LRO_SESSIONS; i++) {
3050 struct lro *lro = &ring_data->lro0_n[i];
3052 update_L3L4_header(ring_data->nic, lro);
3053 queue_rx_frame(lro->parent, lro->vlan_tag);
3054 clear_lro_session(lro);
3062 * tx_intr_handler - Transmit interrupt handler
3063 * @nic : device private variable
3065 * If an interrupt was raised to indicate DMA complete of the
3066 * Tx packet, this function is called. It identifies the last TxD
3067 * whose buffer was freed and frees all skbs whose data have already
3068 * DMA'ed into the NICs internal memory.
3073 static void tx_intr_handler(struct fifo_info *fifo_data)
3075 struct s2io_nic *nic = fifo_data->nic;
3076 struct tx_curr_get_info get_info, put_info;
3077 struct sk_buff *skb = NULL;
3080 unsigned long flags = 0;
3083 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3086 get_info = fifo_data->tx_curr_get_info;
3087 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3088 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
3090 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3091 (get_info.offset != put_info.offset) &&
3092 (txdlp->Host_Control)) {
3093 /* Check for TxD errors */
3094 if (txdlp->Control_1 & TXD_T_CODE) {
3095 unsigned long long err;
3096 err = txdlp->Control_1 & TXD_T_CODE;
3098 nic->mac_control.stats_info->sw_stat.
3102 /* update t_code statistics */
3103 err_mask = err >> 48;
3106 nic->mac_control.stats_info->sw_stat.
3111 nic->mac_control.stats_info->sw_stat.
3112 tx_desc_abort_cnt++;
3116 nic->mac_control.stats_info->sw_stat.
3117 tx_parity_err_cnt++;
3121 nic->mac_control.stats_info->sw_stat.
3126 nic->mac_control.stats_info->sw_stat.
3127 tx_list_proc_err_cnt++;
3132 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3134 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3135 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3137 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3142 /* Updating the statistics block */
3143 nic->dev->stats.tx_bytes += skb->len;
3144 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3145 dev_kfree_skb_irq(skb);
3148 if (get_info.offset == get_info.fifo_len + 1)
3149 get_info.offset = 0;
3150 txdlp = (struct TxD *) fifo_data->list_info
3151 [get_info.offset].list_virt_addr;
3152 fifo_data->tx_curr_get_info.offset =
3156 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3158 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3162 * s2io_mdio_write - Function to write in to MDIO registers
3163 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3164 * @addr : address value
3165 * @value : data value
3166 * @dev : pointer to net_device structure
3168 * This function is used to write values to the MDIO registers
3171 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3174 struct s2io_nic *sp = netdev_priv(dev);
3175 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3177 //address transaction
3178 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3179 | MDIO_MMD_DEV_ADDR(mmd_type)
3180 | MDIO_MMS_PRT_ADDR(0x0);
3181 writeq(val64, &bar0->mdio_control);
3182 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3183 writeq(val64, &bar0->mdio_control);
3188 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3189 | MDIO_MMD_DEV_ADDR(mmd_type)
3190 | MDIO_MMS_PRT_ADDR(0x0)
3191 | MDIO_MDIO_DATA(value)
3192 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3193 writeq(val64, &bar0->mdio_control);
3194 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3195 writeq(val64, &bar0->mdio_control);
3199 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3200 | MDIO_MMD_DEV_ADDR(mmd_type)
3201 | MDIO_MMS_PRT_ADDR(0x0)
3202 | MDIO_OP(MDIO_OP_READ_TRANS);
3203 writeq(val64, &bar0->mdio_control);
3204 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3205 writeq(val64, &bar0->mdio_control);
3211 * s2io_mdio_read - Function to write in to MDIO registers
3212 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3213 * @addr : address value
3214 * @dev : pointer to net_device structure
3216 * This function is used to read values to the MDIO registers
3219 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3223 struct s2io_nic *sp = netdev_priv(dev);
3224 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3226 /* address transaction */
3227 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3228 | MDIO_MMD_DEV_ADDR(mmd_type)
3229 | MDIO_MMS_PRT_ADDR(0x0);
3230 writeq(val64, &bar0->mdio_control);
3231 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3232 writeq(val64, &bar0->mdio_control);
3235 /* Data transaction */
3237 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3238 | MDIO_MMD_DEV_ADDR(mmd_type)
3239 | MDIO_MMS_PRT_ADDR(0x0)
3240 | MDIO_OP(MDIO_OP_READ_TRANS);
3241 writeq(val64, &bar0->mdio_control);
3242 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3243 writeq(val64, &bar0->mdio_control);
3246 /* Read the value from regs */
3247 rval64 = readq(&bar0->mdio_control);
3248 rval64 = rval64 & 0xFFFF0000;
3249 rval64 = rval64 >> 16;
3253 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3254 * @counter : couter value to be updated
3255 * @flag : flag to indicate the status
3256 * @type : counter type
3258 * This function is to check the status of the xpak counters value
3262 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3267 for(i = 0; i <index; i++)
3272 *counter = *counter + 1;
3273 val64 = *regs_stat & mask;
3274 val64 = val64 >> (index * 0x2);
3281 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3282 "service. Excessive temperatures may "
3283 "result in premature transceiver "
3287 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3288 "service Excessive bias currents may "
3289 "indicate imminent laser diode "
3293 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3294 "service Excessive laser output "
3295 "power may saturate far-end "
3299 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3304 val64 = val64 << (index * 0x2);
3305 *regs_stat = (*regs_stat & (~mask)) | (val64);
3308 *regs_stat = *regs_stat & (~mask);
3313 * s2io_updt_xpak_counter - Function to update the xpak counters
3314 * @dev : pointer to net_device struct
3316 * This function is to upate the status of the xpak counters value
3319 static void s2io_updt_xpak_counter(struct net_device *dev)
3327 struct s2io_nic *sp = netdev_priv(dev);
3328 struct stat_block *stat_info = sp->mac_control.stats_info;
3330 /* Check the communication with the MDIO slave */
3333 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3334 if((val64 == 0xFFFF) || (val64 == 0x0000))
3336 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3337 "Returned %llx\n", (unsigned long long)val64);
3341 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3344 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3345 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3346 (unsigned long long)val64);
3350 /* Loading the DOM register to MDIO register */
3352 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3353 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3355 /* Reading the Alarm flags */
3358 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3360 flag = CHECKBIT(val64, 0x7);
3362 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3363 &stat_info->xpak_stat.xpak_regs_stat,
3366 if(CHECKBIT(val64, 0x6))
3367 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3369 flag = CHECKBIT(val64, 0x3);
3371 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3372 &stat_info->xpak_stat.xpak_regs_stat,
3375 if(CHECKBIT(val64, 0x2))
3376 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3378 flag = CHECKBIT(val64, 0x1);
3380 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3381 &stat_info->xpak_stat.xpak_regs_stat,
3384 if(CHECKBIT(val64, 0x0))
3385 stat_info->xpak_stat.alarm_laser_output_power_low++;
3387 /* Reading the Warning flags */
3390 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3392 if(CHECKBIT(val64, 0x7))
3393 stat_info->xpak_stat.warn_transceiver_temp_high++;
3395 if(CHECKBIT(val64, 0x6))
3396 stat_info->xpak_stat.warn_transceiver_temp_low++;
3398 if(CHECKBIT(val64, 0x3))
3399 stat_info->xpak_stat.warn_laser_bias_current_high++;
3401 if(CHECKBIT(val64, 0x2))
3402 stat_info->xpak_stat.warn_laser_bias_current_low++;
3404 if(CHECKBIT(val64, 0x1))
3405 stat_info->xpak_stat.warn_laser_output_power_high++;
3407 if(CHECKBIT(val64, 0x0))
3408 stat_info->xpak_stat.warn_laser_output_power_low++;
3412 * wait_for_cmd_complete - waits for a command to complete.
3413 * @sp : private member of the device structure, which is a pointer to the
3414 * s2io_nic structure.
3415 * Description: Function that waits for a command to Write into RMAC
3416 * ADDR DATA registers to be completed and returns either success or
3417 * error depending on whether the command was complete or not.
3419 * SUCCESS on success and FAILURE on failure.
3422 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3425 int ret = FAILURE, cnt = 0, delay = 1;
3428 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3432 val64 = readq(addr);
3433 if (bit_state == S2IO_BIT_RESET) {
3434 if (!(val64 & busy_bit)) {
3439 if (!(val64 & busy_bit)) {
3456 * check_pci_device_id - Checks if the device id is supported
3458 * Description: Function to check if the pci device id is supported by driver.
3459 * Return value: Actual device id if supported else PCI_ANY_ID
3461 static u16 check_pci_device_id(u16 id)
3464 case PCI_DEVICE_ID_HERC_WIN:
3465 case PCI_DEVICE_ID_HERC_UNI:
3466 return XFRAME_II_DEVICE;
3467 case PCI_DEVICE_ID_S2IO_UNI:
3468 case PCI_DEVICE_ID_S2IO_WIN:
3469 return XFRAME_I_DEVICE;
3476 * s2io_reset - Resets the card.
3477 * @sp : private member of the device structure.
3478 * Description: Function to Reset the card. This function then also
3479 * restores the previously saved PCI configuration space registers as
3480 * the card reset also resets the configuration space.
3485 static void s2io_reset(struct s2io_nic * sp)
3487 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3492 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3493 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3495 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3496 __func__, sp->dev->name);
3498 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3499 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3501 val64 = SW_RESET_ALL;
3502 writeq(val64, &bar0->sw_reset);
3503 if (strstr(sp->product_name, "CX4")) {
3507 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3509 /* Restore the PCI state saved during initialization. */
3510 pci_restore_state(sp->pdev);
3511 pci_read_config_word(sp->pdev, 0x2, &val16);
3512 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3517 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3518 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __func__);
3521 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3525 /* Set swapper to enable I/O register access */
3526 s2io_set_swapper(sp);
3528 /* restore mac_addr entries */
3529 do_s2io_restore_unicast_mc(sp);
3531 /* Restore the MSIX table entries from local variables */
3532 restore_xmsi_data(sp);
3534 /* Clear certain PCI/PCI-X fields after reset */
3535 if (sp->device_type == XFRAME_II_DEVICE) {
3536 /* Clear "detected parity error" bit */
3537 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3539 /* Clearing PCIX Ecc status register */
3540 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3542 /* Clearing PCI_STATUS error reflected here */
3543 writeq(s2BIT(62), &bar0->txpic_int_reg);
3546 /* Reset device statistics maintained by OS */
3547 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3549 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3550 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3551 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3552 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3553 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3554 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3555 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3556 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3557 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3558 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3559 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3560 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3561 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3562 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3563 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3564 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3565 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3566 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3567 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3569 /* SXE-002: Configure link and activity LED to turn it off */
3570 subid = sp->pdev->subsystem_device;
3571 if (((subid & 0xFF) >= 0x07) &&
3572 (sp->device_type == XFRAME_I_DEVICE)) {
3573 val64 = readq(&bar0->gpio_control);
3574 val64 |= 0x0000800000000000ULL;
3575 writeq(val64, &bar0->gpio_control);
3576 val64 = 0x0411040400000000ULL;
3577 writeq(val64, (void __iomem *)bar0 + 0x2700);
3581 * Clear spurious ECC interrupts that would have occured on
3582 * XFRAME II cards after reset.
3584 if (sp->device_type == XFRAME_II_DEVICE) {
3585 val64 = readq(&bar0->pcc_err_reg);
3586 writeq(val64, &bar0->pcc_err_reg);
3589 sp->device_enabled_once = FALSE;
3593 * s2io_set_swapper - to set the swapper controle on the card
3594 * @sp : private member of the device structure,
3595 * pointer to the s2io_nic structure.
3596 * Description: Function to set the swapper control on the card
3597 * correctly depending on the 'endianness' of the system.
3599 * SUCCESS on success and FAILURE on failure.
3602 static int s2io_set_swapper(struct s2io_nic * sp)
3604 struct net_device *dev = sp->dev;
3605 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3606 u64 val64, valt, valr;
3609 * Set proper endian settings and verify the same by reading
3610 * the PIF Feed-back register.
3613 val64 = readq(&bar0->pif_rd_swapper_fb);
3614 if (val64 != 0x0123456789ABCDEFULL) {
3616 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3617 0x8100008181000081ULL, /* FE=1, SE=0 */
3618 0x4200004242000042ULL, /* FE=0, SE=1 */
3619 0}; /* FE=0, SE=0 */
3622 writeq(value[i], &bar0->swapper_ctrl);
3623 val64 = readq(&bar0->pif_rd_swapper_fb);
3624 if (val64 == 0x0123456789ABCDEFULL)
3629 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3631 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3632 (unsigned long long) val64);
3637 valr = readq(&bar0->swapper_ctrl);
3640 valt = 0x0123456789ABCDEFULL;
3641 writeq(valt, &bar0->xmsi_address);
3642 val64 = readq(&bar0->xmsi_address);
3646 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3647 0x0081810000818100ULL, /* FE=1, SE=0 */
3648 0x0042420000424200ULL, /* FE=0, SE=1 */
3649 0}; /* FE=0, SE=0 */
3652 writeq((value[i] | valr), &bar0->swapper_ctrl);
3653 writeq(valt, &bar0->xmsi_address);
3654 val64 = readq(&bar0->xmsi_address);
3660 unsigned long long x = val64;
3661 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3662 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3666 val64 = readq(&bar0->swapper_ctrl);
3667 val64 &= 0xFFFF000000000000ULL;
3671 * The device by default set to a big endian format, so a
3672 * big endian driver need not set anything.
3674 val64 |= (SWAPPER_CTRL_TXP_FE |
3675 SWAPPER_CTRL_TXP_SE |
3676 SWAPPER_CTRL_TXD_R_FE |
3677 SWAPPER_CTRL_TXD_W_FE |
3678 SWAPPER_CTRL_TXF_R_FE |
3679 SWAPPER_CTRL_RXD_R_FE |
3680 SWAPPER_CTRL_RXD_W_FE |
3681 SWAPPER_CTRL_RXF_W_FE |
3682 SWAPPER_CTRL_XMSI_FE |
3683 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3684 if (sp->config.intr_type == INTA)
3685 val64 |= SWAPPER_CTRL_XMSI_SE;
3686 writeq(val64, &bar0->swapper_ctrl);
3689 * Initially we enable all bits to make it accessible by the
3690 * driver, then we selectively enable only those bits that
3693 val64 |= (SWAPPER_CTRL_TXP_FE |
3694 SWAPPER_CTRL_TXP_SE |
3695 SWAPPER_CTRL_TXD_R_FE |
3696 SWAPPER_CTRL_TXD_R_SE |
3697 SWAPPER_CTRL_TXD_W_FE |
3698 SWAPPER_CTRL_TXD_W_SE |
3699 SWAPPER_CTRL_TXF_R_FE |
3700 SWAPPER_CTRL_RXD_R_FE |
3701 SWAPPER_CTRL_RXD_R_SE |
3702 SWAPPER_CTRL_RXD_W_FE |
3703 SWAPPER_CTRL_RXD_W_SE |
3704 SWAPPER_CTRL_RXF_W_FE |
3705 SWAPPER_CTRL_XMSI_FE |
3706 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3707 if (sp->config.intr_type == INTA)
3708 val64 |= SWAPPER_CTRL_XMSI_SE;
3709 writeq(val64, &bar0->swapper_ctrl);
3711 val64 = readq(&bar0->swapper_ctrl);
3714 * Verifying if endian settings are accurate by reading a
3715 * feedback register.
3717 val64 = readq(&bar0->pif_rd_swapper_fb);
3718 if (val64 != 0x0123456789ABCDEFULL) {
3719 /* Endian settings are incorrect, calls for another dekko. */
3720 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3722 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3723 (unsigned long long) val64);
3730 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3732 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3734 int ret = 0, cnt = 0;
3737 val64 = readq(&bar0->xmsi_access);
3738 if (!(val64 & s2BIT(15)))
3744 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3751 static void restore_xmsi_data(struct s2io_nic *nic)
3753 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3758 if (nic->device_type == XFRAME_I_DEVICE)
3761 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3762 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3763 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3764 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3765 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3766 writeq(val64, &bar0->xmsi_access);
3767 if (wait_for_msix_trans(nic, msix_index)) {
3768 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
3774 static void store_xmsi_data(struct s2io_nic *nic)
3776 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3777 u64 val64, addr, data;
3780 if (nic->device_type == XFRAME_I_DEVICE)
3783 /* Store and display */
3784 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3785 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3786 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3787 writeq(val64, &bar0->xmsi_access);
3788 if (wait_for_msix_trans(nic, msix_index)) {
3789 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
3792 addr = readq(&bar0->xmsi_address);
3793 data = readq(&bar0->xmsi_data);
3795 nic->msix_info[i].addr = addr;
3796 nic->msix_info[i].data = data;
3801 static int s2io_enable_msi_x(struct s2io_nic *nic)
3803 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3805 u16 msi_control; /* Temp variable */
3806 int ret, i, j, msix_indx = 1;
3808 nic->entries = kmalloc(nic->num_entries * sizeof(struct msix_entry),
3810 if (!nic->entries) {
3811 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3813 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3816 nic->mac_control.stats_info->sw_stat.mem_allocated
3817 += (nic->num_entries * sizeof(struct msix_entry));
3819 memset(nic->entries, 0, nic->num_entries * sizeof(struct msix_entry));
3822 kmalloc(nic->num_entries * sizeof(struct s2io_msix_entry),
3824 if (!nic->s2io_entries) {
3825 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3827 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3828 kfree(nic->entries);
3829 nic->mac_control.stats_info->sw_stat.mem_freed
3830 += (nic->num_entries * sizeof(struct msix_entry));
3833 nic->mac_control.stats_info->sw_stat.mem_allocated
3834 += (nic->num_entries * sizeof(struct s2io_msix_entry));
3835 memset(nic->s2io_entries, 0,
3836 nic->num_entries * sizeof(struct s2io_msix_entry));
3838 nic->entries[0].entry = 0;
3839 nic->s2io_entries[0].entry = 0;
3840 nic->s2io_entries[0].in_use = MSIX_FLG;
3841 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3842 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3844 for (i = 1; i < nic->num_entries; i++) {
3845 nic->entries[i].entry = ((i - 1) * 8) + 1;
3846 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3847 nic->s2io_entries[i].arg = NULL;
3848 nic->s2io_entries[i].in_use = 0;
3851 rx_mat = readq(&bar0->rx_mat);
3852 for (j = 0; j < nic->config.rx_ring_num; j++) {
3853 rx_mat |= RX_MAT_SET(j, msix_indx);
3854 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3855 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3856 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3859 writeq(rx_mat, &bar0->rx_mat);
3860 readq(&bar0->rx_mat);
3862 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3863 /* We fail init if error or we get less vectors than min required */
3865 DBG_PRINT(ERR_DBG, "s2io: Enabling MSI-X failed\n");
3866 kfree(nic->entries);
3867 nic->mac_control.stats_info->sw_stat.mem_freed
3868 += (nic->num_entries * sizeof(struct msix_entry));
3869 kfree(nic->s2io_entries);
3870 nic->mac_control.stats_info->sw_stat.mem_freed
3871 += (nic->num_entries * sizeof(struct s2io_msix_entry));
3872 nic->entries = NULL;
3873 nic->s2io_entries = NULL;
3878 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3879 * in the herc NIC. (Temp change, needs to be removed later)
3881 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3882 msi_control |= 0x1; /* Enable MSI */
3883 pci_write_config_word(nic->pdev, 0x42, msi_control);
3888 /* Handle software interrupt used during MSI(X) test */
3889 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3891 struct s2io_nic *sp = dev_id;
3893 sp->msi_detected = 1;
3894 wake_up(&sp->msi_wait);
3899 /* Test interrupt path by forcing a a software IRQ */
3900 static int s2io_test_msi(struct s2io_nic *sp)
3902 struct pci_dev *pdev = sp->pdev;
3903 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3907 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3910 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3911 sp->dev->name, pci_name(pdev), pdev->irq);
3915 init_waitqueue_head (&sp->msi_wait);
3916 sp->msi_detected = 0;
3918 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3919 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3920 val64 |= SCHED_INT_CTRL_TIMER_EN;
3921 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3922 writeq(val64, &bar0->scheduled_int_ctrl);
3924 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3926 if (!sp->msi_detected) {
3927 /* MSI(X) test failed, go back to INTx mode */
3928 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3929 "using MSI(X) during test\n", sp->dev->name,
3935 free_irq(sp->entries[1].vector, sp);
3937 writeq(saved64, &bar0->scheduled_int_ctrl);
3942 static void remove_msix_isr(struct s2io_nic *sp)
3947 for (i = 0; i < sp->num_entries; i++) {
3948 if (sp->s2io_entries[i].in_use ==
3949 MSIX_REGISTERED_SUCCESS) {
3950 int vector = sp->entries[i].vector;
3951 void *arg = sp->s2io_entries[i].arg;
3952 free_irq(vector, arg);
3957 kfree(sp->s2io_entries);
3959 sp->s2io_entries = NULL;
3961 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3962 msi_control &= 0xFFFE; /* Disable MSI */
3963 pci_write_config_word(sp->pdev, 0x42, msi_control);
3965 pci_disable_msix(sp->pdev);
3968 static void remove_inta_isr(struct s2io_nic *sp)
3970 struct net_device *dev = sp->dev;
3972 free_irq(sp->pdev->irq, dev);
3975 /* ********************************************************* *
3976 * Functions defined below concern the OS part of the driver *
3977 * ********************************************************* */
3980 * s2io_open - open entry point of the driver
3981 * @dev : pointer to the device structure.
3983 * This function is the open entry point of the driver. It mainly calls a
3984 * function to allocate Rx buffers and inserts them into the buffer
3985 * descriptors and then enables the Rx part of the NIC.
3987 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3991 static int s2io_open(struct net_device *dev)
3993 struct s2io_nic *sp = netdev_priv(dev);
3997 * Make sure you have link off by default every time
3998 * Nic is initialized
4000 netif_carrier_off(dev);
4001 sp->last_link_state = 0;
4003 /* Initialize H/W and enable interrupts */
4004 err = s2io_card_up(sp);
4006 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4008 goto hw_init_failed;
4011 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4012 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4015 goto hw_init_failed;
4017 s2io_start_all_tx_queue(sp);
4021 if (sp->config.intr_type == MSI_X) {
4024 sp->mac_control.stats_info->sw_stat.mem_freed
4025 += (sp->num_entries * sizeof(struct msix_entry));
4027 if (sp->s2io_entries) {
4028 kfree(sp->s2io_entries);
4029 sp->mac_control.stats_info->sw_stat.mem_freed
4030 += (sp->num_entries * sizeof(struct s2io_msix_entry));
4037 * s2io_close -close entry point of the driver
4038 * @dev : device pointer.
4040 * This is the stop entry point of the driver. It needs to undo exactly
4041 * whatever was done by the open entry point,thus it's usually referred to
4042 * as the close function.Among other things this function mainly stops the
4043 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4045 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4049 static int s2io_close(struct net_device *dev)
4051 struct s2io_nic *sp = netdev_priv(dev);
4052 struct config_param *config = &sp->config;
4056 /* Return if the device is already closed *
4057 * Can happen when s2io_card_up failed in change_mtu *
4059 if (!is_s2io_card_up(sp))
4062 s2io_stop_all_tx_queue(sp);
4063 /* delete all populated mac entries */
4064 for (offset = 1; offset < config->max_mc_addr; offset++) {
4065 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4066 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4067 do_s2io_delete_unicast_mc(sp, tmp64);
4076 * s2io_xmit - Tx entry point of te driver
4077 * @skb : the socket buffer containing the Tx data.
4078 * @dev : device pointer.
4080 * This function is the Tx entry point of the driver. S2IO NIC supports
4081 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4082 * NOTE: when device cant queue the pkt,just the trans_start variable will
4085 * 0 on success & 1 on failure.
4088 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4090 struct s2io_nic *sp = netdev_priv(dev);
4091 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4094 struct TxFIFO_element __iomem *tx_fifo;
4095 unsigned long flags = 0;
4097 struct fifo_info *fifo = NULL;
4098 struct mac_info *mac_control;
4099 struct config_param *config;
4100 int do_spin_lock = 1;
4102 int enable_per_list_interrupt = 0;
4103 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
4105 mac_control = &sp->mac_control;
4106 config = &sp->config;
4108 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4110 if (unlikely(skb->len <= 0)) {
4111 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4112 dev_kfree_skb_any(skb);
4116 if (!is_s2io_card_up(sp)) {
4117 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4124 if (sp->vlgrp && vlan_tx_tag_present(skb))
4125 vlan_tag = vlan_tx_tag_get(skb);
4126 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4127 if (skb->protocol == htons(ETH_P_IP)) {
4132 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4133 th = (struct tcphdr *)(((unsigned char *)ip) +
4136 if (ip->protocol == IPPROTO_TCP) {
4137 queue_len = sp->total_tcp_fifos;
4138 queue = (ntohs(th->source) +
4140 sp->fifo_selector[queue_len - 1];
4141 if (queue >= queue_len)
4142 queue = queue_len - 1;
4143 } else if (ip->protocol == IPPROTO_UDP) {
4144 queue_len = sp->total_udp_fifos;
4145 queue = (ntohs(th->source) +
4147 sp->fifo_selector[queue_len - 1];
4148 if (queue >= queue_len)
4149 queue = queue_len - 1;
4150 queue += sp->udp_fifo_idx;
4151 if (skb->len > 1024)
4152 enable_per_list_interrupt = 1;
4157 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4158 /* get fifo number based on skb->priority value */
4159 queue = config->fifo_mapping
4160 [skb->priority & (MAX_TX_FIFOS - 1)];
4161 fifo = &mac_control->fifos[queue];
4164 spin_lock_irqsave(&fifo->tx_lock, flags);
4166 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4167 return NETDEV_TX_LOCKED;
4170 if (sp->config.multiq) {
4171 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4172 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4173 return NETDEV_TX_BUSY;
4175 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4176 if (netif_queue_stopped(dev)) {
4177 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4178 return NETDEV_TX_BUSY;
4182 put_off = (u16) fifo->tx_curr_put_info.offset;
4183 get_off = (u16) fifo->tx_curr_get_info.offset;
4184 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
4186 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4187 /* Avoid "put" pointer going beyond "get" pointer */
4188 if (txdp->Host_Control ||
4189 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4190 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4191 s2io_stop_tx_queue(sp, fifo->fifo_no);
4193 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4197 offload_type = s2io_offload_type(skb);
4198 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4199 txdp->Control_1 |= TXD_TCP_LSO_EN;
4200 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4202 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4204 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4207 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4208 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4209 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4210 if (enable_per_list_interrupt)
4211 if (put_off & (queue_len >> 5))
4212 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4214 txdp->Control_2 |= TXD_VLAN_ENABLE;
4215 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4218 frg_len = skb->len - skb->data_len;
4219 if (offload_type == SKB_GSO_UDP) {
4222 ufo_size = s2io_udp_mss(skb);
4224 txdp->Control_1 |= TXD_UFO_EN;
4225 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4226 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4228 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4229 fifo->ufo_in_band_v[put_off] =
4230 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4232 fifo->ufo_in_band_v[put_off] =
4233 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4235 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4236 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4237 fifo->ufo_in_band_v,
4238 sizeof(u64), PCI_DMA_TODEVICE);
4239 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4240 goto pci_map_failed;
4244 txdp->Buffer_Pointer = pci_map_single
4245 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4246 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4247 goto pci_map_failed;
4249 txdp->Host_Control = (unsigned long) skb;
4250 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4251 if (offload_type == SKB_GSO_UDP)
4252 txdp->Control_1 |= TXD_UFO_EN;
4254 frg_cnt = skb_shinfo(skb)->nr_frags;
4255 /* For fragmented SKB. */
4256 for (i = 0; i < frg_cnt; i++) {
4257 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4258 /* A '0' length fragment will be ignored */
4262 txdp->Buffer_Pointer = (u64) pci_map_page
4263 (sp->pdev, frag->page, frag->page_offset,
4264 frag->size, PCI_DMA_TODEVICE);
4265 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4266 if (offload_type == SKB_GSO_UDP)
4267 txdp->Control_1 |= TXD_UFO_EN;
4269 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4271 if (offload_type == SKB_GSO_UDP)
4272 frg_cnt++; /* as Txd0 was used for inband header */
4274 tx_fifo = mac_control->tx_FIFO_start[queue];
4275 val64 = fifo->list_info[put_off].list_phy_addr;
4276 writeq(val64, &tx_fifo->TxDL_Pointer);
4278 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4281 val64 |= TX_FIFO_SPECIAL_FUNC;
4283 writeq(val64, &tx_fifo->List_Control);
4288 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4290 fifo->tx_curr_put_info.offset = put_off;
4292 /* Avoid "put" pointer going beyond "get" pointer */
4293 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4294 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4296 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4298 s2io_stop_tx_queue(sp, fifo->fifo_no);
4300 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4301 dev->trans_start = jiffies;
4302 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4304 if (sp->config.intr_type == MSI_X)
4305 tx_intr_handler(fifo);
4309 stats->pci_map_fail_cnt++;
4310 s2io_stop_tx_queue(sp, fifo->fifo_no);
4311 stats->mem_freed += skb->truesize;
4313 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4318 s2io_alarm_handle(unsigned long data)
4320 struct s2io_nic *sp = (struct s2io_nic *)data;
4321 struct net_device *dev = sp->dev;
4323 s2io_handle_errors(dev);
4324 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4327 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4329 struct ring_info *ring = (struct ring_info *)dev_id;
4330 struct s2io_nic *sp = ring->nic;
4331 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4333 if (unlikely(!is_s2io_card_up(sp)))
4336 if (sp->config.napi) {
4337 u8 __iomem *addr = NULL;
4340 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4341 addr += (7 - ring->ring_no);
4342 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4345 napi_schedule(&ring->napi);
4347 rx_intr_handler(ring, 0);
4348 s2io_chk_rx_buffers(sp, ring);
4354 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4357 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4358 struct s2io_nic *sp = fifos->nic;
4359 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4360 struct config_param *config = &sp->config;
4363 if (unlikely(!is_s2io_card_up(sp)))
4366 reason = readq(&bar0->general_int_status);
4367 if (unlikely(reason == S2IO_MINUS_ONE))
4368 /* Nothing much can be done. Get out */
4371 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4372 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4374 if (reason & GEN_INTR_TXPIC)
4375 s2io_txpic_intr_handle(sp);
4377 if (reason & GEN_INTR_TXTRAFFIC)
4378 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4380 for (i = 0; i < config->tx_fifo_num; i++)
4381 tx_intr_handler(&fifos[i]);
4383 writeq(sp->general_int_mask, &bar0->general_int_mask);
4384 readl(&bar0->general_int_status);
4387 /* The interrupt was not raised by us */
4391 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4393 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4396 val64 = readq(&bar0->pic_int_status);
4397 if (val64 & PIC_INT_GPIO) {
4398 val64 = readq(&bar0->gpio_int_reg);
4399 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4400 (val64 & GPIO_INT_REG_LINK_UP)) {
4402 * This is unstable state so clear both up/down
4403 * interrupt and adapter to re-evaluate the link state.
4405 val64 |= GPIO_INT_REG_LINK_DOWN;
4406 val64 |= GPIO_INT_REG_LINK_UP;
4407 writeq(val64, &bar0->gpio_int_reg);
4408 val64 = readq(&bar0->gpio_int_mask);
4409 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4410 GPIO_INT_MASK_LINK_DOWN);
4411 writeq(val64, &bar0->gpio_int_mask);
4413 else if (val64 & GPIO_INT_REG_LINK_UP) {
4414 val64 = readq(&bar0->adapter_status);
4415 /* Enable Adapter */
4416 val64 = readq(&bar0->adapter_control);
4417 val64 |= ADAPTER_CNTL_EN;
4418 writeq(val64, &bar0->adapter_control);
4419 val64 |= ADAPTER_LED_ON;
4420 writeq(val64, &bar0->adapter_control);
4421 if (!sp->device_enabled_once)
4422 sp->device_enabled_once = 1;
4424 s2io_link(sp, LINK_UP);
4426 * unmask link down interrupt and mask link-up
4429 val64 = readq(&bar0->gpio_int_mask);
4430 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4431 val64 |= GPIO_INT_MASK_LINK_UP;
4432 writeq(val64, &bar0->gpio_int_mask);
4434 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4435 val64 = readq(&bar0->adapter_status);
4436 s2io_link(sp, LINK_DOWN);
4437 /* Link is down so unmaks link up interrupt */
4438 val64 = readq(&bar0->gpio_int_mask);
4439 val64 &= ~GPIO_INT_MASK_LINK_UP;
4440 val64 |= GPIO_INT_MASK_LINK_DOWN;
4441 writeq(val64, &bar0->gpio_int_mask);
4444 val64 = readq(&bar0->adapter_control);
4445 val64 = val64 &(~ADAPTER_LED_ON);
4446 writeq(val64, &bar0->adapter_control);
4449 val64 = readq(&bar0->gpio_int_mask);
4453 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4454 * @value: alarm bits
4455 * @addr: address value
4456 * @cnt: counter variable
4457 * Description: Check for alarm and increment the counter
4459 * 1 - if alarm bit set
4460 * 0 - if alarm bit is not set
4462 static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
4463 unsigned long long *cnt)
4466 val64 = readq(addr);
4467 if ( val64 & value ) {
4468 writeq(val64, addr);
4477 * s2io_handle_errors - Xframe error indication handler
4478 * @nic: device private variable
4479 * Description: Handle alarms such as loss of link, single or
4480 * double ECC errors, critical and serious errors.
4484 static void s2io_handle_errors(void * dev_id)
4486 struct net_device *dev = (struct net_device *) dev_id;
4487 struct s2io_nic *sp = netdev_priv(dev);
4488 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4489 u64 temp64 = 0,val64=0;
4492 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4493 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4495 if (!is_s2io_card_up(sp))
4498 if (pci_channel_offline(sp->pdev))
4501 memset(&sw_stat->ring_full_cnt, 0,
4502 sizeof(sw_stat->ring_full_cnt));
4504 /* Handling the XPAK counters update */
4505 if(stats->xpak_timer_count < 72000) {
4506 /* waiting for an hour */
4507 stats->xpak_timer_count++;
4509 s2io_updt_xpak_counter(dev);
4510 /* reset the count to zero */
4511 stats->xpak_timer_count = 0;
4514 /* Handling link status change error Intr */
4515 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4516 val64 = readq(&bar0->mac_rmac_err_reg);
4517 writeq(val64, &bar0->mac_rmac_err_reg);
4518 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4519 schedule_work(&sp->set_link_task);
4522 /* In case of a serious error, the device will be Reset. */
4523 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4524 &sw_stat->serious_err_cnt))
4527 /* Check for data parity error */
4528 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4529 &sw_stat->parity_err_cnt))
4532 /* Check for ring full counter */
4533 if (sp->device_type == XFRAME_II_DEVICE) {
4534 val64 = readq(&bar0->ring_bump_counter1);
4535 for (i=0; i<4; i++) {
4536 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4537 temp64 >>= 64 - ((i+1)*16);
4538 sw_stat->ring_full_cnt[i] += temp64;
4541 val64 = readq(&bar0->ring_bump_counter2);
4542 for (i=0; i<4; i++) {
4543 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4544 temp64 >>= 64 - ((i+1)*16);
4545 sw_stat->ring_full_cnt[i+4] += temp64;
4549 val64 = readq(&bar0->txdma_int_status);
4550 /*check for pfc_err*/
4551 if (val64 & TXDMA_PFC_INT) {
4552 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4553 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4554 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4555 &sw_stat->pfc_err_cnt))
4557 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4558 &sw_stat->pfc_err_cnt);
4561 /*check for tda_err*/
4562 if (val64 & TXDMA_TDA_INT) {
4563 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4564 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4565 &sw_stat->tda_err_cnt))
4567 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4568 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4570 /*check for pcc_err*/
4571 if (val64 & TXDMA_PCC_INT) {
4572 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4573 | PCC_N_SERR | PCC_6_COF_OV_ERR
4574 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4575 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4576 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4577 &sw_stat->pcc_err_cnt))
4579 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4580 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4583 /*check for tti_err*/
4584 if (val64 & TXDMA_TTI_INT) {
4585 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4586 &sw_stat->tti_err_cnt))
4588 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4589 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4592 /*check for lso_err*/
4593 if (val64 & TXDMA_LSO_INT) {
4594 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4595 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4596 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4598 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4599 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4602 /*check for tpa_err*/
4603 if (val64 & TXDMA_TPA_INT) {
4604 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4605 &sw_stat->tpa_err_cnt))
4607 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4608 &sw_stat->tpa_err_cnt);
4611 /*check for sm_err*/
4612 if (val64 & TXDMA_SM_INT) {
4613 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4614 &sw_stat->sm_err_cnt))
4618 val64 = readq(&bar0->mac_int_status);
4619 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4620 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4621 &bar0->mac_tmac_err_reg,
4622 &sw_stat->mac_tmac_err_cnt))
4624 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4625 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4626 &bar0->mac_tmac_err_reg,
4627 &sw_stat->mac_tmac_err_cnt);
4630 val64 = readq(&bar0->xgxs_int_status);
4631 if (val64 & XGXS_INT_STATUS_TXGXS) {
4632 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4633 &bar0->xgxs_txgxs_err_reg,
4634 &sw_stat->xgxs_txgxs_err_cnt))
4636 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4637 &bar0->xgxs_txgxs_err_reg,
4638 &sw_stat->xgxs_txgxs_err_cnt);
4641 val64 = readq(&bar0->rxdma_int_status);
4642 if (val64 & RXDMA_INT_RC_INT_M) {
4643 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4644 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4645 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4647 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4648 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4649 &sw_stat->rc_err_cnt);
4650 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4651 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4652 &sw_stat->prc_pcix_err_cnt))
4654 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4655 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4656 &sw_stat->prc_pcix_err_cnt);
4659 if (val64 & RXDMA_INT_RPA_INT_M) {
4660 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4661 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4663 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4664 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4667 if (val64 & RXDMA_INT_RDA_INT_M) {
4668 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4669 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4670 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4671 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4673 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4674 | RDA_MISC_ERR | RDA_PCIX_ERR,
4675 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4678 if (val64 & RXDMA_INT_RTI_INT_M) {
4679 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4680 &sw_stat->rti_err_cnt))
4682 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4683 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4686 val64 = readq(&bar0->mac_int_status);
4687 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4688 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4689 &bar0->mac_rmac_err_reg,
4690 &sw_stat->mac_rmac_err_cnt))
4692 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4693 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4694 &sw_stat->mac_rmac_err_cnt);
4697 val64 = readq(&bar0->xgxs_int_status);
4698 if (val64 & XGXS_INT_STATUS_RXGXS) {
4699 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4700 &bar0->xgxs_rxgxs_err_reg,
4701 &sw_stat->xgxs_rxgxs_err_cnt))
4705 val64 = readq(&bar0->mc_int_status);
4706 if(val64 & MC_INT_STATUS_MC_INT) {
4707 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4708 &sw_stat->mc_err_cnt))
4711 /* Handling Ecc errors */
4712 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4713 writeq(val64, &bar0->mc_err_reg);
4714 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4715 sw_stat->double_ecc_errs++;
4716 if (sp->device_type != XFRAME_II_DEVICE) {
4718 * Reset XframeI only if critical error
4721 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4722 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4726 sw_stat->single_ecc_errs++;
4732 s2io_stop_all_tx_queue(sp);
4733 schedule_work(&sp->rst_timer_task);
4734 sw_stat->soft_reset_cnt++;
4739 * s2io_isr - ISR handler of the device .
4740 * @irq: the irq of the device.
4741 * @dev_id: a void pointer to the dev structure of the NIC.
4742 * Description: This function is the ISR handler of the device. It
4743 * identifies the reason for the interrupt and calls the relevant
4744 * service routines. As a contongency measure, this ISR allocates the
4745 * recv buffers, if their numbers are below the panic value which is
4746 * presently set to 25% of the original number of rcv buffers allocated.
4748 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4749 * IRQ_NONE: will be returned if interrupt is not from our device
4751 static irqreturn_t s2io_isr(int irq, void *dev_id)
4753 struct net_device *dev = (struct net_device *) dev_id;
4754 struct s2io_nic *sp = netdev_priv(dev);
4755 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4758 struct mac_info *mac_control;
4759 struct config_param *config;
4761 /* Pretend we handled any irq's from a disconnected card */
4762 if (pci_channel_offline(sp->pdev))
4765 if (!is_s2io_card_up(sp))
4768 mac_control = &sp->mac_control;
4769 config = &sp->config;
4772 * Identify the cause for interrupt and call the appropriate
4773 * interrupt handler. Causes for the interrupt could be;
4778 reason = readq(&bar0->general_int_status);
4780 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4781 /* Nothing much can be done. Get out */
4785 if (reason & (GEN_INTR_RXTRAFFIC |
4786 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4788 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4791 if (reason & GEN_INTR_RXTRAFFIC) {
4792 napi_schedule(&sp->napi);
4793 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4794 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4795 readl(&bar0->rx_traffic_int);
4799 * rx_traffic_int reg is an R1 register, writing all 1's
4800 * will ensure that the actual interrupt causing bit
4801 * get's cleared and hence a read can be avoided.
4803 if (reason & GEN_INTR_RXTRAFFIC)
4804 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4806 for (i = 0; i < config->rx_ring_num; i++)
4807 rx_intr_handler(&mac_control->rings[i], 0);
4811 * tx_traffic_int reg is an R1 register, writing all 1's
4812 * will ensure that the actual interrupt causing bit get's
4813 * cleared and hence a read can be avoided.
4815 if (reason & GEN_INTR_TXTRAFFIC)
4816 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4818 for (i = 0; i < config->tx_fifo_num; i++)
4819 tx_intr_handler(&mac_control->fifos[i]);
4821 if (reason & GEN_INTR_TXPIC)
4822 s2io_txpic_intr_handle(sp);
4825 * Reallocate the buffers from the interrupt handler itself.
4827 if (!config->napi) {
4828 for (i = 0; i < config->rx_ring_num; i++)
4829 s2io_chk_rx_buffers(sp, &mac_control->rings[i]);
4831 writeq(sp->general_int_mask, &bar0->general_int_mask);
4832 readl(&bar0->general_int_status);
4838 /* The interrupt was not raised by us */
4848 static void s2io_updt_stats(struct s2io_nic *sp)
4850 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4854 if (is_s2io_card_up(sp)) {
4855 /* Apprx 30us on a 133 MHz bus */
4856 val64 = SET_UPDT_CLICKS(10) |
4857 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4858 writeq(val64, &bar0->stat_cfg);
4861 val64 = readq(&bar0->stat_cfg);
4862 if (!(val64 & s2BIT(0)))
4866 break; /* Updt failed */
4872 * s2io_get_stats - Updates the device statistics structure.
4873 * @dev : pointer to the device structure.
4875 * This function updates the device statistics structure in the s2io_nic
4876 * structure and returns a pointer to the same.
4878 * pointer to the updated net_device_stats structure.
4881 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4883 struct s2io_nic *sp = netdev_priv(dev);
4884 struct mac_info *mac_control;
4885 struct config_param *config;
4889 mac_control = &sp->mac_control;
4890 config = &sp->config;
4892 /* Configure Stats for immediate updt */
4893 s2io_updt_stats(sp);
4895 /* Using sp->stats as a staging area, because reset (due to mtu
4896 change, for example) will clear some hardware counters */
4897 dev->stats.tx_packets +=
4898 le32_to_cpu(mac_control->stats_info->tmac_frms) -
4899 sp->stats.tx_packets;
4900 sp->stats.tx_packets =
4901 le32_to_cpu(mac_control->stats_info->tmac_frms);
4902 dev->stats.tx_errors +=
4903 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) -
4904 sp->stats.tx_errors;
4905 sp->stats.tx_errors =
4906 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4907 dev->stats.rx_errors +=
4908 le64_to_cpu(mac_control->stats_info->rmac_drop_frms) -
4909 sp->stats.rx_errors;
4910 sp->stats.rx_errors =
4911 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4912 dev->stats.multicast =
4913 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) -
4914 sp->stats.multicast;
4915 sp->stats.multicast =
4916 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4917 dev->stats.rx_length_errors =
4918 le64_to_cpu(mac_control->stats_info->rmac_long_frms) -
4919 sp->stats.rx_length_errors;
4920 sp->stats.rx_length_errors =
4921 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4923 /* collect per-ring rx_packets and rx_bytes */
4924 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
4925 for (i = 0; i < config->rx_ring_num; i++) {
4926 dev->stats.rx_packets += mac_control->rings[i].rx_packets;
4927 dev->stats.rx_bytes += mac_control->rings[i].rx_bytes;
4930 return (&dev->stats);
4934 * s2io_set_multicast - entry point for multicast address enable/disable.
4935 * @dev : pointer to the device structure
4937 * This function is a driver entry point which gets called by the kernel
4938 * whenever multicast addresses must be enabled/disabled. This also gets
4939 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4940 * determine, if multicast address must be enabled or if promiscuous mode
4941 * is to be disabled etc.
4946 static void s2io_set_multicast(struct net_device *dev)
4949 struct dev_mc_list *mclist;
4950 struct s2io_nic *sp = netdev_priv(dev);
4951 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4952 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4954 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4956 struct config_param *config = &sp->config;
4958 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4959 /* Enable all Multicast addresses */
4960 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4961 &bar0->rmac_addr_data0_mem);
4962 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4963 &bar0->rmac_addr_data1_mem);
4964 val64 = RMAC_ADDR_CMD_MEM_WE |
4965 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4966 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4967 writeq(val64, &bar0->rmac_addr_cmd_mem);
4968 /* Wait till command completes */
4969 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4970 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4974 sp->all_multi_pos = config->max_mc_addr - 1;
4975 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4976 /* Disable all Multicast addresses */
4977 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4978 &bar0->rmac_addr_data0_mem);
4979 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4980 &bar0->rmac_addr_data1_mem);
4981 val64 = RMAC_ADDR_CMD_MEM_WE |
4982 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4983 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4984 writeq(val64, &bar0->rmac_addr_cmd_mem);
4985 /* Wait till command completes */
4986 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4987 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4991 sp->all_multi_pos = 0;
4994 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4995 /* Put the NIC into promiscuous mode */
4996 add = &bar0->mac_cfg;
4997 val64 = readq(&bar0->mac_cfg);
4998 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5000 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5001 writel((u32) val64, add);
5002 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5003 writel((u32) (val64 >> 32), (add + 4));
5005 if (vlan_tag_strip != 1) {
5006 val64 = readq(&bar0->rx_pa_cfg);
5007 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5008 writeq(val64, &bar0->rx_pa_cfg);
5009 sp->vlan_strip_flag = 0;
5012 val64 = readq(&bar0->mac_cfg);
5013 sp->promisc_flg = 1;
5014 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5016 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5017 /* Remove the NIC from promiscuous mode */
5018 add = &bar0->mac_cfg;
5019 val64 = readq(&bar0->mac_cfg);
5020 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5022 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5023 writel((u32) val64, add);
5024 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5025 writel((u32) (val64 >> 32), (add + 4));
5027 if (vlan_tag_strip != 0) {
5028 val64 = readq(&bar0->rx_pa_cfg);
5029 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5030 writeq(val64, &bar0->rx_pa_cfg);
5031 sp->vlan_strip_flag = 1;
5034 val64 = readq(&bar0->mac_cfg);
5035 sp->promisc_flg = 0;
5036 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
5040 /* Update individual M_CAST address list */
5041 if ((!sp->m_cast_flg) && dev->mc_count) {
5043 (config->max_mc_addr - config->max_mac_addr)) {
5044 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5046 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5047 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5051 prev_cnt = sp->mc_addr_count;
5052 sp->mc_addr_count = dev->mc_count;
5054 /* Clear out the previous list of Mc in the H/W. */
5055 for (i = 0; i < prev_cnt; i++) {
5056 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5057 &bar0->rmac_addr_data0_mem);
5058 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5059 &bar0->rmac_addr_data1_mem);
5060 val64 = RMAC_ADDR_CMD_MEM_WE |
5061 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5062 RMAC_ADDR_CMD_MEM_OFFSET
5063 (config->mc_start_offset + i);
5064 writeq(val64, &bar0->rmac_addr_cmd_mem);
5066 /* Wait for command completes */
5067 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5068 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5070 DBG_PRINT(ERR_DBG, "%s: Adding ",
5072 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5077 /* Create the new Rx filter list and update the same in H/W. */
5078 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5079 i++, mclist = mclist->next) {
5080 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5083 for (j = 0; j < ETH_ALEN; j++) {
5084 mac_addr |= mclist->dmi_addr[j];
5088 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5089 &bar0->rmac_addr_data0_mem);
5090 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5091 &bar0->rmac_addr_data1_mem);
5092 val64 = RMAC_ADDR_CMD_MEM_WE |
5093 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5094 RMAC_ADDR_CMD_MEM_OFFSET
5095 (i + config->mc_start_offset);
5096 writeq(val64, &bar0->rmac_addr_cmd_mem);
5098 /* Wait for command completes */
5099 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5100 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5102 DBG_PRINT(ERR_DBG, "%s: Adding ",
5104 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5111 /* read from CAM unicast & multicast addresses and store it in
5112 * def_mac_addr structure
5114 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5118 struct config_param *config = &sp->config;
5120 /* store unicast & multicast mac addresses */
5121 for (offset = 0; offset < config->max_mc_addr; offset++) {
5122 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5123 /* if read fails disable the entry */
5124 if (mac_addr == FAILURE)
5125 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5126 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5130 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5131 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5134 struct config_param *config = &sp->config;
5135 /* restore unicast mac address */
5136 for (offset = 0; offset < config->max_mac_addr; offset++)
5137 do_s2io_prog_unicast(sp->dev,
5138 sp->def_mac_addr[offset].mac_addr);
5140 /* restore multicast mac address */
5141 for (offset = config->mc_start_offset;
5142 offset < config->max_mc_addr; offset++)
5143 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5146 /* add a multicast MAC address to CAM */
5147 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5151 struct config_param *config = &sp->config;
5153 for (i = 0; i < ETH_ALEN; i++) {
5155 mac_addr |= addr[i];
5157 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5160 /* check if the multicast mac already preset in CAM */
5161 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5163 tmp64 = do_s2io_read_unicast_mc(sp, i);
5164 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5167 if (tmp64 == mac_addr)
5170 if (i == config->max_mc_addr) {
5172 "CAM full no space left for multicast MAC\n");
5175 /* Update the internal structure with this new mac address */
5176 do_s2io_copy_mac_addr(sp, i, mac_addr);
5178 return (do_s2io_add_mac(sp, mac_addr, i));
5181 /* add MAC address to CAM */
5182 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5185 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5187 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5188 &bar0->rmac_addr_data0_mem);
5191 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5192 RMAC_ADDR_CMD_MEM_OFFSET(off);
5193 writeq(val64, &bar0->rmac_addr_cmd_mem);
5195 /* Wait till command completes */
5196 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5197 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5199 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5204 /* deletes a specified unicast/multicast mac entry from CAM */
5205 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5208 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5209 struct config_param *config = &sp->config;
5212 offset < config->max_mc_addr; offset++) {
5213 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5214 if (tmp64 == addr) {
5215 /* disable the entry by writing 0xffffffffffffULL */
5216 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5218 /* store the new mac list from CAM */
5219 do_s2io_store_unicast_mc(sp);
5223 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5224 (unsigned long long)addr);
5228 /* read mac entries from CAM */
5229 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5231 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5232 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5236 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5237 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5238 writeq(val64, &bar0->rmac_addr_cmd_mem);
5240 /* Wait till command completes */
5241 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5242 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5244 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5247 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5248 return (tmp64 >> 16);
5252 * s2io_set_mac_addr driver entry point
5255 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5257 struct sockaddr *addr = p;
5259 if (!is_valid_ether_addr(addr->sa_data))
5262 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5264 /* store the MAC address in CAM */
5265 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5268 * do_s2io_prog_unicast - Programs the Xframe mac address
5269 * @dev : pointer to the device structure.
5270 * @addr: a uchar pointer to the new mac address which is to be set.
5271 * Description : This procedure will program the Xframe to receive
5272 * frames with new Mac Address
5273 * Return value: SUCCESS on success and an appropriate (-)ve integer
5274 * as defined in errno.h file on failure.
5277 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5279 struct s2io_nic *sp = netdev_priv(dev);
5280 register u64 mac_addr = 0, perm_addr = 0;
5283 struct config_param *config = &sp->config;
5286 * Set the new MAC address as the new unicast filter and reflect this
5287 * change on the device address registered with the OS. It will be
5290 for (i = 0; i < ETH_ALEN; i++) {
5292 mac_addr |= addr[i];
5294 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5297 /* check if the dev_addr is different than perm_addr */
5298 if (mac_addr == perm_addr)
5301 /* check if the mac already preset in CAM */
5302 for (i = 1; i < config->max_mac_addr; i++) {
5303 tmp64 = do_s2io_read_unicast_mc(sp, i);
5304 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5307 if (tmp64 == mac_addr) {
5309 "MAC addr:0x%llx already present in CAM\n",
5310 (unsigned long long)mac_addr);
5314 if (i == config->max_mac_addr) {
5315 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5318 /* Update the internal structure with this new mac address */
5319 do_s2io_copy_mac_addr(sp, i, mac_addr);
5320 return (do_s2io_add_mac(sp, mac_addr, i));
5324 * s2io_ethtool_sset - Sets different link parameters.
5325 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5326 * @info: pointer to the structure with parameters given by ethtool to set
5329 * The function sets different link parameters provided by the user onto
5335 static int s2io_ethtool_sset(struct net_device *dev,
5336 struct ethtool_cmd *info)
5338 struct s2io_nic *sp = netdev_priv(dev);
5339 if ((info->autoneg == AUTONEG_ENABLE) ||
5340 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5343 s2io_close(sp->dev);
5351 * s2io_ethtol_gset - Return link specific information.
5352 * @sp : private member of the device structure, pointer to the
5353 * s2io_nic structure.
5354 * @info : pointer to the structure with parameters given by ethtool
5355 * to return link information.
5357 * Returns link specific information like speed, duplex etc.. to ethtool.
5359 * return 0 on success.
5362 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5364 struct s2io_nic *sp = netdev_priv(dev);
5365 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5366 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5367 info->port = PORT_FIBRE;
5369 /* info->transceiver */
5370 info->transceiver = XCVR_EXTERNAL;
5372 if (netif_carrier_ok(sp->dev)) {
5373 info->speed = 10000;
5374 info->duplex = DUPLEX_FULL;
5380 info->autoneg = AUTONEG_DISABLE;
5385 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5386 * @sp : private member of the device structure, which is a pointer to the
5387 * s2io_nic structure.
5388 * @info : pointer to the structure with parameters given by ethtool to
5389 * return driver information.
5391 * Returns driver specefic information like name, version etc.. to ethtool.
5396 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5397 struct ethtool_drvinfo *info)
5399 struct s2io_nic *sp = netdev_priv(dev);
5401 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5402 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5403 strncpy(info->fw_version, "", sizeof(info->fw_version));
5404 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5405 info->regdump_len = XENA_REG_SPACE;
5406 info->eedump_len = XENA_EEPROM_SPACE;
5410 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5411 * @sp: private member of the device structure, which is a pointer to the
5412 * s2io_nic structure.
5413 * @regs : pointer to the structure with parameters given by ethtool for
5414 * dumping the registers.
5415 * @reg_space: The input argumnet into which all the registers are dumped.
5417 * Dumps the entire register space of xFrame NIC into the user given
5423 static void s2io_ethtool_gregs(struct net_device *dev,
5424 struct ethtool_regs *regs, void *space)
5428 u8 *reg_space = (u8 *) space;
5429 struct s2io_nic *sp = netdev_priv(dev);
5431 regs->len = XENA_REG_SPACE;
5432 regs->version = sp->pdev->subsystem_device;
5434 for (i = 0; i < regs->len; i += 8) {
5435 reg = readq(sp->bar0 + i);
5436 memcpy((reg_space + i), ®, 8);
5441 * s2io_phy_id - timer function that alternates adapter LED.
5442 * @data : address of the private member of the device structure, which
5443 * is a pointer to the s2io_nic structure, provided as an u32.
5444 * Description: This is actually the timer function that alternates the
5445 * adapter LED bit of the adapter control bit to set/reset every time on
5446 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5447 * once every second.
5449 static void s2io_phy_id(unsigned long data)
5451 struct s2io_nic *sp = (struct s2io_nic *) data;
5452 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5456 subid = sp->pdev->subsystem_device;
5457 if ((sp->device_type == XFRAME_II_DEVICE) ||
5458 ((subid & 0xFF) >= 0x07)) {
5459 val64 = readq(&bar0->gpio_control);
5460 val64 ^= GPIO_CTRL_GPIO_0;
5461 writeq(val64, &bar0->gpio_control);
5463 val64 = readq(&bar0->adapter_control);
5464 val64 ^= ADAPTER_LED_ON;
5465 writeq(val64, &bar0->adapter_control);
5468 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5472 * s2io_ethtool_idnic - To physically identify the nic on the system.
5473 * @sp : private member of the device structure, which is a pointer to the
5474 * s2io_nic structure.
5475 * @id : pointer to the structure with identification parameters given by
5477 * Description: Used to physically identify the NIC on the system.
5478 * The Link LED will blink for a time specified by the user for
5480 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5481 * identification is possible only if it's link is up.
5483 * int , returns 0 on success
5486 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5488 u64 val64 = 0, last_gpio_ctrl_val;
5489 struct s2io_nic *sp = netdev_priv(dev);
5490 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5493 subid = sp->pdev->subsystem_device;
5494 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5495 if ((sp->device_type == XFRAME_I_DEVICE) &&
5496 ((subid & 0xFF) < 0x07)) {
5497 val64 = readq(&bar0->adapter_control);
5498 if (!(val64 & ADAPTER_CNTL_EN)) {
5500 "Adapter Link down, cannot blink LED\n");
5504 if (sp->id_timer.function == NULL) {
5505 init_timer(&sp->id_timer);
5506 sp->id_timer.function = s2io_phy_id;
5507 sp->id_timer.data = (unsigned long) sp;
5509 mod_timer(&sp->id_timer, jiffies);
5511 msleep_interruptible(data * HZ);
5513 msleep_interruptible(MAX_FLICKER_TIME);
5514 del_timer_sync(&sp->id_timer);
5516 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5517 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5518 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5524 static void s2io_ethtool_gringparam(struct net_device *dev,
5525 struct ethtool_ringparam *ering)
5527 struct s2io_nic *sp = netdev_priv(dev);
5528 int i,tx_desc_count=0,rx_desc_count=0;
5530 if (sp->rxd_mode == RXD_MODE_1)
5531 ering->rx_max_pending = MAX_RX_DESC_1;
5532 else if (sp->rxd_mode == RXD_MODE_3B)
5533 ering->rx_max_pending = MAX_RX_DESC_2;
5535 ering->tx_max_pending = MAX_TX_DESC;
5536 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5537 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5539 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5540 ering->tx_pending = tx_desc_count;
5542 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5543 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5545 ering->rx_pending = rx_desc_count;
5547 ering->rx_mini_max_pending = 0;
5548 ering->rx_mini_pending = 0;
5549 if(sp->rxd_mode == RXD_MODE_1)
5550 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5551 else if (sp->rxd_mode == RXD_MODE_3B)
5552 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5553 ering->rx_jumbo_pending = rx_desc_count;
5557 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5558 * @sp : private member of the device structure, which is a pointer to the
5559 * s2io_nic structure.
5560 * @ep : pointer to the structure with pause parameters given by ethtool.
5562 * Returns the Pause frame generation and reception capability of the NIC.
5566 static void s2io_ethtool_getpause_data(struct net_device *dev,
5567 struct ethtool_pauseparam *ep)
5570 struct s2io_nic *sp = netdev_priv(dev);
5571 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5573 val64 = readq(&bar0->rmac_pause_cfg);
5574 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5575 ep->tx_pause = TRUE;
5576 if (val64 & RMAC_PAUSE_RX_ENABLE)
5577 ep->rx_pause = TRUE;
5578 ep->autoneg = FALSE;
5582 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5583 * @sp : private member of the device structure, which is a pointer to the
5584 * s2io_nic structure.
5585 * @ep : pointer to the structure with pause parameters given by ethtool.
5587 * It can be used to set or reset Pause frame generation or reception
5588 * support of the NIC.
5590 * int, returns 0 on Success
5593 static int s2io_ethtool_setpause_data(struct net_device *dev,
5594 struct ethtool_pauseparam *ep)
5597 struct s2io_nic *sp = netdev_priv(dev);
5598 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5600 val64 = readq(&bar0->rmac_pause_cfg);
5602 val64 |= RMAC_PAUSE_GEN_ENABLE;
5604 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5606 val64 |= RMAC_PAUSE_RX_ENABLE;
5608 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5609 writeq(val64, &bar0->rmac_pause_cfg);
5614 * read_eeprom - reads 4 bytes of data from user given offset.
5615 * @sp : private member of the device structure, which is a pointer to the
5616 * s2io_nic structure.
5617 * @off : offset at which the data must be written
5618 * @data : Its an output parameter where the data read at the given
5621 * Will read 4 bytes of data from the user given offset and return the
5623 * NOTE: Will allow to read only part of the EEPROM visible through the
5626 * -1 on failure and 0 on success.
5629 #define S2IO_DEV_ID 5
5630 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5635 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5637 if (sp->device_type == XFRAME_I_DEVICE) {
5638 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5639 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5640 I2C_CONTROL_CNTL_START;
5641 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5643 while (exit_cnt < 5) {
5644 val64 = readq(&bar0->i2c_control);
5645 if (I2C_CONTROL_CNTL_END(val64)) {
5646 *data = I2C_CONTROL_GET_DATA(val64);
5655 if (sp->device_type == XFRAME_II_DEVICE) {
5656 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5657 SPI_CONTROL_BYTECNT(0x3) |
5658 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5659 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5660 val64 |= SPI_CONTROL_REQ;
5661 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5662 while (exit_cnt < 5) {
5663 val64 = readq(&bar0->spi_control);
5664 if (val64 & SPI_CONTROL_NACK) {
5667 } else if (val64 & SPI_CONTROL_DONE) {
5668 *data = readq(&bar0->spi_data);
5681 * write_eeprom - actually writes the relevant part of the data value.
5682 * @sp : private member of the device structure, which is a pointer to the
5683 * s2io_nic structure.
5684 * @off : offset at which the data must be written
5685 * @data : The data that is to be written
5686 * @cnt : Number of bytes of the data that are actually to be written into
5687 * the Eeprom. (max of 3)
5689 * Actually writes the relevant part of the data value into the Eeprom
5690 * through the I2C bus.
5692 * 0 on success, -1 on failure.
5695 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5697 int exit_cnt = 0, ret = -1;
5699 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5701 if (sp->device_type == XFRAME_I_DEVICE) {
5702 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5703 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5704 I2C_CONTROL_CNTL_START;
5705 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5707 while (exit_cnt < 5) {
5708 val64 = readq(&bar0->i2c_control);
5709 if (I2C_CONTROL_CNTL_END(val64)) {
5710 if (!(val64 & I2C_CONTROL_NACK))
5719 if (sp->device_type == XFRAME_II_DEVICE) {
5720 int write_cnt = (cnt == 8) ? 0 : cnt;
5721 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5723 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5724 SPI_CONTROL_BYTECNT(write_cnt) |
5725 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5726 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5727 val64 |= SPI_CONTROL_REQ;
5728 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5729 while (exit_cnt < 5) {
5730 val64 = readq(&bar0->spi_control);
5731 if (val64 & SPI_CONTROL_NACK) {
5734 } else if (val64 & SPI_CONTROL_DONE) {
5744 static void s2io_vpd_read(struct s2io_nic *nic)
5748 int i=0, cnt, fail = 0;
5749 int vpd_addr = 0x80;
5751 if (nic->device_type == XFRAME_II_DEVICE) {
5752 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5756 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5759 strcpy(nic->serial_num, "NOT AVAILABLE");
5761 vpd_data = kmalloc(256, GFP_KERNEL);
5763 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5766 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5768 for (i = 0; i < 256; i +=4 ) {
5769 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5770 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5771 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5772 for (cnt = 0; cnt <5; cnt++) {
5774 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5779 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5783 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5784 (u32 *)&vpd_data[i]);
5788 /* read serial number of adapter */
5789 for (cnt = 0; cnt < 256; cnt++) {
5790 if ((vpd_data[cnt] == 'S') &&
5791 (vpd_data[cnt+1] == 'N') &&
5792 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5793 memset(nic->serial_num, 0, VPD_STRING_LEN);
5794 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5801 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5802 memset(nic->product_name, 0, vpd_data[1]);
5803 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5806 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5810 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5811 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5812 * @eeprom : pointer to the user level structure provided by ethtool,
5813 * containing all relevant information.
5814 * @data_buf : user defined value to be written into Eeprom.
5815 * Description: Reads the values stored in the Eeprom at given offset
5816 * for a given length. Stores these values int the input argument data
5817 * buffer 'data_buf' and returns these to the caller (ethtool.)
5822 static int s2io_ethtool_geeprom(struct net_device *dev,
5823 struct ethtool_eeprom *eeprom, u8 * data_buf)
5827 struct s2io_nic *sp = netdev_priv(dev);
5829 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5831 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5832 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5834 for (i = 0; i < eeprom->len; i += 4) {
5835 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5836 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5840 memcpy((data_buf + i), &valid, 4);
5846 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5847 * @sp : private member of the device structure, which is a pointer to the
5848 * s2io_nic structure.
5849 * @eeprom : pointer to the user level structure provided by ethtool,
5850 * containing all relevant information.
5851 * @data_buf ; user defined value to be written into Eeprom.
5853 * Tries to write the user provided value in the Eeprom, at the offset
5854 * given by the user.
5856 * 0 on success, -EFAULT on failure.
5859 static int s2io_ethtool_seeprom(struct net_device *dev,
5860 struct ethtool_eeprom *eeprom,
5863 int len = eeprom->len, cnt = 0;
5864 u64 valid = 0, data;
5865 struct s2io_nic *sp = netdev_priv(dev);
5867 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5869 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5870 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5876 data = (u32) data_buf[cnt] & 0x000000FF;
5878 valid = (u32) (data << 24);
5882 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5884 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5886 "write into the specified offset\n");
5897 * s2io_register_test - reads and writes into all clock domains.
5898 * @sp : private member of the device structure, which is a pointer to the
5899 * s2io_nic structure.
5900 * @data : variable that returns the result of each of the test conducted b
5903 * Read and write into all clock domains. The NIC has 3 clock domains,
5904 * see that registers in all the three regions are accessible.
5909 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5911 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5912 u64 val64 = 0, exp_val;
5915 val64 = readq(&bar0->pif_rd_swapper_fb);
5916 if (val64 != 0x123456789abcdefULL) {
5918 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5921 val64 = readq(&bar0->rmac_pause_cfg);
5922 if (val64 != 0xc000ffff00000000ULL) {
5924 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5927 val64 = readq(&bar0->rx_queue_cfg);
5928 if (sp->device_type == XFRAME_II_DEVICE)
5929 exp_val = 0x0404040404040404ULL;
5931 exp_val = 0x0808080808080808ULL;
5932 if (val64 != exp_val) {
5934 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5937 val64 = readq(&bar0->xgxs_efifo_cfg);
5938 if (val64 != 0x000000001923141EULL) {
5940 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5943 val64 = 0x5A5A5A5A5A5A5A5AULL;
5944 writeq(val64, &bar0->xmsi_data);
5945 val64 = readq(&bar0->xmsi_data);
5946 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5948 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5951 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5952 writeq(val64, &bar0->xmsi_data);
5953 val64 = readq(&bar0->xmsi_data);
5954 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5956 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5964 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5965 * @sp : private member of the device structure, which is a pointer to the
5966 * s2io_nic structure.
5967 * @data:variable that returns the result of each of the test conducted by
5970 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5976 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5979 u64 ret_data, org_4F0, org_7F0;
5980 u8 saved_4F0 = 0, saved_7F0 = 0;
5981 struct net_device *dev = sp->dev;
5983 /* Test Write Error at offset 0 */
5984 /* Note that SPI interface allows write access to all areas
5985 * of EEPROM. Hence doing all negative testing only for Xframe I.
5987 if (sp->device_type == XFRAME_I_DEVICE)
5988 if (!write_eeprom(sp, 0, 0, 3))
5991 /* Save current values at offsets 0x4F0 and 0x7F0 */
5992 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5994 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5997 /* Test Write at offset 4f0 */
5998 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6000 if (read_eeprom(sp, 0x4F0, &ret_data))
6003 if (ret_data != 0x012345) {
6004 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6005 "Data written %llx Data read %llx\n",
6006 dev->name, (unsigned long long)0x12345,
6007 (unsigned long long)ret_data);
6011 /* Reset the EEPROM data go FFFF */
6012 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6014 /* Test Write Request Error at offset 0x7c */
6015 if (sp->device_type == XFRAME_I_DEVICE)
6016 if (!write_eeprom(sp, 0x07C, 0, 3))
6019 /* Test Write Request at offset 0x7f0 */
6020 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6022 if (read_eeprom(sp, 0x7F0, &ret_data))
6025 if (ret_data != 0x012345) {
6026 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6027 "Data written %llx Data read %llx\n",
6028 dev->name, (unsigned long long)0x12345,
6029 (unsigned long long)ret_data);
6033 /* Reset the EEPROM data go FFFF */
6034 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6036 if (sp->device_type == XFRAME_I_DEVICE) {
6037 /* Test Write Error at offset 0x80 */
6038 if (!write_eeprom(sp, 0x080, 0, 3))
6041 /* Test Write Error at offset 0xfc */
6042 if (!write_eeprom(sp, 0x0FC, 0, 3))
6045 /* Test Write Error at offset 0x100 */
6046 if (!write_eeprom(sp, 0x100, 0, 3))
6049 /* Test Write Error at offset 4ec */
6050 if (!write_eeprom(sp, 0x4EC, 0, 3))
6054 /* Restore values at offsets 0x4F0 and 0x7F0 */
6056 write_eeprom(sp, 0x4F0, org_4F0, 3);
6058 write_eeprom(sp, 0x7F0, org_7F0, 3);
6065 * s2io_bist_test - invokes the MemBist test of the card .
6066 * @sp : private member of the device structure, which is a pointer to the
6067 * s2io_nic structure.
6068 * @data:variable that returns the result of each of the test conducted by
6071 * This invokes the MemBist test of the card. We give around
6072 * 2 secs time for the Test to complete. If it's still not complete
6073 * within this peiod, we consider that the test failed.
6075 * 0 on success and -1 on failure.
6078 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
6081 int cnt = 0, ret = -1;
6083 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6084 bist |= PCI_BIST_START;
6085 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6088 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6089 if (!(bist & PCI_BIST_START)) {
6090 *data = (bist & PCI_BIST_CODE_MASK);
6102 * s2io-link_test - verifies the link state of the nic
6103 * @sp ; private member of the device structure, which is a pointer to the
6104 * s2io_nic structure.
6105 * @data: variable that returns the result of each of the test conducted by
6108 * The function verifies the link state of the NIC and updates the input
6109 * argument 'data' appropriately.
6114 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
6116 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6119 val64 = readq(&bar0->adapter_status);
6120 if(!(LINK_IS_UP(val64)))
6129 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6130 * @sp - private member of the device structure, which is a pointer to the
6131 * s2io_nic structure.
6132 * @data - variable that returns the result of each of the test
6133 * conducted by the driver.
6135 * This is one of the offline test that tests the read and write
6136 * access to the RldRam chip on the NIC.
6141 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
6143 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6145 int cnt, iteration = 0, test_fail = 0;
6147 val64 = readq(&bar0->adapter_control);
6148 val64 &= ~ADAPTER_ECC_EN;
6149 writeq(val64, &bar0->adapter_control);
6151 val64 = readq(&bar0->mc_rldram_test_ctrl);
6152 val64 |= MC_RLDRAM_TEST_MODE;
6153 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6155 val64 = readq(&bar0->mc_rldram_mrs);
6156 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6157 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6159 val64 |= MC_RLDRAM_MRS_ENABLE;
6160 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6162 while (iteration < 2) {
6163 val64 = 0x55555555aaaa0000ULL;
6164 if (iteration == 1) {
6165 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6167 writeq(val64, &bar0->mc_rldram_test_d0);
6169 val64 = 0xaaaa5a5555550000ULL;
6170 if (iteration == 1) {
6171 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6173 writeq(val64, &bar0->mc_rldram_test_d1);
6175 val64 = 0x55aaaaaaaa5a0000ULL;
6176 if (iteration == 1) {
6177 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6179 writeq(val64, &bar0->mc_rldram_test_d2);
6181 val64 = (u64) (0x0000003ffffe0100ULL);
6182 writeq(val64, &bar0->mc_rldram_test_add);
6184 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6186 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6188 for (cnt = 0; cnt < 5; cnt++) {
6189 val64 = readq(&bar0->mc_rldram_test_ctrl);
6190 if (val64 & MC_RLDRAM_TEST_DONE)
6198 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6199 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6201 for (cnt = 0; cnt < 5; cnt++) {
6202 val64 = readq(&bar0->mc_rldram_test_ctrl);
6203 if (val64 & MC_RLDRAM_TEST_DONE)
6211 val64 = readq(&bar0->mc_rldram_test_ctrl);
6212 if (!(val64 & MC_RLDRAM_TEST_PASS))
6220 /* Bring the adapter out of test mode */
6221 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6227 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6228 * @sp : private member of the device structure, which is a pointer to the
6229 * s2io_nic structure.
6230 * @ethtest : pointer to a ethtool command specific structure that will be
6231 * returned to the user.
6232 * @data : variable that returns the result of each of the test
6233 * conducted by the driver.
6235 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6236 * the health of the card.
6241 static void s2io_ethtool_test(struct net_device *dev,
6242 struct ethtool_test *ethtest,
6245 struct s2io_nic *sp = netdev_priv(dev);
6246 int orig_state = netif_running(sp->dev);
6248 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6249 /* Offline Tests. */
6251 s2io_close(sp->dev);
6253 if (s2io_register_test(sp, &data[0]))
6254 ethtest->flags |= ETH_TEST_FL_FAILED;
6258 if (s2io_rldram_test(sp, &data[3]))
6259 ethtest->flags |= ETH_TEST_FL_FAILED;
6263 if (s2io_eeprom_test(sp, &data[1]))
6264 ethtest->flags |= ETH_TEST_FL_FAILED;
6266 if (s2io_bist_test(sp, &data[4]))
6267 ethtest->flags |= ETH_TEST_FL_FAILED;
6277 "%s: is not up, cannot run test\n",
6286 if (s2io_link_test(sp, &data[2]))
6287 ethtest->flags |= ETH_TEST_FL_FAILED;
6296 static void s2io_get_ethtool_stats(struct net_device *dev,
6297 struct ethtool_stats *estats,
6301 struct s2io_nic *sp = netdev_priv(dev);
6302 struct stat_block *stat_info = sp->mac_control.stats_info;
6304 s2io_updt_stats(sp);
6306 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6307 le32_to_cpu(stat_info->tmac_frms);
6309 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6310 le32_to_cpu(stat_info->tmac_data_octets);
6311 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
6313 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6314 le32_to_cpu(stat_info->tmac_mcst_frms);
6316 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6317 le32_to_cpu(stat_info->tmac_bcst_frms);
6318 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
6320 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6321 le32_to_cpu(stat_info->tmac_ttl_octets);
6323 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6324 le32_to_cpu(stat_info->tmac_ucst_frms);
6326 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6327 le32_to_cpu(stat_info->tmac_nucst_frms);
6329 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6330 le32_to_cpu(stat_info->tmac_any_err_frms);
6331 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
6332 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
6334 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6335 le32_to_cpu(stat_info->tmac_vld_ip);
6337 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6338 le32_to_cpu(stat_info->tmac_drop_ip);
6340 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6341 le32_to_cpu(stat_info->tmac_icmp);
6343 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6344 le32_to_cpu(stat_info->tmac_rst_tcp);
6345 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
6346 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6347 le32_to_cpu(stat_info->tmac_udp);
6349 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6350 le32_to_cpu(stat_info->rmac_vld_frms);
6352 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6353 le32_to_cpu(stat_info->rmac_data_octets);
6354 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6355 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
6357 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6358 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6360 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6361 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
6362 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
6363 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
6364 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6365 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
6366 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6368 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6369 le32_to_cpu(stat_info->rmac_ttl_octets);
6371 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6372 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6374 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6375 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
6377 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6378 le32_to_cpu(stat_info->rmac_discarded_frms);
6380 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6381 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6382 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6383 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
6385 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6386 le32_to_cpu(stat_info->rmac_usized_frms);
6388 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6389 le32_to_cpu(stat_info->rmac_osized_frms);
6391 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6392 le32_to_cpu(stat_info->rmac_frag_frms);
6394 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6395 le32_to_cpu(stat_info->rmac_jabber_frms);
6396 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6397 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6398 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6399 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6400 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6401 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6403 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
6404 le32_to_cpu(stat_info->rmac_ip);
6405 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6406 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
6408 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
6409 le32_to_cpu(stat_info->rmac_drop_ip);
6411 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
6412 le32_to_cpu(stat_info->rmac_icmp);
6413 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
6415 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
6416 le32_to_cpu(stat_info->rmac_udp);
6418 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6419 le32_to_cpu(stat_info->rmac_err_drp_udp);
6420 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6421 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6422 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6423 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6424 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6425 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6426 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6427 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6428 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6429 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6430 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6431 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6432 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6433 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6434 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6435 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6436 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
6438 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6439 le32_to_cpu(stat_info->rmac_pause_cnt);
6440 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6441 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
6443 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6444 le32_to_cpu(stat_info->rmac_accepted_ip);
6445 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
6446 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6447 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6448 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6449 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6450 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6451 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6452 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6453 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6454 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6455 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6456 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6457 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6458 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6459 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6460 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6461 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6462 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6463 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
6465 /* Enhanced statistics exist only for Hercules */
6466 if(sp->device_type == XFRAME_II_DEVICE) {
6468 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6470 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6472 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6473 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6474 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6475 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6476 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6477 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6478 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6479 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6480 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6481 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6482 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6483 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6484 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6485 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6489 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6490 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
6491 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6492 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6493 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6494 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
6495 for (k = 0; k < MAX_RX_RINGS; k++)
6496 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
6497 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6498 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6499 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6500 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6501 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6502 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6503 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6504 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6505 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6506 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6507 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6508 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
6509 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6510 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6511 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6512 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
6513 if (stat_info->sw_stat.num_aggregations) {
6514 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6517 * Since 64-bit divide does not work on all platforms,
6518 * do repeated subtraction.
6520 while (tmp >= stat_info->sw_stat.num_aggregations) {
6521 tmp -= stat_info->sw_stat.num_aggregations;
6524 tmp_stats[i++] = count;
6528 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
6529 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
6530 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
6531 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6532 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6533 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6534 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6535 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6536 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6538 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6539 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6540 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6541 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6542 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6544 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6545 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6546 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6547 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6548 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6549 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6550 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6551 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6552 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
6553 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6554 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6555 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6556 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6557 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6558 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6559 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6560 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6561 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6562 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6563 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6564 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6565 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6566 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6567 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6568 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6569 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
6572 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6574 return (XENA_REG_SPACE);
6578 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
6580 struct s2io_nic *sp = netdev_priv(dev);
6582 return (sp->rx_csum);
6585 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6587 struct s2io_nic *sp = netdev_priv(dev);
6597 static int s2io_get_eeprom_len(struct net_device *dev)
6599 return (XENA_EEPROM_SPACE);
6602 static int s2io_get_sset_count(struct net_device *dev, int sset)
6604 struct s2io_nic *sp = netdev_priv(dev);
6608 return S2IO_TEST_LEN;
6610 switch(sp->device_type) {
6611 case XFRAME_I_DEVICE:
6612 return XFRAME_I_STAT_LEN;
6613 case XFRAME_II_DEVICE:
6614 return XFRAME_II_STAT_LEN;
6623 static void s2io_ethtool_get_strings(struct net_device *dev,
6624 u32 stringset, u8 * data)
6627 struct s2io_nic *sp = netdev_priv(dev);
6629 switch (stringset) {
6631 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6634 stat_size = sizeof(ethtool_xena_stats_keys);
6635 memcpy(data, ðtool_xena_stats_keys,stat_size);
6636 if(sp->device_type == XFRAME_II_DEVICE) {
6637 memcpy(data + stat_size,
6638 ðtool_enhanced_stats_keys,
6639 sizeof(ethtool_enhanced_stats_keys));
6640 stat_size += sizeof(ethtool_enhanced_stats_keys);
6643 memcpy(data + stat_size, ðtool_driver_stats_keys,
6644 sizeof(ethtool_driver_stats_keys));
6648 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6651 dev->features |= NETIF_F_IP_CSUM;
6653 dev->features &= ~NETIF_F_IP_CSUM;
6658 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6660 return (dev->features & NETIF_F_TSO) != 0;
6662 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6665 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6667 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6672 static const struct ethtool_ops netdev_ethtool_ops = {
6673 .get_settings = s2io_ethtool_gset,
6674 .set_settings = s2io_ethtool_sset,
6675 .get_drvinfo = s2io_ethtool_gdrvinfo,
6676 .get_regs_len = s2io_ethtool_get_regs_len,
6677 .get_regs = s2io_ethtool_gregs,
6678 .get_link = ethtool_op_get_link,
6679 .get_eeprom_len = s2io_get_eeprom_len,
6680 .get_eeprom = s2io_ethtool_geeprom,
6681 .set_eeprom = s2io_ethtool_seeprom,
6682 .get_ringparam = s2io_ethtool_gringparam,
6683 .get_pauseparam = s2io_ethtool_getpause_data,
6684 .set_pauseparam = s2io_ethtool_setpause_data,
6685 .get_rx_csum = s2io_ethtool_get_rx_csum,
6686 .set_rx_csum = s2io_ethtool_set_rx_csum,
6687 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6688 .set_sg = ethtool_op_set_sg,
6689 .get_tso = s2io_ethtool_op_get_tso,
6690 .set_tso = s2io_ethtool_op_set_tso,
6691 .set_ufo = ethtool_op_set_ufo,
6692 .self_test = s2io_ethtool_test,
6693 .get_strings = s2io_ethtool_get_strings,
6694 .phys_id = s2io_ethtool_idnic,
6695 .get_ethtool_stats = s2io_get_ethtool_stats,
6696 .get_sset_count = s2io_get_sset_count,
6700 * s2io_ioctl - Entry point for the Ioctl
6701 * @dev : Device pointer.
6702 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6703 * a proprietary structure used to pass information to the driver.
6704 * @cmd : This is used to distinguish between the different commands that
6705 * can be passed to the IOCTL functions.
6707 * Currently there are no special functionality supported in IOCTL, hence
6708 * function always return EOPNOTSUPPORTED
6711 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6717 * s2io_change_mtu - entry point to change MTU size for the device.
6718 * @dev : device pointer.
6719 * @new_mtu : the new MTU size for the device.
6720 * Description: A driver entry point to change MTU size for the device.
6721 * Before changing the MTU the device must be stopped.
6723 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6727 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6729 struct s2io_nic *sp = netdev_priv(dev);
6732 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6733 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6739 if (netif_running(dev)) {
6740 s2io_stop_all_tx_queue(sp);
6742 ret = s2io_card_up(sp);
6744 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6748 s2io_wake_all_tx_queue(sp);
6749 } else { /* Device is down */
6750 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6751 u64 val64 = new_mtu;
6753 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6760 * s2io_set_link - Set the LInk status
6761 * @data: long pointer to device private structue
6762 * Description: Sets the link status for the adapter
6765 static void s2io_set_link(struct work_struct *work)
6767 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6768 struct net_device *dev = nic->dev;
6769 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6775 if (!netif_running(dev))
6778 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6779 /* The card is being reset, no point doing anything */
6783 subid = nic->pdev->subsystem_device;
6784 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6786 * Allow a small delay for the NICs self initiated
6787 * cleanup to complete.
6792 val64 = readq(&bar0->adapter_status);
6793 if (LINK_IS_UP(val64)) {
6794 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6795 if (verify_xena_quiescence(nic)) {
6796 val64 = readq(&bar0->adapter_control);
6797 val64 |= ADAPTER_CNTL_EN;
6798 writeq(val64, &bar0->adapter_control);
6799 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6800 nic->device_type, subid)) {
6801 val64 = readq(&bar0->gpio_control);
6802 val64 |= GPIO_CTRL_GPIO_0;
6803 writeq(val64, &bar0->gpio_control);
6804 val64 = readq(&bar0->gpio_control);
6806 val64 |= ADAPTER_LED_ON;
6807 writeq(val64, &bar0->adapter_control);
6809 nic->device_enabled_once = TRUE;
6811 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6812 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6813 s2io_stop_all_tx_queue(nic);
6816 val64 = readq(&bar0->adapter_control);
6817 val64 |= ADAPTER_LED_ON;
6818 writeq(val64, &bar0->adapter_control);
6819 s2io_link(nic, LINK_UP);
6821 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6823 val64 = readq(&bar0->gpio_control);
6824 val64 &= ~GPIO_CTRL_GPIO_0;
6825 writeq(val64, &bar0->gpio_control);
6826 val64 = readq(&bar0->gpio_control);
6829 val64 = readq(&bar0->adapter_control);
6830 val64 = val64 &(~ADAPTER_LED_ON);
6831 writeq(val64, &bar0->adapter_control);
6832 s2io_link(nic, LINK_DOWN);
6834 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6840 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6842 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6843 u64 *temp2, int size)
6845 struct net_device *dev = sp->dev;
6846 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6848 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6849 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6852 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6854 * As Rx frame are not going to be processed,
6855 * using same mapped address for the Rxd
6858 rxdp1->Buffer0_ptr = *temp0;
6860 *skb = dev_alloc_skb(size);
6862 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6863 DBG_PRINT(INFO_DBG, "memory to allocate ");
6864 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6865 sp->mac_control.stats_info->sw_stat. \
6866 mem_alloc_fail_cnt++;
6869 sp->mac_control.stats_info->sw_stat.mem_allocated
6870 += (*skb)->truesize;
6871 /* storing the mapped addr in a temp variable
6872 * such it will be used for next rxd whose
6873 * Host Control is NULL
6875 rxdp1->Buffer0_ptr = *temp0 =
6876 pci_map_single( sp->pdev, (*skb)->data,
6877 size - NET_IP_ALIGN,
6878 PCI_DMA_FROMDEVICE);
6879 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6880 goto memalloc_failed;
6881 rxdp->Host_Control = (unsigned long) (*skb);
6883 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6884 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6885 /* Two buffer Mode */
6887 rxdp3->Buffer2_ptr = *temp2;
6888 rxdp3->Buffer0_ptr = *temp0;
6889 rxdp3->Buffer1_ptr = *temp1;
6891 *skb = dev_alloc_skb(size);
6893 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6894 DBG_PRINT(INFO_DBG, "memory to allocate ");
6895 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6896 sp->mac_control.stats_info->sw_stat. \
6897 mem_alloc_fail_cnt++;
6900 sp->mac_control.stats_info->sw_stat.mem_allocated
6901 += (*skb)->truesize;
6902 rxdp3->Buffer2_ptr = *temp2 =
6903 pci_map_single(sp->pdev, (*skb)->data,
6905 PCI_DMA_FROMDEVICE);
6906 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6907 goto memalloc_failed;
6908 rxdp3->Buffer0_ptr = *temp0 =
6909 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6910 PCI_DMA_FROMDEVICE);
6911 if (pci_dma_mapping_error(sp->pdev,
6912 rxdp3->Buffer0_ptr)) {
6913 pci_unmap_single (sp->pdev,
6914 (dma_addr_t)rxdp3->Buffer2_ptr,
6915 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6916 goto memalloc_failed;
6918 rxdp->Host_Control = (unsigned long) (*skb);
6920 /* Buffer-1 will be dummy buffer not used */
6921 rxdp3->Buffer1_ptr = *temp1 =
6922 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6923 PCI_DMA_FROMDEVICE);
6924 if (pci_dma_mapping_error(sp->pdev,
6925 rxdp3->Buffer1_ptr)) {
6926 pci_unmap_single (sp->pdev,
6927 (dma_addr_t)rxdp3->Buffer0_ptr,
6928 BUF0_LEN, PCI_DMA_FROMDEVICE);
6929 pci_unmap_single (sp->pdev,
6930 (dma_addr_t)rxdp3->Buffer2_ptr,
6931 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6932 goto memalloc_failed;
6938 stats->pci_map_fail_cnt++;
6939 stats->mem_freed += (*skb)->truesize;
6940 dev_kfree_skb(*skb);
6944 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6947 struct net_device *dev = sp->dev;
6948 if (sp->rxd_mode == RXD_MODE_1) {
6949 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6950 } else if (sp->rxd_mode == RXD_MODE_3B) {
6951 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6952 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6953 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6957 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6959 int i, j, k, blk_cnt = 0, size;
6960 struct mac_info * mac_control = &sp->mac_control;
6961 struct config_param *config = &sp->config;
6962 struct net_device *dev = sp->dev;
6963 struct RxD_t *rxdp = NULL;
6964 struct sk_buff *skb = NULL;
6965 struct buffAdd *ba = NULL;
6966 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6968 /* Calculate the size based on ring mode */
6969 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6970 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6971 if (sp->rxd_mode == RXD_MODE_1)
6972 size += NET_IP_ALIGN;
6973 else if (sp->rxd_mode == RXD_MODE_3B)
6974 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6976 for (i = 0; i < config->rx_ring_num; i++) {
6977 blk_cnt = config->rx_cfg[i].num_rxd /
6978 (rxd_count[sp->rxd_mode] +1);
6980 for (j = 0; j < blk_cnt; j++) {
6981 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6982 rxdp = mac_control->rings[i].
6983 rx_blocks[j].rxds[k].virt_addr;
6984 if(sp->rxd_mode == RXD_MODE_3B)
6985 ba = &mac_control->rings[i].ba[j][k];
6986 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6987 &skb,(u64 *)&temp0_64,
6994 set_rxd_buffer_size(sp, rxdp, size);
6996 /* flip the Ownership bit to Hardware */
6997 rxdp->Control_1 |= RXD_OWN_XENA;
7005 static int s2io_add_isr(struct s2io_nic * sp)
7008 struct net_device *dev = sp->dev;
7011 if (sp->config.intr_type == MSI_X)
7012 ret = s2io_enable_msi_x(sp);
7014 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7015 sp->config.intr_type = INTA;
7018 /* Store the values of the MSIX table in the struct s2io_nic structure */
7019 store_xmsi_data(sp);
7021 /* After proper initialization of H/W, register ISR */
7022 if (sp->config.intr_type == MSI_X) {
7023 int i, msix_rx_cnt = 0;
7025 for (i = 0; i < sp->num_entries; i++) {
7026 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7027 if (sp->s2io_entries[i].type ==
7029 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7031 err = request_irq(sp->entries[i].vector,
7032 s2io_msix_ring_handle, 0,
7034 sp->s2io_entries[i].arg);
7035 } else if (sp->s2io_entries[i].type ==
7037 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7039 err = request_irq(sp->entries[i].vector,
7040 s2io_msix_fifo_handle, 0,
7042 sp->s2io_entries[i].arg);
7045 /* if either data or addr is zero print it. */
7046 if (!(sp->msix_info[i].addr &&
7047 sp->msix_info[i].data)) {
7049 "%s @Addr:0x%llx Data:0x%llx\n",
7051 (unsigned long long)
7052 sp->msix_info[i].addr,
7053 (unsigned long long)
7054 ntohl(sp->msix_info[i].data));
7058 remove_msix_isr(sp);
7061 "%s:MSI-X-%d registration "
7062 "failed\n", dev->name, i);
7065 "%s: Defaulting to INTA\n",
7067 sp->config.intr_type = INTA;
7070 sp->s2io_entries[i].in_use =
7071 MSIX_REGISTERED_SUCCESS;
7075 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
7077 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
7078 " through alarm vector\n");
7081 if (sp->config.intr_type == INTA) {
7082 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7085 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7092 static void s2io_rem_isr(struct s2io_nic * sp)
7094 if (sp->config.intr_type == MSI_X)
7095 remove_msix_isr(sp);
7097 remove_inta_isr(sp);
7100 static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
7103 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7104 register u64 val64 = 0;
7105 struct config_param *config;
7106 config = &sp->config;
7108 if (!is_s2io_card_up(sp))
7111 del_timer_sync(&sp->alarm_timer);
7112 /* If s2io_set_link task is executing, wait till it completes. */
7113 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
7116 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7119 if (sp->config.napi) {
7121 if (config->intr_type == MSI_X) {
7122 for (; off < sp->config.rx_ring_num; off++)
7123 napi_disable(&sp->mac_control.rings[off].napi);
7126 napi_disable(&sp->napi);
7129 /* disable Tx and Rx traffic on the NIC */
7135 /* stop the tx queue, indicate link down */
7136 s2io_link(sp, LINK_DOWN);
7138 /* Check if the device is Quiescent and then Reset the NIC */
7140 /* As per the HW requirement we need to replenish the
7141 * receive buffer to avoid the ring bump. Since there is
7142 * no intention of processing the Rx frame at this pointwe are
7143 * just settting the ownership bit of rxd in Each Rx
7144 * ring to HW and set the appropriate buffer size
7145 * based on the ring mode
7147 rxd_owner_bit_reset(sp);
7149 val64 = readq(&bar0->adapter_status);
7150 if (verify_xena_quiescence(sp)) {
7151 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
7159 "s2io_close:Device not Quiescent ");
7160 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7161 (unsigned long long) val64);
7168 /* Free all Tx buffers */
7169 free_tx_buffers(sp);
7171 /* Free all Rx buffers */
7172 free_rx_buffers(sp);
7174 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7177 static void s2io_card_down(struct s2io_nic * sp)
7179 do_s2io_card_down(sp, 1);
7182 static int s2io_card_up(struct s2io_nic * sp)
7185 struct mac_info *mac_control;
7186 struct config_param *config;
7187 struct net_device *dev = (struct net_device *) sp->dev;
7190 /* Initialize the H/W I/O registers */
7193 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7201 * Initializing the Rx buffers. For now we are considering only 1
7202 * Rx ring and initializing buffers into 30 Rx blocks
7204 mac_control = &sp->mac_control;
7205 config = &sp->config;
7207 for (i = 0; i < config->rx_ring_num; i++) {
7208 mac_control->rings[i].mtu = dev->mtu;
7209 ret = fill_rx_buffers(sp, &mac_control->rings[i], 1);
7211 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7214 free_rx_buffers(sp);
7217 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7218 mac_control->rings[i].rx_bufs_left);
7221 /* Initialise napi */
7223 if (config->intr_type == MSI_X) {
7224 for (i = 0; i < sp->config.rx_ring_num; i++)
7225 napi_enable(&sp->mac_control.rings[i].napi);
7227 napi_enable(&sp->napi);
7231 /* Maintain the state prior to the open */
7232 if (sp->promisc_flg)
7233 sp->promisc_flg = 0;
7234 if (sp->m_cast_flg) {
7236 sp->all_multi_pos= 0;
7239 /* Setting its receive mode */
7240 s2io_set_multicast(dev);
7243 /* Initialize max aggregatable pkts per session based on MTU */
7244 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7245 /* Check if we can use(if specified) user provided value */
7246 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7247 sp->lro_max_aggr_per_sess = lro_max_pkts;
7250 /* Enable Rx Traffic and interrupts on the NIC */
7251 if (start_nic(sp)) {
7252 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7254 free_rx_buffers(sp);
7258 /* Add interrupt service routine */
7259 if (s2io_add_isr(sp) != 0) {
7260 if (sp->config.intr_type == MSI_X)
7263 free_rx_buffers(sp);
7267 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7269 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7271 /* Enable select interrupts */
7272 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7273 if (sp->config.intr_type != INTA) {
7274 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7275 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7277 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7278 interruptible |= TX_PIC_INTR;
7279 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7286 * s2io_restart_nic - Resets the NIC.
7287 * @data : long pointer to the device private structure
7289 * This function is scheduled to be run by the s2io_tx_watchdog
7290 * function after 0.5 secs to reset the NIC. The idea is to reduce
7291 * the run time of the watch dog routine which is run holding a
7295 static void s2io_restart_nic(struct work_struct *work)
7297 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7298 struct net_device *dev = sp->dev;
7302 if (!netif_running(dev))
7306 if (s2io_card_up(sp)) {
7307 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7310 s2io_wake_all_tx_queue(sp);
7311 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7318 * s2io_tx_watchdog - Watchdog for transmit side.
7319 * @dev : Pointer to net device structure
7321 * This function is triggered if the Tx Queue is stopped
7322 * for a pre-defined amount of time when the Interface is still up.
7323 * If the Interface is jammed in such a situation, the hardware is
7324 * reset (by s2io_close) and restarted again (by s2io_open) to
7325 * overcome any problem that might have been caused in the hardware.
7330 static void s2io_tx_watchdog(struct net_device *dev)
7332 struct s2io_nic *sp = netdev_priv(dev);
7334 if (netif_carrier_ok(dev)) {
7335 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
7336 schedule_work(&sp->rst_timer_task);
7337 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
7342 * rx_osm_handler - To perform some OS related operations on SKB.
7343 * @sp: private member of the device structure,pointer to s2io_nic structure.
7344 * @skb : the socket buffer pointer.
7345 * @len : length of the packet
7346 * @cksum : FCS checksum of the frame.
7347 * @ring_no : the ring from which this RxD was extracted.
7349 * This function is called by the Rx interrupt serivce routine to perform
7350 * some OS related operations on the SKB before passing it to the upper
7351 * layers. It mainly checks if the checksum is OK, if so adds it to the
7352 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7353 * to the upper layer. If the checksum is wrong, it increments the Rx
7354 * packet error count, frees the SKB and returns error.
7356 * SUCCESS on success and -1 on failure.
7358 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7360 struct s2io_nic *sp = ring_data->nic;
7361 struct net_device *dev = (struct net_device *) ring_data->dev;
7362 struct sk_buff *skb = (struct sk_buff *)
7363 ((unsigned long) rxdp->Host_Control);
7364 int ring_no = ring_data->ring_no;
7365 u16 l3_csum, l4_csum;
7366 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7367 struct lro *uninitialized_var(lro);
7373 /* Check for parity error */
7375 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7377 err_mask = err >> 48;
7380 sp->mac_control.stats_info->sw_stat.
7381 rx_parity_err_cnt++;
7385 sp->mac_control.stats_info->sw_stat.
7390 sp->mac_control.stats_info->sw_stat.
7391 rx_parity_abort_cnt++;
7395 sp->mac_control.stats_info->sw_stat.
7400 sp->mac_control.stats_info->sw_stat.
7405 sp->mac_control.stats_info->sw_stat.
7410 sp->mac_control.stats_info->sw_stat.
7411 rx_buf_size_err_cnt++;
7415 sp->mac_control.stats_info->sw_stat.
7416 rx_rxd_corrupt_cnt++;
7420 sp->mac_control.stats_info->sw_stat.
7425 * Drop the packet if bad transfer code. Exception being
7426 * 0x5, which could be due to unsupported IPv6 extension header.
7427 * In this case, we let stack handle the packet.
7428 * Note that in this case, since checksum will be incorrect,
7429 * stack will validate the same.
7431 if (err_mask != 0x5) {
7432 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7433 dev->name, err_mask);
7434 dev->stats.rx_crc_errors++;
7435 sp->mac_control.stats_info->sw_stat.mem_freed
7438 ring_data->rx_bufs_left -= 1;
7439 rxdp->Host_Control = 0;
7444 /* Updating statistics */
7445 ring_data->rx_packets++;
7446 rxdp->Host_Control = 0;
7447 if (sp->rxd_mode == RXD_MODE_1) {
7448 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7450 ring_data->rx_bytes += len;
7453 } else if (sp->rxd_mode == RXD_MODE_3B) {
7454 int get_block = ring_data->rx_curr_get_info.block_index;
7455 int get_off = ring_data->rx_curr_get_info.offset;
7456 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7457 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7458 unsigned char *buff = skb_push(skb, buf0_len);
7460 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7461 ring_data->rx_bytes += buf0_len + buf2_len;
7462 memcpy(buff, ba->ba_0, buf0_len);
7463 skb_put(skb, buf2_len);
7466 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
7467 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7469 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7470 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7471 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7473 * NIC verifies if the Checksum of the received
7474 * frame is Ok or not and accordingly returns
7475 * a flag in the RxD.
7477 skb->ip_summed = CHECKSUM_UNNECESSARY;
7478 if (ring_data->lro) {
7483 ret = s2io_club_tcp_session(ring_data,
7484 skb->data, &tcp, &tcp_len, &lro,
7487 case 3: /* Begin anew */
7490 case 1: /* Aggregate */
7492 lro_append_pkt(sp, lro,
7496 case 4: /* Flush session */
7498 lro_append_pkt(sp, lro,
7500 queue_rx_frame(lro->parent,
7502 clear_lro_session(lro);
7503 sp->mac_control.stats_info->
7504 sw_stat.flush_max_pkts++;
7507 case 2: /* Flush both */
7508 lro->parent->data_len =
7510 sp->mac_control.stats_info->
7511 sw_stat.sending_both++;
7512 queue_rx_frame(lro->parent,
7514 clear_lro_session(lro);
7516 case 0: /* sessions exceeded */
7517 case -1: /* non-TCP or not
7521 * First pkt in session not
7522 * L3/L4 aggregatable
7527 "%s: Samadhana!!\n",
7534 * Packet with erroneous checksum, let the
7535 * upper layers deal with it.
7537 skb->ip_summed = CHECKSUM_NONE;
7540 skb->ip_summed = CHECKSUM_NONE;
7542 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7544 skb_record_rx_queue(skb, ring_no);
7545 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7547 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7552 * s2io_link - stops/starts the Tx queue.
7553 * @sp : private member of the device structure, which is a pointer to the
7554 * s2io_nic structure.
7555 * @link : inidicates whether link is UP/DOWN.
7557 * This function stops/starts the Tx queue depending on whether the link
7558 * status of the NIC is is down or up. This is called by the Alarm
7559 * interrupt handler whenever a link change interrupt comes up.
7564 static void s2io_link(struct s2io_nic * sp, int link)
7566 struct net_device *dev = (struct net_device *) sp->dev;
7568 if (link != sp->last_link_state) {
7570 if (link == LINK_DOWN) {
7571 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7572 s2io_stop_all_tx_queue(sp);
7573 netif_carrier_off(dev);
7574 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7575 sp->mac_control.stats_info->sw_stat.link_up_time =
7576 jiffies - sp->start_time;
7577 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7579 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7580 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7581 sp->mac_control.stats_info->sw_stat.link_down_time =
7582 jiffies - sp->start_time;
7583 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7584 netif_carrier_on(dev);
7585 s2io_wake_all_tx_queue(sp);
7588 sp->last_link_state = link;
7589 sp->start_time = jiffies;
7593 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7594 * @sp : private member of the device structure, which is a pointer to the
7595 * s2io_nic structure.
7597 * This function initializes a few of the PCI and PCI-X configuration registers
7598 * with recommended values.
7603 static void s2io_init_pci(struct s2io_nic * sp)
7605 u16 pci_cmd = 0, pcix_cmd = 0;
7607 /* Enable Data Parity Error Recovery in PCI-X command register. */
7608 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7610 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7612 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7615 /* Set the PErr Response bit in PCI command register. */
7616 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7617 pci_write_config_word(sp->pdev, PCI_COMMAND,
7618 (pci_cmd | PCI_COMMAND_PARITY));
7619 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7622 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7625 if ((tx_fifo_num > MAX_TX_FIFOS) ||
7626 (tx_fifo_num < 1)) {
7627 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7628 "(%d) not supported\n", tx_fifo_num);
7630 if (tx_fifo_num < 1)
7633 tx_fifo_num = MAX_TX_FIFOS;
7635 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7636 DBG_PRINT(ERR_DBG, "tx fifos\n");
7640 *dev_multiq = multiq;
7642 if (tx_steering_type && (1 == tx_fifo_num)) {
7643 if (tx_steering_type != TX_DEFAULT_STEERING)
7645 "s2io: Tx steering is not supported with "
7646 "one fifo. Disabling Tx steering.\n");
7647 tx_steering_type = NO_STEERING;
7650 if ((tx_steering_type < NO_STEERING) ||
7651 (tx_steering_type > TX_DEFAULT_STEERING)) {
7652 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7654 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7655 tx_steering_type = NO_STEERING;
7658 if (rx_ring_num > MAX_RX_RINGS) {
7659 DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
7661 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7663 rx_ring_num = MAX_RX_RINGS;
7666 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7667 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7668 "Defaulting to INTA\n");
7669 *dev_intr_type = INTA;
7672 if ((*dev_intr_type == MSI_X) &&
7673 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7674 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7675 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7676 "Defaulting to INTA\n");
7677 *dev_intr_type = INTA;
7680 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7681 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7682 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7689 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7690 * or Traffic class respectively.
7691 * @nic: device private variable
7692 * Description: The function configures the receive steering to
7693 * desired receive ring.
7694 * Return Value: SUCCESS on success and
7695 * '-1' on failure (endian settings incorrect).
7697 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7699 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7700 register u64 val64 = 0;
7702 if (ds_codepoint > 63)
7705 val64 = RTS_DS_MEM_DATA(ring);
7706 writeq(val64, &bar0->rts_ds_mem_data);
7708 val64 = RTS_DS_MEM_CTRL_WE |
7709 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7710 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7712 writeq(val64, &bar0->rts_ds_mem_ctrl);
7714 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7715 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7719 static const struct net_device_ops s2io_netdev_ops = {
7720 .ndo_open = s2io_open,
7721 .ndo_stop = s2io_close,
7722 .ndo_get_stats = s2io_get_stats,
7723 .ndo_start_xmit = s2io_xmit,
7724 .ndo_validate_addr = eth_validate_addr,
7725 .ndo_set_multicast_list = s2io_set_multicast,
7726 .ndo_do_ioctl = s2io_ioctl,
7727 .ndo_set_mac_address = s2io_set_mac_addr,
7728 .ndo_change_mtu = s2io_change_mtu,
7729 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7730 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7731 .ndo_tx_timeout = s2io_tx_watchdog,
7732 #ifdef CONFIG_NET_POLL_CONTROLLER
7733 .ndo_poll_controller = s2io_netpoll,
7738 * s2io_init_nic - Initialization of the adapter .
7739 * @pdev : structure containing the PCI related information of the device.
7740 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7742 * The function initializes an adapter identified by the pci_dec structure.
7743 * All OS related initialization including memory and device structure and
7744 * initlaization of the device private variable is done. Also the swapper
7745 * control register is initialized to enable read and write into the I/O
7746 * registers of the device.
7748 * returns 0 on success and negative on failure.
7751 static int __devinit
7752 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7754 struct s2io_nic *sp;
7755 struct net_device *dev;
7757 int dma_flag = FALSE;
7758 u32 mac_up, mac_down;
7759 u64 val64 = 0, tmp64 = 0;
7760 struct XENA_dev_config __iomem *bar0 = NULL;
7762 struct mac_info *mac_control;
7763 struct config_param *config;
7765 u8 dev_intr_type = intr_type;
7768 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7772 if ((ret = pci_enable_device(pdev))) {
7774 "s2io_init_nic: pci_enable_device failed\n");
7778 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7779 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7781 if (pci_set_consistent_dma_mask
7782 (pdev, DMA_BIT_MASK(64))) {
7784 "Unable to obtain 64bit DMA for \
7785 consistent allocations\n");
7786 pci_disable_device(pdev);
7789 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7790 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7792 pci_disable_device(pdev);
7795 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7796 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __func__, ret);
7797 pci_disable_device(pdev);
7801 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7803 dev = alloc_etherdev(sizeof(struct s2io_nic));
7805 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7806 pci_disable_device(pdev);
7807 pci_release_regions(pdev);
7811 pci_set_master(pdev);
7812 pci_set_drvdata(pdev, dev);
7813 SET_NETDEV_DEV(dev, &pdev->dev);
7815 /* Private member variable initialized to s2io NIC structure */
7816 sp = netdev_priv(dev);
7817 memset(sp, 0, sizeof(struct s2io_nic));
7820 sp->high_dma_flag = dma_flag;
7821 sp->device_enabled_once = FALSE;
7822 if (rx_ring_mode == 1)
7823 sp->rxd_mode = RXD_MODE_1;
7824 if (rx_ring_mode == 2)
7825 sp->rxd_mode = RXD_MODE_3B;
7827 sp->config.intr_type = dev_intr_type;
7829 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7830 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7831 sp->device_type = XFRAME_II_DEVICE;
7833 sp->device_type = XFRAME_I_DEVICE;
7835 sp->lro = lro_enable;
7837 /* Initialize some PCI/PCI-X fields of the NIC. */
7841 * Setting the device configuration parameters.
7842 * Most of these parameters can be specified by the user during
7843 * module insertion as they are module loadable parameters. If
7844 * these parameters are not not specified during load time, they
7845 * are initialized with default values.
7847 mac_control = &sp->mac_control;
7848 config = &sp->config;
7850 config->napi = napi;
7851 config->tx_steering_type = tx_steering_type;
7853 /* Tx side parameters. */
7854 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7855 config->tx_fifo_num = MAX_TX_FIFOS;
7857 config->tx_fifo_num = tx_fifo_num;
7859 /* Initialize the fifos used for tx steering */
7860 if (config->tx_fifo_num < 5) {
7861 if (config->tx_fifo_num == 1)
7862 sp->total_tcp_fifos = 1;
7864 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7865 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7866 sp->total_udp_fifos = 1;
7867 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7869 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7870 FIFO_OTHER_MAX_NUM);
7871 sp->udp_fifo_idx = sp->total_tcp_fifos;
7872 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7873 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7876 config->multiq = dev_multiq;
7877 for (i = 0; i < config->tx_fifo_num; i++) {
7878 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7879 config->tx_cfg[i].fifo_priority = i;
7882 /* mapping the QoS priority to the configured fifos */
7883 for (i = 0; i < MAX_TX_FIFOS; i++)
7884 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7886 /* map the hashing selector table to the configured fifos */
7887 for (i = 0; i < config->tx_fifo_num; i++)
7888 sp->fifo_selector[i] = fifo_selector[i];
7891 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7892 for (i = 0; i < config->tx_fifo_num; i++) {
7893 config->tx_cfg[i].f_no_snoop =
7894 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7895 if (config->tx_cfg[i].fifo_len < 65) {
7896 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7900 /* + 2 because one Txd for skb->data and one Txd for UFO */
7901 config->max_txds = MAX_SKB_FRAGS + 2;
7903 /* Rx side parameters. */
7904 config->rx_ring_num = rx_ring_num;
7905 for (i = 0; i < config->rx_ring_num; i++) {
7906 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7907 (rxd_count[sp->rxd_mode] + 1);
7908 config->rx_cfg[i].ring_priority = i;
7909 mac_control->rings[i].rx_bufs_left = 0;
7910 mac_control->rings[i].rxd_mode = sp->rxd_mode;
7911 mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode];
7912 mac_control->rings[i].pdev = sp->pdev;
7913 mac_control->rings[i].dev = sp->dev;
7916 for (i = 0; i < rx_ring_num; i++) {
7917 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7918 config->rx_cfg[i].f_no_snoop =
7919 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7922 /* Setting Mac Control parameters */
7923 mac_control->rmac_pause_time = rmac_pause_time;
7924 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7925 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7928 /* initialize the shared memory used by the NIC and the host */
7929 if (init_shared_mem(sp)) {
7930 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7933 goto mem_alloc_failed;
7936 sp->bar0 = pci_ioremap_bar(pdev, 0);
7938 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7941 goto bar0_remap_failed;
7944 sp->bar1 = pci_ioremap_bar(pdev, 2);
7946 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7949 goto bar1_remap_failed;
7952 dev->irq = pdev->irq;
7953 dev->base_addr = (unsigned long) sp->bar0;
7955 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7956 for (j = 0; j < MAX_TX_FIFOS; j++) {
7957 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7958 (sp->bar1 + (j * 0x00020000));
7961 /* Driver entry points */
7962 dev->netdev_ops = &s2io_netdev_ops;
7963 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7964 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7966 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7967 if (sp->high_dma_flag == TRUE)
7968 dev->features |= NETIF_F_HIGHDMA;
7969 dev->features |= NETIF_F_TSO;
7970 dev->features |= NETIF_F_TSO6;
7971 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7972 dev->features |= NETIF_F_UFO;
7973 dev->features |= NETIF_F_HW_CSUM;
7975 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7976 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7977 INIT_WORK(&sp->set_link_task, s2io_set_link);
7979 pci_save_state(sp->pdev);
7981 /* Setting swapper control on the NIC, for proper reset operation */
7982 if (s2io_set_swapper(sp)) {
7983 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7986 goto set_swap_failed;
7989 /* Verify if the Herc works on the slot its placed into */
7990 if (sp->device_type & XFRAME_II_DEVICE) {
7991 mode = s2io_verify_pci_mode(sp);
7993 DBG_PRINT(ERR_DBG, "%s: ", __func__);
7994 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7996 goto set_swap_failed;
8000 if (sp->config.intr_type == MSI_X) {
8001 sp->num_entries = config->rx_ring_num + 1;
8002 ret = s2io_enable_msi_x(sp);
8005 ret = s2io_test_msi(sp);
8006 /* rollback MSI-X, will re-enable during add_isr() */
8007 remove_msix_isr(sp);
8012 "s2io: MSI-X requested but failed to enable\n");
8013 sp->config.intr_type = INTA;
8017 if (config->intr_type == MSI_X) {
8018 for (i = 0; i < config->rx_ring_num ; i++)
8019 netif_napi_add(dev, &mac_control->rings[i].napi,
8020 s2io_poll_msix, 64);
8022 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8025 /* Not needed for Herc */
8026 if (sp->device_type & XFRAME_I_DEVICE) {
8028 * Fix for all "FFs" MAC address problems observed on
8031 fix_mac_address(sp);
8036 * MAC address initialization.
8037 * For now only one mac address will be read and used.
8040 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8041 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8042 writeq(val64, &bar0->rmac_addr_cmd_mem);
8043 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8044 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
8045 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8046 mac_down = (u32) tmp64;
8047 mac_up = (u32) (tmp64 >> 32);
8049 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8050 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8051 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8052 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8053 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8054 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8056 /* Set the factory defined MAC address initially */
8057 dev->addr_len = ETH_ALEN;
8058 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8059 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8061 /* initialize number of multicast & unicast MAC entries variables */
8062 if (sp->device_type == XFRAME_I_DEVICE) {
8063 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8064 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8065 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8066 } else if (sp->device_type == XFRAME_II_DEVICE) {
8067 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8068 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8069 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8072 /* store mac addresses from CAM to s2io_nic structure */
8073 do_s2io_store_unicast_mc(sp);
8075 /* Configure MSIX vector for number of rings configured plus one */
8076 if ((sp->device_type == XFRAME_II_DEVICE) &&
8077 (config->intr_type == MSI_X))
8078 sp->num_entries = config->rx_ring_num + 1;
8080 /* Store the values of the MSIX table in the s2io_nic structure */
8081 store_xmsi_data(sp);
8082 /* reset Nic and bring it to known state */
8086 * Initialize link state flags
8087 * and the card state parameter
8091 /* Initialize spinlocks */
8092 for (i = 0; i < sp->config.tx_fifo_num; i++)
8093 spin_lock_init(&mac_control->fifos[i].tx_lock);
8096 * SXE-002: Configure link and activity LED to init state
8099 subid = sp->pdev->subsystem_device;
8100 if ((subid & 0xFF) >= 0x07) {
8101 val64 = readq(&bar0->gpio_control);
8102 val64 |= 0x0000800000000000ULL;
8103 writeq(val64, &bar0->gpio_control);
8104 val64 = 0x0411040400000000ULL;
8105 writeq(val64, (void __iomem *) bar0 + 0x2700);
8106 val64 = readq(&bar0->gpio_control);
8109 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8111 if (register_netdev(dev)) {
8112 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8114 goto register_failed;
8117 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
8118 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
8119 sp->product_name, pdev->revision);
8120 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8121 s2io_driver_version);
8122 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %pM\n", dev->name, dev->dev_addr);
8123 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
8124 if (sp->device_type & XFRAME_II_DEVICE) {
8125 mode = s2io_print_pci_mode(sp);
8127 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8129 unregister_netdev(dev);
8130 goto set_swap_failed;
8133 switch(sp->rxd_mode) {
8135 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8139 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8144 switch (sp->config.napi) {
8146 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8149 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8153 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8154 sp->config.tx_fifo_num);
8156 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8157 sp->config.rx_ring_num);
8159 switch(sp->config.intr_type) {
8161 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8164 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8167 if (sp->config.multiq) {
8168 for (i = 0; i < sp->config.tx_fifo_num; i++)
8169 mac_control->fifos[i].multiq = config->multiq;
8170 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8173 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8176 switch (sp->config.tx_steering_type) {
8178 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8179 " transmit\n", dev->name);
8181 case TX_PRIORITY_STEERING:
8182 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8183 " transmit\n", dev->name);
8185 case TX_DEFAULT_STEERING:
8186 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8187 " transmit\n", dev->name);
8191 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8194 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8195 " enabled\n", dev->name);
8196 /* Initialize device name */
8197 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8200 sp->vlan_strip_flag = 1;
8202 sp->vlan_strip_flag = 0;
8205 * Make Link state as off at this point, when the Link change
8206 * interrupt comes the state will be automatically changed to
8209 netif_carrier_off(dev);
8220 free_shared_mem(sp);
8221 pci_disable_device(pdev);
8222 pci_release_regions(pdev);
8223 pci_set_drvdata(pdev, NULL);
8230 * s2io_rem_nic - Free the PCI device
8231 * @pdev: structure containing the PCI related information of the device.
8232 * Description: This function is called by the Pci subsystem to release a
8233 * PCI device and free up all resource held up by the device. This could
8234 * be in response to a Hot plug event or when the driver is to be removed
8238 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8240 struct net_device *dev =
8241 (struct net_device *) pci_get_drvdata(pdev);
8242 struct s2io_nic *sp;
8245 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8249 flush_scheduled_work();
8251 sp = netdev_priv(dev);
8252 unregister_netdev(dev);
8254 free_shared_mem(sp);
8257 pci_release_regions(pdev);
8258 pci_set_drvdata(pdev, NULL);
8260 pci_disable_device(pdev);
8264 * s2io_starter - Entry point for the driver
8265 * Description: This function is the entry point for the driver. It verifies
8266 * the module loadable parameters and initializes PCI configuration space.
8269 static int __init s2io_starter(void)
8271 return pci_register_driver(&s2io_driver);
8275 * s2io_closer - Cleanup routine for the driver
8276 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8279 static __exit void s2io_closer(void)
8281 pci_unregister_driver(&s2io_driver);
8282 DBG_PRINT(INIT_DBG, "cleanup done\n");
8285 module_init(s2io_starter);
8286 module_exit(s2io_closer);
8288 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8289 struct tcphdr **tcp, struct RxD_t *rxdp,
8290 struct s2io_nic *sp)
8293 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8295 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8296 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8301 /* Checking for DIX type or DIX type with VLAN */
8303 || (l2_type == 4)) {
8304 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8306 * If vlan stripping is disabled and the frame is VLAN tagged,
8307 * shift the offset by the VLAN header size bytes.
8309 if ((!sp->vlan_strip_flag) &&
8310 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8311 ip_off += HEADER_VLAN_SIZE;
8313 /* LLC, SNAP etc are considered non-mergeable */
8317 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8318 ip_len = (u8)((*ip)->ihl);
8320 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8325 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8328 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8329 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8330 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8335 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8337 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8340 static void initiate_new_session(struct lro *lro, u8 *l2h,
8341 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
8343 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8347 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8348 lro->tcp_ack = tcp->ack_seq;
8350 lro->total_len = ntohs(ip->tot_len);
8352 lro->vlan_tag = vlan_tag;
8354 * check if we saw TCP timestamp. Other consistency checks have
8355 * already been done.
8357 if (tcp->doff == 8) {
8359 ptr = (__be32 *)(tcp+1);
8361 lro->cur_tsval = ntohl(*(ptr+1));
8362 lro->cur_tsecr = *(ptr+2);
8367 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8369 struct iphdr *ip = lro->iph;
8370 struct tcphdr *tcp = lro->tcph;
8372 struct stat_block *statinfo = sp->mac_control.stats_info;
8373 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8375 /* Update L3 header */
8376 ip->tot_len = htons(lro->total_len);
8378 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8381 /* Update L4 header */
8382 tcp->ack_seq = lro->tcp_ack;
8383 tcp->window = lro->window;
8385 /* Update tsecr field if this session has timestamps enabled */
8387 __be32 *ptr = (__be32 *)(tcp + 1);
8388 *(ptr+2) = lro->cur_tsecr;
8391 /* Update counters required for calculation of
8392 * average no. of packets aggregated.
8394 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8395 statinfo->sw_stat.num_aggregations++;
8398 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8399 struct tcphdr *tcp, u32 l4_pyld)
8401 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8402 lro->total_len += l4_pyld;
8403 lro->frags_len += l4_pyld;
8404 lro->tcp_next_seq += l4_pyld;
8407 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8408 lro->tcp_ack = tcp->ack_seq;
8409 lro->window = tcp->window;
8413 /* Update tsecr and tsval from this packet */
8414 ptr = (__be32 *)(tcp+1);
8415 lro->cur_tsval = ntohl(*(ptr+1));
8416 lro->cur_tsecr = *(ptr + 2);
8420 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8421 struct tcphdr *tcp, u32 tcp_pyld_len)
8425 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
8427 if (!tcp_pyld_len) {
8428 /* Runt frame or a pure ack */
8432 if (ip->ihl != 5) /* IP has options */
8435 /* If we see CE codepoint in IP header, packet is not mergeable */
8436 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8439 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8440 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
8441 tcp->ece || tcp->cwr || !tcp->ack) {
8443 * Currently recognize only the ack control word and
8444 * any other control field being set would result in
8445 * flushing the LRO session
8451 * Allow only one TCP timestamp option. Don't aggregate if
8452 * any other options are detected.
8454 if (tcp->doff != 5 && tcp->doff != 8)
8457 if (tcp->doff == 8) {
8458 ptr = (u8 *)(tcp + 1);
8459 while (*ptr == TCPOPT_NOP)
8461 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8464 /* Ensure timestamp value increases monotonically */
8466 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8469 /* timestamp echo reply should be non-zero */
8470 if (*((__be32 *)(ptr+6)) == 0)
8478 s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
8479 u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
8480 struct s2io_nic *sp)
8483 struct tcphdr *tcph;
8487 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8489 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8490 ip->saddr, ip->daddr);
8494 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8495 tcph = (struct tcphdr *)*tcp;
8496 *tcp_len = get_l4_pyld_length(ip, tcph);
8497 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8498 struct lro *l_lro = &ring_data->lro0_n[i];
8499 if (l_lro->in_use) {
8500 if (check_for_socket_match(l_lro, ip, tcph))
8502 /* Sock pair matched */
8505 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8506 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8507 "0x%x, actual 0x%x\n", __func__,
8508 (*lro)->tcp_next_seq,
8511 sp->mac_control.stats_info->
8512 sw_stat.outof_sequence_pkts++;
8517 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8518 ret = 1; /* Aggregate */
8520 ret = 2; /* Flush both */
8526 /* Before searching for available LRO objects,
8527 * check if the pkt is L3/L4 aggregatable. If not
8528 * don't create new LRO session. Just send this
8531 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8535 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8536 struct lro *l_lro = &ring_data->lro0_n[i];
8537 if (!(l_lro->in_use)) {
8539 ret = 3; /* Begin anew */
8545 if (ret == 0) { /* sessions exceeded */
8546 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8554 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8558 update_L3L4_header(sp, *lro);
8561 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8562 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8563 update_L3L4_header(sp, *lro);
8564 ret = 4; /* Flush the LRO */
8568 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8576 static void clear_lro_session(struct lro *lro)
8578 static u16 lro_struct_size = sizeof(struct lro);
8580 memset(lro, 0, lro_struct_size);
8583 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8585 struct net_device *dev = skb->dev;
8586 struct s2io_nic *sp = netdev_priv(dev);
8588 skb->protocol = eth_type_trans(skb, dev);
8589 if (sp->vlgrp && vlan_tag
8590 && (sp->vlan_strip_flag)) {
8591 /* Queueing the vlan frame to the upper layer */
8592 if (sp->config.napi)
8593 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8595 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8597 if (sp->config.napi)
8598 netif_receive_skb(skb);
8604 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8605 struct sk_buff *skb,
8608 struct sk_buff *first = lro->parent;
8610 first->len += tcp_len;
8611 first->data_len = lro->frags_len;
8612 skb_pull(skb, (skb->len - tcp_len));
8613 if (skb_shinfo(first)->frag_list)
8614 lro->last_frag->next = skb;
8616 skb_shinfo(first)->frag_list = skb;
8617 first->truesize += skb->truesize;
8618 lro->last_frag = skb;
8619 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8624 * s2io_io_error_detected - called when PCI error is detected
8625 * @pdev: Pointer to PCI device
8626 * @state: The current pci connection state
8628 * This function is called after a PCI bus error affecting
8629 * this device has been detected.
8631 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8632 pci_channel_state_t state)
8634 struct net_device *netdev = pci_get_drvdata(pdev);
8635 struct s2io_nic *sp = netdev_priv(netdev);
8637 netif_device_detach(netdev);
8639 if (netif_running(netdev)) {
8640 /* Bring down the card, while avoiding PCI I/O */
8641 do_s2io_card_down(sp, 0);
8643 pci_disable_device(pdev);
8645 return PCI_ERS_RESULT_NEED_RESET;
8649 * s2io_io_slot_reset - called after the pci bus has been reset.
8650 * @pdev: Pointer to PCI device
8652 * Restart the card from scratch, as if from a cold-boot.
8653 * At this point, the card has exprienced a hard reset,
8654 * followed by fixups by BIOS, and has its config space
8655 * set up identically to what it was at cold boot.
8657 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8659 struct net_device *netdev = pci_get_drvdata(pdev);
8660 struct s2io_nic *sp = netdev_priv(netdev);
8662 if (pci_enable_device(pdev)) {
8663 printk(KERN_ERR "s2io: "
8664 "Cannot re-enable PCI device after reset.\n");
8665 return PCI_ERS_RESULT_DISCONNECT;
8668 pci_set_master(pdev);
8671 return PCI_ERS_RESULT_RECOVERED;
8675 * s2io_io_resume - called when traffic can start flowing again.
8676 * @pdev: Pointer to PCI device
8678 * This callback is called when the error recovery driver tells
8679 * us that its OK to resume normal operation.
8681 static void s2io_io_resume(struct pci_dev *pdev)
8683 struct net_device *netdev = pci_get_drvdata(pdev);
8684 struct s2io_nic *sp = netdev_priv(netdev);
8686 if (netif_running(netdev)) {
8687 if (s2io_card_up(sp)) {
8688 printk(KERN_ERR "s2io: "
8689 "Can't bring device back up after reset.\n");
8693 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8695 printk(KERN_ERR "s2io: "
8696 "Can't resetore mac addr after reset.\n");
8701 netif_device_attach(netdev);
8702 netif_tx_wake_all_queues(netdev);