git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8568EMDS";
  16         compatible = "MPC8568EMDS", "MPC85xxMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 ethernet3 = &enet3;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 pci0 = &pci0;
  28                 pci1 = &pci1;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,8568@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         d-cache-line-size = <32>;       // 32 bytes
  39                         i-cache-line-size = <32>;       // 32 bytes
  40                         d-cache-size = <0x8000>;                // L1, 32K
  41                         i-cache-size = <0x8000>;                // L1, 32K
  42                         timebase-frequency = <0>;
  43                         bus-frequency = <0>;
  44                         clock-frequency = <0>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x0 0x10000000>;
  51         };
  52
  53         bcsr@f8000000 {
  54                 device_type = "board-control";
  55                 reg = <0xf8000000 0x8000>;
  56         };
  57
  58         soc8568@e0000000 {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 device_type = "soc";
  62                 ranges = <0x0 0xe0000000 0x100000>;
  63                 reg = <0xe0000000 0x1000>;
  64                 bus-frequency = <0>;
  65
  66                 memory-controller@2000 {
  67                         compatible = "fsl,8568-memory-controller";
  68                         reg = <0x2000 0x1000>;
  69                         interrupt-parent = <&mpic>;
  70                         interrupts = <18 2>;
  71                 };
  72
  73                 l2-cache-controller@20000 {
  74                         compatible = "fsl,8568-l2-cache-controller";
  75                         reg = <0x20000 0x1000>;
  76                         cache-line-size = <32>; // 32 bytes
  77                         cache-size = <0x80000>; // L2, 512K
  78                         interrupt-parent = <&mpic>;
  79                         interrupts = <16 2>;
  80                 };
  81
  82                 i2c@3000 {
  83                         #address-cells = <1>;
  84                         #size-cells = <0>;
  85                         cell-index = <0>;
  86                         compatible = "fsl-i2c";
  87                         reg = <0x3000 0x100>;
  88                         interrupts = <43 2>;
  89                         interrupt-parent = <&mpic>;
  90                         dfsrr;
  91
  92                         rtc@68 {
  93                                 compatible = "dallas,ds1374";
  94                                 reg = <0x68>;
  95                         };
  96                 };
  97
  98                 i2c@3100 {
  99                         #address-cells = <1>;
 100                         #size-cells = <0>;
 101                         cell-index = <1>;
 102                         compatible = "fsl-i2c";
 103                         reg = <0x3100 0x100>;
 104                         interrupts = <43 2>;
 105                         interrupt-parent = <&mpic>;
 106                         dfsrr;
 107                 };
 108
 109                 mdio@24520 {
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                         compatible = "fsl,gianfar-mdio";
 113                         reg = <0x24520 0x20>;
 114
 115                         phy0: ethernet-phy@7 {
 116                                 interrupt-parent = <&mpic>;
 117                                 interrupts = <1 1>;
 118                                 reg = <0x7>;
 119                                 device_type = "ethernet-phy";
 120                         };
 121                         phy1: ethernet-phy@1 {
 122                                 interrupt-parent = <&mpic>;
 123                                 interrupts = <2 1>;
 124                                 reg = <0x1>;
 125                                 device_type = "ethernet-phy";
 126                         };
 127                         phy2: ethernet-phy@2 {
 128                                 interrupt-parent = <&mpic>;
 129                                 interrupts = <1 1>;
 130                                 reg = <0x2>;
 131                                 device_type = "ethernet-phy";
 132                         };
 133                         phy3: ethernet-phy@3 {
 134                                 interrupt-parent = <&mpic>;
 135                                 interrupts = <2 1>;
 136                                 reg = <0x3>;
 137                                 device_type = "ethernet-phy";
 138                         };
 139                 };
 140
 141                 enet0: ethernet@24000 {
 142                         cell-index = <0>;
 143                         device_type = "network";
 144                         model = "eTSEC";
 145                         compatible = "gianfar";
 146                         reg = <0x24000 0x1000>;
 147                         local-mac-address = [ 00 00 00 00 00 00 ];
 148                         interrupts = <29 2 30 2 34 2>;
 149                         interrupt-parent = <&mpic>;
 150                         phy-handle = <&phy2>;
 151                 };
 152
 153                 enet1: ethernet@25000 {
 154                         cell-index = <1>;
 155                         device_type = "network";
 156                         model = "eTSEC";
 157                         compatible = "gianfar";
 158                         reg = <0x25000 0x1000>;
 159                         local-mac-address = [ 00 00 00 00 00 00 ];
 160                         interrupts = <35 2 36 2 40 2>;
 161                         interrupt-parent = <&mpic>;
 162                         phy-handle = <&phy3>;
 163                 };
 164
 165                 serial0: serial@4500 {
 166                         cell-index = <0>;
 167                         device_type = "serial";
 168                         compatible = "ns16550";
 169                         reg = <0x4500 0x100>;
 170                         clock-frequency = <0>;
 171                         interrupts = <42 2>;
 172                         interrupt-parent = <&mpic>;
 173                 };
 174
 175                 global-utilities@e0000 {        //global utilities block
 176                         compatible = "fsl,mpc8548-guts";
 177                         reg = <0xe0000 0x1000>;
 178                         fsl,has-rstcr;
 179                 };
 180
 181                 serial1: serial@4600 {
 182                         cell-index = <1>;
 183                         device_type = "serial";
 184                         compatible = "ns16550";
 185                         reg = <0x4600 0x100>;
 186                         clock-frequency = <0>;
 187                         interrupts = <42 2>;
 188                         interrupt-parent = <&mpic>;
 189                 };
 190
 191                 crypto@30000 {
 192                         device_type = "crypto";
 193                         model = "SEC2";
 194                         compatible = "talitos";
 195                         reg = <0x30000 0xf000>;
 196                         interrupts = <45 2>;
 197                         interrupt-parent = <&mpic>;
 198                         num-channels = <4>;
 199                         channel-fifo-len = <24>;
 200                         exec-units-mask = <0xfe>;
 201                         descriptor-types-mask = <0x12b0ebf>;
 202                 };
 203
 204                 mpic: pic@40000 {
 205                         clock-frequency = <0>;
 206                         interrupt-controller;
 207                         #address-cells = <0>;
 208                         #interrupt-cells = <2>;
 209                         reg = <0x40000 0x40000>;
 210                         compatible = "chrp,open-pic";
 211                         device_type = "open-pic";
 212                         big-endian;
 213                 };
 214
 215                 par_io@e0100 {
 216                         reg = <0xe0100 0x100>;
 217                         device_type = "par_io";
 218                         num-ports = <7>;
 219
 220                         pio1: ucc_pin@01 {
 221                                 pio-map = <
 222                         /* port  pin  dir  open_drain  assignment  has_irq */
 223                                         0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
 224                                         0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
 225                                         0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
 226                                         0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
 227                                         0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
 228                                         0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
 229                                         0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
 230                                         0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
 231                                         0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
 232                                         0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
 233                                         0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
 234                                         0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
 235                                         0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
 236                                         0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
 237                                         0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
 238                                         0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
 239                                         0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
 240                                         0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
 241                                         0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
 242                                         0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
 243                                         0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
 244                                         0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
 245                                         0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
 246                         };
 247
 248                         pio2: ucc_pin@02 {
 249                                 pio-map = <
 250                         /* port  pin  dir  open_drain  assignment  has_irq */
 251                                         0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
 252                                         0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
 253                                         0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
 254                                         0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
 255                                         0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
 256                                         0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
 257                                         0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
 258                                         0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
 259                                         0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
 260                                         0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
 261                                         0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
 262                                         0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
 263                                         0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
 264                                         0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
 265                                         0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
 266                                         0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
 267                                         0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
 268                                         0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
 269                                         0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
 270                                         0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
 271                                         0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
 272                                         0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
 273                                         0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
 274                                         0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
 275                                         0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
 276                         };
 277                 };
 278         };
 279
 280         qe@e0080000 {
 281                 #address-cells = <1>;
 282                 #size-cells = <1>;
 283                 device_type = "qe";
 284                 compatible = "fsl,qe";
 285                 ranges = <0x0 0xe0080000 0x40000>;
 286                 reg = <0xe0080000 0x480>;
 287                 brg-frequency = <0>;
 288                 bus-frequency = <396000000>;
 289
 290                 muram@10000 {
 291                         #address-cells = <1>;
 292                         #size-cells = <1>;
 293                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 294                         ranges = <0x0 0x10000 0x10000>;
 295
 296                         data-only@0 {
 297                                 compatible = "fsl,qe-muram-data",
 298                                              "fsl,cpm-muram-data";
 299                                 reg = <0x0 0x10000>;
 300                         };
 301                 };
 302
 303                 spi@4c0 {
 304                         cell-index = <0>;
 305                         compatible = "fsl,spi";
 306                         reg = <0x4c0 0x40>;
 307                         interrupts = <2>;
 308                         interrupt-parent = <&qeic>;
 309                         mode = "cpu";
 310                 };
 311
 312                 spi@500 {
 313                         cell-index = <1>;
 314                         compatible = "fsl,spi";
 315                         reg = <0x500 0x40>;
 316                         interrupts = <1>;
 317                         interrupt-parent = <&qeic>;
 318                         mode = "cpu";
 319                 };
 320
 321                 enet2: ucc@2000 {
 322                         device_type = "network";
 323                         compatible = "ucc_geth";
 324                         cell-index = <1>;
 325                         reg = <0x2000 0x200>;
 326                         interrupts = <32>;
 327                         interrupt-parent = <&qeic>;
 328                         local-mac-address = [ 00 00 00 00 00 00 ];
 329                         rx-clock-name = "none";
 330                         tx-clock-name = "clk16";
 331                         pio-handle = <&pio1>;
 332                         phy-handle = <&phy0>;
 333                         phy-connection-type = "rgmii-id";
 334                 };
 335
 336                 enet3: ucc@3000 {
 337                         device_type = "network";
 338                         compatible = "ucc_geth";
 339                         cell-index = <2>;
 340                         reg = <0x3000 0x200>;
 341                         interrupts = <33>;
 342                         interrupt-parent = <&qeic>;
 343                         local-mac-address = [ 00 00 00 00 00 00 ];
 344                         rx-clock-name = "none";
 345                         tx-clock-name = "clk16";
 346                         pio-handle = <&pio2>;
 347                         phy-handle = <&phy1>;
 348                         phy-connection-type = "rgmii-id";
 349                 };
 350
 351                 mdio@2120 {
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         reg = <0x2120 0x18>;
 355                         compatible = "fsl,ucc-mdio";
 356
 357                         /* These are the same PHYs as on
 358                          * gianfar's MDIO bus */
 359                         qe_phy0: ethernet-phy@07 {
 360                                 interrupt-parent = <&mpic>;
 361                                 interrupts = <1 1>;
 362                                 reg = <0x7>;
 363                                 device_type = "ethernet-phy";
 364                         };
 365                         qe_phy1: ethernet-phy@01 {
 366                                 interrupt-parent = <&mpic>;
 367                                 interrupts = <2 1>;
 368                                 reg = <0x1>;
 369                                 device_type = "ethernet-phy";
 370                         };
 371                         qe_phy2: ethernet-phy@02 {
 372                                 interrupt-parent = <&mpic>;
 373                                 interrupts = <1 1>;
 374                                 reg = <0x2>;
 375                                 device_type = "ethernet-phy";
 376                         };
 377                         qe_phy3: ethernet-phy@03 {
 378                                 interrupt-parent = <&mpic>;
 379                                 interrupts = <2 1>;
 380                                 reg = <0x3>;
 381                                 device_type = "ethernet-phy";
 382                         };
 383                 };
 384
 385                 qeic: interrupt-controller@80 {
 386                         interrupt-controller;
 387                         compatible = "fsl,qe-ic";
 388                         #address-cells = <0>;
 389                         #interrupt-cells = <1>;
 390                         reg = <0x80 0x80>;
 391                         big-endian;
 392                         interrupts = <46 2 46 2>; //high:30 low:30
 393                         interrupt-parent = <&mpic>;
 394                 };
 395
 396         };
 397
 398         pci0: pci@e0008000 {
 399                 cell-index = <0>;
 400                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 401                 interrupt-map = <
 402                         /* IDSEL 0x12 AD18 */
 403                         0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
 404                         0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
 405                         0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
 406                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 407
 408                         /* IDSEL 0x13 AD19 */
 409                         0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
 410                         0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
 411                         0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
 412                         0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 413
 414                 interrupt-parent = <&mpic>;
 415                 interrupts = <24 2>;
 416                 bus-range = <0 255>;
 417                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 418                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 419                 clock-frequency = <66666666>;
 420                 #interrupt-cells = <1>;
 421                 #size-cells = <2>;
 422                 #address-cells = <3>;
 423                 reg = <0xe0008000 0x1000>;
 424                 compatible = "fsl,mpc8540-pci";
 425                 device_type = "pci";
 426         };
 427
 428         /* PCI Express */
 429         pci1: pcie@e000a000 {
 430                 cell-index = <2>;
 431                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 432                 interrupt-map = <
 433
 434                         /* IDSEL 0x0 (PEX) */
 435                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 436                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 437                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 438                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 439
 440                 interrupt-parent = <&mpic>;
 441                 interrupts = <26 2>;
 442                 bus-range = <0 255>;
 443                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 444                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 445                 clock-frequency = <33333333>;
 446                 #interrupt-cells = <1>;
 447                 #size-cells = <2>;
 448                 #address-cells = <3>;
 449                 reg = <0xe000a000 0x1000>;
 450                 compatible = "fsl,mpc8548-pcie";
 451                 device_type = "pci";
 452                 pcie@0 {
 453                         reg = <0x0 0x0 0x0 0x0 0x0>;
 454                         #size-cells = <2>;
 455                         #address-cells = <3>;
 456                         device_type = "pci";
 457                         ranges = <0x2000000 0x0 0xa0000000
 458                                   0x2000000 0x0 0xa0000000
 459                                   0x0 0x10000000
 460
 461                                   0x1000000 0x0 0x0
 462                                   0x1000000 0x0 0x0
 463                                   0x0 0x800000>;
 464                 };
 465         };
 466 };