2 * MPC8572 DS Core0 Device Tree Source in CAMP mode.
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
7 * eth1, crypto, pci0, pci1.
9 * Copyright 2007-2009 Freescale Semiconductor Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
19 model = "fsl,MPC8572DS";
20 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
52 device_type = "memory";
53 reg = <0x0 0x0>; // Filled by U-Boot
60 compatible = "simple-bus";
61 ranges = <0x0 0xffe00000 0x100000>;
62 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
63 bus-frequency = <0>; // Filled out by uboot.
65 memory-controller@2000 {
66 compatible = "fsl,mpc8572-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
72 memory-controller@6000 {
73 compatible = "fsl,mpc8572-memory-controller";
74 reg = <0x6000 0x1000>;
75 interrupt-parent = <&mpic>;
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8572-l2-cache-controller";
81 reg = <0x20000 0x1000>;
82 cache-line-size = <32>; // 32 bytes
83 cache-size = <0x80000>; // L2, 512K
84 interrupt-parent = <&mpic>;
92 compatible = "fsl-i2c";
95 interrupt-parent = <&mpic>;
100 #address-cells = <1>;
103 compatible = "fsl-i2c";
104 reg = <0x3100 0x100>;
106 interrupt-parent = <&mpic>;
111 #address-cells = <1>;
113 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
115 ranges = <0x0 0x21100 0x200>;
118 compatible = "fsl,mpc8572-dma-channel",
119 "fsl,eloplus-dma-channel";
122 interrupt-parent = <&mpic>;
126 compatible = "fsl,mpc8572-dma-channel",
127 "fsl,eloplus-dma-channel";
130 interrupt-parent = <&mpic>;
134 compatible = "fsl,mpc8572-dma-channel",
135 "fsl,eloplus-dma-channel";
138 interrupt-parent = <&mpic>;
142 compatible = "fsl,mpc8572-dma-channel",
143 "fsl,eloplus-dma-channel";
146 interrupt-parent = <&mpic>;
151 enet0: ethernet@24000 {
152 #address-cells = <1>;
155 device_type = "network";
157 compatible = "gianfar";
158 reg = <0x24000 0x1000>;
159 ranges = <0x0 0x24000 0x1000>;
160 local-mac-address = [ 00 00 00 00 00 00 ];
161 interrupts = <29 2 30 2 34 2>;
162 interrupt-parent = <&mpic>;
163 phy-handle = <&phy0>;
164 phy-connection-type = "rgmii-id";
167 #address-cells = <1>;
169 compatible = "fsl,gianfar-mdio";
172 phy0: ethernet-phy@0 {
173 interrupt-parent = <&mpic>;
177 phy1: ethernet-phy@1 {
178 interrupt-parent = <&mpic>;
185 enet1: ethernet@25000 {
187 device_type = "network";
189 compatible = "gianfar";
190 reg = <0x25000 0x1000>;
191 local-mac-address = [ 00 00 00 00 00 00 ];
192 interrupts = <35 2 36 2 40 2>;
193 interrupt-parent = <&mpic>;
194 phy-handle = <&phy1>;
195 phy-connection-type = "rgmii-id";
198 serial0: serial@4500 {
200 device_type = "serial";
201 compatible = "ns16550";
202 reg = <0x4500 0x100>;
203 clock-frequency = <0>;
206 global-utilities@e0000 { //global utilities block
207 compatible = "fsl,mpc8572-guts";
208 reg = <0xe0000 0x1000>;
213 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
214 "fsl,sec2.1", "fsl,sec2.0";
215 reg = <0x30000 0x10000>;
216 interrupts = <45 2 58 2>;
217 interrupt-parent = <&mpic>;
218 fsl,num-channels = <4>;
219 fsl,channel-fifo-len = <24>;
220 fsl,exec-units-mask = <0x9fe>;
221 fsl,descriptor-types-mask = <0x3ab0ebf>;
225 interrupt-controller;
226 #address-cells = <0>;
227 #interrupt-cells = <2>;
228 reg = <0x40000 0x40000>;
229 compatible = "chrp,open-pic";
230 device_type = "open-pic";
231 protected-sources = <
232 31 32 33 37 38 39 /* enet2 enet3 */
233 76 77 78 79 26 42 /* dma2 pci2 serial*/
234 0xe0 0xe1 0xe2 0xe3 /* msi */
240 pci0: pcie@ffe08000 {
241 compatible = "fsl,mpc8548-pcie";
243 #interrupt-cells = <1>;
245 #address-cells = <3>;
246 reg = <0xffe08000 0x1000>;
248 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
249 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
250 clock-frequency = <33333333>;
251 interrupt-parent = <&mpic>;
253 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
255 /* IDSEL 0x11 func 0 - PCI slot 1 */
256 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
257 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
258 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
259 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
261 /* IDSEL 0x11 func 1 - PCI slot 1 */
262 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
263 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
264 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
265 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
267 /* IDSEL 0x11 func 2 - PCI slot 1 */
268 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
269 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
270 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
271 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
273 /* IDSEL 0x11 func 3 - PCI slot 1 */
274 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
275 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
276 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
277 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
279 /* IDSEL 0x11 func 4 - PCI slot 1 */
280 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
281 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
282 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
283 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
285 /* IDSEL 0x11 func 5 - PCI slot 1 */
286 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
287 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
288 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
289 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
291 /* IDSEL 0x11 func 6 - PCI slot 1 */
292 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
293 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
294 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
295 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
297 /* IDSEL 0x11 func 7 - PCI slot 1 */
298 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
299 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
300 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
301 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
303 /* IDSEL 0x12 func 0 - PCI slot 2 */
304 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
305 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
306 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
307 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
309 /* IDSEL 0x12 func 1 - PCI slot 2 */
310 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
311 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
312 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
313 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
315 /* IDSEL 0x12 func 2 - PCI slot 2 */
316 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
317 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
318 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
319 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
321 /* IDSEL 0x12 func 3 - PCI slot 2 */
322 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
323 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
324 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
325 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
327 /* IDSEL 0x12 func 4 - PCI slot 2 */
328 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
329 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
330 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
331 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
333 /* IDSEL 0x12 func 5 - PCI slot 2 */
334 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
335 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
336 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
337 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
339 /* IDSEL 0x12 func 6 - PCI slot 2 */
340 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
341 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
342 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
343 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
345 /* IDSEL 0x12 func 7 - PCI slot 2 */
346 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
347 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
348 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
349 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
352 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
353 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
354 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
355 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
358 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
361 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
362 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
364 // IDSEL 0x1f IDE/SATA
365 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
366 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
371 reg = <0x0 0x0 0x0 0x0 0x0>;
373 #address-cells = <3>;
375 ranges = <0x2000000 0x0 0x80000000
376 0x2000000 0x0 0x80000000
383 reg = <0x0 0x0 0x0 0x0 0x0>;
385 #address-cells = <3>;
386 ranges = <0x2000000 0x0 0x80000000
387 0x2000000 0x0 0x80000000
395 #interrupt-cells = <2>;
397 #address-cells = <2>;
398 reg = <0xf000 0x0 0x0 0x0 0x0>;
399 ranges = <0x1 0x0 0x1000000 0x0 0x0
401 interrupt-parent = <&i8259>;
403 i8259: interrupt-controller@20 {
407 interrupt-controller;
408 device_type = "interrupt-controller";
409 #address-cells = <0>;
410 #interrupt-cells = <2>;
411 compatible = "chrp,iic";
413 interrupt-parent = <&mpic>;
418 #address-cells = <1>;
419 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
420 interrupts = <1 3 12 3>;
426 compatible = "pnpPNP,303";
431 compatible = "pnpPNP,f03";
436 compatible = "pnpPNP,b00";
437 reg = <0x1 0x70 0x2>;
441 reg = <0x1 0x400 0x80>;
449 pci1: pcie@ffe09000 {
450 compatible = "fsl,mpc8548-pcie";
452 #interrupt-cells = <1>;
454 #address-cells = <3>;
455 reg = <0xffe09000 0x1000>;
457 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
458 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
459 clock-frequency = <33333333>;
460 interrupt-parent = <&mpic>;
462 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
465 0000 0x0 0x0 0x1 &mpic 0x4 0x1
466 0000 0x0 0x0 0x2 &mpic 0x5 0x1
467 0000 0x0 0x0 0x3 &mpic 0x6 0x1
468 0000 0x0 0x0 0x4 &mpic 0x7 0x1
471 reg = <0x0 0x0 0x0 0x0 0x0>;
473 #address-cells = <3>;
475 ranges = <0x2000000 0x0 0xa0000000
476 0x2000000 0x0 0xa0000000