git.oblomov.eu Git - linux-2.6/blob - drivers/video/matrox/matroxfb_g450.c

   1 /*
   2  *
   3  * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450.
   4  *
   5  * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
   6  *
   7  * Portions Copyright (c) 2001 Matrox Graphics Inc.
   8  *
   9  * Version: 1.65 2002/08/14
  10  *
  11  * See matroxfb_base.c for contributors.
  12  *
  13  */
  14
  15 #include "matroxfb_base.h"
  16 #include "matroxfb_misc.h"
  17 #include "matroxfb_DAC1064.h"
  18 #include "g450_pll.h"
  19 #include <linux/matroxfb.h>
  20 #include <asm/uaccess.h>
  21 #include <asm/div64.h>
  22
  23 #include "matroxfb_g450.h"
  24
  25 /* Definition of the various controls */
  26 struct mctl {
  27         struct v4l2_queryctrl desc;
  28         size_t control;
  29 };
  30
  31 #define BLMIN   0xF3
  32 #define WLMAX   0x3FF
  33
  34 static const struct mctl g450_controls[] =
  35 {       { { V4L2_CID_BRIGHTNESS, V4L2_CTRL_TYPE_INTEGER,
  36           "brightness",
  37           0, WLMAX-BLMIN, 1, 370-BLMIN,
  38           0,
  39         }, offsetof(struct matrox_fb_info, altout.tvo_params.brightness) },
  40         { { V4L2_CID_CONTRAST, V4L2_CTRL_TYPE_INTEGER,
  41           "contrast",
  42           0, 1023, 1, 127,
  43           0,
  44         }, offsetof(struct matrox_fb_info, altout.tvo_params.contrast) },
  45         { { V4L2_CID_SATURATION, V4L2_CTRL_TYPE_INTEGER,
  46           "saturation",
  47           0, 255, 1, 165,
  48           0,
  49         }, offsetof(struct matrox_fb_info, altout.tvo_params.saturation) },
  50         { { V4L2_CID_HUE, V4L2_CTRL_TYPE_INTEGER,
  51           "hue",
  52           0, 255, 1, 0,
  53           0,
  54         }, offsetof(struct matrox_fb_info, altout.tvo_params.hue) },
  55         { { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN,
  56           "test output",
  57           0, 1, 1, 0,
  58           0,
  59         }, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
  60 };
  61
  62 #define G450CTRLS (sizeof(g450_controls)/sizeof(g450_controls[0]))
  63
  64 /* Return: positive number: id found
  65            -EINVAL:         id not found, return failure
  66            -ENOENT:         id not found, create fake disabled control */
  67 static int get_ctrl_id(__u32 v4l2_id) {
  68         int i;
  69
  70         for (i = 0; i < G450CTRLS; i++) {
  71                 if (v4l2_id < g450_controls[i].desc.id) {
  72                         if (g450_controls[i].desc.id == 0x08000000) {
  73                                 return -EINVAL;
  74                         }
  75                         return -ENOENT;
  76                 }
  77                 if (v4l2_id == g450_controls[i].desc.id) {
  78                         return i;
  79                 }
  80         }
  81         return -EINVAL;
  82 }
  83
  84 static inline int* get_ctrl_ptr(WPMINFO unsigned int idx) {
  85         return (int*)((char*)MINFO + g450_controls[idx].control);
  86 }
  87
  88 static void tvo_fill_defaults(WPMINFO2) {
  89         unsigned int i;
  90
  91         for (i = 0; i < G450CTRLS; i++) {
  92                 *get_ctrl_ptr(PMINFO i) = g450_controls[i].desc.default_value;
  93         }
  94 }
  95
  96 static int cve2_get_reg(WPMINFO int reg) {
  97         unsigned long flags;
  98         int val;
  99
 100         matroxfb_DAC_lock_irqsave(flags);
 101         matroxfb_DAC_out(PMINFO 0x87, reg);
 102         val = matroxfb_DAC_in(PMINFO 0x88);
 103         matroxfb_DAC_unlock_irqrestore(flags);
 104         return val;
 105 }
 106
 107 static void cve2_set_reg(WPMINFO int reg, int val) {
 108         unsigned long flags;
 109
 110         matroxfb_DAC_lock_irqsave(flags);
 111         matroxfb_DAC_out(PMINFO 0x87, reg);
 112         matroxfb_DAC_out(PMINFO 0x88, val);
 113         matroxfb_DAC_unlock_irqrestore(flags);
 114 }
 115
 116 static void cve2_set_reg10(WPMINFO int reg, int val) {
 117         unsigned long flags;
 118
 119         matroxfb_DAC_lock_irqsave(flags);
 120         matroxfb_DAC_out(PMINFO 0x87, reg);
 121         matroxfb_DAC_out(PMINFO 0x88, val >> 2);
 122         matroxfb_DAC_out(PMINFO 0x87, reg + 1);
 123         matroxfb_DAC_out(PMINFO 0x88, val & 3);
 124         matroxfb_DAC_unlock_irqrestore(flags);
 125 }
 126
 127 static void g450_compute_bwlevel(CPMINFO int *bl, int *wl) {
 128         const int b = ACCESS_FBINFO(altout.tvo_params.brightness) + BLMIN;
 129         const int c = ACCESS_FBINFO(altout.tvo_params.contrast);
 130
 131         *bl = max(b - c, BLMIN);
 132         *wl = min(b + c, WLMAX);
 133 }
 134
 135 static int g450_query_ctrl(void* md, struct v4l2_queryctrl *p) {
 136         int i;
 137
 138         i = get_ctrl_id(p->id);
 139         if (i >= 0) {
 140                 *p = g450_controls[i].desc;
 141                 return 0;
 142         }
 143         if (i == -ENOENT) {
 144                 static const struct v4l2_queryctrl disctrl =
 145                         { .flags = V4L2_CTRL_FLAG_DISABLED };
 146
 147                 i = p->id;
 148                 *p = disctrl;
 149                 p->id = i;
 150                 sprintf(p->name, "Ctrl #%08X", i);
 151                 return 0;
 152         }
 153         return -EINVAL;
 154 }
 155
 156 static int g450_set_ctrl(void* md, struct v4l2_control *p) {
 157         int i;
 158         MINFO_FROM(md);
 159
 160         i = get_ctrl_id(p->id);
 161         if (i < 0) return -EINVAL;
 162
 163         /*
 164          * Check if changed.
 165          */
 166         if (p->value == *get_ctrl_ptr(PMINFO i)) return 0;
 167
 168         /*
 169          * Check limits.
 170          */
 171         if (p->value > g450_controls[i].desc.maximum) return -EINVAL;
 172         if (p->value < g450_controls[i].desc.minimum) return -EINVAL;
 173
 174         /*
 175          * Store new value.
 176          */
 177         *get_ctrl_ptr(PMINFO i) = p->value;
 178
 179         switch (p->id) {
 180                 case V4L2_CID_BRIGHTNESS:
 181                 case V4L2_CID_CONTRAST:
 182                         {
 183                                 int blacklevel, whitelevel;
 184                                 g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel);
 185                                 cve2_set_reg10(PMINFO 0x0e, blacklevel);
 186                                 cve2_set_reg10(PMINFO 0x1e, whitelevel);
 187                         }
 188                         break;
 189                 case V4L2_CID_SATURATION:
 190                         cve2_set_reg(PMINFO 0x20, p->value);
 191                         cve2_set_reg(PMINFO 0x22, p->value);
 192                         break;
 193                 case V4L2_CID_HUE:
 194                         cve2_set_reg(PMINFO 0x25, p->value);
 195                         break;
 196                 case MATROXFB_CID_TESTOUT:
 197                         {
 198                                 unsigned char val = cve2_get_reg (PMINFO 0x05);
 199                                 if (p->value) val |=  0x02;
 200                                 else          val &= ~0x02;
 201                                 cve2_set_reg(PMINFO 0x05, val);
 202                         }
 203                         break;
 204         }
 205
 206
 207         return 0;
 208 }
 209
 210 static int g450_get_ctrl(void* md, struct v4l2_control *p) {
 211         int i;
 212         MINFO_FROM(md);
 213
 214         i = get_ctrl_id(p->id);
 215         if (i < 0) return -EINVAL;
 216         p->value = *get_ctrl_ptr(PMINFO i);
 217         return 0;
 218 }
 219
 220 struct output_desc {
 221         unsigned int    h_vis;
 222         unsigned int    h_f_porch;
 223         unsigned int    h_sync;
 224         unsigned int    h_b_porch;
 225         unsigned long long int  chromasc;
 226         unsigned int    burst;
 227         unsigned int    v_total;
 228 };
 229
 230 static void computeRegs(WPMINFO struct mavenregs* r, struct my_timming* mt, const struct output_desc* outd) {
 231         u_int32_t chromasc;
 232         u_int32_t hlen;
 233         u_int32_t hsl;
 234         u_int32_t hbp;
 235         u_int32_t hfp;
 236         u_int32_t hvis;
 237         unsigned int pixclock;
 238         unsigned long long piic;
 239         int mnp;
 240         int over;
 241
 242         r->regs[0x80] = 0x03;   /* | 0x40 for SCART */
 243
 244         hvis = ((mt->HDisplay << 1) + 3) & ~3;
 245
 246         if (hvis >= 2048) {
 247                 hvis = 2044;
 248         }
 249
 250         piic = 1000000000ULL * hvis;
 251         do_div(piic, outd->h_vis);
 252
 253         dprintk(KERN_DEBUG "Want %u kHz pixclock\n", (unsigned int)piic);
 254
 255         mnp = matroxfb_g450_setclk(PMINFO piic, M_VIDEO_PLL);
 256
 257         mt->mnp = mnp;
 258         mt->pixclock = g450_mnp2f(PMINFO mnp);
 259
 260         dprintk(KERN_DEBUG "MNP=%08X\n", mnp);
 261
 262         pixclock = 1000000000U / mt->pixclock;
 263
 264         dprintk(KERN_DEBUG "Got %u ps pixclock\n", pixclock);
 265
 266         piic = outd->chromasc;
 267         do_div(piic, mt->pixclock);
 268         chromasc = piic;
 269
 270         dprintk(KERN_DEBUG "Chroma is %08X\n", chromasc);
 271
 272         r->regs[0] = piic >> 24;
 273         r->regs[1] = piic >> 16;
 274         r->regs[2] = piic >>  8;
 275         r->regs[3] = piic >>  0;
 276         hbp = (((outd->h_b_porch + pixclock) / pixclock)) & ~1;
 277         hfp = (((outd->h_f_porch + pixclock) / pixclock)) & ~1;
 278         hsl = (((outd->h_sync + pixclock) / pixclock)) & ~1;
 279         hlen = hvis + hfp + hsl + hbp;
 280         over = hlen & 0x0F;
 281
 282         dprintk(KERN_DEBUG "WL: vis=%u, hf=%u, hs=%u, hb=%u, total=%u\n", hvis, hfp, hsl, hbp, hlen);
 283
 284         if (over) {
 285                 hfp -= over;
 286                 hlen -= over;
 287                 if (over <= 2) {
 288                 } else if (over < 10) {
 289                         hfp += 4;
 290                         hlen += 4;
 291                 } else {
 292                         hfp += 16;
 293                         hlen += 16;
 294                 }
 295         }
 296
 297         /* maybe cve2 has requirement 800 < hlen < 1184 */
 298         r->regs[0x08] = hsl;
 299         r->regs[0x09] = (outd->burst + pixclock - 1) / pixclock;        /* burst length */
 300         r->regs[0x0A] = hbp;
 301         r->regs[0x2C] = hfp;
 302         r->regs[0x31] = hvis / 8;
 303         r->regs[0x32] = hvis & 7;
 304
 305         dprintk(KERN_DEBUG "PG: vis=%04X, hf=%02X, hs=%02X, hb=%02X, total=%04X\n", hvis, hfp, hsl, hbp, hlen);
 306
 307         r->regs[0x84] = 1;      /* x sync point */
 308         r->regs[0x85] = 0;
 309         hvis = hvis >> 1;
 310         hlen = hlen >> 1;
 311
 312         dprintk(KERN_DEBUG "hlen=%u hvis=%u\n", hlen, hvis);
 313
 314         mt->interlaced = 1;
 315
 316         mt->HDisplay = hvis & ~7;
 317         mt->HSyncStart = mt->HDisplay + 8;
 318         mt->HSyncEnd = (hlen & ~7) - 8;
 319         mt->HTotal = hlen;
 320
 321         {
 322                 int upper;
 323                 unsigned int vtotal;
 324                 unsigned int vsyncend;
 325                 unsigned int vdisplay;
 326
 327                 vtotal = mt->VTotal;
 328                 vsyncend = mt->VSyncEnd;
 329                 vdisplay = mt->VDisplay;
 330                 if (vtotal < outd->v_total) {
 331                         unsigned int yovr = outd->v_total - vtotal;
 332
 333                         vsyncend += yovr >> 1;
 334                 } else if (vtotal > outd->v_total) {
 335                         vdisplay = outd->v_total - 4;
 336                         vsyncend = outd->v_total;
 337                 }
 338                 upper = (outd->v_total - vsyncend) >> 1;        /* in field lines */
 339                 r->regs[0x17] = outd->v_total / 4;
 340                 r->regs[0x18] = outd->v_total & 3;
 341                 r->regs[0x33] = upper - 1;      /* upper blanking */
 342                 r->regs[0x82] = upper;          /* y sync point */
 343                 r->regs[0x83] = upper >> 8;
 344
 345                 mt->VDisplay = vdisplay;
 346                 mt->VSyncStart = outd->v_total - 2;
 347                 mt->VSyncEnd = outd->v_total;
 348                 mt->VTotal = outd->v_total;
 349         }
 350 }
 351
 352 static void cve2_init_TVdata(int norm, struct mavenregs* data, const struct output_desc** outd) {
 353         static const struct output_desc paloutd = {
 354                 .h_vis     = 52148148,  // ps
 355                 .h_f_porch =  1407407,  // ps
 356                 .h_sync    =  4666667,  // ps
 357                 .h_b_porch =  5777778,  // ps
 358                 .chromasc  = 19042247534182ULL, // 4433618.750 Hz
 359                 .burst     =  2518518,  // ps
 360                 .v_total   =      625,
 361         };
 362         static const struct output_desc ntscoutd = {
 363                 .h_vis     = 52888889,  // ps
 364                 .h_f_porch =  1333333,  // ps
 365                 .h_sync    =  4666667,  // ps
 366                 .h_b_porch =  4666667,  // ps
 367                 .chromasc  = 15374030659475ULL, // 3579545.454 Hz
 368                 .burst     =  2418418,  // ps
 369                 .v_total   =      525,  // lines
 370         };
 371
 372         static const struct mavenregs palregs = { {
 373                 0x2A, 0x09, 0x8A, 0xCB, /* 00: chroma subcarrier */
 374                 0x00,
 375                 0x00,   /* test */
 376                 0xF9,   /* modified by code (F9 written...) */
 377                 0x00,   /* ? not written */
 378                 0x7E,   /* 08 */
 379                 0x44,   /* 09 */
 380                 0x9C,   /* 0A */
 381                 0x2E,   /* 0B */
 382                 0x21,   /* 0C */
 383                 0x00,   /* ? not written */
 384 //              0x3F, 0x03, /* 0E-0F */
 385                 0x3C, 0x03,
 386                 0x3C, 0x03, /* 10-11 */
 387                 0x1A,   /* 12 */
 388                 0x2A,   /* 13 */
 389                 0x1C, 0x3D, 0x14, /* 14-16 */
 390                 0x9C, 0x01, /* 17-18 */
 391                 0x00,   /* 19 */
 392                 0xFE,   /* 1A */
 393                 0x7E,   /* 1B */
 394                 0x60,   /* 1C */
 395                 0x05,   /* 1D */
 396 //              0x89, 0x03, /* 1E-1F */
 397                 0xAD, 0x03,
 398 //              0x72,   /* 20 */
 399                 0xA5,
 400                 0x07,   /* 21 */
 401 //              0x72,   /* 22 */
 402                 0xA5,
 403                 0x00,   /* 23 */
 404                 0x00,   /* 24 */
 405                 0x00,   /* 25 */
 406                 0x08,   /* 26 */
 407                 0x04,   /* 27 */
 408                 0x00,   /* 28 */
 409                 0x1A,   /* 29 */
 410                 0x55, 0x01, /* 2A-2B */
 411                 0x26,   /* 2C */
 412                 0x07, 0x7E, /* 2D-2E */
 413                 0x02, 0x54, /* 2F-30 */
 414                 0xB0, 0x00, /* 31-32 */
 415                 0x14,   /* 33 */
 416                 0x49,   /* 34 */
 417                 0x00,   /* 35 written multiple times */
 418                 0x00,   /* 36 not written */
 419                 0xA3,   /* 37 */
 420                 0xC8,   /* 38 */
 421                 0x22,   /* 39 */
 422                 0x02,   /* 3A */
 423                 0x22,   /* 3B */
 424                 0x3F, 0x03, /* 3C-3D */
 425                 0x00,   /* 3E written multiple times */
 426                 0x00,   /* 3F not written */
 427         } };
 428         static struct mavenregs ntscregs = { {
 429                 0x21, 0xF0, 0x7C, 0x1F, /* 00: chroma subcarrier */
 430                 0x00,
 431                 0x00,   /* test */
 432                 0xF9,   /* modified by code (F9 written...) */
 433                 0x00,   /* ? not written */
 434                 0x7E,   /* 08 */
 435                 0x43,   /* 09 */
 436                 0x7E,   /* 0A */
 437                 0x3D,   /* 0B */
 438                 0x00,   /* 0C */
 439                 0x00,   /* ? not written */
 440                 0x41, 0x00, /* 0E-0F */
 441                 0x3C, 0x00, /* 10-11 */
 442                 0x17,   /* 12 */
 443                 0x21,   /* 13 */
 444                 0x1B, 0x1B, 0x24, /* 14-16 */
 445                 0x83, 0x01, /* 17-18 */
 446                 0x00,   /* 19 */
 447                 0x0F,   /* 1A */
 448                 0x0F,   /* 1B */
 449                 0x60,   /* 1C */
 450                 0x05,   /* 1D */
 451                 //0x89, 0x02, /* 1E-1F */
 452                 0xC0, 0x02, /* 1E-1F */
 453                 //0x5F, /* 20 */
 454                 0x9C,   /* 20 */
 455                 0x04,   /* 21 */
 456                 //0x5F, /* 22 */
 457                 0x9C,   /* 22 */
 458                 0x01,   /* 23 */
 459                 0x02,   /* 24 */
 460                 0x00,   /* 25 */
 461                 0x0A,   /* 26 */
 462                 0x05,   /* 27 */
 463                 0x00,   /* 28 */
 464                 0x10,   /* 29 */
 465                 0xFF, 0x03, /* 2A-2B */
 466                 0x24,   /* 2C */
 467                 0x0F, 0x78, /* 2D-2E */
 468                 0x00, 0x00, /* 2F-30 */
 469                 0xB2, 0x04, /* 31-32 */
 470                 0x14,   /* 33 */
 471                 0x02,   /* 34 */
 472                 0x00,   /* 35 written multiple times */
 473                 0x00,   /* 36 not written */
 474                 0xA3,   /* 37 */
 475                 0xC8,   /* 38 */
 476                 0x15,   /* 39 */
 477                 0x05,   /* 3A */
 478                 0x3B,   /* 3B */
 479                 0x3C, 0x00, /* 3C-3D */
 480                 0x00,   /* 3E written multiple times */
 481                 0x00,   /* never written */
 482         } };
 483
 484         if (norm == MATROXFB_OUTPUT_MODE_PAL) {
 485                 *data = palregs;
 486                 *outd = &paloutd;
 487         } else {
 488                 *data = ntscregs;
 489                 *outd = &ntscoutd;
 490         }
 491         return;
 492 }
 493
 494 #define LR(x) cve2_set_reg(PMINFO (x), m->regs[(x)])
 495 static void cve2_init_TV(WPMINFO const struct mavenregs* m) {
 496         int i;
 497
 498         LR(0x80);
 499         LR(0x82); LR(0x83);
 500         LR(0x84); LR(0x85);
 501
 502         cve2_set_reg(PMINFO 0x3E, 0x01);
 503
 504         for (i = 0; i < 0x3E; i++) {
 505                 LR(i);
 506         }
 507         cve2_set_reg(PMINFO 0x3E, 0x00);
 508 }
 509
 510 static int matroxfb_g450_compute(void* md, struct my_timming* mt) {
 511         MINFO_FROM(md);
 512
 513         dprintk(KERN_DEBUG "Computing, mode=%u\n", ACCESS_FBINFO(outputs[1]).mode);
 514
 515         if (mt->crtc == MATROXFB_SRC_CRTC2 &&
 516             ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) {
 517                 const struct output_desc* outd;
 518
 519                 cve2_init_TVdata(ACCESS_FBINFO(outputs[1]).mode, &ACCESS_FBINFO(hw).maven, &outd);
 520                 {
 521                         int blacklevel, whitelevel;
 522                         g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel);
 523                         ACCESS_FBINFO(hw).maven.regs[0x0E] = blacklevel >> 2;
 524                         ACCESS_FBINFO(hw).maven.regs[0x0F] = blacklevel & 3;
 525                         ACCESS_FBINFO(hw).maven.regs[0x1E] = whitelevel >> 2;
 526                         ACCESS_FBINFO(hw).maven.regs[0x1F] = whitelevel & 3;
 527
 528                         ACCESS_FBINFO(hw).maven.regs[0x20] =
 529                         ACCESS_FBINFO(hw).maven.regs[0x22] = ACCESS_FBINFO(altout.tvo_params.saturation);
 530
 531                         ACCESS_FBINFO(hw).maven.regs[0x25] = ACCESS_FBINFO(altout.tvo_params.hue);
 532
 533                         if (ACCESS_FBINFO(altout.tvo_params.testout)) {
 534                                 ACCESS_FBINFO(hw).maven.regs[0x05] |= 0x02;
 535                         }
 536                 }
 537                 computeRegs(PMINFO &ACCESS_FBINFO(hw).maven, mt, outd);
 538         } else if (mt->mnp < 0) {
 539                 /* We must program clocks before CRTC2, otherwise interlaced mode
 540                    startup may fail */
 541                 mt->mnp = matroxfb_g450_setclk(PMINFO mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
 542                 mt->pixclock = g450_mnp2f(PMINFO mt->mnp);
 543         }
 544         dprintk(KERN_DEBUG "Pixclock = %u\n", mt->pixclock);
 545         return 0;
 546 }
 547
 548 static int matroxfb_g450_program(void* md) {
 549         MINFO_FROM(md);
 550
 551         if (ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) {
 552                 cve2_init_TV(PMINFO &ACCESS_FBINFO(hw).maven);
 553         }
 554         return 0;
 555 }
 556
 557 static int matroxfb_g450_verify_mode(void* md, u_int32_t arg) {
 558         switch (arg) {
 559                 case MATROXFB_OUTPUT_MODE_PAL:
 560                 case MATROXFB_OUTPUT_MODE_NTSC:
 561                 case MATROXFB_OUTPUT_MODE_MONITOR:
 562                         return 0;
 563         }
 564         return -EINVAL;
 565 }
 566
 567 static int g450_dvi_compute(void* md, struct my_timming* mt) {
 568         MINFO_FROM(md);
 569
 570         if (mt->mnp < 0) {
 571                 mt->mnp = matroxfb_g450_setclk(PMINFO mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
 572                 mt->pixclock = g450_mnp2f(PMINFO mt->mnp);
 573         }
 574         return 0;
 575 }
 576
 577 static struct matrox_altout matroxfb_g450_altout = {
 578         .name           = "Secondary output",
 579         .compute        = matroxfb_g450_compute,
 580         .program        = matroxfb_g450_program,
 581         .verifymode     = matroxfb_g450_verify_mode,
 582         .getqueryctrl   = g450_query_ctrl,
 583         .getctrl        = g450_get_ctrl,
 584         .setctrl        = g450_set_ctrl,
 585 };
 586
 587 static struct matrox_altout matroxfb_g450_dvi = {
 588         .name           = "DVI output",
 589         .compute        = g450_dvi_compute,
 590 };
 591
 592 void matroxfb_g450_connect(WPMINFO2) {
 593         if (ACCESS_FBINFO(devflags.g450dac)) {
 594                 down_write(&ACCESS_FBINFO(altout.lock));
 595                 tvo_fill_defaults(PMINFO2);
 596                 ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src;
 597                 ACCESS_FBINFO(outputs[1]).data = MINFO;
 598                 ACCESS_FBINFO(outputs[1]).output = &matroxfb_g450_altout;
 599                 ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
 600                 ACCESS_FBINFO(outputs[2]).src = ACCESS_FBINFO(outputs[2]).default_src;
 601                 ACCESS_FBINFO(outputs[2]).data = MINFO;
 602                 ACCESS_FBINFO(outputs[2]).output = &matroxfb_g450_dvi;
 603                 ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
 604                 up_write(&ACCESS_FBINFO(altout.lock));
 605         }
 606 }
 607
 608 void matroxfb_g450_shutdown(WPMINFO2) {
 609         if (ACCESS_FBINFO(devflags.g450dac)) {
 610                 down_write(&ACCESS_FBINFO(altout.lock));
 611                 ACCESS_FBINFO(outputs[1]).src = MATROXFB_SRC_NONE;
 612                 ACCESS_FBINFO(outputs[1]).output = NULL;
 613                 ACCESS_FBINFO(outputs[1]).data = NULL;
 614                 ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
 615                 ACCESS_FBINFO(outputs[2]).src = MATROXFB_SRC_NONE;
 616                 ACCESS_FBINFO(outputs[2]).output = NULL;
 617                 ACCESS_FBINFO(outputs[2]).data = NULL;
 618                 ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
 619                 up_write(&ACCESS_FBINFO(altout.lock));
 620         }
 621 }
 622
 623 EXPORT_SYMBOL(matroxfb_g450_connect);
 624 EXPORT_SYMBOL(matroxfb_g450_shutdown);
 625
 626 MODULE_AUTHOR("(c) 2000-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
 627 MODULE_DESCRIPTION("Matrox G450/G550 output driver");
 628 MODULE_LICENSE("GPL");