git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/sysdev/cpm1.c

   1 /*
   2  * General Purpose functions for the global management of the
   3  * Communication Processor Module.
   4  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
   5  *
   6  * In addition to the individual control of the communication
   7  * channels, there are a few functions that globally affect the
   8  * communication processor.
   9  *
  10  * Buffer descriptors must be allocated from the dual ported memory
  11  * space.  The allocator for that is here.  When the communication
  12  * process is reset, we reclaim the memory available.  There is
  13  * currently no deallocator for this memory.
  14  * The amount of space available is platform dependent.  On the
  15  * MBX, the EPPC software loads additional microcode into the
  16  * communication processor, and uses some of the DP ram for this
  17  * purpose.  Current, the first 512 bytes and the last 256 bytes of
  18  * memory are used.  Right now I am conservative and only use the
  19  * memory that can never be used for microcode.  If there are
  20  * applications that require more DP ram, we can expand the boundaries
  21  * but then we have to be careful of any downloaded microcode.
  22  */
  23 #include <linux/errno.h>
  24 #include <linux/sched.h>
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/param.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/module.h>
  33 #include <asm/page.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/8xx_immap.h>
  36 #include <asm/cpm1.h>
  37 #include <asm/io.h>
  38 #include <asm/tlbflush.h>
  39 #include <asm/rheap.h>
  40 #include <asm/prom.h>
  41 #include <asm/cpm.h>
  42
  43 #include <asm/fs_pd.h>
  44
  45 #define CPM_MAP_SIZE    (0x4000)
  46
  47 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
  48 immap_t __iomem *mpc8xx_immr;
  49 static cpic8xx_t __iomem *cpic_reg;
  50
  51 static struct irq_host *cpm_pic_host;
  52
  53 static void cpm_mask_irq(unsigned int irq)
  54 {
  55         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  56
  57         clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  58 }
  59
  60 static void cpm_unmask_irq(unsigned int irq)
  61 {
  62         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  63
  64         setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  65 }
  66
  67 static void cpm_end_irq(unsigned int irq)
  68 {
  69         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  70
  71         out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
  72 }
  73
  74 static struct irq_chip cpm_pic = {
  75         .typename = " CPM PIC ",
  76         .mask = cpm_mask_irq,
  77         .unmask = cpm_unmask_irq,
  78         .eoi = cpm_end_irq,
  79 };
  80
  81 int cpm_get_irq(void)
  82 {
  83         int cpm_vec;
  84
  85         /* Get the vector by setting the ACK bit and then reading
  86          * the register.
  87          */
  88         out_be16(&cpic_reg->cpic_civr, 1);
  89         cpm_vec = in_be16(&cpic_reg->cpic_civr);
  90         cpm_vec >>= 11;
  91
  92         return irq_linear_revmap(cpm_pic_host, cpm_vec);
  93 }
  94
  95 static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
  96                           irq_hw_number_t hw)
  97 {
  98         pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
  99
 100         get_irq_desc(virq)->status |= IRQ_LEVEL;
 101         set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
 102         return 0;
 103 }
 104
 105 /* The CPM can generate the error interrupt when there is a race condition
 106  * between generating and masking interrupts.  All we have to do is ACK it
 107  * and return.  This is a no-op function so we don't need any special
 108  * tests in the interrupt handler.
 109  */
 110 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
 111 {
 112         return IRQ_HANDLED;
 113 }
 114
 115 static struct irqaction cpm_error_irqaction = {
 116         .handler = cpm_error_interrupt,
 117         .mask = CPU_MASK_NONE,
 118         .name = "error",
 119 };
 120
 121 static struct irq_host_ops cpm_pic_host_ops = {
 122         .map = cpm_pic_host_map,
 123 };
 124
 125 unsigned int cpm_pic_init(void)
 126 {
 127         struct device_node *np = NULL;
 128         struct resource res;
 129         unsigned int sirq = NO_IRQ, hwirq, eirq;
 130         int ret;
 131
 132         pr_debug("cpm_pic_init\n");
 133
 134         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
 135         if (np == NULL)
 136                 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
 137         if (np == NULL) {
 138                 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
 139                 return sirq;
 140         }
 141
 142         ret = of_address_to_resource(np, 0, &res);
 143         if (ret)
 144                 goto end;
 145
 146         cpic_reg = ioremap(res.start, res.end - res.start + 1);
 147         if (cpic_reg == NULL)
 148                 goto end;
 149
 150         sirq = irq_of_parse_and_map(np, 0);
 151         if (sirq == NO_IRQ)
 152                 goto end;
 153
 154         /* Initialize the CPM interrupt controller. */
 155         hwirq = (unsigned int)irq_map[sirq].hwirq;
 156         out_be32(&cpic_reg->cpic_cicr,
 157             (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
 158                 ((hwirq/2) << 13) | CICR_HP_MASK);
 159
 160         out_be32(&cpic_reg->cpic_cimr, 0);
 161
 162         cpm_pic_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
 163                                       64, &cpm_pic_host_ops, 64);
 164         if (cpm_pic_host == NULL) {
 165                 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
 166                 sirq = NO_IRQ;
 167                 goto end;
 168         }
 169
 170         /* Install our own error handler. */
 171         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
 172         if (np == NULL)
 173                 np = of_find_node_by_type(NULL, "cpm");
 174         if (np == NULL) {
 175                 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
 176                 goto end;
 177         }
 178
 179         eirq = irq_of_parse_and_map(np, 0);
 180         if (eirq == NO_IRQ)
 181                 goto end;
 182
 183         if (setup_irq(eirq, &cpm_error_irqaction))
 184                 printk(KERN_ERR "Could not allocate CPM error IRQ!");
 185
 186         setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
 187
 188 end:
 189         of_node_put(np);
 190         return sirq;
 191 }
 192
 193 void __init cpm_reset(void)
 194 {
 195         sysconf8xx_t __iomem *siu_conf;
 196
 197         mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
 198         if (!mpc8xx_immr) {
 199                 printk(KERN_CRIT "Could not map IMMR\n");
 200                 return;
 201         }
 202
 203         cpmp = &mpc8xx_immr->im_cpm;
 204
 205 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
 206         /* Perform a reset.
 207         */
 208         out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
 209
 210         /* Wait for it.
 211         */
 212         while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
 213 #endif
 214
 215 #ifdef CONFIG_UCODE_PATCH
 216         cpm_load_patch(cpmp);
 217 #endif
 218
 219         /* Set SDMA Bus Request priority 5.
 220          * On 860T, this also enables FEC priority 6.  I am not sure
 221          * this is what we realy want for some applications, but the
 222          * manual recommends it.
 223          * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
 224          */
 225         siu_conf = immr_map(im_siu_conf);
 226         out_be32(&siu_conf->sc_sdcr, 1);
 227         immr_unmap(siu_conf);
 228
 229         cpm_muram_init();
 230 }
 231
 232 static DEFINE_SPINLOCK(cmd_lock);
 233
 234 #define MAX_CR_CMD_LOOPS        10000
 235
 236 int cpm_command(u32 command, u8 opcode)
 237 {
 238         int i, ret;
 239         unsigned long flags;
 240
 241         if (command & 0xffffff0f)
 242                 return -EINVAL;
 243
 244         spin_lock_irqsave(&cmd_lock, flags);
 245
 246         ret = 0;
 247         out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
 248         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
 249                 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
 250                         goto out;
 251
 252         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
 253         ret = -EIO;
 254 out:
 255         spin_unlock_irqrestore(&cmd_lock, flags);
 256         return ret;
 257 }
 258 EXPORT_SYMBOL(cpm_command);
 259
 260 /* Set a baud rate generator.  This needs lots of work.  There are
 261  * four BRGs, any of which can be wired to any channel.
 262  * The internal baud rate clock is the system clock divided by 16.
 263  * This assumes the baudrate is 16x oversampled by the uart.
 264  */
 265 #define BRG_INT_CLK             (get_brgfreq())
 266 #define BRG_UART_CLK            (BRG_INT_CLK/16)
 267 #define BRG_UART_CLK_DIV16      (BRG_UART_CLK/16)
 268
 269 void
 270 cpm_setbrg(uint brg, uint rate)
 271 {
 272         u32 __iomem *bp;
 273
 274         /* This is good enough to get SMCs running.....
 275         */
 276         bp = &cpmp->cp_brgc1;
 277         bp += brg;
 278         /* The BRG has a 12-bit counter.  For really slow baud rates (or
 279          * really fast processors), we may have to further divide by 16.
 280          */
 281         if (((BRG_UART_CLK / rate) - 1) < 4096)
 282                 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
 283         else
 284                 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
 285                               CPM_BRG_EN | CPM_BRG_DIV16);
 286 }
 287
 288 struct cpm_ioport16 {
 289         __be16 dir, par, odr_sor, dat, intr;
 290         __be16 res[3];
 291 };
 292
 293 struct cpm_ioport32 {
 294         __be32 dir, par, sor;
 295 };
 296
 297 static void cpm1_set_pin32(int port, int pin, int flags)
 298 {
 299         struct cpm_ioport32 __iomem *iop;
 300         pin = 1 << (31 - pin);
 301
 302         if (port == CPM_PORTB)
 303                 iop = (struct cpm_ioport32 __iomem *)
 304                       &mpc8xx_immr->im_cpm.cp_pbdir;
 305         else
 306                 iop = (struct cpm_ioport32 __iomem *)
 307                       &mpc8xx_immr->im_cpm.cp_pedir;
 308
 309         if (flags & CPM_PIN_OUTPUT)
 310                 setbits32(&iop->dir, pin);
 311         else
 312                 clrbits32(&iop->dir, pin);
 313
 314         if (!(flags & CPM_PIN_GPIO))
 315                 setbits32(&iop->par, pin);
 316         else
 317                 clrbits32(&iop->par, pin);
 318
 319         if (port == CPM_PORTB) {
 320                 if (flags & CPM_PIN_OPENDRAIN)
 321                         setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 322                 else
 323                         clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 324         }
 325
 326         if (port == CPM_PORTE) {
 327                 if (flags & CPM_PIN_SECONDARY)
 328                         setbits32(&iop->sor, pin);
 329                 else
 330                         clrbits32(&iop->sor, pin);
 331
 332                 if (flags & CPM_PIN_OPENDRAIN)
 333                         setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 334                 else
 335                         clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 336         }
 337 }
 338
 339 static void cpm1_set_pin16(int port, int pin, int flags)
 340 {
 341         struct cpm_ioport16 __iomem *iop =
 342                 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
 343
 344         pin = 1 << (15 - pin);
 345
 346         if (port != 0)
 347                 iop += port - 1;
 348
 349         if (flags & CPM_PIN_OUTPUT)
 350                 setbits16(&iop->dir, pin);
 351         else
 352                 clrbits16(&iop->dir, pin);
 353
 354         if (!(flags & CPM_PIN_GPIO))
 355                 setbits16(&iop->par, pin);
 356         else
 357                 clrbits16(&iop->par, pin);
 358
 359         if (port == CPM_PORTA) {
 360                 if (flags & CPM_PIN_OPENDRAIN)
 361                         setbits16(&iop->odr_sor, pin);
 362                 else
 363                         clrbits16(&iop->odr_sor, pin);
 364         }
 365         if (port == CPM_PORTC) {
 366                 if (flags & CPM_PIN_SECONDARY)
 367                         setbits16(&iop->odr_sor, pin);
 368                 else
 369                         clrbits16(&iop->odr_sor, pin);
 370         }
 371 }
 372
 373 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
 374 {
 375         if (port == CPM_PORTB || port == CPM_PORTE)
 376                 cpm1_set_pin32(port, pin, flags);
 377         else
 378                 cpm1_set_pin16(port, pin, flags);
 379 }
 380
 381 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
 382 {
 383         int shift;
 384         int i, bits = 0;
 385         u32 __iomem *reg;
 386         u32 mask = 7;
 387
 388         u8 clk_map[][3] = {
 389                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 390                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 391                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 392                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 393                 {CPM_CLK_SCC1, CPM_CLK1, 4},
 394                 {CPM_CLK_SCC1, CPM_CLK2, 5},
 395                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 396                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 397
 398                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 399                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 400                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 401                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 402                 {CPM_CLK_SCC2, CPM_CLK1, 4},
 403                 {CPM_CLK_SCC2, CPM_CLK2, 5},
 404                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 405                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 406
 407                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 408                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 409                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 410                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 411                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 412                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 413                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 414                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 415
 416                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 417                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 418                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 419                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 420                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 421                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 422                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 423                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 424
 425                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 426                 {CPM_CLK_SMC1, CPM_BRG2, 1},
 427                 {CPM_CLK_SMC1, CPM_BRG3, 2},
 428                 {CPM_CLK_SMC1, CPM_BRG4, 3},
 429                 {CPM_CLK_SMC1, CPM_CLK1, 4},
 430                 {CPM_CLK_SMC1, CPM_CLK2, 5},
 431                 {CPM_CLK_SMC1, CPM_CLK3, 6},
 432                 {CPM_CLK_SMC1, CPM_CLK4, 7},
 433
 434                 {CPM_CLK_SMC2, CPM_BRG1, 0},
 435                 {CPM_CLK_SMC2, CPM_BRG2, 1},
 436                 {CPM_CLK_SMC2, CPM_BRG3, 2},
 437                 {CPM_CLK_SMC2, CPM_BRG4, 3},
 438                 {CPM_CLK_SMC2, CPM_CLK5, 4},
 439                 {CPM_CLK_SMC2, CPM_CLK6, 5},
 440                 {CPM_CLK_SMC2, CPM_CLK7, 6},
 441                 {CPM_CLK_SMC2, CPM_CLK8, 7},
 442         };
 443
 444         switch (target) {
 445         case CPM_CLK_SCC1:
 446                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 447                 shift = 0;
 448                 break;
 449
 450         case CPM_CLK_SCC2:
 451                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 452                 shift = 8;
 453                 break;
 454
 455         case CPM_CLK_SCC3:
 456                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 457                 shift = 16;
 458                 break;
 459
 460         case CPM_CLK_SCC4:
 461                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 462                 shift = 24;
 463                 break;
 464
 465         case CPM_CLK_SMC1:
 466                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 467                 shift = 12;
 468                 break;
 469
 470         case CPM_CLK_SMC2:
 471                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 472                 shift = 28;
 473                 break;
 474
 475         default:
 476                 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
 477                 return -EINVAL;
 478         }
 479
 480         if (reg == &mpc8xx_immr->im_cpm.cp_sicr && mode == CPM_CLK_RX)
 481                 shift += 3;
 482
 483         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 484                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 485                         bits = clk_map[i][2];
 486                         break;
 487                 }
 488         }
 489
 490         if (i == ARRAY_SIZE(clk_map)) {
 491                 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
 492                 return -EINVAL;
 493         }
 494
 495         bits <<= shift;
 496         mask <<= shift;
 497         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 498
 499         return 0;
 500 }