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   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Virtual clocks are introduced as a convenient tools.
   5  * They are sources for other clocks and not supposed
   6  * to be requested from drivers directly.
   7  *
   8  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   9  * Copyright (C) 2007-2008 Nokia Corporation
  10  *
  11  * Written by Paul Walmsley
  12  */
  13
  14 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  15 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  16
  17 #include <asm/arch/control.h>
  18
  19 #include "clock.h"
  20 #include "cm.h"
  21 #include "cm-regbits-34xx.h"
  22 #include "prm.h"
  23 #include "prm-regbits-34xx.h"
  24
  25 static void omap3_dpll_recalc(struct clk *clk);
  26 static void omap3_clkoutx2_recalc(struct clk *clk);
  27
  28 /*
  29  * DPLL1 supplies clock to the MPU.
  30  * DPLL2 supplies clock to the IVA2.
  31  * DPLL3 supplies CORE domain clocks.
  32  * DPLL4 supplies peripheral clocks.
  33  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  34  */
  35
  36 /* PRM CLOCKS */
  37
  38 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  39 static struct clk omap_32k_fck = {
  40         .name           = "omap_32k_fck",
  41         .rate           = 32768,
  42         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  43                                 ALWAYS_ENABLED,
  44         .recalc         = &propagate_rate,
  45 };
  46
  47 static struct clk secure_32k_fck = {
  48         .name           = "secure_32k_fck",
  49         .rate           = 32768,
  50         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  51                                 ALWAYS_ENABLED,
  52         .recalc         = &propagate_rate,
  53 };
  54
  55 /* Virtual source clocks for osc_sys_ck */
  56 static struct clk virt_12m_ck = {
  57         .name           = "virt_12m_ck",
  58         .rate           = 12000000,
  59         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  60                                 ALWAYS_ENABLED,
  61         .recalc         = &propagate_rate,
  62 };
  63
  64 static struct clk virt_13m_ck = {
  65         .name           = "virt_13m_ck",
  66         .rate           = 13000000,
  67         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  68                                 ALWAYS_ENABLED,
  69         .recalc         = &propagate_rate,
  70 };
  71
  72 static struct clk virt_16_8m_ck = {
  73         .name           = "virt_16_8m_ck",
  74         .rate           = 16800000,
  75         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
  76                                 ALWAYS_ENABLED,
  77         .recalc         = &propagate_rate,
  78 };
  79
  80 static struct clk virt_19_2m_ck = {
  81         .name           = "virt_19_2m_ck",
  82         .rate           = 19200000,
  83         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  84                                 ALWAYS_ENABLED,
  85         .recalc         = &propagate_rate,
  86 };
  87
  88 static struct clk virt_26m_ck = {
  89         .name           = "virt_26m_ck",
  90         .rate           = 26000000,
  91         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  92                                 ALWAYS_ENABLED,
  93         .recalc         = &propagate_rate,
  94 };
  95
  96 static struct clk virt_38_4m_ck = {
  97         .name           = "virt_38_4m_ck",
  98         .rate           = 38400000,
  99         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 100                                 ALWAYS_ENABLED,
 101         .recalc         = &propagate_rate,
 102 };
 103
 104 static const struct clksel_rate osc_sys_12m_rates[] = {
 105         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 106         { .div = 0 }
 107 };
 108
 109 static const struct clksel_rate osc_sys_13m_rates[] = {
 110         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 111         { .div = 0 }
 112 };
 113
 114 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 115         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 116         { .div = 0 }
 117 };
 118
 119 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 120         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 121         { .div = 0 }
 122 };
 123
 124 static const struct clksel_rate osc_sys_26m_rates[] = {
 125         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 126         { .div = 0 }
 127 };
 128
 129 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 130         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 131         { .div = 0 }
 132 };
 133
 134 static const struct clksel osc_sys_clksel[] = {
 135         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 136         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 137         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 138         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 139         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 140         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 141         { .parent = NULL },
 142 };
 143
 144 /* Oscillator clock */
 145 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 146 static struct clk osc_sys_ck = {
 147         .name           = "osc_sys_ck",
 148         .init           = &omap2_init_clksel_parent,
 149         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 150         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 151         .clksel         = osc_sys_clksel,
 152         /* REVISIT: deal with autoextclkmode? */
 153         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 154                                 ALWAYS_ENABLED,
 155         .recalc         = &omap2_clksel_recalc,
 156 };
 157
 158 static const struct clksel_rate div2_rates[] = {
 159         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 160         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 161         { .div = 0 }
 162 };
 163
 164 static const struct clksel sys_clksel[] = {
 165         { .parent = &osc_sys_ck, .rates = div2_rates },
 166         { .parent = NULL }
 167 };
 168
 169 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 170 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 171 static struct clk sys_ck = {
 172         .name           = "sys_ck",
 173         .parent         = &osc_sys_ck,
 174         .init           = &omap2_init_clksel_parent,
 175         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 176         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 177         .clksel         = sys_clksel,
 178         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 179         .recalc         = &omap2_clksel_recalc,
 180 };
 181
 182 static struct clk sys_altclk = {
 183         .name           = "sys_altclk",
 184         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 185         .recalc         = &propagate_rate,
 186 };
 187
 188 /* Optional external clock input for some McBSPs */
 189 static struct clk mcbsp_clks = {
 190         .name           = "mcbsp_clks",
 191         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 192         .recalc         = &propagate_rate,
 193 };
 194
 195 /* PRM EXTERNAL CLOCK OUTPUT */
 196
 197 static struct clk sys_clkout1 = {
 198         .name           = "sys_clkout1",
 199         .parent         = &osc_sys_ck,
 200         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 201         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 202         .flags          = CLOCK_IN_OMAP343X,
 203         .recalc         = &followparent_recalc,
 204 };
 205
 206 /* DPLLS */
 207
 208 /* CM CLOCKS */
 209
 210 static const struct clksel_rate dpll_bypass_rates[] = {
 211         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 212         { .div = 0 }
 213 };
 214
 215 static const struct clksel_rate dpll_locked_rates[] = {
 216         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 217         { .div = 0 }
 218 };
 219
 220 static const struct clksel_rate div16_dpll_rates[] = {
 221         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 222         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 223         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 224         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 225         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 226         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 227         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 228         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 229         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 230         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 231         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 232         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 233         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 234         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 235         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 236         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 237         { .div = 0 }
 238 };
 239
 240 /* DPLL1 */
 241 /* MPU clock source */
 242 /* Type: DPLL */
 243 static const struct dpll_data dpll1_dd = {
 244         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 245         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 246         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 247         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 248         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 249         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 250         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 251         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 252 };
 253
 254 static struct clk dpll1_ck = {
 255         .name           = "dpll1_ck",
 256         .parent         = &sys_ck,
 257         .dpll_data      = &dpll1_dd,
 258         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 259         .recalc         = &omap3_dpll_recalc,
 260 };
 261
 262 /*
 263  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 264  * DPLL isn't bypassed.
 265  */
 266 static struct clk dpll1_x2_ck = {
 267         .name           = "dpll1_x2_ck",
 268         .parent         = &dpll1_ck,
 269         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 270                                 PARENT_CONTROLS_CLOCK,
 271         .recalc         = &omap3_clkoutx2_recalc,
 272 };
 273
 274 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 275 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 276         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 277         { .parent = NULL }
 278 };
 279
 280 /*
 281  * Does not exist in the TRM - needed to separate the M2 divider from
 282  * bypass selection in mpu_ck
 283  */
 284 static struct clk dpll1_x2m2_ck = {
 285         .name           = "dpll1_x2m2_ck",
 286         .parent         = &dpll1_x2_ck,
 287         .init           = &omap2_init_clksel_parent,
 288         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 289         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 290         .clksel         = div16_dpll1_x2m2_clksel,
 291         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 292                                 PARENT_CONTROLS_CLOCK,
 293         .recalc         = &omap2_clksel_recalc,
 294 };
 295
 296 /* DPLL2 */
 297 /* IVA2 clock source */
 298 /* Type: DPLL */
 299
 300 static const struct dpll_data dpll2_dd = {
 301         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 302         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 303         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 304         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 305         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 306         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 307         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 308         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 309 };
 310
 311 static struct clk dpll2_ck = {
 312         .name           = "dpll2_ck",
 313         .parent         = &sys_ck,
 314         .dpll_data      = &dpll2_dd,
 315         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 316         .recalc         = &omap3_dpll_recalc,
 317 };
 318
 319 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 320         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 321         { .parent = NULL }
 322 };
 323
 324 /*
 325  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 326  * or CLKOUTX2. CLKOUT seems most plausible.
 327  */
 328 static struct clk dpll2_m2_ck = {
 329         .name           = "dpll2_m2_ck",
 330         .parent         = &dpll2_ck,
 331         .init           = &omap2_init_clksel_parent,
 332         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 333                                           OMAP3430_CM_CLKSEL2_PLL),
 334         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 335         .clksel         = div16_dpll2_m2x2_clksel,
 336         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 337                                 PARENT_CONTROLS_CLOCK,
 338         .recalc         = &omap2_clksel_recalc,
 339 };
 340
 341 /* DPLL3 */
 342 /* Source clock for all interfaces and for some device fclks */
 343 /* Type: DPLL */
 344 static const struct dpll_data dpll3_dd = {
 345         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 346         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 347         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 348         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 349         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 350         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 351         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 352         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 353 };
 354
 355 static struct clk dpll3_ck = {
 356         .name           = "dpll3_ck",
 357         .parent         = &sys_ck,
 358         .dpll_data      = &dpll3_dd,
 359         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 360         .recalc         = &omap3_dpll_recalc,
 361 };
 362
 363 /*
 364  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 365  * DPLL isn't bypassed
 366  */
 367 static struct clk dpll3_x2_ck = {
 368         .name           = "dpll3_x2_ck",
 369         .parent         = &dpll3_ck,
 370         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 371                                 PARENT_CONTROLS_CLOCK,
 372         .recalc         = &omap3_clkoutx2_recalc,
 373 };
 374
 375 static const struct clksel_rate div31_dpll3_rates[] = {
 376         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 377         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 378         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 379         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 380         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 381         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 382         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 383         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 384         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 385         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 386         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 387         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 388         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 389         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 390         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 391         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 392         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 393         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 394         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 395         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 396         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 397         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 398         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 399         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 400         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 401         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 402         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 403         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 404         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 405         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 406         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 407         { .div = 0 },
 408 };
 409
 410 static const struct clksel div31_dpll3m2_clksel[] = {
 411         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 412         { .parent = NULL }
 413 };
 414
 415 /*
 416  * DPLL3 output M2
 417  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 418  * that code is ready, this should remain a 'read-only' clksel clock.
 419  */
 420 static struct clk dpll3_m2_ck = {
 421         .name           = "dpll3_m2_ck",
 422         .parent         = &dpll3_ck,
 423         .init           = &omap2_init_clksel_parent,
 424         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 425         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 426         .clksel         = div31_dpll3m2_clksel,
 427         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 428                                 PARENT_CONTROLS_CLOCK,
 429         .recalc         = &omap2_clksel_recalc,
 430 };
 431
 432 static const struct clksel core_ck_clksel[] = {
 433         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 434         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 435         { .parent = NULL }
 436 };
 437
 438 static struct clk core_ck = {
 439         .name           = "core_ck",
 440         .init           = &omap2_init_clksel_parent,
 441         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 442         .clksel_mask    = OMAP3430_ST_CORE_CLK,
 443         .clksel         = core_ck_clksel,
 444         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 445                                 PARENT_CONTROLS_CLOCK,
 446         .recalc         = &omap2_clksel_recalc,
 447 };
 448
 449 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 450         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 451         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 452         { .parent = NULL }
 453 };
 454
 455 static struct clk dpll3_m2x2_ck = {
 456         .name           = "dpll3_m2x2_ck",
 457         .init           = &omap2_init_clksel_parent,
 458         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 459         .clksel_mask    = OMAP3430_ST_CORE_CLK,
 460         .clksel         = dpll3_m2x2_ck_clksel,
 461         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 462                                 PARENT_CONTROLS_CLOCK,
 463         .recalc         = &omap2_clksel_recalc,
 464 };
 465
 466 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 467 static const struct clksel div16_dpll3_clksel[] = {
 468         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 469         { .parent = NULL }
 470 };
 471
 472 /* This virtual clock is the source for dpll3_m3x2_ck */
 473 static struct clk dpll3_m3_ck = {
 474         .name           = "dpll3_m3_ck",
 475         .parent         = &dpll3_ck,
 476         .init           = &omap2_init_clksel_parent,
 477         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 478         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 479         .clksel         = div16_dpll3_clksel,
 480         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 481                                 PARENT_CONTROLS_CLOCK,
 482         .recalc         = &omap2_clksel_recalc,
 483 };
 484
 485 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 486 static struct clk dpll3_m3x2_ck = {
 487         .name           = "dpll3_m3x2_ck",
 488         .parent         = &dpll3_m3_ck,
 489         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 490         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 491         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 492         .recalc         = &omap3_clkoutx2_recalc,
 493 };
 494
 495 static const struct clksel emu_core_alwon_ck_clksel[] = {
 496         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 497         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 498         { .parent = NULL }
 499 };
 500
 501 static struct clk emu_core_alwon_ck = {
 502         .name           = "emu_core_alwon_ck",
 503         .parent         = &dpll3_m3x2_ck,
 504         .init           = &omap2_init_clksel_parent,
 505         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 506         .clksel_mask    = OMAP3430_ST_CORE_CLK,
 507         .clksel         = emu_core_alwon_ck_clksel,
 508         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 509                                 PARENT_CONTROLS_CLOCK,
 510         .recalc         = &omap2_clksel_recalc,
 511 };
 512
 513 /* DPLL4 */
 514 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 515 /* Type: DPLL */
 516 static const struct dpll_data dpll4_dd = {
 517         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 518         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 519         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 520         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 521         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 522         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 523         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 524         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 525 };
 526
 527 static struct clk dpll4_ck = {
 528         .name           = "dpll4_ck",
 529         .parent         = &sys_ck,
 530         .dpll_data      = &dpll4_dd,
 531         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 532         .recalc         = &omap3_dpll_recalc,
 533 };
 534
 535 /*
 536  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 537  * DPLL isn't bypassed --
 538  * XXX does this serve any downstream clocks?
 539  */
 540 static struct clk dpll4_x2_ck = {
 541         .name           = "dpll4_x2_ck",
 542         .parent         = &dpll4_ck,
 543         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 544                                 PARENT_CONTROLS_CLOCK,
 545         .recalc         = &omap3_clkoutx2_recalc,
 546 };
 547
 548 static const struct clksel div16_dpll4_clksel[] = {
 549         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 550         { .parent = NULL }
 551 };
 552
 553 /* This virtual clock is the source for dpll4_m2x2_ck */
 554 static struct clk dpll4_m2_ck = {
 555         .name           = "dpll4_m2_ck",
 556         .parent         = &dpll4_ck,
 557         .init           = &omap2_init_clksel_parent,
 558         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 559         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 560         .clksel         = div16_dpll4_clksel,
 561         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 562                                 PARENT_CONTROLS_CLOCK,
 563         .recalc         = &omap2_clksel_recalc,
 564 };
 565
 566 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 567 static struct clk dpll4_m2x2_ck = {
 568         .name           = "dpll4_m2x2_ck",
 569         .parent         = &dpll4_m2_ck,
 570         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 571         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 572         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 573         .recalc         = &omap3_clkoutx2_recalc,
 574 };
 575
 576 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 577         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 578         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 579         { .parent = NULL }
 580 };
 581
 582 static struct clk omap_96m_alwon_fck = {
 583         .name           = "omap_96m_alwon_fck",
 584         .parent         = &dpll4_m2x2_ck,
 585         .init           = &omap2_init_clksel_parent,
 586         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 587         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
 588         .clksel         = omap_96m_alwon_fck_clksel,
 589         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 590                                  PARENT_CONTROLS_CLOCK,
 591         .recalc         = &omap2_clksel_recalc,
 592 };
 593
 594 static struct clk omap_96m_fck = {
 595         .name           = "omap_96m_fck",
 596         .parent         = &omap_96m_alwon_fck,
 597         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 598                                 PARENT_CONTROLS_CLOCK,
 599         .recalc         = &followparent_recalc,
 600 };
 601
 602 static const struct clksel cm_96m_fck_clksel[] = {
 603         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 604         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 605         { .parent = NULL }
 606 };
 607
 608 static struct clk cm_96m_fck = {
 609         .name           = "cm_96m_fck",
 610         .parent         = &dpll4_m2x2_ck,
 611         .init           = &omap2_init_clksel_parent,
 612         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 613         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
 614         .clksel         = cm_96m_fck_clksel,
 615         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 616                                 PARENT_CONTROLS_CLOCK,
 617         .recalc         = &omap2_clksel_recalc,
 618 };
 619
 620 /* This virtual clock is the source for dpll4_m3x2_ck */
 621 static struct clk dpll4_m3_ck = {
 622         .name           = "dpll4_m3_ck",
 623         .parent         = &dpll4_ck,
 624         .init           = &omap2_init_clksel_parent,
 625         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 626         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 627         .clksel         = div16_dpll4_clksel,
 628         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 629                                 PARENT_CONTROLS_CLOCK,
 630         .recalc         = &omap2_clksel_recalc,
 631 };
 632
 633 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 634 static struct clk dpll4_m3x2_ck = {
 635         .name           = "dpll4_m3x2_ck",
 636         .parent         = &dpll4_m3_ck,
 637         .init           = &omap2_init_clksel_parent,
 638         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 639         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 640         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 641         .recalc         = &omap3_clkoutx2_recalc,
 642 };
 643
 644 static const struct clksel virt_omap_54m_fck_clksel[] = {
 645         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 646         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 647         { .parent = NULL }
 648 };
 649
 650 static struct clk virt_omap_54m_fck = {
 651         .name           = "virt_omap_54m_fck",
 652         .parent         = &dpll4_m3x2_ck,
 653         .init           = &omap2_init_clksel_parent,
 654         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 655         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
 656         .clksel         = virt_omap_54m_fck_clksel,
 657         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 658                                 PARENT_CONTROLS_CLOCK,
 659         .recalc         = &omap2_clksel_recalc,
 660 };
 661
 662 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 663         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 664         { .div = 0 }
 665 };
 666
 667 static const struct clksel_rate omap_54m_alt_rates[] = {
 668         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 669         { .div = 0 }
 670 };
 671
 672 static const struct clksel omap_54m_clksel[] = {
 673         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 674         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 675         { .parent = NULL }
 676 };
 677
 678 static struct clk omap_54m_fck = {
 679         .name           = "omap_54m_fck",
 680         .init           = &omap2_init_clksel_parent,
 681         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 682         .clksel_mask    = OMAP3430_SOURCE_54M,
 683         .clksel         = omap_54m_clksel,
 684         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 685                                 PARENT_CONTROLS_CLOCK,
 686         .recalc         = &omap2_clksel_recalc,
 687 };
 688
 689 static const struct clksel_rate omap_48m_96md2_rates[] = {
 690         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 691         { .div = 0 }
 692 };
 693
 694 static const struct clksel_rate omap_48m_alt_rates[] = {
 695         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 696         { .div = 0 }
 697 };
 698
 699 static const struct clksel omap_48m_clksel[] = {
 700         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 701         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 702         { .parent = NULL }
 703 };
 704
 705 static struct clk omap_48m_fck = {
 706         .name           = "omap_48m_fck",
 707         .init           = &omap2_init_clksel_parent,
 708         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 709         .clksel_mask    = OMAP3430_SOURCE_48M,
 710         .clksel         = omap_48m_clksel,
 711         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 712                                 PARENT_CONTROLS_CLOCK,
 713         .recalc         = &omap2_clksel_recalc,
 714 };
 715
 716 static struct clk omap_12m_fck = {
 717         .name           = "omap_12m_fck",
 718         .parent         = &omap_48m_fck,
 719         .fixed_div      = 4,
 720         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 721                                 PARENT_CONTROLS_CLOCK,
 722         .recalc         = &omap2_fixed_divisor_recalc,
 723 };
 724
 725 /* This virstual clock is the source for dpll4_m4x2_ck */
 726 static struct clk dpll4_m4_ck = {
 727         .name           = "dpll4_m4_ck",
 728         .parent         = &dpll4_ck,
 729         .init           = &omap2_init_clksel_parent,
 730         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 731         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 732         .clksel         = div16_dpll4_clksel,
 733         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 734                                 PARENT_CONTROLS_CLOCK,
 735         .recalc         = &omap2_clksel_recalc,
 736 };
 737
 738 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 739 static struct clk dpll4_m4x2_ck = {
 740         .name           = "dpll4_m4x2_ck",
 741         .parent         = &dpll4_m4_ck,
 742         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 743         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 744         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 745         .recalc         = &omap3_clkoutx2_recalc,
 746 };
 747
 748 /* This virtual clock is the source for dpll4_m5x2_ck */
 749 static struct clk dpll4_m5_ck = {
 750         .name           = "dpll4_m5_ck",
 751         .parent         = &dpll4_ck,
 752         .init           = &omap2_init_clksel_parent,
 753         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 754         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 755         .clksel         = div16_dpll4_clksel,
 756         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 757                                 PARENT_CONTROLS_CLOCK,
 758         .recalc         = &omap2_clksel_recalc,
 759 };
 760
 761 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 762 static struct clk dpll4_m5x2_ck = {
 763         .name           = "dpll4_m5x2_ck",
 764         .parent         = &dpll4_m5_ck,
 765         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 766         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 767         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 768         .recalc         = &omap3_clkoutx2_recalc,
 769 };
 770
 771 /* This virtual clock is the source for dpll4_m6x2_ck */
 772 static struct clk dpll4_m6_ck = {
 773         .name           = "dpll4_m6_ck",
 774         .parent         = &dpll4_ck,
 775         .init           = &omap2_init_clksel_parent,
 776         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 777         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 778         .clksel         = div16_dpll4_clksel,
 779         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 780                                 PARENT_CONTROLS_CLOCK,
 781         .recalc         = &omap2_clksel_recalc,
 782 };
 783
 784 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 785 static struct clk dpll4_m6x2_ck = {
 786         .name           = "dpll4_m6x2_ck",
 787         .parent         = &dpll4_m6_ck,
 788         .init           = &omap2_init_clksel_parent,
 789         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 790         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 791         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 792         .recalc         = &omap3_clkoutx2_recalc,
 793 };
 794
 795 static struct clk emu_per_alwon_ck = {
 796         .name           = "emu_per_alwon_ck",
 797         .parent         = &dpll4_m6x2_ck,
 798         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 799                                 PARENT_CONTROLS_CLOCK,
 800         .recalc         = &followparent_recalc,
 801 };
 802
 803 /* DPLL5 */
 804 /* Supplies 120MHz clock, USIM source clock */
 805 /* Type: DPLL */
 806 /* 3430ES2 only */
 807 static const struct dpll_data dpll5_dd = {
 808         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 809         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 810         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 811         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 812         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 813         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 814         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 815         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 816 };
 817
 818 static struct clk dpll5_ck = {
 819         .name           = "dpll5_ck",
 820         .parent         = &sys_ck,
 821         .dpll_data      = &dpll5_dd,
 822         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 823                                 ALWAYS_ENABLED,
 824         .recalc         = &omap3_dpll_recalc,
 825 };
 826
 827 static const struct clksel div16_dpll5_clksel[] = {
 828         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 829         { .parent = NULL }
 830 };
 831
 832 static struct clk dpll5_m2_ck = {
 833         .name           = "dpll5_m2_ck",
 834         .parent         = &dpll5_ck,
 835         .init           = &omap2_init_clksel_parent,
 836         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 837         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 838         .clksel         = div16_dpll5_clksel,
 839         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 840                                 PARENT_CONTROLS_CLOCK,
 841         .recalc         = &omap2_clksel_recalc,
 842 };
 843
 844 static const struct clksel omap_120m_fck_clksel[] = {
 845         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 846         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 847         { .parent = NULL }
 848 };
 849
 850 static struct clk omap_120m_fck = {
 851         .name           = "omap_120m_fck",
 852         .parent         = &dpll5_m2_ck,
 853         .init           = &omap2_init_clksel_parent,
 854         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 855         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 856         .clksel         = omap_120m_fck_clksel,
 857         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 858                                 PARENT_CONTROLS_CLOCK,
 859         .recalc         = &omap2_clksel_recalc,
 860 };
 861
 862 /* CM EXTERNAL CLOCK OUTPUTS */
 863
 864 static const struct clksel_rate clkout2_src_core_rates[] = {
 865         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 866         { .div = 0 }
 867 };
 868
 869 static const struct clksel_rate clkout2_src_sys_rates[] = {
 870         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 871         { .div = 0 }
 872 };
 873
 874 static const struct clksel_rate clkout2_src_96m_rates[] = {
 875         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 876         { .div = 0 }
 877 };
 878
 879 static const struct clksel_rate clkout2_src_54m_rates[] = {
 880         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 881         { .div = 0 }
 882 };
 883
 884 static const struct clksel clkout2_src_clksel[] = {
 885         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 886         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 887         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 888         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 889         { .parent = NULL }
 890 };
 891
 892 static struct clk clkout2_src_ck = {
 893         .name           = "clkout2_src_ck",
 894         .init           = &omap2_init_clksel_parent,
 895         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 896         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 897         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 898         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 899         .clksel         = clkout2_src_clksel,
 900         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 901         .recalc         = &omap2_clksel_recalc,
 902 };
 903
 904 static const struct clksel_rate sys_clkout2_rates[] = {
 905         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 906         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 907         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 908         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 909         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 910         { .div = 0 },
 911 };
 912
 913 static const struct clksel sys_clkout2_clksel[] = {
 914         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 915         { .parent = NULL },
 916 };
 917
 918 static struct clk sys_clkout2 = {
 919         .name           = "sys_clkout2",
 920         .init           = &omap2_init_clksel_parent,
 921         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 922         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 923         .clksel         = sys_clkout2_clksel,
 924         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 925         .recalc         = &omap2_clksel_recalc,
 926 };
 927
 928 /* CM OUTPUT CLOCKS */
 929
 930 static struct clk corex2_fck = {
 931         .name           = "corex2_fck",
 932         .parent         = &dpll3_m2x2_ck,
 933         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 934                                 PARENT_CONTROLS_CLOCK,
 935         .recalc         = &followparent_recalc,
 936 };
 937
 938 /* DPLL power domain clock controls */
 939
 940 static const struct clksel div2_core_clksel[] = {
 941         { .parent = &core_ck, .rates = div2_rates },
 942         { .parent = NULL }
 943 };
 944
 945 /*
 946  * REVISIT: Are these in DPLL power domain or CM power domain? docs
 947  * may be inconsistent here?
 948  */
 949 static struct clk dpll1_fck = {
 950         .name           = "dpll1_fck",
 951         .parent         = &core_ck,
 952         .init           = &omap2_init_clksel_parent,
 953         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 954         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
 955         .clksel         = div2_core_clksel,
 956         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 957                                 PARENT_CONTROLS_CLOCK,
 958         .recalc         = &omap2_clksel_recalc,
 959 };
 960
 961 /*
 962  * MPU clksel:
 963  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
 964  * derives from the high-frequency bypass clock originating from DPLL3,
 965  * called 'dpll1_fck'
 966  */
 967 static const struct clksel mpu_clksel[] = {
 968         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
 969         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
 970         { .parent = NULL }
 971 };
 972
 973 static struct clk mpu_ck = {
 974         .name           = "mpu_ck",
 975         .parent         = &dpll1_x2m2_ck,
 976         .init           = &omap2_init_clksel_parent,
 977         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 978         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
 979         .clksel         = mpu_clksel,
 980         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 981                                 PARENT_CONTROLS_CLOCK,
 982         .recalc         = &omap2_clksel_recalc,
 983 };
 984
 985 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
 986 static const struct clksel_rate arm_fck_rates[] = {
 987         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 988         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 989         { .div = 0 },
 990 };
 991
 992 static const struct clksel arm_fck_clksel[] = {
 993         { .parent = &mpu_ck, .rates = arm_fck_rates },
 994         { .parent = NULL }
 995 };
 996
 997 static struct clk arm_fck = {
 998         .name           = "arm_fck",
 999         .parent         = &mpu_ck,
1000         .init           = &omap2_init_clksel_parent,
1001         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1002         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1003         .clksel         = arm_fck_clksel,
1004         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1005                                 PARENT_CONTROLS_CLOCK,
1006         .recalc         = &omap2_clksel_recalc,
1007 };
1008
1009 /*
1010  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1011  * although it is referenced - so this is a guess
1012  */
1013 static struct clk emu_mpu_alwon_ck = {
1014         .name           = "emu_mpu_alwon_ck",
1015         .parent         = &mpu_ck,
1016         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1017                                 PARENT_CONTROLS_CLOCK,
1018         .recalc         = &followparent_recalc,
1019 };
1020
1021 static struct clk dpll2_fck = {
1022         .name           = "dpll2_fck",
1023         .parent         = &core_ck,
1024         .init           = &omap2_init_clksel_parent,
1025         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1026         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1027         .clksel         = div2_core_clksel,
1028         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1029                                 PARENT_CONTROLS_CLOCK,
1030         .recalc         = &omap2_clksel_recalc,
1031 };
1032
1033 /*
1034  * IVA2 clksel:
1035  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1036  * derives from the high-frequency bypass clock originating from DPLL3,
1037  * called 'dpll2_fck'
1038  */
1039
1040 static const struct clksel iva2_clksel[] = {
1041         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1042         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1043         { .parent = NULL }
1044 };
1045
1046 static struct clk iva2_ck = {
1047         .name           = "iva2_ck",
1048         .parent         = &dpll2_m2_ck,
1049         .init           = &omap2_init_clksel_parent,
1050         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1051         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1052         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1053                                           OMAP3430_CM_IDLEST_PLL),
1054         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1055         .clksel         = iva2_clksel,
1056         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1057         .recalc         = &omap2_clksel_recalc,
1058 };
1059
1060 /* Common interface clocks */
1061
1062 static struct clk l3_ick = {
1063         .name           = "l3_ick",
1064         .parent         = &core_ck,
1065         .init           = &omap2_init_clksel_parent,
1066         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1067         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1068         .clksel         = div2_core_clksel,
1069         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1070                                 PARENT_CONTROLS_CLOCK,
1071         .recalc         = &omap2_clksel_recalc,
1072 };
1073
1074 static const struct clksel div2_l3_clksel[] = {
1075         { .parent = &l3_ick, .rates = div2_rates },
1076         { .parent = NULL }
1077 };
1078
1079 static struct clk l4_ick = {
1080         .name           = "l4_ick",
1081         .parent         = &l3_ick,
1082         .init           = &omap2_init_clksel_parent,
1083         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1084         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1085         .clksel         = div2_l3_clksel,
1086         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1087                                 PARENT_CONTROLS_CLOCK,
1088         .recalc         = &omap2_clksel_recalc,
1089
1090 };
1091
1092 static const struct clksel div2_l4_clksel[] = {
1093         { .parent = &l4_ick, .rates = div2_rates },
1094         { .parent = NULL }
1095 };
1096
1097 static struct clk rm_ick = {
1098         .name           = "rm_ick",
1099         .parent         = &l4_ick,
1100         .init           = &omap2_init_clksel_parent,
1101         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1102         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1103         .clksel         = div2_l4_clksel,
1104         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1105         .recalc         = &omap2_clksel_recalc,
1106 };
1107
1108 /* GFX power domain */
1109
1110 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1111
1112 static const struct clksel gfx_l3_clksel[] = {
1113         { .parent = &l3_ick, .rates = gfx_l3_rates },
1114         { .parent = NULL }
1115 };
1116
1117 static struct clk gfx_l3_fck = {
1118         .name           = "gfx_l3_fck",
1119         .parent         = &l3_ick,
1120         .init           = &omap2_init_clksel_parent,
1121         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1122         .enable_bit     = OMAP_EN_GFX_SHIFT,
1123         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1124         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1125         .clksel         = gfx_l3_clksel,
1126         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1127         .recalc         = &omap2_clksel_recalc,
1128 };
1129
1130 static struct clk gfx_l3_ick = {
1131         .name           = "gfx_l3_ick",
1132         .parent         = &l3_ick,
1133         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1134         .enable_bit     = OMAP_EN_GFX_SHIFT,
1135         .flags          = CLOCK_IN_OMAP3430ES1,
1136         .recalc         = &followparent_recalc,
1137 };
1138
1139 static struct clk gfx_cg1_ck = {
1140         .name           = "gfx_cg1_ck",
1141         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1142         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1143         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1144         .flags          = CLOCK_IN_OMAP3430ES1,
1145         .recalc         = &followparent_recalc,
1146 };
1147
1148 static struct clk gfx_cg2_ck = {
1149         .name           = "gfx_cg2_ck",
1150         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1151         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1152         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1153         .flags          = CLOCK_IN_OMAP3430ES1,
1154         .recalc         = &followparent_recalc,
1155 };
1156
1157 /* SGX power domain - 3430ES2 only */
1158
1159 static const struct clksel_rate sgx_core_rates[] = {
1160         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1161         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1162         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1163         { .div = 0 },
1164 };
1165
1166 static const struct clksel_rate sgx_96m_rates[] = {
1167         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1168         { .div = 0 },
1169 };
1170
1171 static const struct clksel sgx_clksel[] = {
1172         { .parent = &core_ck,    .rates = sgx_core_rates },
1173         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1174         { .parent = NULL },
1175 };
1176
1177 static struct clk sgx_fck = {
1178         .name           = "sgx_fck",
1179         .init           = &omap2_init_clksel_parent,
1180         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1181         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1182         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1183         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1184         .clksel         = sgx_clksel,
1185         .flags          = CLOCK_IN_OMAP3430ES2,
1186         .recalc         = &omap2_clksel_recalc,
1187 };
1188
1189 static struct clk sgx_ick = {
1190         .name           = "sgx_ick",
1191         .parent         = &l3_ick,
1192         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1193         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1194         .flags          = CLOCK_IN_OMAP3430ES2,
1195         .recalc         = &followparent_recalc,
1196 };
1197
1198 /* CORE power domain */
1199
1200 static struct clk d2d_26m_fck = {
1201         .name           = "d2d_26m_fck",
1202         .parent         = &sys_ck,
1203         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1204         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1205         .flags          = CLOCK_IN_OMAP3430ES1,
1206         .recalc         = &followparent_recalc,
1207 };
1208
1209 static const struct clksel omap343x_gpt_clksel[] = {
1210         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1211         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1212         { .parent = NULL}
1213 };
1214
1215 static struct clk gpt10_fck = {
1216         .name           = "gpt10_fck",
1217         .parent         = &sys_ck,
1218         .init           = &omap2_init_clksel_parent,
1219         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1220         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1221         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1222         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1223         .clksel         = omap343x_gpt_clksel,
1224         .flags          = CLOCK_IN_OMAP343X,
1225         .recalc         = &omap2_clksel_recalc,
1226 };
1227
1228 static struct clk gpt11_fck = {
1229         .name           = "gpt11_fck",
1230         .parent         = &sys_ck,
1231         .init           = &omap2_init_clksel_parent,
1232         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1233         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1234         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1235         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1236         .clksel         = omap343x_gpt_clksel,
1237         .flags          = CLOCK_IN_OMAP343X,
1238         .recalc         = &omap2_clksel_recalc,
1239 };
1240
1241 static struct clk cpefuse_fck = {
1242         .name           = "cpefuse_fck",
1243         .parent         = &sys_ck,
1244         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1245         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1246         .flags          = CLOCK_IN_OMAP3430ES2,
1247         .recalc         = &followparent_recalc,
1248 };
1249
1250 static struct clk ts_fck = {
1251         .name           = "ts_fck",
1252         .parent         = &omap_32k_fck,
1253         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1254         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1255         .flags          = CLOCK_IN_OMAP3430ES2,
1256         .recalc         = &followparent_recalc,
1257 };
1258
1259 static struct clk usbtll_fck = {
1260         .name           = "usbtll_fck",
1261         .parent         = &omap_120m_fck,
1262         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1263         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1264         .flags          = CLOCK_IN_OMAP3430ES2,
1265         .recalc         = &followparent_recalc,
1266 };
1267
1268 /* CORE 96M FCLK-derived clocks */
1269
1270 static struct clk core_96m_fck = {
1271         .name           = "core_96m_fck",
1272         .parent         = &omap_96m_fck,
1273         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1274                                 PARENT_CONTROLS_CLOCK,
1275         .recalc         = &followparent_recalc,
1276 };
1277
1278 static struct clk mmchs3_fck = {
1279         .name           = "mmchs_fck",
1280         .id             = 3,
1281         .parent         = &core_96m_fck,
1282         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1283         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1284         .flags          = CLOCK_IN_OMAP3430ES2,
1285         .recalc         = &followparent_recalc,
1286 };
1287
1288 static struct clk mmchs2_fck = {
1289         .name           = "mmchs_fck",
1290         .id             = 2,
1291         .parent         = &core_96m_fck,
1292         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1293         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1294         .flags          = CLOCK_IN_OMAP343X,
1295         .recalc         = &followparent_recalc,
1296 };
1297
1298 static struct clk mspro_fck = {
1299         .name           = "mspro_fck",
1300         .parent         = &core_96m_fck,
1301         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1302         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1303         .flags          = CLOCK_IN_OMAP343X,
1304         .recalc         = &followparent_recalc,
1305 };
1306
1307 static struct clk mmchs1_fck = {
1308         .name           = "mmchs_fck",
1309         .id             = 1,
1310         .parent         = &core_96m_fck,
1311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1312         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1313         .flags          = CLOCK_IN_OMAP343X,
1314         .recalc         = &followparent_recalc,
1315 };
1316
1317 static struct clk i2c3_fck = {
1318         .name           = "i2c_fck",
1319         .id             = 3,
1320         .parent         = &core_96m_fck,
1321         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1322         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1323         .flags          = CLOCK_IN_OMAP343X,
1324         .recalc         = &followparent_recalc,
1325 };
1326
1327 static struct clk i2c2_fck = {
1328         .name           = "i2c_fck",
1329         .id             = 2,
1330         .parent         = &core_96m_fck,
1331         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1333         .flags          = CLOCK_IN_OMAP343X,
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk i2c1_fck = {
1338         .name           = "i2c_fck",
1339         .id             = 1,
1340         .parent         = &core_96m_fck,
1341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1342         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1343         .flags          = CLOCK_IN_OMAP343X,
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 /*
1348  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1349  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1350  */
1351 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1352         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1353         { .div = 0 }
1354 };
1355
1356 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1357         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1358         { .div = 0 }
1359 };
1360
1361 static const struct clksel mcbsp_15_clksel[] = {
1362         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1363         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1364         { .parent = NULL }
1365 };
1366
1367 static struct clk mcbsp5_fck = {
1368         .name           = "mcbsp5_fck",
1369         .init           = &omap2_init_clksel_parent,
1370         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1372         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1373         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1374         .clksel         = mcbsp_15_clksel,
1375         .flags          = CLOCK_IN_OMAP343X,
1376         .recalc         = &omap2_clksel_recalc,
1377 };
1378
1379 static struct clk mcbsp1_fck = {
1380         .name           = "mcbsp1_fck",
1381         .init           = &omap2_init_clksel_parent,
1382         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1384         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1385         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1386         .clksel         = mcbsp_15_clksel,
1387         .flags          = CLOCK_IN_OMAP343X,
1388         .recalc         = &omap2_clksel_recalc,
1389 };
1390
1391 /* CORE_48M_FCK-derived clocks */
1392
1393 static struct clk core_48m_fck = {
1394         .name           = "core_48m_fck",
1395         .parent         = &omap_48m_fck,
1396         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1397                                 PARENT_CONTROLS_CLOCK,
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 static struct clk mcspi4_fck = {
1402         .name           = "mcspi_fck",
1403         .id             = 4,
1404         .parent         = &core_48m_fck,
1405         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1407         .flags          = CLOCK_IN_OMAP343X,
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk mcspi3_fck = {
1412         .name           = "mcspi_fck",
1413         .id             = 3,
1414         .parent         = &core_48m_fck,
1415         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1416         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1417         .flags          = CLOCK_IN_OMAP343X,
1418         .recalc         = &followparent_recalc,
1419 };
1420
1421 static struct clk mcspi2_fck = {
1422         .name           = "mcspi_fck",
1423         .id             = 2,
1424         .parent         = &core_48m_fck,
1425         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1426         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1427         .flags          = CLOCK_IN_OMAP343X,
1428         .recalc         = &followparent_recalc,
1429 };
1430
1431 static struct clk mcspi1_fck = {
1432         .name           = "mcspi_fck",
1433         .id             = 1,
1434         .parent         = &core_48m_fck,
1435         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1436         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1437         .flags          = CLOCK_IN_OMAP343X,
1438         .recalc         = &followparent_recalc,
1439 };
1440
1441 static struct clk uart2_fck = {
1442         .name           = "uart2_fck",
1443         .parent         = &core_48m_fck,
1444         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1445         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1446         .flags          = CLOCK_IN_OMAP343X,
1447         .recalc         = &followparent_recalc,
1448 };
1449
1450 static struct clk uart1_fck = {
1451         .name           = "uart1_fck",
1452         .parent         = &core_48m_fck,
1453         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1455         .flags          = CLOCK_IN_OMAP343X,
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 static struct clk fshostusb_fck = {
1460         .name           = "fshostusb_fck",
1461         .parent         = &core_48m_fck,
1462         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1463         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1464         .flags          = CLOCK_IN_OMAP3430ES1,
1465         .recalc         = &followparent_recalc,
1466 };
1467
1468 /* CORE_12M_FCK based clocks */
1469
1470 static struct clk core_12m_fck = {
1471         .name           = "core_12m_fck",
1472         .parent         = &omap_12m_fck,
1473         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1474                                 PARENT_CONTROLS_CLOCK,
1475         .recalc         = &followparent_recalc,
1476 };
1477
1478 static struct clk hdq_fck = {
1479         .name           = "hdq_fck",
1480         .parent         = &core_12m_fck,
1481         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1482         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1483         .flags          = CLOCK_IN_OMAP343X,
1484         .recalc         = &followparent_recalc,
1485 };
1486
1487 /* DPLL3-derived clock */
1488
1489 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1490         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1491         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1492         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1493         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1494         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1495         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1496         { .div = 0 }
1497 };
1498
1499 static const struct clksel ssi_ssr_clksel[] = {
1500         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1501         { .parent = NULL }
1502 };
1503
1504 static struct clk ssi_ssr_fck = {
1505         .name           = "ssi_ssr_fck",
1506         .init           = &omap2_init_clksel_parent,
1507         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1508         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1509         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1510         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1511         .clksel         = ssi_ssr_clksel,
1512         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1513         .recalc         = &omap2_clksel_recalc,
1514 };
1515
1516 static struct clk ssi_sst_fck = {
1517         .name           = "ssi_sst_fck",
1518         .parent         = &ssi_ssr_fck,
1519         .fixed_div      = 2,
1520         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1521         .recalc         = &omap2_fixed_divisor_recalc,
1522 };
1523
1524
1525
1526 /* CORE_L3_ICK based clocks */
1527
1528 static struct clk core_l3_ick = {
1529         .name           = "core_l3_ick",
1530         .parent         = &l3_ick,
1531         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1532                                 PARENT_CONTROLS_CLOCK,
1533         .recalc         = &followparent_recalc,
1534 };
1535
1536 static struct clk hsotgusb_ick = {
1537         .name           = "hsotgusb_ick",
1538         .parent         = &core_l3_ick,
1539         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1540         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1541         .flags          = CLOCK_IN_OMAP343X,
1542         .recalc         = &followparent_recalc,
1543 };
1544
1545 static struct clk sdrc_ick = {
1546         .name           = "sdrc_ick",
1547         .parent         = &core_l3_ick,
1548         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1549         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1550         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk gpmc_fck = {
1555         .name           = "gpmc_fck",
1556         .parent         = &core_l3_ick,
1557         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1558                                 ENABLE_ON_INIT,
1559         .recalc         = &followparent_recalc,
1560 };
1561
1562 /* SECURITY_L3_ICK based clocks */
1563
1564 static struct clk security_l3_ick = {
1565         .name           = "security_l3_ick",
1566         .parent         = &l3_ick,
1567         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1568                                 PARENT_CONTROLS_CLOCK,
1569         .recalc         = &followparent_recalc,
1570 };
1571
1572 static struct clk pka_ick = {
1573         .name           = "pka_ick",
1574         .parent         = &security_l3_ick,
1575         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1576         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1577         .flags          = CLOCK_IN_OMAP343X,
1578         .recalc         = &followparent_recalc,
1579 };
1580
1581 /* CORE_L4_ICK based clocks */
1582
1583 static struct clk core_l4_ick = {
1584         .name           = "core_l4_ick",
1585         .parent         = &l4_ick,
1586         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1587                                 PARENT_CONTROLS_CLOCK,
1588         .recalc         = &followparent_recalc,
1589 };
1590
1591 static struct clk usbtll_ick = {
1592         .name           = "usbtll_ick",
1593         .parent         = &core_l4_ick,
1594         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1595         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1596         .flags          = CLOCK_IN_OMAP3430ES2,
1597         .recalc         = &followparent_recalc,
1598 };
1599
1600 static struct clk mmchs3_ick = {
1601         .name           = "mmchs_ick",
1602         .id             = 3,
1603         .parent         = &core_l4_ick,
1604         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1605         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1606         .flags          = CLOCK_IN_OMAP3430ES2,
1607         .recalc         = &followparent_recalc,
1608 };
1609
1610 /* Intersystem Communication Registers - chassis mode only */
1611 static struct clk icr_ick = {
1612         .name           = "icr_ick",
1613         .parent         = &core_l4_ick,
1614         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1615         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1616         .flags          = CLOCK_IN_OMAP343X,
1617         .recalc         = &followparent_recalc,
1618 };
1619
1620 static struct clk aes2_ick = {
1621         .name           = "aes2_ick",
1622         .parent         = &core_l4_ick,
1623         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1624         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1625         .flags          = CLOCK_IN_OMAP343X,
1626         .recalc         = &followparent_recalc,
1627 };
1628
1629 static struct clk sha12_ick = {
1630         .name           = "sha12_ick",
1631         .parent         = &core_l4_ick,
1632         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1633         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1634         .flags          = CLOCK_IN_OMAP343X,
1635         .recalc         = &followparent_recalc,
1636 };
1637
1638 static struct clk des2_ick = {
1639         .name           = "des2_ick",
1640         .parent         = &core_l4_ick,
1641         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1642         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1643         .flags          = CLOCK_IN_OMAP343X,
1644         .recalc         = &followparent_recalc,
1645 };
1646
1647 static struct clk mmchs2_ick = {
1648         .name           = "mmchs_ick",
1649         .id             = 2,
1650         .parent         = &core_l4_ick,
1651         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1652         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1653         .flags          = CLOCK_IN_OMAP343X,
1654         .recalc         = &followparent_recalc,
1655 };
1656
1657 static struct clk mmchs1_ick = {
1658         .name           = "mmchs_ick",
1659         .id             = 1,
1660         .parent         = &core_l4_ick,
1661         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1662         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1663         .flags          = CLOCK_IN_OMAP343X,
1664         .recalc         = &followparent_recalc,
1665 };
1666
1667 static struct clk mspro_ick = {
1668         .name           = "mspro_ick",
1669         .parent         = &core_l4_ick,
1670         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1671         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1672         .flags          = CLOCK_IN_OMAP343X,
1673         .recalc         = &followparent_recalc,
1674 };
1675
1676 static struct clk hdq_ick = {
1677         .name           = "hdq_ick",
1678         .parent         = &core_l4_ick,
1679         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1680         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1681         .flags          = CLOCK_IN_OMAP343X,
1682         .recalc         = &followparent_recalc,
1683 };
1684
1685 static struct clk mcspi4_ick = {
1686         .name           = "mcspi_ick",
1687         .id             = 4,
1688         .parent         = &core_l4_ick,
1689         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1690         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1691         .flags          = CLOCK_IN_OMAP343X,
1692         .recalc         = &followparent_recalc,
1693 };
1694
1695 static struct clk mcspi3_ick = {
1696         .name           = "mcspi_ick",
1697         .id             = 3,
1698         .parent         = &core_l4_ick,
1699         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1700         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1701         .flags          = CLOCK_IN_OMAP343X,
1702         .recalc         = &followparent_recalc,
1703 };
1704
1705 static struct clk mcspi2_ick = {
1706         .name           = "mcspi_ick",
1707         .id             = 2,
1708         .parent         = &core_l4_ick,
1709         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1710         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1711         .flags          = CLOCK_IN_OMAP343X,
1712         .recalc         = &followparent_recalc,
1713 };
1714
1715 static struct clk mcspi1_ick = {
1716         .name           = "mcspi_ick",
1717         .id             = 1,
1718         .parent         = &core_l4_ick,
1719         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1720         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1721         .flags          = CLOCK_IN_OMAP343X,
1722         .recalc         = &followparent_recalc,
1723 };
1724
1725 static struct clk i2c3_ick = {
1726         .name           = "i2c_ick",
1727         .id             = 3,
1728         .parent         = &core_l4_ick,
1729         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1730         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1731         .flags          = CLOCK_IN_OMAP343X,
1732         .recalc         = &followparent_recalc,
1733 };
1734
1735 static struct clk i2c2_ick = {
1736         .name           = "i2c_ick",
1737         .id             = 2,
1738         .parent         = &core_l4_ick,
1739         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1740         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1741         .flags          = CLOCK_IN_OMAP343X,
1742         .recalc         = &followparent_recalc,
1743 };
1744
1745 static struct clk i2c1_ick = {
1746         .name           = "i2c_ick",
1747         .id             = 1,
1748         .parent         = &core_l4_ick,
1749         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1750         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1751         .flags          = CLOCK_IN_OMAP343X,
1752         .recalc         = &followparent_recalc,
1753 };
1754
1755 static struct clk uart2_ick = {
1756         .name           = "uart2_ick",
1757         .parent         = &core_l4_ick,
1758         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1759         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1760         .flags          = CLOCK_IN_OMAP343X,
1761         .recalc         = &followparent_recalc,
1762 };
1763
1764 static struct clk uart1_ick = {
1765         .name           = "uart1_ick",
1766         .parent         = &core_l4_ick,
1767         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1768         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1769         .flags          = CLOCK_IN_OMAP343X,
1770         .recalc         = &followparent_recalc,
1771 };
1772
1773 static struct clk gpt11_ick = {
1774         .name           = "gpt11_ick",
1775         .parent         = &core_l4_ick,
1776         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1778         .flags          = CLOCK_IN_OMAP343X,
1779         .recalc         = &followparent_recalc,
1780 };
1781
1782 static struct clk gpt10_ick = {
1783         .name           = "gpt10_ick",
1784         .parent         = &core_l4_ick,
1785         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1786         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1787         .flags          = CLOCK_IN_OMAP343X,
1788         .recalc         = &followparent_recalc,
1789 };
1790
1791 static struct clk mcbsp5_ick = {
1792         .name           = "mcbsp5_ick",
1793         .parent         = &core_l4_ick,
1794         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1795         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1796         .flags          = CLOCK_IN_OMAP343X,
1797         .recalc         = &followparent_recalc,
1798 };
1799
1800 static struct clk mcbsp1_ick = {
1801         .name           = "mcbsp1_ick",
1802         .parent         = &core_l4_ick,
1803         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1804         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1805         .flags          = CLOCK_IN_OMAP343X,
1806         .recalc         = &followparent_recalc,
1807 };
1808
1809 static struct clk fac_ick = {
1810         .name           = "fac_ick",
1811         .parent         = &core_l4_ick,
1812         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1813         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1814         .flags          = CLOCK_IN_OMAP3430ES1,
1815         .recalc         = &followparent_recalc,
1816 };
1817
1818 static struct clk mailboxes_ick = {
1819         .name           = "mailboxes_ick",
1820         .parent         = &core_l4_ick,
1821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1822         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1823         .flags          = CLOCK_IN_OMAP343X,
1824         .recalc         = &followparent_recalc,
1825 };
1826
1827 static struct clk omapctrl_ick = {
1828         .name           = "omapctrl_ick",
1829         .parent         = &core_l4_ick,
1830         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1831         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1832         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1833         .recalc         = &followparent_recalc,
1834 };
1835
1836 /* SSI_L4_ICK based clocks */
1837
1838 static struct clk ssi_l4_ick = {
1839         .name           = "ssi_l4_ick",
1840         .parent         = &l4_ick,
1841         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1842                                 PARENT_CONTROLS_CLOCK,
1843         .recalc         = &followparent_recalc,
1844 };
1845
1846 static struct clk ssi_ick = {
1847         .name           = "ssi_ick",
1848         .parent         = &ssi_l4_ick,
1849         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1850         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1851         .flags          = CLOCK_IN_OMAP343X,
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1856  * but l4_ick makes more sense to me */
1857
1858 static const struct clksel usb_l4_clksel[] = {
1859         { .parent = &l4_ick, .rates = div2_rates },
1860         { .parent = NULL },
1861 };
1862
1863 static struct clk usb_l4_ick = {
1864         .name           = "usb_l4_ick",
1865         .parent         = &l4_ick,
1866         .init           = &omap2_init_clksel_parent,
1867         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1868         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1869         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1870         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1871         .clksel         = usb_l4_clksel,
1872         .flags          = CLOCK_IN_OMAP3430ES1,
1873         .recalc         = &omap2_clksel_recalc,
1874 };
1875
1876 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1877
1878 /* SECURITY_L4_ICK2 based clocks */
1879
1880 static struct clk security_l4_ick2 = {
1881         .name           = "security_l4_ick2",
1882         .parent         = &l4_ick,
1883         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1884                                 PARENT_CONTROLS_CLOCK,
1885         .recalc         = &followparent_recalc,
1886 };
1887
1888 static struct clk aes1_ick = {
1889         .name           = "aes1_ick",
1890         .parent         = &security_l4_ick2,
1891         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1892         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1893         .flags          = CLOCK_IN_OMAP343X,
1894         .recalc         = &followparent_recalc,
1895 };
1896
1897 static struct clk rng_ick = {
1898         .name           = "rng_ick",
1899         .parent         = &security_l4_ick2,
1900         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1901         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
1902         .flags          = CLOCK_IN_OMAP343X,
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk sha11_ick = {
1907         .name           = "sha11_ick",
1908         .parent         = &security_l4_ick2,
1909         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1910         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
1911         .flags          = CLOCK_IN_OMAP343X,
1912         .recalc         = &followparent_recalc,
1913 };
1914
1915 static struct clk des1_ick = {
1916         .name           = "des1_ick",
1917         .parent         = &security_l4_ick2,
1918         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1919         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
1920         .flags          = CLOCK_IN_OMAP343X,
1921         .recalc         = &followparent_recalc,
1922 };
1923
1924 /* DSS */
1925 static const struct clksel dss1_alwon_fck_clksel[] = {
1926         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
1927         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
1928         { .parent = NULL }
1929 };
1930
1931 static struct clk dss1_alwon_fck = {
1932         .name           = "dss1_alwon_fck",
1933         .parent         = &dpll4_m4x2_ck,
1934         .init           = &omap2_init_clksel_parent,
1935         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1936         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1937         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1938         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
1939         .clksel         = dss1_alwon_fck_clksel,
1940         .flags          = CLOCK_IN_OMAP343X,
1941         .recalc         = &omap2_clksel_recalc,
1942 };
1943
1944 static struct clk dss_tv_fck = {
1945         .name           = "dss_tv_fck",
1946         .parent         = &omap_54m_fck,
1947         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1948         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1949         .flags          = CLOCK_IN_OMAP343X,
1950         .recalc         = &followparent_recalc,
1951 };
1952
1953 static struct clk dss_96m_fck = {
1954         .name           = "dss_96m_fck",
1955         .parent         = &omap_96m_fck,
1956         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1957         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1958         .flags          = CLOCK_IN_OMAP343X,
1959         .recalc         = &followparent_recalc,
1960 };
1961
1962 static struct clk dss2_alwon_fck = {
1963         .name           = "dss2_alwon_fck",
1964         .parent         = &sys_ck,
1965         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1966         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
1967         .flags          = CLOCK_IN_OMAP343X,
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk dss_ick = {
1972         /* Handles both L3 and L4 clocks */
1973         .name           = "dss_ick",
1974         .parent         = &l4_ick,
1975         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1976         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1977         .flags          = CLOCK_IN_OMAP343X,
1978         .recalc         = &followparent_recalc,
1979 };
1980
1981 /* CAM */
1982
1983 static const struct clksel cam_mclk_clksel[] = {
1984         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
1985         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
1986         { .parent = NULL }
1987 };
1988
1989 static struct clk cam_mclk = {
1990         .name           = "cam_mclk",
1991         .parent         = &dpll4_m5x2_ck,
1992         .init           = &omap2_init_clksel_parent,
1993         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1994         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
1995         .clksel         = cam_mclk_clksel,
1996         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1997         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1998         .flags          = CLOCK_IN_OMAP343X,
1999         .recalc         = &omap2_clksel_recalc,
2000 };
2001
2002 static struct clk cam_l3_ick = {
2003         .name           = "cam_l3_ick",
2004         .parent         = &l3_ick,
2005         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2006         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2007         .flags          = CLOCK_IN_OMAP343X,
2008         .recalc         = &followparent_recalc,
2009 };
2010
2011 static struct clk cam_l4_ick = {
2012         .name           = "cam_l4_ick",
2013         .parent         = &l4_ick,
2014         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2015         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2016         .flags          = CLOCK_IN_OMAP343X,
2017         .recalc         = &followparent_recalc,
2018 };
2019
2020 /* USBHOST - 3430ES2 only */
2021
2022 static struct clk usbhost_120m_fck = {
2023         .name           = "usbhost_120m_fck",
2024         .parent         = &omap_120m_fck,
2025         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2026         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2027         .flags          = CLOCK_IN_OMAP3430ES2,
2028         .recalc         = &followparent_recalc,
2029 };
2030
2031 static struct clk usbhost_48m_fck = {
2032         .name           = "usbhost_48m_fck",
2033         .parent         = &omap_48m_fck,
2034         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2035         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2036         .flags          = CLOCK_IN_OMAP3430ES2,
2037         .recalc         = &followparent_recalc,
2038 };
2039
2040 static struct clk usbhost_l3_ick = {
2041         .name           = "usbhost_l3_ick",
2042         .parent         = &l3_ick,
2043         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2044         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2045         .flags          = CLOCK_IN_OMAP3430ES2,
2046         .recalc         = &followparent_recalc,
2047 };
2048
2049 static struct clk usbhost_l4_ick = {
2050         .name           = "usbhost_l4_ick",
2051         .parent         = &l4_ick,
2052         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2053         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2054         .flags          = CLOCK_IN_OMAP3430ES2,
2055         .recalc         = &followparent_recalc,
2056 };
2057
2058 static struct clk usbhost_sar_fck = {
2059         .name           = "usbhost_sar_fck",
2060         .parent         = &osc_sys_ck,
2061         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2062         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2063         .flags          = CLOCK_IN_OMAP3430ES2,
2064         .recalc         = &followparent_recalc,
2065 };
2066
2067 /* WKUP */
2068
2069 static const struct clksel_rate usim_96m_rates[] = {
2070         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2071         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2072         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2073         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2074         { .div = 0 },
2075 };
2076
2077 static const struct clksel_rate usim_120m_rates[] = {
2078         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2079         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2080         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2081         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2082         { .div = 0 },
2083 };
2084
2085 static const struct clksel usim_clksel[] = {
2086         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2087         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2088         { .parent = &sys_ck,            .rates = div2_rates },
2089         { .parent = NULL },
2090 };
2091
2092 /* 3430ES2 only */
2093 static struct clk usim_fck = {
2094         .name           = "usim_fck",
2095         .init           = &omap2_init_clksel_parent,
2096         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2097         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2098         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2099         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2100         .clksel         = usim_clksel,
2101         .flags          = CLOCK_IN_OMAP3430ES2,
2102         .recalc         = &omap2_clksel_recalc,
2103 };
2104
2105 static struct clk gpt1_fck = {
2106         .name           = "gpt1_fck",
2107         .init           = &omap2_init_clksel_parent,
2108         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2109         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2110         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2111         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2112         .clksel         = omap343x_gpt_clksel,
2113         .flags          = CLOCK_IN_OMAP343X,
2114         .recalc         = &omap2_clksel_recalc,
2115 };
2116
2117 static struct clk wkup_32k_fck = {
2118         .name           = "wkup_32k_fck",
2119         .parent         = &omap_32k_fck,
2120         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2121         .recalc         = &followparent_recalc,
2122 };
2123
2124 static struct clk gpio1_fck = {
2125         .name           = "gpio1_fck",
2126         .parent         = &wkup_32k_fck,
2127         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2128         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2129         .flags          = CLOCK_IN_OMAP343X,
2130         .recalc         = &followparent_recalc,
2131 };
2132
2133 static struct clk wdt2_fck = {
2134         .name           = "wdt2_fck",
2135         .parent         = &wkup_32k_fck,
2136         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2137         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2138         .flags          = CLOCK_IN_OMAP343X,
2139         .recalc         = &followparent_recalc,
2140 };
2141
2142 static struct clk wkup_l4_ick = {
2143         .name           = "wkup_l4_ick",
2144         .parent         = &sys_ck,
2145         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2146         .recalc         = &followparent_recalc,
2147 };
2148
2149 /* 3430ES2 only */
2150 /* Never specifically named in the TRM, so we have to infer a likely name */
2151 static struct clk usim_ick = {
2152         .name           = "usim_ick",
2153         .parent         = &wkup_l4_ick,
2154         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2155         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2156         .flags          = CLOCK_IN_OMAP3430ES2,
2157         .recalc         = &followparent_recalc,
2158 };
2159
2160 static struct clk wdt2_ick = {
2161         .name           = "wdt2_ick",
2162         .parent         = &wkup_l4_ick,
2163         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2164         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2165         .flags          = CLOCK_IN_OMAP343X,
2166         .recalc         = &followparent_recalc,
2167 };
2168
2169 static struct clk wdt1_ick = {
2170         .name           = "wdt1_ick",
2171         .parent         = &wkup_l4_ick,
2172         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2173         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2174         .flags          = CLOCK_IN_OMAP343X,
2175         .recalc         = &followparent_recalc,
2176 };
2177
2178 static struct clk gpio1_ick = {
2179         .name           = "gpio1_ick",
2180         .parent         = &wkup_l4_ick,
2181         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2182         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2183         .flags          = CLOCK_IN_OMAP343X,
2184         .recalc         = &followparent_recalc,
2185 };
2186
2187 static struct clk omap_32ksync_ick = {
2188         .name           = "omap_32ksync_ick",
2189         .parent         = &wkup_l4_ick,
2190         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2191         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2192         .flags          = CLOCK_IN_OMAP343X,
2193         .recalc         = &followparent_recalc,
2194 };
2195
2196 static struct clk gpt12_ick = {
2197         .name           = "gpt12_ick",
2198         .parent         = &wkup_l4_ick,
2199         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2200         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2201         .flags          = CLOCK_IN_OMAP343X,
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 static struct clk gpt1_ick = {
2206         .name           = "gpt1_ick",
2207         .parent         = &wkup_l4_ick,
2208         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2209         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2210         .flags          = CLOCK_IN_OMAP343X,
2211         .recalc         = &followparent_recalc,
2212 };
2213
2214
2215
2216 /* PER clock domain */
2217
2218 static struct clk per_96m_fck = {
2219         .name           = "per_96m_fck",
2220         .parent         = &omap_96m_alwon_fck,
2221         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2222                                 PARENT_CONTROLS_CLOCK,
2223         .recalc         = &followparent_recalc,
2224 };
2225
2226 static struct clk per_48m_fck = {
2227         .name           = "per_48m_fck",
2228         .parent         = &omap_48m_fck,
2229         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2230                                 PARENT_CONTROLS_CLOCK,
2231         .recalc         = &followparent_recalc,
2232 };
2233
2234 static struct clk uart3_fck = {
2235         .name           = "uart3_fck",
2236         .parent         = &per_48m_fck,
2237         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2238         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2239         .flags          = CLOCK_IN_OMAP343X,
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 static struct clk gpt2_fck = {
2244         .name           = "gpt2_fck",
2245         .init           = &omap2_init_clksel_parent,
2246         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2247         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2248         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2249         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2250         .clksel         = omap343x_gpt_clksel,
2251         .flags          = CLOCK_IN_OMAP343X,
2252         .recalc         = &omap2_clksel_recalc,
2253 };
2254
2255 static struct clk gpt3_fck = {
2256         .name           = "gpt3_fck",
2257         .init           = &omap2_init_clksel_parent,
2258         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2259         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2260         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2261         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2262         .clksel         = omap343x_gpt_clksel,
2263         .flags          = CLOCK_IN_OMAP343X,
2264         .recalc         = &omap2_clksel_recalc,
2265 };
2266
2267 static struct clk gpt4_fck = {
2268         .name           = "gpt4_fck",
2269         .init           = &omap2_init_clksel_parent,
2270         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2271         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2272         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2273         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2274         .clksel         = omap343x_gpt_clksel,
2275         .flags          = CLOCK_IN_OMAP343X,
2276         .recalc         = &omap2_clksel_recalc,
2277 };
2278
2279 static struct clk gpt5_fck = {
2280         .name           = "gpt5_fck",
2281         .init           = &omap2_init_clksel_parent,
2282         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2283         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2284         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2285         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2286         .clksel         = omap343x_gpt_clksel,
2287         .flags          = CLOCK_IN_OMAP343X,
2288         .recalc         = &omap2_clksel_recalc,
2289 };
2290
2291 static struct clk gpt6_fck = {
2292         .name           = "gpt6_fck",
2293         .init           = &omap2_init_clksel_parent,
2294         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2295         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2296         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2297         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2298         .clksel         = omap343x_gpt_clksel,
2299         .flags          = CLOCK_IN_OMAP343X,
2300         .recalc         = &omap2_clksel_recalc,
2301 };
2302
2303 static struct clk gpt7_fck = {
2304         .name           = "gpt7_fck",
2305         .init           = &omap2_init_clksel_parent,
2306         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2307         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2308         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2309         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2310         .clksel         = omap343x_gpt_clksel,
2311         .flags          = CLOCK_IN_OMAP343X,
2312         .recalc         = &omap2_clksel_recalc,
2313 };
2314
2315 static struct clk gpt8_fck = {
2316         .name           = "gpt8_fck",
2317         .init           = &omap2_init_clksel_parent,
2318         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2319         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2320         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2321         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2322         .clksel         = omap343x_gpt_clksel,
2323         .flags          = CLOCK_IN_OMAP343X,
2324         .recalc         = &omap2_clksel_recalc,
2325 };
2326
2327 static struct clk gpt9_fck = {
2328         .name           = "gpt9_fck",
2329         .init           = &omap2_init_clksel_parent,
2330         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2331         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2332         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2333         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2334         .clksel         = omap343x_gpt_clksel,
2335         .flags          = CLOCK_IN_OMAP343X,
2336         .recalc         = &omap2_clksel_recalc,
2337 };
2338
2339 static struct clk per_32k_alwon_fck = {
2340         .name           = "per_32k_alwon_fck",
2341         .parent         = &omap_32k_fck,
2342         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2343         .recalc         = &followparent_recalc,
2344 };
2345
2346 static struct clk gpio6_fck = {
2347         .name           = "gpio6_fck",
2348         .parent         = &per_32k_alwon_fck,
2349         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2350         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2351         .flags          = CLOCK_IN_OMAP343X,
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 static struct clk gpio5_fck = {
2356         .name           = "gpio5_fck",
2357         .parent         = &per_32k_alwon_fck,
2358         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2359         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2360         .flags          = CLOCK_IN_OMAP343X,
2361         .recalc         = &followparent_recalc,
2362 };
2363
2364 static struct clk gpio4_fck = {
2365         .name           = "gpio4_fck",
2366         .parent         = &per_32k_alwon_fck,
2367         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2368         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2369         .flags          = CLOCK_IN_OMAP343X,
2370         .recalc         = &followparent_recalc,
2371 };
2372
2373 static struct clk gpio3_fck = {
2374         .name           = "gpio3_fck",
2375         .parent         = &per_32k_alwon_fck,
2376         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2377         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2378         .flags          = CLOCK_IN_OMAP343X,
2379         .recalc         = &followparent_recalc,
2380 };
2381
2382 static struct clk gpio2_fck = {
2383         .name           = "gpio2_fck",
2384         .parent         = &per_32k_alwon_fck,
2385         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2386         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2387         .flags          = CLOCK_IN_OMAP343X,
2388         .recalc         = &followparent_recalc,
2389 };
2390
2391 static struct clk wdt3_fck = {
2392         .name           = "wdt3_fck",
2393         .parent         = &per_32k_alwon_fck,
2394         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2395         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2396         .flags          = CLOCK_IN_OMAP343X,
2397         .recalc         = &followparent_recalc,
2398 };
2399
2400 static struct clk per_l4_ick = {
2401         .name           = "per_l4_ick",
2402         .parent         = &l4_ick,
2403         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2404                                 PARENT_CONTROLS_CLOCK,
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk gpio6_ick = {
2409         .name           = "gpio6_ick",
2410         .parent         = &per_l4_ick,
2411         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2412         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2413         .flags          = CLOCK_IN_OMAP343X,
2414         .recalc         = &followparent_recalc,
2415 };
2416
2417 static struct clk gpio5_ick = {
2418         .name           = "gpio5_ick",
2419         .parent         = &per_l4_ick,
2420         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2421         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2422         .flags          = CLOCK_IN_OMAP343X,
2423         .recalc         = &followparent_recalc,
2424 };
2425
2426 static struct clk gpio4_ick = {
2427         .name           = "gpio4_ick",
2428         .parent         = &per_l4_ick,
2429         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2430         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2431         .flags          = CLOCK_IN_OMAP343X,
2432         .recalc         = &followparent_recalc,
2433 };
2434
2435 static struct clk gpio3_ick = {
2436         .name           = "gpio3_ick",
2437         .parent         = &per_l4_ick,
2438         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2439         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2440         .flags          = CLOCK_IN_OMAP343X,
2441         .recalc         = &followparent_recalc,
2442 };
2443
2444 static struct clk gpio2_ick = {
2445         .name           = "gpio2_ick",
2446         .parent         = &per_l4_ick,
2447         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2448         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2449         .flags          = CLOCK_IN_OMAP343X,
2450         .recalc         = &followparent_recalc,
2451 };
2452
2453 static struct clk wdt3_ick = {
2454         .name           = "wdt3_ick",
2455         .parent         = &per_l4_ick,
2456         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2457         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2458         .flags          = CLOCK_IN_OMAP343X,
2459         .recalc         = &followparent_recalc,
2460 };
2461
2462 static struct clk uart3_ick = {
2463         .name           = "uart3_ick",
2464         .parent         = &per_l4_ick,
2465         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2466         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2467         .flags          = CLOCK_IN_OMAP343X,
2468         .recalc         = &followparent_recalc,
2469 };
2470
2471 static struct clk gpt9_ick = {
2472         .name           = "gpt9_ick",
2473         .parent         = &per_l4_ick,
2474         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2475         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2476         .flags          = CLOCK_IN_OMAP343X,
2477         .recalc         = &followparent_recalc,
2478 };
2479
2480 static struct clk gpt8_ick = {
2481         .name           = "gpt8_ick",
2482         .parent         = &per_l4_ick,
2483         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2484         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2485         .flags          = CLOCK_IN_OMAP343X,
2486         .recalc         = &followparent_recalc,
2487 };
2488
2489 static struct clk gpt7_ick = {
2490         .name           = "gpt7_ick",
2491         .parent         = &per_l4_ick,
2492         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2493         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2494         .flags          = CLOCK_IN_OMAP343X,
2495         .recalc         = &followparent_recalc,
2496 };
2497
2498 static struct clk gpt6_ick = {
2499         .name           = "gpt6_ick",
2500         .parent         = &per_l4_ick,
2501         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2502         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2503         .flags          = CLOCK_IN_OMAP343X,
2504         .recalc         = &followparent_recalc,
2505 };
2506
2507 static struct clk gpt5_ick = {
2508         .name           = "gpt5_ick",
2509         .parent         = &per_l4_ick,
2510         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2511         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2512         .flags          = CLOCK_IN_OMAP343X,
2513         .recalc         = &followparent_recalc,
2514 };
2515
2516 static struct clk gpt4_ick = {
2517         .name           = "gpt4_ick",
2518         .parent         = &per_l4_ick,
2519         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2520         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2521         .flags          = CLOCK_IN_OMAP343X,
2522         .recalc         = &followparent_recalc,
2523 };
2524
2525 static struct clk gpt3_ick = {
2526         .name           = "gpt3_ick",
2527         .parent         = &per_l4_ick,
2528         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2529         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2530         .flags          = CLOCK_IN_OMAP343X,
2531         .recalc         = &followparent_recalc,
2532 };
2533
2534 static struct clk gpt2_ick = {
2535         .name           = "gpt2_ick",
2536         .parent         = &per_l4_ick,
2537         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2538         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2539         .flags          = CLOCK_IN_OMAP343X,
2540         .recalc         = &followparent_recalc,
2541 };
2542
2543 static struct clk mcbsp2_ick = {
2544         .name           = "mcbsp2_ick",
2545         .parent         = &per_l4_ick,
2546         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2547         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2548         .flags          = CLOCK_IN_OMAP343X,
2549         .recalc         = &followparent_recalc,
2550 };
2551
2552 static struct clk mcbsp3_ick = {
2553         .name           = "mcbsp3_ick",
2554         .parent         = &per_l4_ick,
2555         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2556         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2557         .flags          = CLOCK_IN_OMAP343X,
2558         .recalc         = &followparent_recalc,
2559 };
2560
2561 static struct clk mcbsp4_ick = {
2562         .name           = "mcbsp4_ick",
2563         .parent         = &per_l4_ick,
2564         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2565         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2566         .flags          = CLOCK_IN_OMAP343X,
2567         .recalc         = &followparent_recalc,
2568 };
2569
2570 static const struct clksel mcbsp_234_clksel[] = {
2571         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2572         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2573         { .parent = NULL }
2574 };
2575
2576 static struct clk mcbsp2_fck = {
2577         .name           = "mcbsp2_fck",
2578         .init           = &omap2_init_clksel_parent,
2579         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2580         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2581         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2582         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2583         .clksel         = mcbsp_234_clksel,
2584         .flags          = CLOCK_IN_OMAP343X,
2585         .recalc         = &omap2_clksel_recalc,
2586 };
2587
2588 static struct clk mcbsp3_fck = {
2589         .name           = "mcbsp3_fck",
2590         .init           = &omap2_init_clksel_parent,
2591         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2592         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2593         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2594         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2595         .clksel         = mcbsp_234_clksel,
2596         .flags          = CLOCK_IN_OMAP343X,
2597         .recalc         = &omap2_clksel_recalc,
2598 };
2599
2600 static struct clk mcbsp4_fck = {
2601         .name           = "mcbsp4_fck",
2602         .init           = &omap2_init_clksel_parent,
2603         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2604         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2605         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2606         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2607         .clksel         = mcbsp_234_clksel,
2608         .flags          = CLOCK_IN_OMAP343X,
2609         .recalc         = &omap2_clksel_recalc,
2610 };
2611
2612 /* EMU clocks */
2613
2614 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2615
2616 static const struct clksel_rate emu_src_sys_rates[] = {
2617         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2618         { .div = 0 },
2619 };
2620
2621 static const struct clksel_rate emu_src_core_rates[] = {
2622         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2623         { .div = 0 },
2624 };
2625
2626 static const struct clksel_rate emu_src_per_rates[] = {
2627         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2628         { .div = 0 },
2629 };
2630
2631 static const struct clksel_rate emu_src_mpu_rates[] = {
2632         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2633         { .div = 0 },
2634 };
2635
2636 static const struct clksel emu_src_clksel[] = {
2637         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2638         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2639         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2640         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2641         { .parent = NULL },
2642 };
2643
2644 /*
2645  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2646  * to switch the source of some of the EMU clocks.
2647  * XXX Are there CLKEN bits for these EMU clks?
2648  */
2649 static struct clk emu_src_ck = {
2650         .name           = "emu_src_ck",
2651         .init           = &omap2_init_clksel_parent,
2652         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2653         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2654         .clksel         = emu_src_clksel,
2655         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2656         .recalc         = &omap2_clksel_recalc,
2657 };
2658
2659 static const struct clksel_rate pclk_emu_rates[] = {
2660         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2661         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2662         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2663         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2664         { .div = 0 },
2665 };
2666
2667 static const struct clksel pclk_emu_clksel[] = {
2668         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2669         { .parent = NULL },
2670 };
2671
2672 static struct clk pclk_fck = {
2673         .name           = "pclk_fck",
2674         .init           = &omap2_init_clksel_parent,
2675         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2676         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2677         .clksel         = pclk_emu_clksel,
2678         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2679         .recalc         = &omap2_clksel_recalc,
2680 };
2681
2682 static const struct clksel_rate pclkx2_emu_rates[] = {
2683         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2684         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2685         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2686         { .div = 0 },
2687 };
2688
2689 static const struct clksel pclkx2_emu_clksel[] = {
2690         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2691         { .parent = NULL },
2692 };
2693
2694 static struct clk pclkx2_fck = {
2695         .name           = "pclkx2_fck",
2696         .init           = &omap2_init_clksel_parent,
2697         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2698         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2699         .clksel         = pclkx2_emu_clksel,
2700         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2701         .recalc         = &omap2_clksel_recalc,
2702 };
2703
2704 static const struct clksel atclk_emu_clksel[] = {
2705         { .parent = &emu_src_ck, .rates = div2_rates },
2706         { .parent = NULL },
2707 };
2708
2709 static struct clk atclk_fck = {
2710         .name           = "atclk_fck",
2711         .init           = &omap2_init_clksel_parent,
2712         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2713         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2714         .clksel         = atclk_emu_clksel,
2715         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2716         .recalc         = &omap2_clksel_recalc,
2717 };
2718
2719 static struct clk traceclk_src_fck = {
2720         .name           = "traceclk_src_fck",
2721         .init           = &omap2_init_clksel_parent,
2722         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2723         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2724         .clksel         = emu_src_clksel,
2725         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2726         .recalc         = &omap2_clksel_recalc,
2727 };
2728
2729 static const struct clksel_rate traceclk_rates[] = {
2730         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2731         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2732         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2733         { .div = 0 },
2734 };
2735
2736 static const struct clksel traceclk_clksel[] = {
2737         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2738         { .parent = NULL },
2739 };
2740
2741 static struct clk traceclk_fck = {
2742         .name           = "traceclk_fck",
2743         .init           = &omap2_init_clksel_parent,
2744         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2745         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2746         .clksel         = traceclk_clksel,
2747         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2748         .recalc         = &omap2_clksel_recalc,
2749 };
2750
2751 /* SR clocks */
2752
2753 /* SmartReflex fclk (VDD1) */
2754 static struct clk sr1_fck = {
2755         .name           = "sr1_fck",
2756         .parent         = &sys_ck,
2757         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2758         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2759         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2760         .recalc         = &followparent_recalc,
2761 };
2762
2763 /* SmartReflex fclk (VDD2) */
2764 static struct clk sr2_fck = {
2765         .name           = "sr2_fck",
2766         .parent         = &sys_ck,
2767         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2768         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2769         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2770         .recalc         = &followparent_recalc,
2771 };
2772
2773 static struct clk sr_l4_ick = {
2774         .name           = "sr_l4_ick",
2775         .parent         = &l4_ick,
2776         .flags          = CLOCK_IN_OMAP343X,
2777         .recalc         = &followparent_recalc,
2778 };
2779
2780 /* SECURE_32K_FCK clocks */
2781
2782 static struct clk gpt12_fck = {
2783         .name           = "gpt12_fck",
2784         .parent         = &secure_32k_fck,
2785         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2786         .recalc         = &followparent_recalc,
2787 };
2788
2789 static struct clk wdt1_fck = {
2790         .name           = "wdt1_fck",
2791         .parent         = &secure_32k_fck,
2792         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2793         .recalc         = &followparent_recalc,
2794 };
2795
2796 static struct clk *onchip_34xx_clks[] __initdata = {
2797         &omap_32k_fck,
2798         &virt_12m_ck,
2799         &virt_13m_ck,
2800         &virt_16_8m_ck,
2801         &virt_19_2m_ck,
2802         &virt_26m_ck,
2803         &virt_38_4m_ck,
2804         &osc_sys_ck,
2805         &sys_ck,
2806         &sys_altclk,
2807         &mcbsp_clks,
2808         &sys_clkout1,
2809         &dpll1_ck,
2810         &dpll1_x2_ck,
2811         &dpll1_x2m2_ck,
2812         &dpll2_ck,
2813         &dpll2_m2_ck,
2814         &dpll3_ck,
2815         &core_ck,
2816         &dpll3_x2_ck,
2817         &dpll3_m2_ck,
2818         &dpll3_m2x2_ck,
2819         &dpll3_m3_ck,
2820         &dpll3_m3x2_ck,
2821         &emu_core_alwon_ck,
2822         &dpll4_ck,
2823         &dpll4_x2_ck,
2824         &omap_96m_alwon_fck,
2825         &omap_96m_fck,
2826         &cm_96m_fck,
2827         &virt_omap_54m_fck,
2828         &omap_54m_fck,
2829         &omap_48m_fck,
2830         &omap_12m_fck,
2831         &dpll4_m2_ck,
2832         &dpll4_m2x2_ck,
2833         &dpll4_m3_ck,
2834         &dpll4_m3x2_ck,
2835         &dpll4_m4_ck,
2836         &dpll4_m4x2_ck,
2837         &dpll4_m5_ck,
2838         &dpll4_m5x2_ck,
2839         &dpll4_m6_ck,
2840         &dpll4_m6x2_ck,
2841         &emu_per_alwon_ck,
2842         &dpll5_ck,
2843         &dpll5_m2_ck,
2844         &omap_120m_fck,
2845         &clkout2_src_ck,
2846         &sys_clkout2,
2847         &corex2_fck,
2848         &dpll1_fck,
2849         &mpu_ck,
2850         &arm_fck,
2851         &emu_mpu_alwon_ck,
2852         &dpll2_fck,
2853         &iva2_ck,
2854         &l3_ick,
2855         &l4_ick,
2856         &rm_ick,
2857         &gfx_l3_fck,
2858         &gfx_l3_ick,
2859         &gfx_cg1_ck,
2860         &gfx_cg2_ck,
2861         &sgx_fck,
2862         &sgx_ick,
2863         &d2d_26m_fck,
2864         &gpt10_fck,
2865         &gpt11_fck,
2866         &cpefuse_fck,
2867         &ts_fck,
2868         &usbtll_fck,
2869         &core_96m_fck,
2870         &mmchs3_fck,
2871         &mmchs2_fck,
2872         &mspro_fck,
2873         &mmchs1_fck,
2874         &i2c3_fck,
2875         &i2c2_fck,
2876         &i2c1_fck,
2877         &mcbsp5_fck,
2878         &mcbsp1_fck,
2879         &core_48m_fck,
2880         &mcspi4_fck,
2881         &mcspi3_fck,
2882         &mcspi2_fck,
2883         &mcspi1_fck,
2884         &uart2_fck,
2885         &uart1_fck,
2886         &fshostusb_fck,
2887         &core_12m_fck,
2888         &hdq_fck,
2889         &ssi_ssr_fck,
2890         &ssi_sst_fck,
2891         &core_l3_ick,
2892         &hsotgusb_ick,
2893         &sdrc_ick,
2894         &gpmc_fck,
2895         &security_l3_ick,
2896         &pka_ick,
2897         &core_l4_ick,
2898         &usbtll_ick,
2899         &mmchs3_ick,
2900         &icr_ick,
2901         &aes2_ick,
2902         &sha12_ick,
2903         &des2_ick,
2904         &mmchs2_ick,
2905         &mmchs1_ick,
2906         &mspro_ick,
2907         &hdq_ick,
2908         &mcspi4_ick,
2909         &mcspi3_ick,
2910         &mcspi2_ick,
2911         &mcspi1_ick,
2912         &i2c3_ick,
2913         &i2c2_ick,
2914         &i2c1_ick,
2915         &uart2_ick,
2916         &uart1_ick,
2917         &gpt11_ick,
2918         &gpt10_ick,
2919         &mcbsp5_ick,
2920         &mcbsp1_ick,
2921         &fac_ick,
2922         &mailboxes_ick,
2923         &omapctrl_ick,
2924         &ssi_l4_ick,
2925         &ssi_ick,
2926         &usb_l4_ick,
2927         &security_l4_ick2,
2928         &aes1_ick,
2929         &rng_ick,
2930         &sha11_ick,
2931         &des1_ick,
2932         &dss1_alwon_fck,
2933         &dss_tv_fck,
2934         &dss_96m_fck,
2935         &dss2_alwon_fck,
2936         &dss_ick,
2937         &cam_mclk,
2938         &cam_l3_ick,
2939         &cam_l4_ick,
2940         &usbhost_120m_fck,
2941         &usbhost_48m_fck,
2942         &usbhost_l3_ick,
2943         &usbhost_l4_ick,
2944         &usbhost_sar_fck,
2945         &usim_fck,
2946         &gpt1_fck,
2947         &wkup_32k_fck,
2948         &gpio1_fck,
2949         &wdt2_fck,
2950         &wkup_l4_ick,
2951         &usim_ick,
2952         &wdt2_ick,
2953         &wdt1_ick,
2954         &gpio1_ick,
2955         &omap_32ksync_ick,
2956         &gpt12_ick,
2957         &gpt1_ick,
2958         &per_96m_fck,
2959         &per_48m_fck,
2960         &uart3_fck,
2961         &gpt2_fck,
2962         &gpt3_fck,
2963         &gpt4_fck,
2964         &gpt5_fck,
2965         &gpt6_fck,
2966         &gpt7_fck,
2967         &gpt8_fck,
2968         &gpt9_fck,
2969         &per_32k_alwon_fck,
2970         &gpio6_fck,
2971         &gpio5_fck,
2972         &gpio4_fck,
2973         &gpio3_fck,
2974         &gpio2_fck,
2975         &wdt3_fck,
2976         &per_l4_ick,
2977         &gpio6_ick,
2978         &gpio5_ick,
2979         &gpio4_ick,
2980         &gpio3_ick,
2981         &gpio2_ick,
2982         &wdt3_ick,
2983         &uart3_ick,
2984         &gpt9_ick,
2985         &gpt8_ick,
2986         &gpt7_ick,
2987         &gpt6_ick,
2988         &gpt5_ick,
2989         &gpt4_ick,
2990         &gpt3_ick,
2991         &gpt2_ick,
2992         &mcbsp2_ick,
2993         &mcbsp3_ick,
2994         &mcbsp4_ick,
2995         &mcbsp2_fck,
2996         &mcbsp3_fck,
2997         &mcbsp4_fck,
2998         &emu_src_ck,
2999         &pclk_fck,
3000         &pclkx2_fck,
3001         &atclk_fck,
3002         &traceclk_src_fck,
3003         &traceclk_fck,
3004         &sr1_fck,
3005         &sr2_fck,
3006         &sr_l4_ick,
3007         &secure_32k_fck,
3008         &gpt12_fck,
3009         &wdt1_fck,
3010 };
3011
3012 #endif