1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
51 #define I915_NUM_PIPE 2
56 * 1.2: Add Power Management
57 * 1.3: Add vblank support
58 * 1.4: Fix cmdbuffer path, add heap destroy
59 * 1.5: Add vblank pipe configuration
60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
63 #define DRIVER_MAJOR 1
64 #define DRIVER_MINOR 6
65 #define DRIVER_PATCHLEVEL 0
67 #define WATCH_COHERENCY 0
72 #define WATCH_INACTIVE 0
73 #define WATCH_PWRITE 0
75 #define I915_GEM_PHYS_CURSOR_0 1
76 #define I915_GEM_PHYS_CURSOR_1 2
77 #define I915_GEM_PHYS_OVERLAY_REGS 3
78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
80 struct drm_i915_gem_phys_object {
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
87 typedef struct _drm_i915_ring_buffer {
95 struct drm_gem_object *ring_obj;
96 } drm_i915_ring_buffer_t;
99 struct mem_block *next;
100 struct mem_block *prev;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header;
107 struct opregion_acpi;
108 struct opregion_swsci;
109 struct opregion_asle;
111 struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
119 struct drm_i915_master_private {
120 drm_local_map_t *sarea;
121 struct _drm_i915_sarea *sarea_priv;
123 #define I915_FENCE_REG_NONE -1
125 struct drm_i915_fence_reg {
126 struct drm_gem_object *obj;
129 typedef struct drm_i915_private {
130 struct drm_device *dev;
136 drm_i915_ring_buffer_t ring;
138 drm_dma_handle_t *status_page_dmah;
139 void *hw_status_page;
140 dma_addr_t dma_status_page;
142 unsigned int status_gfx_addr;
143 drm_local_map_t hws_map;
144 struct drm_gem_object *hws_obj;
152 wait_queue_head_t irq_queue;
153 atomic_t irq_received;
154 /** Protects user_irq_refcount and irq_mask_reg */
155 spinlock_t user_irq_lock;
156 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
157 int user_irq_refcount;
158 /** Cached value of IMR to avoid reads in updating the bitfield */
162 int tex_lru_log_granularity;
163 int allow_batchbuffer;
164 struct mem_block *agp_heap;
165 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
168 bool cursor_needs_physical;
174 struct intel_opregion opregion;
177 int backlight_duty_cycle; /* restore backlight to this value */
178 bool panel_wants_dither;
179 struct drm_display_mode *panel_fixed_mode;
180 struct drm_display_mode *vbt_mode; /* if any */
182 /* Feature bits from the VBIOS */
183 unsigned int int_tv_support:1;
184 unsigned int lvds_dither:1;
185 unsigned int lvds_vbt:1;
186 unsigned int int_crt_support:1;
188 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
189 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
190 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
197 u32 saveRENDERSTANDBY;
221 u32 savePFIT_PGM_RATIOS;
223 u32 saveBLC_PWM_CTL2;
248 u32 savePP_ON_DELAYS;
249 u32 savePP_OFF_DELAYS;
257 u32 savePFIT_CONTROL;
258 u32 save_palette_a[256];
259 u32 save_palette_b[256];
260 u32 saveFBC_CFB_BASE;
263 u32 saveFBC_CONTROL2;
267 u32 saveCACHE_MODE_0;
270 u32 saveMI_ARB_STATE;
280 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
284 struct drm_mm gtt_space;
286 struct io_mapping *gtt_mapping;
290 * List of objects currently involved in rendering from the
293 * Includes buffers having the contents of their GPU caches
294 * flushed, not necessarily primitives. last_rendering_seqno
295 * represents when the rendering involved will be completed.
297 * A reference is held on the buffer while on this list.
299 struct list_head active_list;
302 * List of objects which are not in the ringbuffer but which
303 * still have a write_domain which needs to be flushed before
306 * last_rendering_seqno is 0 while an object is in this list.
308 * A reference is held on the buffer while on this list.
310 struct list_head flushing_list;
313 * LRU list of objects which are not in the ringbuffer and
314 * are ready to unbind, but are still in the GTT.
316 * last_rendering_seqno is 0 while an object is in this list.
318 * A reference is not held on the buffer while on this list,
319 * as merely being GTT-bound shouldn't prevent its being
320 * freed, and we'll pull it off the list in the free path.
322 struct list_head inactive_list;
325 * List of breadcrumbs associated with GPU requests currently
328 struct list_head request_list;
331 * We leave the user IRQ off as much as possible,
332 * but this means that requests will finish and never
333 * be retired once the system goes idle. Set a timer to
334 * fire periodically while the ring is running. When it
335 * fires, go retire requests.
337 struct delayed_work retire_work;
339 uint32_t next_gem_seqno;
342 * Waiting sequence number, if any
344 uint32_t waiting_gem_seqno;
347 * Last seq seen at irq time
349 uint32_t irq_gem_seqno;
352 * Flag if the X Server, and thus DRM, is not currently in
353 * control of the device.
355 * This is set between LeaveVT and EnterVT. It needs to be
356 * replaced with a semaphore. It also needs to be
357 * transitioned away from for kernel modesetting.
362 * Flag if the hardware appears to be wedged.
364 * This is set when attempts to idle the device timeout.
365 * It prevents command submission from occuring and makes
366 * every pending request fail
370 /** Bit 6 swizzling required for X tiling */
371 uint32_t bit_6_swizzle_x;
372 /** Bit 6 swizzling required for Y tiling */
373 uint32_t bit_6_swizzle_y;
375 /* storage for physical objects */
376 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
378 } drm_i915_private_t;
380 /** driver private structure attached to each drm_gem_object */
381 struct drm_i915_gem_object {
382 struct drm_gem_object *obj;
384 /** Current space allocated to this object in the GTT, if any. */
385 struct drm_mm_node *gtt_space;
387 /** This object's place on the active/flushing/inactive lists */
388 struct list_head list;
391 * This is set if the object is on the active or flushing lists
392 * (has pending rendering), and is not set if it's on inactive (ready
398 * This is set if the object has been written to since last bound
403 /** AGP memory structure for our GTT binding. */
404 DRM_AGP_MEM *agp_mem;
406 struct page **page_list;
409 * Current offset of the object in GTT space.
411 * This is the same as gtt_space->start
415 * Required alignment for the object
417 uint32_t gtt_alignment;
419 * Fake offset for use by mmap(2)
421 uint64_t mmap_offset;
424 * Fence register bits (if any) for this object. Will be set
425 * as needed when mapped into the GTT.
426 * Protected by dev->struct_mutex.
430 /** Boolean whether this object has a valid gtt offset. */
433 /** How many users have pinned this object in GTT space */
436 /** Breadcrumb of last rendering to the buffer. */
437 uint32_t last_rendering_seqno;
439 /** Current tiling mode for the object. */
440 uint32_t tiling_mode;
443 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
447 * If present, while GEM_DOMAIN_CPU is in the read domain this array
448 * flags which individual pages are valid.
450 uint8_t *page_cpu_valid;
452 /** User space pin count and filp owning the pin */
453 uint32_t user_pin_count;
454 struct drm_file *pin_filp;
456 /** for phy allocated objects */
457 struct drm_i915_gem_phys_object *phys_obj;
461 * Request queue structure.
463 * The request queue allows us to note sequence numbers that have been emitted
464 * and may be associated with active buffers to be retired.
466 * By keeping this list, we can avoid having to do questionable
467 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
468 * an emission time with seqnos for tracking how far ahead of the GPU we are.
470 struct drm_i915_gem_request {
471 /** GEM sequence number associated with this request. */
474 /** Time at which this request was emitted, in jiffies. */
475 unsigned long emitted_jiffies;
477 struct list_head list;
480 struct drm_i915_file_private {
482 uint32_t last_gem_seqno;
483 uint32_t last_gem_throttle_seqno;
487 enum intel_chip_family {
494 extern struct drm_ioctl_desc i915_ioctls[];
495 extern int i915_max_ioctl;
496 extern unsigned int i915_fbpercrtc;
498 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
499 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
502 extern void i915_kernel_lost_context(struct drm_device * dev);
503 extern int i915_driver_load(struct drm_device *, unsigned long flags);
504 extern int i915_driver_unload(struct drm_device *);
505 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
506 extern void i915_driver_lastclose(struct drm_device * dev);
507 extern void i915_driver_preclose(struct drm_device *dev,
508 struct drm_file *file_priv);
509 extern void i915_driver_postclose(struct drm_device *dev,
510 struct drm_file *file_priv);
511 extern int i915_driver_device_is_agp(struct drm_device * dev);
512 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
514 extern int i915_emit_box(struct drm_device *dev,
515 struct drm_clip_rect __user *boxes,
516 int i, int DR1, int DR4);
519 extern int i915_irq_emit(struct drm_device *dev, void *data,
520 struct drm_file *file_priv);
521 extern int i915_irq_wait(struct drm_device *dev, void *data,
522 struct drm_file *file_priv);
523 void i915_user_irq_get(struct drm_device *dev);
524 void i915_user_irq_put(struct drm_device *dev);
525 extern void i915_enable_interrupt (struct drm_device *dev);
527 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
528 extern void i915_driver_irq_preinstall(struct drm_device * dev);
529 extern int i915_driver_irq_postinstall(struct drm_device *dev);
530 extern void i915_driver_irq_uninstall(struct drm_device * dev);
531 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
532 struct drm_file *file_priv);
533 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
534 struct drm_file *file_priv);
535 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
536 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
537 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
538 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
539 extern int i915_vblank_swap(struct drm_device *dev, void *data,
540 struct drm_file *file_priv);
541 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
544 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
547 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
551 extern int i915_mem_alloc(struct drm_device *dev, void *data,
552 struct drm_file *file_priv);
553 extern int i915_mem_free(struct drm_device *dev, void *data,
554 struct drm_file *file_priv);
555 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
556 struct drm_file *file_priv);
557 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
558 struct drm_file *file_priv);
559 extern void i915_mem_takedown(struct mem_block **heap);
560 extern void i915_mem_release(struct drm_device * dev,
561 struct drm_file *file_priv, struct mem_block *heap);
563 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
564 struct drm_file *file_priv);
565 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
566 struct drm_file *file_priv);
567 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
568 struct drm_file *file_priv);
569 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
570 struct drm_file *file_priv);
571 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
572 struct drm_file *file_priv);
573 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
574 struct drm_file *file_priv);
575 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
576 struct drm_file *file_priv);
577 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
578 struct drm_file *file_priv);
579 int i915_gem_execbuffer(struct drm_device *dev, void *data,
580 struct drm_file *file_priv);
581 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
582 struct drm_file *file_priv);
583 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
584 struct drm_file *file_priv);
585 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
586 struct drm_file *file_priv);
587 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
588 struct drm_file *file_priv);
589 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
590 struct drm_file *file_priv);
591 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
592 struct drm_file *file_priv);
593 int i915_gem_set_tiling(struct drm_device *dev, void *data,
594 struct drm_file *file_priv);
595 int i915_gem_get_tiling(struct drm_device *dev, void *data,
596 struct drm_file *file_priv);
597 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
598 struct drm_file *file_priv);
599 void i915_gem_load(struct drm_device *dev);
600 int i915_gem_proc_init(struct drm_minor *minor);
601 void i915_gem_proc_cleanup(struct drm_minor *minor);
602 int i915_gem_init_object(struct drm_gem_object *obj);
603 void i915_gem_free_object(struct drm_gem_object *obj);
604 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
605 void i915_gem_object_unpin(struct drm_gem_object *obj);
606 int i915_gem_object_unbind(struct drm_gem_object *obj);
607 void i915_gem_lastclose(struct drm_device *dev);
608 uint32_t i915_get_gem_seqno(struct drm_device *dev);
609 void i915_gem_retire_requests(struct drm_device *dev);
610 void i915_gem_retire_work_handler(struct work_struct *work);
611 void i915_gem_clflush_object(struct drm_gem_object *obj);
612 int i915_gem_object_set_domain(struct drm_gem_object *obj,
613 uint32_t read_domains,
614 uint32_t write_domain);
615 int i915_gem_init_ringbuffer(struct drm_device *dev);
616 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
617 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
619 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
620 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
622 int i915_gem_attach_phys_object(struct drm_device *dev,
623 struct drm_gem_object *obj, int id);
624 void i915_gem_detach_phys_object(struct drm_device *dev,
625 struct drm_gem_object *obj);
626 void i915_gem_free_all_phys_object(struct drm_device *dev);
628 /* i915_gem_tiling.c */
629 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
631 /* i915_gem_debug.c */
632 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
633 const char *where, uint32_t mark);
635 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
637 #define i915_verify_inactive(dev, file, line)
639 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
640 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
641 const char *where, uint32_t mark);
642 void i915_dump_lru(struct drm_device *dev, const char *where);
645 extern int i915_save_state(struct drm_device *dev);
646 extern int i915_restore_state(struct drm_device *dev);
649 extern int i915_save_state(struct drm_device *dev);
650 extern int i915_restore_state(struct drm_device *dev);
653 /* i915_opregion.c */
654 extern int intel_opregion_init(struct drm_device *dev);
655 extern void intel_opregion_free(struct drm_device *dev);
656 extern void opregion_asle_intr(struct drm_device *dev);
657 extern void opregion_enable_asle(struct drm_device *dev);
659 static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
660 static inline void intel_opregion_free(struct drm_device *dev) { return; }
661 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
662 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
666 extern void intel_modeset_init(struct drm_device *dev);
667 extern void intel_modeset_cleanup(struct drm_device *dev);
670 * Lock test for when it's just for synchronization of ring access.
672 * In that case, we don't need to do it when GEM is initialized as nobody else
673 * has access to the ring.
675 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
676 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
677 LOCK_TEST_WITH_RETURN(dev, file_priv); \
680 #define I915_READ(reg) readl(dev_priv->regs + (reg))
681 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
682 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
683 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
684 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
685 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
687 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
689 #define I915_WRITE64(reg, val) (writel(val, dev_priv->regs + (reg)), \
690 writel(upper_32_bits(val), dev_priv->regs + \
693 #define POSTING_READ(reg) (void)I915_READ(reg)
695 #define I915_VERBOSE 0
697 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
700 #define BEGIN_LP_RING(n) do { \
702 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
703 if (dev_priv->ring.space < (n)*4) \
704 i915_wait_ring(dev, (n)*4, __func__); \
706 outring = dev_priv->ring.tail; \
707 ringmask = dev_priv->ring.tail_mask; \
708 virt = dev_priv->ring.virtual_start; \
711 #define OUT_RING(n) do { \
712 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
713 *(volatile unsigned int *)(virt + outring) = (n); \
716 outring &= ringmask; \
719 #define ADVANCE_LP_RING() do { \
720 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
721 dev_priv->ring.tail = outring; \
722 dev_priv->ring.space -= outcount * 4; \
723 I915_WRITE(PRB0_TAIL, outring); \
727 * Reads a dword out of the status page, which is written to from the command
728 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
731 * The following dwords have a reserved meaning:
732 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
733 * 0x04: ring 0 head pointer
734 * 0x05: ring 1 head pointer (915-class)
735 * 0x06: ring 2 head pointer (915-class)
736 * 0x10-0x1b: Context status DWords (GM45)
737 * 0x1f: Last written status offset. (GM45)
739 * The area from dword 0x20 to 0x3ff is available for driver usage.
741 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
742 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
743 #define I915_GEM_HWS_INDEX 0x20
744 #define I915_BREADCRUMB_INDEX 0x21
746 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
748 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
749 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
750 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
751 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
752 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
754 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
755 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
756 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
757 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
758 (dev)->pci_device == 0x27AE)
759 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
760 (dev)->pci_device == 0x2982 || \
761 (dev)->pci_device == 0x2992 || \
762 (dev)->pci_device == 0x29A2 || \
763 (dev)->pci_device == 0x2A02 || \
764 (dev)->pci_device == 0x2A12 || \
765 (dev)->pci_device == 0x2A42 || \
766 (dev)->pci_device == 0x2E02 || \
767 (dev)->pci_device == 0x2E12 || \
768 (dev)->pci_device == 0x2E22)
770 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
772 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
774 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
775 (dev)->pci_device == 0x2E12 || \
776 (dev)->pci_device == 0x2E22 || \
779 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
780 (dev)->pci_device == 0x29B2 || \
781 (dev)->pci_device == 0x29D2)
783 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
784 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
786 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
787 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
789 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
790 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
791 * rows, which changed the alignment requirements and fence programming.
793 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
795 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev))
797 #define PRIMARY_RINGBUFFER_SIZE (128*1024)