git.oblomov.eu Git - linux-2.6/blob - drivers/net/s6gmac.c

   1 /*
   2  * Ethernet driver for S6105 on chip network device
   3  * (c)2008 emlix GmbH http://www.emlix.com
   4  * Authors:     Oskar Schirmer <os@emlix.com>
   5  *              Daniel Gloeckner <dg@emlix.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/types.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/netdevice.h>
  20 #include <linux/etherdevice.h>
  21 #include <linux/if.h>
  22 #include <linux/stddef.h>
  23 #include <linux/mii.h>
  24 #include <linux/phy.h>
  25 #include <linux/platform_device.h>
  26 #include <variant/hardware.h>
  27 #include <variant/dmac.h>
  28
  29 #define DRV_NAME "s6gmac"
  30 #define DRV_PRMT DRV_NAME ": "
  31
  32
  33 /* register declarations */
  34
  35 #define S6_GMAC_MACCONF1        0x000
  36 #define S6_GMAC_MACCONF1_TXENA          0
  37 #define S6_GMAC_MACCONF1_SYNCTX         1
  38 #define S6_GMAC_MACCONF1_RXENA          2
  39 #define S6_GMAC_MACCONF1_SYNCRX         3
  40 #define S6_GMAC_MACCONF1_TXFLOWCTRL     4
  41 #define S6_GMAC_MACCONF1_RXFLOWCTRL     5
  42 #define S6_GMAC_MACCONF1_LOOPBACK       8
  43 #define S6_GMAC_MACCONF1_RESTXFUNC      16
  44 #define S6_GMAC_MACCONF1_RESRXFUNC      17
  45 #define S6_GMAC_MACCONF1_RESTXMACCTRL   18
  46 #define S6_GMAC_MACCONF1_RESRXMACCTRL   19
  47 #define S6_GMAC_MACCONF1_SIMULRES       30
  48 #define S6_GMAC_MACCONF1_SOFTRES        31
  49 #define S6_GMAC_MACCONF2        0x004
  50 #define S6_GMAC_MACCONF2_FULL           0
  51 #define S6_GMAC_MACCONF2_CRCENA         1
  52 #define S6_GMAC_MACCONF2_PADCRCENA      2
  53 #define S6_GMAC_MACCONF2_LENGTHFCHK     4
  54 #define S6_GMAC_MACCONF2_HUGEFRAMENA    5
  55 #define S6_GMAC_MACCONF2_IFMODE         8
  56 #define S6_GMAC_MACCONF2_IFMODE_NIBBLE          1
  57 #define S6_GMAC_MACCONF2_IFMODE_BYTE            2
  58 #define S6_GMAC_MACCONF2_IFMODE_MASK            3
  59 #define S6_GMAC_MACCONF2_PREAMBLELEN    12
  60 #define S6_GMAC_MACCONF2_PREAMBLELEN_MASK       0x0F
  61 #define S6_GMAC_MACIPGIFG       0x008
  62 #define S6_GMAC_MACIPGIFG_B2BINTERPGAP  0
  63 #define S6_GMAC_MACIPGIFG_B2BINTERPGAP_MASK     0x7F
  64 #define S6_GMAC_MACIPGIFG_MINIFGENFORCE 8
  65 #define S6_GMAC_MACIPGIFG_B2BINTERPGAP2 16
  66 #define S6_GMAC_MACIPGIFG_B2BINTERPGAP1 24
  67 #define S6_GMAC_MACHALFDUPLEX   0x00C
  68 #define S6_GMAC_MACHALFDUPLEX_COLLISWIN 0
  69 #define S6_GMAC_MACHALFDUPLEX_COLLISWIN_MASK    0x3F
  70 #define S6_GMAC_MACHALFDUPLEX_RETXMAX   12
  71 #define S6_GMAC_MACHALFDUPLEX_RETXMAX_MASK      0x0F
  72 #define S6_GMAC_MACHALFDUPLEX_EXCESSDEF 16
  73 #define S6_GMAC_MACHALFDUPLEX_NOBACKOFF 17
  74 #define S6_GMAC_MACHALFDUPLEX_BPNOBCKOF 18
  75 #define S6_GMAC_MACHALFDUPLEX_ALTBEBENA 19
  76 #define S6_GMAC_MACHALFDUPLEX_ALTBEBTRN 20
  77 #define S6_GMAC_MACHALFDUPLEX_ALTBEBTR_MASK     0x0F
  78 #define S6_GMAC_MACMAXFRAMELEN  0x010
  79 #define S6_GMAC_MACMIICONF      0x020
  80 #define S6_GMAC_MACMIICONF_CSEL         0
  81 #define S6_GMAC_MACMIICONF_CSEL_DIV10           0
  82 #define S6_GMAC_MACMIICONF_CSEL_DIV12           1
  83 #define S6_GMAC_MACMIICONF_CSEL_DIV14           2
  84 #define S6_GMAC_MACMIICONF_CSEL_DIV18           3
  85 #define S6_GMAC_MACMIICONF_CSEL_DIV24           4
  86 #define S6_GMAC_MACMIICONF_CSEL_DIV34           5
  87 #define S6_GMAC_MACMIICONF_CSEL_DIV68           6
  88 #define S6_GMAC_MACMIICONF_CSEL_DIV168          7
  89 #define S6_GMAC_MACMIICONF_CSEL_MASK            7
  90 #define S6_GMAC_MACMIICONF_PREAMBLESUPR 4
  91 #define S6_GMAC_MACMIICONF_SCANAUTOINCR 5
  92 #define S6_GMAC_MACMIICMD       0x024
  93 #define S6_GMAC_MACMIICMD_READ          0
  94 #define S6_GMAC_MACMIICMD_SCAN          1
  95 #define S6_GMAC_MACMIIADDR      0x028
  96 #define S6_GMAC_MACMIIADDR_REG          0
  97 #define S6_GMAC_MACMIIADDR_REG_MASK             0x1F
  98 #define S6_GMAC_MACMIIADDR_PHY          8
  99 #define S6_GMAC_MACMIIADDR_PHY_MASK             0x1F
 100 #define S6_GMAC_MACMIICTRL      0x02C
 101 #define S6_GMAC_MACMIISTAT      0x030
 102 #define S6_GMAC_MACMIIINDI      0x034
 103 #define S6_GMAC_MACMIIINDI_BUSY         0
 104 #define S6_GMAC_MACMIIINDI_SCAN         1
 105 #define S6_GMAC_MACMIIINDI_INVAL        2
 106 #define S6_GMAC_MACINTERFSTAT   0x03C
 107 #define S6_GMAC_MACINTERFSTAT_LINKFAIL  3
 108 #define S6_GMAC_MACINTERFSTAT_EXCESSDEF 9
 109 #define S6_GMAC_MACSTATADDR1    0x040
 110 #define S6_GMAC_MACSTATADDR2    0x044
 111
 112 #define S6_GMAC_FIFOCONF0       0x048
 113 #define S6_GMAC_FIFOCONF0_HSTRSTWT      0
 114 #define S6_GMAC_FIFOCONF0_HSTRSTSR      1
 115 #define S6_GMAC_FIFOCONF0_HSTRSTFR      2
 116 #define S6_GMAC_FIFOCONF0_HSTRSTST      3
 117 #define S6_GMAC_FIFOCONF0_HSTRSTFT      4
 118 #define S6_GMAC_FIFOCONF0_WTMENREQ      8
 119 #define S6_GMAC_FIFOCONF0_SRFENREQ      9
 120 #define S6_GMAC_FIFOCONF0_FRFENREQ      10
 121 #define S6_GMAC_FIFOCONF0_STFENREQ      11
 122 #define S6_GMAC_FIFOCONF0_FTFENREQ      12
 123 #define S6_GMAC_FIFOCONF0_WTMENRPLY     16
 124 #define S6_GMAC_FIFOCONF0_SRFENRPLY     17
 125 #define S6_GMAC_FIFOCONF0_FRFENRPLY     18
 126 #define S6_GMAC_FIFOCONF0_STFENRPLY     19
 127 #define S6_GMAC_FIFOCONF0_FTFENRPLY     20
 128 #define S6_GMAC_FIFOCONF1       0x04C
 129 #define S6_GMAC_FIFOCONF2       0x050
 130 #define S6_GMAC_FIFOCONF2_CFGLWM        0
 131 #define S6_GMAC_FIFOCONF2_CFGHWM        16
 132 #define S6_GMAC_FIFOCONF3       0x054
 133 #define S6_GMAC_FIFOCONF3_CFGFTTH       0
 134 #define S6_GMAC_FIFOCONF3_CFGHWMFT      16
 135 #define S6_GMAC_FIFOCONF4       0x058
 136 #define S6_GMAC_FIFOCONF_RSV_PREVDROP   0
 137 #define S6_GMAC_FIFOCONF_RSV_RUNT       1
 138 #define S6_GMAC_FIFOCONF_RSV_FALSECAR   2
 139 #define S6_GMAC_FIFOCONF_RSV_CODEERR    3
 140 #define S6_GMAC_FIFOCONF_RSV_CRCERR     4
 141 #define S6_GMAC_FIFOCONF_RSV_LENGTHERR  5
 142 #define S6_GMAC_FIFOCONF_RSV_LENRANGE   6
 143 #define S6_GMAC_FIFOCONF_RSV_OK         7
 144 #define S6_GMAC_FIFOCONF_RSV_MULTICAST  8
 145 #define S6_GMAC_FIFOCONF_RSV_BROADCAST  9
 146 #define S6_GMAC_FIFOCONF_RSV_DRIBBLE    10
 147 #define S6_GMAC_FIFOCONF_RSV_CTRLFRAME  11
 148 #define S6_GMAC_FIFOCONF_RSV_PAUSECTRL  12
 149 #define S6_GMAC_FIFOCONF_RSV_UNOPCODE   13
 150 #define S6_GMAC_FIFOCONF_RSV_VLANTAG    14
 151 #define S6_GMAC_FIFOCONF_RSV_LONGEVENT  15
 152 #define S6_GMAC_FIFOCONF_RSV_TRUNCATED  16
 153 #define S6_GMAC_FIFOCONF_RSV_MASK               0x3FFFF
 154 #define S6_GMAC_FIFOCONF5       0x05C
 155 #define S6_GMAC_FIFOCONF5_DROPLT64      18
 156 #define S6_GMAC_FIFOCONF5_CFGBYTM       19
 157 #define S6_GMAC_FIFOCONF5_RXDROPSIZE    20
 158 #define S6_GMAC_FIFOCONF5_RXDROPSIZE_MASK       0xF
 159
 160 #define S6_GMAC_STAT_REGS       0x080
 161 #define S6_GMAC_STAT_SIZE_MIN           12
 162 #define S6_GMAC_STATTR64        0x080
 163 #define S6_GMAC_STATTR64_SIZE           18
 164 #define S6_GMAC_STATTR127       0x084
 165 #define S6_GMAC_STATTR127_SIZE          18
 166 #define S6_GMAC_STATTR255       0x088
 167 #define S6_GMAC_STATTR255_SIZE          18
 168 #define S6_GMAC_STATTR511       0x08C
 169 #define S6_GMAC_STATTR511_SIZE          18
 170 #define S6_GMAC_STATTR1K        0x090
 171 #define S6_GMAC_STATTR1K_SIZE           18
 172 #define S6_GMAC_STATTRMAX       0x094
 173 #define S6_GMAC_STATTRMAX_SIZE          18
 174 #define S6_GMAC_STATTRMGV       0x098
 175 #define S6_GMAC_STATTRMGV_SIZE          18
 176 #define S6_GMAC_STATRBYT        0x09C
 177 #define S6_GMAC_STATRBYT_SIZE           24
 178 #define S6_GMAC_STATRPKT        0x0A0
 179 #define S6_GMAC_STATRPKT_SIZE           18
 180 #define S6_GMAC_STATRFCS        0x0A4
 181 #define S6_GMAC_STATRFCS_SIZE           12
 182 #define S6_GMAC_STATRMCA        0x0A8
 183 #define S6_GMAC_STATRMCA_SIZE           18
 184 #define S6_GMAC_STATRBCA        0x0AC
 185 #define S6_GMAC_STATRBCA_SIZE           22
 186 #define S6_GMAC_STATRXCF        0x0B0
 187 #define S6_GMAC_STATRXCF_SIZE           18
 188 #define S6_GMAC_STATRXPF        0x0B4
 189 #define S6_GMAC_STATRXPF_SIZE           12
 190 #define S6_GMAC_STATRXUO        0x0B8
 191 #define S6_GMAC_STATRXUO_SIZE           12
 192 #define S6_GMAC_STATRALN        0x0BC
 193 #define S6_GMAC_STATRALN_SIZE           12
 194 #define S6_GMAC_STATRFLR        0x0C0
 195 #define S6_GMAC_STATRFLR_SIZE           16
 196 #define S6_GMAC_STATRCDE        0x0C4
 197 #define S6_GMAC_STATRCDE_SIZE           12
 198 #define S6_GMAC_STATRCSE        0x0C8
 199 #define S6_GMAC_STATRCSE_SIZE           12
 200 #define S6_GMAC_STATRUND        0x0CC
 201 #define S6_GMAC_STATRUND_SIZE           12
 202 #define S6_GMAC_STATROVR        0x0D0
 203 #define S6_GMAC_STATROVR_SIZE           12
 204 #define S6_GMAC_STATRFRG        0x0D4
 205 #define S6_GMAC_STATRFRG_SIZE           12
 206 #define S6_GMAC_STATRJBR        0x0D8
 207 #define S6_GMAC_STATRJBR_SIZE           12
 208 #define S6_GMAC_STATRDRP        0x0DC
 209 #define S6_GMAC_STATRDRP_SIZE           12
 210 #define S6_GMAC_STATTBYT        0x0E0
 211 #define S6_GMAC_STATTBYT_SIZE           24
 212 #define S6_GMAC_STATTPKT        0x0E4
 213 #define S6_GMAC_STATTPKT_SIZE           18
 214 #define S6_GMAC_STATTMCA        0x0E8
 215 #define S6_GMAC_STATTMCA_SIZE           18
 216 #define S6_GMAC_STATTBCA        0x0EC
 217 #define S6_GMAC_STATTBCA_SIZE           18
 218 #define S6_GMAC_STATTXPF        0x0F0
 219 #define S6_GMAC_STATTXPF_SIZE           12
 220 #define S6_GMAC_STATTDFR        0x0F4
 221 #define S6_GMAC_STATTDFR_SIZE           12
 222 #define S6_GMAC_STATTEDF        0x0F8
 223 #define S6_GMAC_STATTEDF_SIZE           12
 224 #define S6_GMAC_STATTSCL        0x0FC
 225 #define S6_GMAC_STATTSCL_SIZE           12
 226 #define S6_GMAC_STATTMCL        0x100
 227 #define S6_GMAC_STATTMCL_SIZE           12
 228 #define S6_GMAC_STATTLCL        0x104
 229 #define S6_GMAC_STATTLCL_SIZE           12
 230 #define S6_GMAC_STATTXCL        0x108
 231 #define S6_GMAC_STATTXCL_SIZE           12
 232 #define S6_GMAC_STATTNCL        0x10C
 233 #define S6_GMAC_STATTNCL_SIZE           13
 234 #define S6_GMAC_STATTPFH        0x110
 235 #define S6_GMAC_STATTPFH_SIZE           12
 236 #define S6_GMAC_STATTDRP        0x114
 237 #define S6_GMAC_STATTDRP_SIZE           12
 238 #define S6_GMAC_STATTJBR        0x118
 239 #define S6_GMAC_STATTJBR_SIZE           12
 240 #define S6_GMAC_STATTFCS        0x11C
 241 #define S6_GMAC_STATTFCS_SIZE           12
 242 #define S6_GMAC_STATTXCF        0x120
 243 #define S6_GMAC_STATTXCF_SIZE           12
 244 #define S6_GMAC_STATTOVR        0x124
 245 #define S6_GMAC_STATTOVR_SIZE           12
 246 #define S6_GMAC_STATTUND        0x128
 247 #define S6_GMAC_STATTUND_SIZE           12
 248 #define S6_GMAC_STATTFRG        0x12C
 249 #define S6_GMAC_STATTFRG_SIZE           12
 250 #define S6_GMAC_STATCARRY(n)    (0x130 + 4*(n))
 251 #define S6_GMAC_STATCARRYMSK(n) (0x138 + 4*(n))
 252 #define S6_GMAC_STATCARRY1_RDRP         0
 253 #define S6_GMAC_STATCARRY1_RJBR         1
 254 #define S6_GMAC_STATCARRY1_RFRG         2
 255 #define S6_GMAC_STATCARRY1_ROVR         3
 256 #define S6_GMAC_STATCARRY1_RUND         4
 257 #define S6_GMAC_STATCARRY1_RCSE         5
 258 #define S6_GMAC_STATCARRY1_RCDE         6
 259 #define S6_GMAC_STATCARRY1_RFLR         7
 260 #define S6_GMAC_STATCARRY1_RALN         8
 261 #define S6_GMAC_STATCARRY1_RXUO         9
 262 #define S6_GMAC_STATCARRY1_RXPF         10
 263 #define S6_GMAC_STATCARRY1_RXCF         11
 264 #define S6_GMAC_STATCARRY1_RBCA         12
 265 #define S6_GMAC_STATCARRY1_RMCA         13
 266 #define S6_GMAC_STATCARRY1_RFCS         14
 267 #define S6_GMAC_STATCARRY1_RPKT         15
 268 #define S6_GMAC_STATCARRY1_RBYT         16
 269 #define S6_GMAC_STATCARRY1_TRMGV        25
 270 #define S6_GMAC_STATCARRY1_TRMAX        26
 271 #define S6_GMAC_STATCARRY1_TR1K         27
 272 #define S6_GMAC_STATCARRY1_TR511        28
 273 #define S6_GMAC_STATCARRY1_TR255        29
 274 #define S6_GMAC_STATCARRY1_TR127        30
 275 #define S6_GMAC_STATCARRY1_TR64         31
 276 #define S6_GMAC_STATCARRY2_TDRP         0
 277 #define S6_GMAC_STATCARRY2_TPFH         1
 278 #define S6_GMAC_STATCARRY2_TNCL         2
 279 #define S6_GMAC_STATCARRY2_TXCL         3
 280 #define S6_GMAC_STATCARRY2_TLCL         4
 281 #define S6_GMAC_STATCARRY2_TMCL         5
 282 #define S6_GMAC_STATCARRY2_TSCL         6
 283 #define S6_GMAC_STATCARRY2_TEDF         7
 284 #define S6_GMAC_STATCARRY2_TDFR         8
 285 #define S6_GMAC_STATCARRY2_TXPF         9
 286 #define S6_GMAC_STATCARRY2_TBCA         10
 287 #define S6_GMAC_STATCARRY2_TMCA         11
 288 #define S6_GMAC_STATCARRY2_TPKT         12
 289 #define S6_GMAC_STATCARRY2_TBYT         13
 290 #define S6_GMAC_STATCARRY2_TFRG         14
 291 #define S6_GMAC_STATCARRY2_TUND         15
 292 #define S6_GMAC_STATCARRY2_TOVR         16
 293 #define S6_GMAC_STATCARRY2_TXCF         17
 294 #define S6_GMAC_STATCARRY2_TFCS         18
 295 #define S6_GMAC_STATCARRY2_TJBR         19
 296
 297 #define S6_GMAC_HOST_PBLKCTRL   0x140
 298 #define S6_GMAC_HOST_PBLKCTRL_TXENA     0
 299 #define S6_GMAC_HOST_PBLKCTRL_RXENA     1
 300 #define S6_GMAC_HOST_PBLKCTRL_TXSRES    2
 301 #define S6_GMAC_HOST_PBLKCTRL_RXSRES    3
 302 #define S6_GMAC_HOST_PBLKCTRL_TXBSIZ    8
 303 #define S6_GMAC_HOST_PBLKCTRL_RXBSIZ    12
 304 #define S6_GMAC_HOST_PBLKCTRL_SIZ_16            4
 305 #define S6_GMAC_HOST_PBLKCTRL_SIZ_32            5
 306 #define S6_GMAC_HOST_PBLKCTRL_SIZ_64            6
 307 #define S6_GMAC_HOST_PBLKCTRL_SIZ_128           7
 308 #define S6_GMAC_HOST_PBLKCTRL_SIZ_MASK          0xF
 309 #define S6_GMAC_HOST_PBLKCTRL_STATENA   16
 310 #define S6_GMAC_HOST_PBLKCTRL_STATAUTOZ 17
 311 #define S6_GMAC_HOST_PBLKCTRL_STATCLEAR 18
 312 #define S6_GMAC_HOST_PBLKCTRL_RGMII     19
 313 #define S6_GMAC_HOST_INTMASK    0x144
 314 #define S6_GMAC_HOST_INTSTAT    0x148
 315 #define S6_GMAC_HOST_INT_TXBURSTOVER    3
 316 #define S6_GMAC_HOST_INT_TXPREWOVER     4
 317 #define S6_GMAC_HOST_INT_RXBURSTUNDER   5
 318 #define S6_GMAC_HOST_INT_RXPOSTRFULL    6
 319 #define S6_GMAC_HOST_INT_RXPOSTRUNDER   7
 320 #define S6_GMAC_HOST_RXFIFOHWM  0x14C
 321 #define S6_GMAC_HOST_CTRLFRAMXP 0x150
 322 #define S6_GMAC_HOST_DSTADDRLO(n) (0x160 + 8*(n))
 323 #define S6_GMAC_HOST_DSTADDRHI(n) (0x164 + 8*(n))
 324 #define S6_GMAC_HOST_DSTMASKLO(n) (0x180 + 8*(n))
 325 #define S6_GMAC_HOST_DSTMASKHI(n) (0x184 + 8*(n))
 326
 327 #define S6_GMAC_BURST_PREWR     0x1B0
 328 #define S6_GMAC_BURST_PREWR_LEN         0
 329 #define S6_GMAC_BURST_PREWR_LEN_MASK            ((1 << 20) - 1)
 330 #define S6_GMAC_BURST_PREWR_CFE         20
 331 #define S6_GMAC_BURST_PREWR_PPE         21
 332 #define S6_GMAC_BURST_PREWR_FCS         22
 333 #define S6_GMAC_BURST_PREWR_PAD         23
 334 #define S6_GMAC_BURST_POSTRD    0x1D0
 335 #define S6_GMAC_BURST_POSTRD_LEN        0
 336 #define S6_GMAC_BURST_POSTRD_LEN_MASK           ((1 << 20) - 1)
 337 #define S6_GMAC_BURST_POSTRD_DROP       20
 338
 339
 340 /* data handling */
 341
 342 #define S6_NUM_TX_SKB   8       /* must be larger than TX fifo size */
 343 #define S6_NUM_RX_SKB   16
 344 #define S6_MAX_FRLEN    1536
 345
 346 struct s6gmac {
 347         u32 reg;
 348         u32 tx_dma;
 349         u32 rx_dma;
 350         u32 io;
 351         u8 tx_chan;
 352         u8 rx_chan;
 353         spinlock_t lock;
 354         u8 tx_skb_i, tx_skb_o;
 355         u8 rx_skb_i, rx_skb_o;
 356         struct sk_buff *tx_skb[S6_NUM_TX_SKB];
 357         struct sk_buff *rx_skb[S6_NUM_RX_SKB];
 358         unsigned long carry[sizeof(struct net_device_stats) / sizeof(long)];
 359         unsigned long stats[sizeof(struct net_device_stats) / sizeof(long)];
 360         struct phy_device *phydev;
 361         struct {
 362                 struct mii_bus *bus;
 363                 int irq[PHY_MAX_ADDR];
 364         } mii;
 365         struct {
 366                 unsigned int mbit;
 367                 u8 giga;
 368                 u8 isup;
 369                 u8 full;
 370         } link;
 371 };
 372
 373 static void s6gmac_rx_fillfifo(struct s6gmac *pd)
 374 {
 375         struct sk_buff *skb;
 376         while ((((u8)(pd->rx_skb_i - pd->rx_skb_o)) < S6_NUM_RX_SKB)
 377                         && (!s6dmac_fifo_full(pd->rx_dma, pd->rx_chan))
 378                         && (skb = dev_alloc_skb(S6_MAX_FRLEN + 2))) {
 379                 pd->rx_skb[(pd->rx_skb_i++) % S6_NUM_RX_SKB] = skb;
 380                 s6dmac_put_fifo_cache(pd->rx_dma, pd->rx_chan,
 381                         pd->io, (u32)skb->data, S6_MAX_FRLEN);
 382         }
 383 }
 384
 385 static void s6gmac_rx_interrupt(struct net_device *dev)
 386 {
 387         struct s6gmac *pd = netdev_priv(dev);
 388         u32 pfx;
 389         struct sk_buff *skb;
 390         while (((u8)(pd->rx_skb_i - pd->rx_skb_o)) >
 391                         s6dmac_pending_count(pd->rx_dma, pd->rx_chan)) {
 392                 skb = pd->rx_skb[(pd->rx_skb_o++) % S6_NUM_RX_SKB];
 393                 pfx = readl(pd->reg + S6_GMAC_BURST_POSTRD);
 394                 if (pfx & (1 << S6_GMAC_BURST_POSTRD_DROP)) {
 395                         dev_kfree_skb_irq(skb);
 396                 } else {
 397                         skb_put(skb, (pfx >> S6_GMAC_BURST_POSTRD_LEN)
 398                                 & S6_GMAC_BURST_POSTRD_LEN_MASK);
 399                         skb->dev = dev;
 400                         skb->protocol = eth_type_trans(skb, dev);
 401                         skb->ip_summed = CHECKSUM_UNNECESSARY;
 402                         netif_rx(skb);
 403                 }
 404         }
 405 }
 406
 407 static void s6gmac_tx_interrupt(struct net_device *dev)
 408 {
 409         struct s6gmac *pd = netdev_priv(dev);
 410         while (((u8)(pd->tx_skb_i - pd->tx_skb_o)) >
 411                         s6dmac_pending_count(pd->tx_dma, pd->tx_chan)) {
 412                 dev_kfree_skb_irq(pd->tx_skb[(pd->tx_skb_o++) % S6_NUM_TX_SKB]);
 413         }
 414         if (!s6dmac_fifo_full(pd->tx_dma, pd->tx_chan))
 415                 netif_wake_queue(dev);
 416 }
 417
 418 struct s6gmac_statinf {
 419         unsigned reg_size : 4; /* 0: unused */
 420         unsigned reg_off : 6;
 421         unsigned net_index : 6;
 422 };
 423
 424 #define S6_STATS_B (8 * sizeof(u32))
 425 #define S6_STATS_C(b, r, f) [b] = { \
 426         BUILD_BUG_ON_ZERO(r##_SIZE < S6_GMAC_STAT_SIZE_MIN) + \
 427         BUILD_BUG_ON_ZERO((r##_SIZE - (S6_GMAC_STAT_SIZE_MIN - 1)) \
 428                         >= (1<<4)) + \
 429         r##_SIZE - (S6_GMAC_STAT_SIZE_MIN - 1), \
 430         BUILD_BUG_ON_ZERO(((unsigned)((r - S6_GMAC_STAT_REGS) / sizeof(u32))) \
 431                         >= ((1<<6)-1)) + \
 432         (r - S6_GMAC_STAT_REGS) / sizeof(u32), \
 433         BUILD_BUG_ON_ZERO((offsetof(struct net_device_stats, f)) \
 434                         % sizeof(unsigned long)) + \
 435         BUILD_BUG_ON_ZERO((((unsigned)(offsetof(struct net_device_stats, f)) \
 436                         / sizeof(unsigned long)) >= (1<<6))) + \
 437         BUILD_BUG_ON_ZERO((sizeof(((struct net_device_stats *)0)->f) \
 438                         != sizeof(unsigned long))) + \
 439         (offsetof(struct net_device_stats, f)) / sizeof(unsigned long)},
 440
 441 static const struct s6gmac_statinf statinf[2][S6_STATS_B] = { {
 442         S6_STATS_C(S6_GMAC_STATCARRY1_RBYT, S6_GMAC_STATRBYT, rx_bytes)
 443         S6_STATS_C(S6_GMAC_STATCARRY1_RPKT, S6_GMAC_STATRPKT, rx_packets)
 444         S6_STATS_C(S6_GMAC_STATCARRY1_RFCS, S6_GMAC_STATRFCS, rx_crc_errors)
 445         S6_STATS_C(S6_GMAC_STATCARRY1_RMCA, S6_GMAC_STATRMCA, multicast)
 446         S6_STATS_C(S6_GMAC_STATCARRY1_RALN, S6_GMAC_STATRALN, rx_frame_errors)
 447         S6_STATS_C(S6_GMAC_STATCARRY1_RFLR, S6_GMAC_STATRFLR, rx_length_errors)
 448         S6_STATS_C(S6_GMAC_STATCARRY1_RCDE, S6_GMAC_STATRCDE, rx_missed_errors)
 449         S6_STATS_C(S6_GMAC_STATCARRY1_RUND, S6_GMAC_STATRUND, rx_length_errors)
 450         S6_STATS_C(S6_GMAC_STATCARRY1_ROVR, S6_GMAC_STATROVR, rx_length_errors)
 451         S6_STATS_C(S6_GMAC_STATCARRY1_RFRG, S6_GMAC_STATRFRG, rx_crc_errors)
 452         S6_STATS_C(S6_GMAC_STATCARRY1_RJBR, S6_GMAC_STATRJBR, rx_crc_errors)
 453         S6_STATS_C(S6_GMAC_STATCARRY1_RDRP, S6_GMAC_STATRDRP, rx_dropped)
 454 }, {
 455         S6_STATS_C(S6_GMAC_STATCARRY2_TBYT, S6_GMAC_STATTBYT, tx_bytes)
 456         S6_STATS_C(S6_GMAC_STATCARRY2_TPKT, S6_GMAC_STATTPKT, tx_packets)
 457         S6_STATS_C(S6_GMAC_STATCARRY2_TEDF, S6_GMAC_STATTEDF, tx_aborted_errors)
 458         S6_STATS_C(S6_GMAC_STATCARRY2_TXCL, S6_GMAC_STATTXCL, tx_aborted_errors)
 459         S6_STATS_C(S6_GMAC_STATCARRY2_TNCL, S6_GMAC_STATTNCL, collisions)
 460         S6_STATS_C(S6_GMAC_STATCARRY2_TDRP, S6_GMAC_STATTDRP, tx_dropped)
 461         S6_STATS_C(S6_GMAC_STATCARRY2_TJBR, S6_GMAC_STATTJBR, tx_errors)
 462         S6_STATS_C(S6_GMAC_STATCARRY2_TFCS, S6_GMAC_STATTFCS, tx_errors)
 463         S6_STATS_C(S6_GMAC_STATCARRY2_TOVR, S6_GMAC_STATTOVR, tx_errors)
 464         S6_STATS_C(S6_GMAC_STATCARRY2_TUND, S6_GMAC_STATTUND, tx_errors)
 465         S6_STATS_C(S6_GMAC_STATCARRY2_TFRG, S6_GMAC_STATTFRG, tx_errors)
 466 } };
 467
 468 static void s6gmac_stats_collect(struct s6gmac *pd,
 469                 const struct s6gmac_statinf *inf)
 470 {
 471         int b;
 472         for (b = 0; b < S6_STATS_B; b++) {
 473                 if (inf[b].reg_size) {
 474                         pd->stats[inf[b].net_index] +=
 475                                 readl(pd->reg + S6_GMAC_STAT_REGS
 476                                         + sizeof(u32) * inf[b].reg_off);
 477                 }
 478         }
 479 }
 480
 481 static void s6gmac_stats_carry(struct s6gmac *pd,
 482                 const struct s6gmac_statinf *inf, u32 mask)
 483 {
 484         int b;
 485         while (mask) {
 486                 b = fls(mask) - 1;
 487                 mask &= ~(1 << b);
 488                 pd->carry[inf[b].net_index] += (1 << inf[b].reg_size);
 489         }
 490 }
 491
 492 static inline u32 s6gmac_stats_pending(struct s6gmac *pd, int carry)
 493 {
 494         int r = readl(pd->reg + S6_GMAC_STATCARRY(carry)) &
 495                 ~readl(pd->reg + S6_GMAC_STATCARRYMSK(carry));
 496         return r;
 497 }
 498
 499 static inline void s6gmac_stats_interrupt(struct s6gmac *pd, int carry)
 500 {
 501         u32 mask;
 502         mask = s6gmac_stats_pending(pd, carry);
 503         if (mask) {
 504                 writel(mask, pd->reg + S6_GMAC_STATCARRY(carry));
 505                 s6gmac_stats_carry(pd, &statinf[carry][0], mask);
 506         }
 507 }
 508
 509 static irqreturn_t s6gmac_interrupt(int irq, void *dev_id)
 510 {
 511         struct net_device *dev = (struct net_device *)dev_id;
 512         struct s6gmac *pd = netdev_priv(dev);
 513         if (!dev)
 514                 return IRQ_NONE;
 515         spin_lock(&pd->lock);
 516         if (s6dmac_termcnt_irq(pd->rx_dma, pd->rx_chan))
 517                 s6gmac_rx_interrupt(dev);
 518         s6gmac_rx_fillfifo(pd);
 519         if (s6dmac_termcnt_irq(pd->tx_dma, pd->tx_chan))
 520                 s6gmac_tx_interrupt(dev);
 521         s6gmac_stats_interrupt(pd, 0);
 522         s6gmac_stats_interrupt(pd, 1);
 523         spin_unlock(&pd->lock);
 524         return IRQ_HANDLED;
 525 }
 526
 527 static inline void s6gmac_set_dstaddr(struct s6gmac *pd, int n,
 528         u32 addrlo, u32 addrhi, u32 masklo, u32 maskhi)
 529 {
 530         writel(addrlo, pd->reg + S6_GMAC_HOST_DSTADDRLO(n));
 531         writel(addrhi, pd->reg + S6_GMAC_HOST_DSTADDRHI(n));
 532         writel(masklo, pd->reg + S6_GMAC_HOST_DSTMASKLO(n));
 533         writel(maskhi, pd->reg + S6_GMAC_HOST_DSTMASKHI(n));
 534 }
 535
 536 static inline void s6gmac_stop_device(struct net_device *dev)
 537 {
 538         struct s6gmac *pd = netdev_priv(dev);
 539         writel(0, pd->reg + S6_GMAC_MACCONF1);
 540 }
 541
 542 static inline void s6gmac_init_device(struct net_device *dev)
 543 {
 544         struct s6gmac *pd = netdev_priv(dev);
 545         int is_rgmii = !!(pd->phydev->supported
 546                 & (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half));
 547 #if 0
 548         writel(1 << S6_GMAC_MACCONF1_SYNCTX |
 549                 1 << S6_GMAC_MACCONF1_SYNCRX |
 550                 1 << S6_GMAC_MACCONF1_TXFLOWCTRL |
 551                 1 << S6_GMAC_MACCONF1_RXFLOWCTRL |
 552                 1 << S6_GMAC_MACCONF1_RESTXFUNC |
 553                 1 << S6_GMAC_MACCONF1_RESRXFUNC |
 554                 1 << S6_GMAC_MACCONF1_RESTXMACCTRL |
 555                 1 << S6_GMAC_MACCONF1_RESRXMACCTRL,
 556                 pd->reg + S6_GMAC_MACCONF1);
 557 #endif
 558         writel(1 << S6_GMAC_MACCONF1_SOFTRES, pd->reg + S6_GMAC_MACCONF1);
 559         udelay(1000);
 560         writel(1 << S6_GMAC_MACCONF1_TXENA | 1 << S6_GMAC_MACCONF1_RXENA,
 561                 pd->reg + S6_GMAC_MACCONF1);
 562         writel(1 << S6_GMAC_HOST_PBLKCTRL_TXSRES |
 563                 1 << S6_GMAC_HOST_PBLKCTRL_RXSRES,
 564                 pd->reg + S6_GMAC_HOST_PBLKCTRL);
 565         writel(S6_GMAC_HOST_PBLKCTRL_SIZ_128 << S6_GMAC_HOST_PBLKCTRL_TXBSIZ |
 566                 S6_GMAC_HOST_PBLKCTRL_SIZ_128 << S6_GMAC_HOST_PBLKCTRL_RXBSIZ |
 567                 1 << S6_GMAC_HOST_PBLKCTRL_STATENA |
 568                 1 << S6_GMAC_HOST_PBLKCTRL_STATCLEAR |
 569                 is_rgmii << S6_GMAC_HOST_PBLKCTRL_RGMII,
 570                 pd->reg + S6_GMAC_HOST_PBLKCTRL);
 571         writel(1 << S6_GMAC_MACCONF1_TXENA |
 572                 1 << S6_GMAC_MACCONF1_RXENA |
 573                 (dev->flags & IFF_LOOPBACK ? 1 : 0)
 574                         << S6_GMAC_MACCONF1_LOOPBACK,
 575                 pd->reg + S6_GMAC_MACCONF1);
 576         writel(dev->mtu && (dev->mtu < (S6_MAX_FRLEN - ETH_HLEN-ETH_FCS_LEN)) ?
 577                         dev->mtu+ETH_HLEN+ETH_FCS_LEN : S6_MAX_FRLEN,
 578                 pd->reg + S6_GMAC_MACMAXFRAMELEN);
 579         writel((pd->link.full ? 1 : 0) << S6_GMAC_MACCONF2_FULL |
 580                 1 << S6_GMAC_MACCONF2_PADCRCENA |
 581                 1 << S6_GMAC_MACCONF2_LENGTHFCHK |
 582                 (pd->link.giga ?
 583                         S6_GMAC_MACCONF2_IFMODE_BYTE :
 584                         S6_GMAC_MACCONF2_IFMODE_NIBBLE)
 585                         << S6_GMAC_MACCONF2_IFMODE |
 586                 7 << S6_GMAC_MACCONF2_PREAMBLELEN,
 587                 pd->reg + S6_GMAC_MACCONF2);
 588         writel(0, pd->reg + S6_GMAC_MACSTATADDR1);
 589         writel(0, pd->reg + S6_GMAC_MACSTATADDR2);
 590         writel(1 << S6_GMAC_FIFOCONF0_WTMENREQ |
 591                 1 << S6_GMAC_FIFOCONF0_SRFENREQ |
 592                 1 << S6_GMAC_FIFOCONF0_FRFENREQ |
 593                 1 << S6_GMAC_FIFOCONF0_STFENREQ |
 594                 1 << S6_GMAC_FIFOCONF0_FTFENREQ,
 595                 pd->reg + S6_GMAC_FIFOCONF0);
 596         writel(128 << S6_GMAC_FIFOCONF3_CFGFTTH |
 597                 128 << S6_GMAC_FIFOCONF3_CFGHWMFT,
 598                 pd->reg + S6_GMAC_FIFOCONF3);
 599         writel((S6_GMAC_FIFOCONF_RSV_MASK & ~(
 600                         1 << S6_GMAC_FIFOCONF_RSV_RUNT |
 601                         1 << S6_GMAC_FIFOCONF_RSV_CRCERR |
 602                         1 << S6_GMAC_FIFOCONF_RSV_OK |
 603                         1 << S6_GMAC_FIFOCONF_RSV_DRIBBLE |
 604                         1 << S6_GMAC_FIFOCONF_RSV_CTRLFRAME |
 605                         1 << S6_GMAC_FIFOCONF_RSV_PAUSECTRL |
 606                         1 << S6_GMAC_FIFOCONF_RSV_UNOPCODE |
 607                         1 << S6_GMAC_FIFOCONF_RSV_TRUNCATED)) |
 608                 1 << S6_GMAC_FIFOCONF5_DROPLT64 |
 609                 pd->link.giga << S6_GMAC_FIFOCONF5_CFGBYTM |
 610                 1 << S6_GMAC_FIFOCONF5_RXDROPSIZE,
 611                 pd->reg + S6_GMAC_FIFOCONF5);
 612         writel(1 << S6_GMAC_FIFOCONF_RSV_RUNT |
 613                 1 << S6_GMAC_FIFOCONF_RSV_CRCERR |
 614                 1 << S6_GMAC_FIFOCONF_RSV_DRIBBLE |
 615                 1 << S6_GMAC_FIFOCONF_RSV_CTRLFRAME |
 616                 1 << S6_GMAC_FIFOCONF_RSV_PAUSECTRL |
 617                 1 << S6_GMAC_FIFOCONF_RSV_UNOPCODE |
 618                 1 << S6_GMAC_FIFOCONF_RSV_TRUNCATED,
 619                 pd->reg + S6_GMAC_FIFOCONF4);
 620         s6gmac_set_dstaddr(pd, 0,
 621                 0xFFFFFFFF, 0x0000FFFF, 0xFFFFFFFF, 0x0000FFFF);
 622         s6gmac_set_dstaddr(pd, 1,
 623                 dev->dev_addr[5] |
 624                 dev->dev_addr[4] << 8 |
 625                 dev->dev_addr[3] << 16 |
 626                 dev->dev_addr[2] << 24,
 627                 dev->dev_addr[1] |
 628                 dev->dev_addr[0] << 8,
 629                 0xFFFFFFFF, 0x0000FFFF);
 630         s6gmac_set_dstaddr(pd, 2,
 631                 0x00000000, 0x00000100, 0x00000000, 0x00000100);
 632         s6gmac_set_dstaddr(pd, 3,
 633                 0x00000000, 0x00000000, 0x00000000, 0x00000000);
 634         writel(1 << S6_GMAC_HOST_PBLKCTRL_TXENA |
 635                 1 << S6_GMAC_HOST_PBLKCTRL_RXENA |
 636                 S6_GMAC_HOST_PBLKCTRL_SIZ_128 << S6_GMAC_HOST_PBLKCTRL_TXBSIZ |
 637                 S6_GMAC_HOST_PBLKCTRL_SIZ_128 << S6_GMAC_HOST_PBLKCTRL_RXBSIZ |
 638                 1 << S6_GMAC_HOST_PBLKCTRL_STATENA |
 639                 1 << S6_GMAC_HOST_PBLKCTRL_STATCLEAR |
 640                 is_rgmii << S6_GMAC_HOST_PBLKCTRL_RGMII,
 641                 pd->reg + S6_GMAC_HOST_PBLKCTRL);
 642 }
 643
 644 static void s6mii_enable(struct s6gmac *pd)
 645 {
 646         writel(readl(pd->reg + S6_GMAC_MACCONF1) &
 647                 ~(1 << S6_GMAC_MACCONF1_SOFTRES),
 648                 pd->reg + S6_GMAC_MACCONF1);
 649         writel((readl(pd->reg + S6_GMAC_MACMIICONF)
 650                 & ~(S6_GMAC_MACMIICONF_CSEL_MASK << S6_GMAC_MACMIICONF_CSEL))
 651                 | (S6_GMAC_MACMIICONF_CSEL_DIV168 << S6_GMAC_MACMIICONF_CSEL),
 652                 pd->reg + S6_GMAC_MACMIICONF);
 653 }
 654
 655 static int s6mii_busy(struct s6gmac *pd, int tmo)
 656 {
 657         while (readl(pd->reg + S6_GMAC_MACMIIINDI)) {
 658                 if (--tmo == 0)
 659                         return -ETIME;
 660                 udelay(64);
 661         }
 662         return 0;
 663 }
 664
 665 static int s6mii_read(struct mii_bus *bus, int phy_addr, int regnum)
 666 {
 667         struct s6gmac *pd = bus->priv;
 668         s6mii_enable(pd);
 669         if (s6mii_busy(pd, 256))
 670                 return -ETIME;
 671         writel(phy_addr << S6_GMAC_MACMIIADDR_PHY |
 672                 regnum << S6_GMAC_MACMIIADDR_REG,
 673                 pd->reg + S6_GMAC_MACMIIADDR);
 674         writel(1 << S6_GMAC_MACMIICMD_READ, pd->reg + S6_GMAC_MACMIICMD);
 675         writel(0, pd->reg + S6_GMAC_MACMIICMD);
 676         if (s6mii_busy(pd, 256))
 677                 return -ETIME;
 678         return (u16)readl(pd->reg + S6_GMAC_MACMIISTAT);
 679 }
 680
 681 static int s6mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
 682 {
 683         struct s6gmac *pd = bus->priv;
 684         s6mii_enable(pd);
 685         if (s6mii_busy(pd, 256))
 686                 return -ETIME;
 687         writel(phy_addr << S6_GMAC_MACMIIADDR_PHY |
 688                 regnum << S6_GMAC_MACMIIADDR_REG,
 689                 pd->reg + S6_GMAC_MACMIIADDR);
 690         writel(value, pd->reg + S6_GMAC_MACMIICTRL);
 691         if (s6mii_busy(pd, 256))
 692                 return -ETIME;
 693         return 0;
 694 }
 695
 696 static int s6mii_reset(struct mii_bus *bus)
 697 {
 698         struct s6gmac *pd = bus->priv;
 699         s6mii_enable(pd);
 700         if (s6mii_busy(pd, PHY_INIT_TIMEOUT))
 701                 return -ETIME;
 702         return 0;
 703 }
 704
 705 static void s6gmac_set_rgmii_txclock(struct s6gmac *pd)
 706 {
 707         u32 pllsel = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL);
 708         pllsel &= ~(S6_GREG1_PLLSEL_GMAC_MASK << S6_GREG1_PLLSEL_GMAC);
 709         switch (pd->link.mbit) {
 710         case 10:
 711                 pllsel |= S6_GREG1_PLLSEL_GMAC_2500KHZ << S6_GREG1_PLLSEL_GMAC;
 712                 break;
 713         case 100:
 714                 pllsel |= S6_GREG1_PLLSEL_GMAC_25MHZ << S6_GREG1_PLLSEL_GMAC;
 715                 break;
 716         case 1000:
 717                 pllsel |= S6_GREG1_PLLSEL_GMAC_125MHZ << S6_GREG1_PLLSEL_GMAC;
 718                 break;
 719         default:
 720                 return;
 721         }
 722         writel(pllsel, S6_REG_GREG1 + S6_GREG1_PLLSEL);
 723 }
 724
 725 static inline void s6gmac_linkisup(struct net_device *dev, int isup)
 726 {
 727         struct s6gmac *pd = netdev_priv(dev);
 728         struct phy_device *phydev = pd->phydev;
 729
 730         pd->link.full = phydev->duplex;
 731         pd->link.giga = (phydev->speed == 1000);
 732         if (pd->link.mbit != phydev->speed) {
 733                 pd->link.mbit = phydev->speed;
 734                 s6gmac_set_rgmii_txclock(pd);
 735         }
 736         pd->link.isup = isup;
 737         if (isup)
 738                 netif_carrier_on(dev);
 739         phy_print_status(phydev);
 740 }
 741
 742 static void s6gmac_adjust_link(struct net_device *dev)
 743 {
 744         struct s6gmac *pd = netdev_priv(dev);
 745         struct phy_device *phydev = pd->phydev;
 746         if (pd->link.isup &&
 747                         (!phydev->link ||
 748                         (pd->link.mbit != phydev->speed) ||
 749                         (pd->link.full != phydev->duplex))) {
 750                 pd->link.isup = 0;
 751                 netif_tx_disable(dev);
 752                 if (!phydev->link) {
 753                         netif_carrier_off(dev);
 754                         phy_print_status(phydev);
 755                 }
 756         }
 757         if (!pd->link.isup && phydev->link) {
 758                 if (pd->link.full != phydev->duplex) {
 759                         u32 maccfg = readl(pd->reg + S6_GMAC_MACCONF2);
 760                         if (phydev->duplex)
 761                                 maccfg |= 1 << S6_GMAC_MACCONF2_FULL;
 762                         else
 763                                 maccfg &= ~(1 << S6_GMAC_MACCONF2_FULL);
 764                         writel(maccfg, pd->reg + S6_GMAC_MACCONF2);
 765                 }
 766
 767                 if (pd->link.giga != (phydev->speed == 1000)) {
 768                         u32 fifocfg = readl(pd->reg + S6_GMAC_FIFOCONF5);
 769                         u32 maccfg = readl(pd->reg + S6_GMAC_MACCONF2);
 770                         maccfg &= ~(S6_GMAC_MACCONF2_IFMODE_MASK
 771                                      << S6_GMAC_MACCONF2_IFMODE);
 772                         if (phydev->speed == 1000) {
 773                                 fifocfg |= 1 << S6_GMAC_FIFOCONF5_CFGBYTM;
 774                                 maccfg |= S6_GMAC_MACCONF2_IFMODE_BYTE
 775                                            << S6_GMAC_MACCONF2_IFMODE;
 776                         } else {
 777                                 fifocfg &= ~(1 << S6_GMAC_FIFOCONF5_CFGBYTM);
 778                                 maccfg |= S6_GMAC_MACCONF2_IFMODE_NIBBLE
 779                                            << S6_GMAC_MACCONF2_IFMODE;
 780                         }
 781                         writel(fifocfg, pd->reg + S6_GMAC_FIFOCONF5);
 782                         writel(maccfg, pd->reg + S6_GMAC_MACCONF2);
 783                 }
 784
 785                 if (!s6dmac_fifo_full(pd->tx_dma, pd->tx_chan))
 786                         netif_wake_queue(dev);
 787                 s6gmac_linkisup(dev, 1);
 788         }
 789 }
 790
 791 static inline int s6gmac_phy_start(struct net_device *dev)
 792 {
 793         struct s6gmac *pd = netdev_priv(dev);
 794         int i = 0;
 795         struct phy_device *p = NULL;
 796         while ((!(p = pd->mii.bus->phy_map[i])) && (i < PHY_MAX_ADDR))
 797                 i++;
 798         p = phy_connect(dev, dev_name(&p->dev), &s6gmac_adjust_link, 0,
 799                         PHY_INTERFACE_MODE_RGMII);
 800         if (IS_ERR(p)) {
 801                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 802                 return PTR_ERR(p);
 803         }
 804         p->supported &= PHY_GBIT_FEATURES;
 805         p->advertising = p->supported;
 806         pd->phydev = p;
 807         return 0;
 808 }
 809
 810 static inline void s6gmac_init_stats(struct net_device *dev)
 811 {
 812         struct s6gmac *pd = netdev_priv(dev);
 813         u32 mask;
 814         mask =  1 << S6_GMAC_STATCARRY1_RDRP |
 815                 1 << S6_GMAC_STATCARRY1_RJBR |
 816                 1 << S6_GMAC_STATCARRY1_RFRG |
 817                 1 << S6_GMAC_STATCARRY1_ROVR |
 818                 1 << S6_GMAC_STATCARRY1_RUND |
 819                 1 << S6_GMAC_STATCARRY1_RCDE |
 820                 1 << S6_GMAC_STATCARRY1_RFLR |
 821                 1 << S6_GMAC_STATCARRY1_RALN |
 822                 1 << S6_GMAC_STATCARRY1_RMCA |
 823                 1 << S6_GMAC_STATCARRY1_RFCS |
 824                 1 << S6_GMAC_STATCARRY1_RPKT |
 825                 1 << S6_GMAC_STATCARRY1_RBYT;
 826         writel(mask, pd->reg + S6_GMAC_STATCARRY(0));
 827         writel(~mask, pd->reg + S6_GMAC_STATCARRYMSK(0));
 828         mask =  1 << S6_GMAC_STATCARRY2_TDRP |
 829                 1 << S6_GMAC_STATCARRY2_TNCL |
 830                 1 << S6_GMAC_STATCARRY2_TXCL |
 831                 1 << S6_GMAC_STATCARRY2_TEDF |
 832                 1 << S6_GMAC_STATCARRY2_TPKT |
 833                 1 << S6_GMAC_STATCARRY2_TBYT |
 834                 1 << S6_GMAC_STATCARRY2_TFRG |
 835                 1 << S6_GMAC_STATCARRY2_TUND |
 836                 1 << S6_GMAC_STATCARRY2_TOVR |
 837                 1 << S6_GMAC_STATCARRY2_TFCS |
 838                 1 << S6_GMAC_STATCARRY2_TJBR;
 839         writel(mask, pd->reg + S6_GMAC_STATCARRY(1));
 840         writel(~mask, pd->reg + S6_GMAC_STATCARRYMSK(1));
 841 }
 842
 843 static inline void s6gmac_init_dmac(struct net_device *dev)
 844 {
 845         struct s6gmac *pd = netdev_priv(dev);
 846         s6dmac_disable_chan(pd->tx_dma, pd->tx_chan);
 847         s6dmac_disable_chan(pd->rx_dma, pd->rx_chan);
 848         s6dmac_disable_error_irqs(pd->tx_dma, 1 << S6_HIFDMA_GMACTX);
 849         s6dmac_disable_error_irqs(pd->rx_dma, 1 << S6_HIFDMA_GMACRX);
 850 }
 851
 852 static int s6gmac_tx(struct sk_buff *skb, struct net_device *dev)
 853 {
 854         struct s6gmac *pd = netdev_priv(dev);
 855         unsigned long flags;
 856         spin_lock_irqsave(&pd->lock, flags);
 857         dev->trans_start = jiffies;
 858         writel(skb->len << S6_GMAC_BURST_PREWR_LEN |
 859                 0 << S6_GMAC_BURST_PREWR_CFE |
 860                 1 << S6_GMAC_BURST_PREWR_PPE |
 861                 1 << S6_GMAC_BURST_PREWR_FCS |
 862                 ((skb->len < ETH_ZLEN) ? 1 : 0) << S6_GMAC_BURST_PREWR_PAD,
 863                 pd->reg + S6_GMAC_BURST_PREWR);
 864         s6dmac_put_fifo_cache(pd->tx_dma, pd->tx_chan,
 865                 (u32)skb->data, pd->io, skb->len);
 866         if (s6dmac_fifo_full(pd->tx_dma, pd->tx_chan))
 867                 netif_stop_queue(dev);
 868         if (((u8)(pd->tx_skb_i - pd->tx_skb_o)) >= S6_NUM_TX_SKB) {
 869                 printk(KERN_ERR "GMAC BUG: skb tx ring overflow [%x, %x]\n",
 870                         pd->tx_skb_o, pd->tx_skb_i);
 871                 BUG();
 872         }
 873         pd->tx_skb[(pd->tx_skb_i++) % S6_NUM_TX_SKB] = skb;
 874         spin_unlock_irqrestore(&pd->lock, flags);
 875         return 0;
 876 }
 877
 878 static void s6gmac_tx_timeout(struct net_device *dev)
 879 {
 880         struct s6gmac *pd = netdev_priv(dev);
 881         unsigned long flags;
 882         spin_lock_irqsave(&pd->lock, flags);
 883         s6gmac_tx_interrupt(dev);
 884         spin_unlock_irqrestore(&pd->lock, flags);
 885 }
 886
 887 static int s6gmac_open(struct net_device *dev)
 888 {
 889         struct s6gmac *pd = netdev_priv(dev);
 890         unsigned long flags;
 891         phy_read_status(pd->phydev);
 892         spin_lock_irqsave(&pd->lock, flags);
 893         pd->link.mbit = 0;
 894         s6gmac_linkisup(dev, pd->phydev->link);
 895         s6gmac_init_device(dev);
 896         s6gmac_init_stats(dev);
 897         s6gmac_init_dmac(dev);
 898         s6gmac_rx_fillfifo(pd);
 899         s6dmac_enable_chan(pd->rx_dma, pd->rx_chan,
 900                 2, 1, 0, 1, 0, 0, 0, 7, -1, 2, 0, 1);
 901         s6dmac_enable_chan(pd->tx_dma, pd->tx_chan,
 902                 2, 0, 1, 0, 0, 0, 0, 7, -1, 2, 0, 1);
 903         writel(0 << S6_GMAC_HOST_INT_TXBURSTOVER |
 904                 0 << S6_GMAC_HOST_INT_TXPREWOVER |
 905                 0 << S6_GMAC_HOST_INT_RXBURSTUNDER |
 906                 0 << S6_GMAC_HOST_INT_RXPOSTRFULL |
 907                 0 << S6_GMAC_HOST_INT_RXPOSTRUNDER,
 908                 pd->reg + S6_GMAC_HOST_INTMASK);
 909         spin_unlock_irqrestore(&pd->lock, flags);
 910         phy_start(pd->phydev);
 911         netif_start_queue(dev);
 912         return 0;
 913 }
 914
 915 static int s6gmac_stop(struct net_device *dev)
 916 {
 917         struct s6gmac *pd = netdev_priv(dev);
 918         unsigned long flags;
 919         netif_stop_queue(dev);
 920         phy_stop(pd->phydev);
 921         spin_lock_irqsave(&pd->lock, flags);
 922         s6gmac_init_dmac(dev);
 923         s6gmac_stop_device(dev);
 924         while (pd->tx_skb_i != pd->tx_skb_o)
 925                 dev_kfree_skb(pd->tx_skb[(pd->tx_skb_o++) % S6_NUM_TX_SKB]);
 926         while (pd->rx_skb_i != pd->rx_skb_o)
 927                 dev_kfree_skb(pd->rx_skb[(pd->rx_skb_o++) % S6_NUM_RX_SKB]);
 928         spin_unlock_irqrestore(&pd->lock, flags);
 929         return 0;
 930 }
 931
 932 static struct net_device_stats *s6gmac_stats(struct net_device *dev)
 933 {
 934         struct s6gmac *pd = netdev_priv(dev);
 935         struct net_device_stats *st = (struct net_device_stats *)&pd->stats;
 936         int i;
 937         do {
 938                 unsigned long flags;
 939                 spin_lock_irqsave(&pd->lock, flags);
 940                 for (i = 0; i < sizeof(pd->stats) / sizeof(unsigned long); i++)
 941                         pd->stats[i] =
 942                                 pd->carry[i] << (S6_GMAC_STAT_SIZE_MIN - 1);
 943                 s6gmac_stats_collect(pd, &statinf[0][0]);
 944                 s6gmac_stats_collect(pd, &statinf[1][0]);
 945                 i = s6gmac_stats_pending(pd, 0) |
 946                         s6gmac_stats_pending(pd, 1);
 947                 spin_unlock_irqrestore(&pd->lock, flags);
 948         } while (i);
 949         st->rx_errors = st->rx_crc_errors +
 950                         st->rx_frame_errors +
 951                         st->rx_length_errors +
 952                         st->rx_missed_errors;
 953         st->tx_errors += st->tx_aborted_errors;
 954         return st;
 955 }
 956
 957 static int __devinit s6gmac_probe(struct platform_device *pdev)
 958 {
 959         struct net_device *dev;
 960         struct s6gmac *pd;
 961         int res;
 962         unsigned long i;
 963         struct mii_bus *mb;
 964         dev = alloc_etherdev(sizeof(*pd));
 965         if (!dev) {
 966                 printk(KERN_ERR DRV_PRMT "etherdev alloc failed, aborting.\n");
 967                 return -ENOMEM;
 968         }
 969         dev->open = s6gmac_open;
 970         dev->stop = s6gmac_stop;
 971         dev->hard_start_xmit = s6gmac_tx;
 972         dev->tx_timeout = s6gmac_tx_timeout;
 973         dev->watchdog_timeo = HZ;
 974         dev->get_stats = s6gmac_stats;
 975         dev->irq = platform_get_irq(pdev, 0);
 976         pd = netdev_priv(dev);
 977         memset(pd, 0, sizeof(*pd));
 978         spin_lock_init(&pd->lock);
 979         pd->reg = platform_get_resource(pdev, IORESOURCE_MEM, 0)->start;
 980         i = platform_get_resource(pdev, IORESOURCE_DMA, 0)->start;
 981         pd->tx_dma = DMA_MASK_DMAC(i);
 982         pd->tx_chan = DMA_INDEX_CHNL(i);
 983         i = platform_get_resource(pdev, IORESOURCE_DMA, 1)->start;
 984         pd->rx_dma = DMA_MASK_DMAC(i);
 985         pd->rx_chan = DMA_INDEX_CHNL(i);
 986         pd->io = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
 987         res = request_irq(dev->irq, &s6gmac_interrupt, 0, dev->name, dev);
 988         if (res) {
 989                 printk(KERN_ERR DRV_PRMT "irq request failed: %d\n", dev->irq);
 990                 goto errirq;
 991         }
 992         res = register_netdev(dev);
 993         if (res) {
 994                 printk(KERN_ERR DRV_PRMT "error registering device %s\n",
 995                         dev->name);
 996                 goto errdev;
 997         }
 998         mb = mdiobus_alloc();
 999         if (!mb) {
1000                 printk(KERN_ERR DRV_PRMT "error allocating mii bus\n");
1001                 goto errmii;
1002         }
1003         mb->name = "s6gmac_mii";
1004         mb->read = s6mii_read;
1005         mb->write = s6mii_write;
1006         mb->reset = s6mii_reset;
1007         mb->priv = pd;
1008         snprintf(mb->id, MII_BUS_ID_SIZE, "0");
1009         mb->phy_mask = ~(1 << 0);
1010         mb->irq = &pd->mii.irq[0];
1011         for (i = 0; i < PHY_MAX_ADDR; i++) {
1012                 int n = platform_get_irq(pdev, i + 1);
1013                 if (n < 0)
1014                         n = PHY_POLL;
1015                 pd->mii.irq[i] = n;
1016         }
1017         mdiobus_register(mb);
1018         pd->mii.bus = mb;
1019         res = s6gmac_phy_start(dev);
1020         if (res)
1021                 return res;
1022         platform_set_drvdata(pdev, dev);
1023         return 0;
1024 errmii:
1025         unregister_netdev(dev);
1026 errdev:
1027         free_irq(dev->irq, dev);
1028 errirq:
1029         free_netdev(dev);
1030         return res;
1031 }
1032
1033 static int __devexit s6gmac_remove(struct platform_device *pdev)
1034 {
1035         struct net_device *dev = platform_get_drvdata(pdev);
1036         if (dev) {
1037                 struct s6gmac *pd = netdev_priv(dev);
1038                 mdiobus_unregister(pd->mii.bus);
1039                 unregister_netdev(dev);
1040                 free_irq(dev->irq, dev);
1041                 free_netdev(dev);
1042                 platform_set_drvdata(pdev, NULL);
1043         }
1044         return 0;
1045 }
1046
1047 static struct platform_driver s6gmac_driver = {
1048         .probe = s6gmac_probe,
1049         .remove = __devexit_p(s6gmac_remove),
1050         .driver = {
1051                 .name = "s6gmac",
1052                 .owner = THIS_MODULE,
1053         },
1054 };
1055
1056 static int __init s6gmac_init(void)
1057 {
1058         printk(KERN_INFO DRV_PRMT "S6 GMAC ethernet driver\n");
1059         return platform_driver_register(&s6gmac_driver);
1060 }
1061
1062
1063 static void __exit s6gmac_exit(void)
1064 {
1065         platform_driver_unregister(&s6gmac_driver);
1066 }
1067
1068 module_init(s6gmac_init);
1069 module_exit(s6gmac_exit);
1070
1071 MODULE_LICENSE("GPL");
1072 MODULE_DESCRIPTION("S6105 on chip Ethernet driver");
1073 MODULE_AUTHOR("Oskar Schirmer <os@emlix.com>");