git.oblomov.eu Git - linux-2.6/blob - arch/sparc/kernel/irq_64.c

   1 /* irq.c: UltraSparc IRQ handling/init/registry.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   5  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/sched.h>
  10 #include <linux/linkage.h>
  11 #include <linux/ptrace.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/signal.h>
  15 #include <linux/mm.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/slab.h>
  18 #include <linux/random.h>
  19 #include <linux/init.h>
  20 #include <linux/delay.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/irq.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <asm/atomic.h>
  29 #include <asm/system.h>
  30 #include <asm/irq.h>
  31 #include <asm/io.h>
  32 #include <asm/iommu.h>
  33 #include <asm/upa.h>
  34 #include <asm/oplib.h>
  35 #include <asm/prom.h>
  36 #include <asm/timer.h>
  37 #include <asm/smp.h>
  38 #include <asm/starfire.h>
  39 #include <asm/uaccess.h>
  40 #include <asm/cache.h>
  41 #include <asm/cpudata.h>
  42 #include <asm/auxio.h>
  43 #include <asm/head.h>
  44 #include <asm/hypervisor.h>
  45 #include <asm/cacheflush.h>
  46
  47 #include "entry.h"
  48
  49 #define NUM_IVECS       (IMAP_INR + 1)
  50
  51 struct ino_bucket *ivector_table;
  52 unsigned long ivector_table_pa;
  53
  54 /* On several sun4u processors, it is illegal to mix bypass and
  55  * non-bypass accesses.  Therefore we access all INO buckets
  56  * using bypass accesses only.
  57  */
  58 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  59 {
  60         unsigned long ret;
  61
  62         __asm__ __volatile__("ldxa      [%1] %2, %0"
  63                              : "=&r" (ret)
  64                              : "r" (bucket_pa +
  65                                     offsetof(struct ino_bucket,
  66                                              __irq_chain_pa)),
  67                                "i" (ASI_PHYS_USE_EC));
  68
  69         return ret;
  70 }
  71
  72 static void bucket_clear_chain_pa(unsigned long bucket_pa)
  73 {
  74         __asm__ __volatile__("stxa      %%g0, [%0] %1"
  75                              : /* no outputs */
  76                              : "r" (bucket_pa +
  77                                     offsetof(struct ino_bucket,
  78                                              __irq_chain_pa)),
  79                                "i" (ASI_PHYS_USE_EC));
  80 }
  81
  82 static unsigned int bucket_get_virt_irq(unsigned long bucket_pa)
  83 {
  84         unsigned int ret;
  85
  86         __asm__ __volatile__("lduwa     [%1] %2, %0"
  87                              : "=&r" (ret)
  88                              : "r" (bucket_pa +
  89                                     offsetof(struct ino_bucket,
  90                                              __virt_irq)),
  91                                "i" (ASI_PHYS_USE_EC));
  92
  93         return ret;
  94 }
  95
  96 static void bucket_set_virt_irq(unsigned long bucket_pa,
  97                                 unsigned int virt_irq)
  98 {
  99         __asm__ __volatile__("stwa      %0, [%1] %2"
 100                              : /* no outputs */
 101                              : "r" (virt_irq),
 102                                "r" (bucket_pa +
 103                                     offsetof(struct ino_bucket,
 104                                              __virt_irq)),
 105                                "i" (ASI_PHYS_USE_EC));
 106 }
 107
 108 #define irq_work_pa(__cpu)      &(trap_block[(__cpu)].irq_worklist_pa)
 109
 110 static struct {
 111         unsigned int dev_handle;
 112         unsigned int dev_ino;
 113         unsigned int in_use;
 114 } virt_irq_table[NR_IRQS];
 115 static DEFINE_SPINLOCK(virt_irq_alloc_lock);
 116
 117 unsigned char virt_irq_alloc(unsigned int dev_handle,
 118                              unsigned int dev_ino)
 119 {
 120         unsigned long flags;
 121         unsigned char ent;
 122
 123         BUILD_BUG_ON(NR_IRQS >= 256);
 124
 125         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
 126
 127         for (ent = 1; ent < NR_IRQS; ent++) {
 128                 if (!virt_irq_table[ent].in_use)
 129                         break;
 130         }
 131         if (ent >= NR_IRQS) {
 132                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
 133                 ent = 0;
 134         } else {
 135                 virt_irq_table[ent].dev_handle = dev_handle;
 136                 virt_irq_table[ent].dev_ino = dev_ino;
 137                 virt_irq_table[ent].in_use = 1;
 138         }
 139
 140         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
 141
 142         return ent;
 143 }
 144
 145 #ifdef CONFIG_PCI_MSI
 146 void virt_irq_free(unsigned int virt_irq)
 147 {
 148         unsigned long flags;
 149
 150         if (virt_irq >= NR_IRQS)
 151                 return;
 152
 153         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
 154
 155         virt_irq_table[virt_irq].in_use = 0;
 156
 157         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
 158 }
 159 #endif
 160
 161 /*
 162  * /proc/interrupts printing:
 163  */
 164
 165 int show_interrupts(struct seq_file *p, void *v)
 166 {
 167         int i = *(loff_t *) v, j;
 168         struct irqaction * action;
 169         unsigned long flags;
 170
 171         if (i == 0) {
 172                 seq_printf(p, "           ");
 173                 for_each_online_cpu(j)
 174                         seq_printf(p, "CPU%d       ",j);
 175                 seq_putc(p, '\n');
 176         }
 177
 178         if (i < NR_IRQS) {
 179                 spin_lock_irqsave(&irq_desc[i].lock, flags);
 180                 action = irq_desc[i].action;
 181                 if (!action)
 182                         goto skip;
 183                 seq_printf(p, "%3d: ",i);
 184 #ifndef CONFIG_SMP
 185                 seq_printf(p, "%10u ", kstat_irqs(i));
 186 #else
 187                 for_each_online_cpu(j)
 188                         seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
 189 #endif
 190                 seq_printf(p, " %9s", irq_desc[i].chip->typename);
 191                 seq_printf(p, "  %s", action->name);
 192
 193                 for (action=action->next; action; action = action->next)
 194                         seq_printf(p, ", %s", action->name);
 195
 196                 seq_putc(p, '\n');
 197 skip:
 198                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 199         }
 200         return 0;
 201 }
 202
 203 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 204 {
 205         unsigned int tid;
 206
 207         if (this_is_starfire) {
 208                 tid = starfire_translate(imap, cpuid);
 209                 tid <<= IMAP_TID_SHIFT;
 210                 tid &= IMAP_TID_UPA;
 211         } else {
 212                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 213                         unsigned long ver;
 214
 215                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 216                         if ((ver >> 32UL) == __JALAPENO_ID ||
 217                             (ver >> 32UL) == __SERRANO_ID) {
 218                                 tid = cpuid << IMAP_TID_SHIFT;
 219                                 tid &= IMAP_TID_JBUS;
 220                         } else {
 221                                 unsigned int a = cpuid & 0x1f;
 222                                 unsigned int n = (cpuid >> 5) & 0x1f;
 223
 224                                 tid = ((a << IMAP_AID_SHIFT) |
 225                                        (n << IMAP_NID_SHIFT));
 226                                 tid &= (IMAP_AID_SAFARI |
 227                                         IMAP_NID_SAFARI);;
 228                         }
 229                 } else {
 230                         tid = cpuid << IMAP_TID_SHIFT;
 231                         tid &= IMAP_TID_UPA;
 232                 }
 233         }
 234
 235         return tid;
 236 }
 237
 238 struct irq_handler_data {
 239         unsigned long   iclr;
 240         unsigned long   imap;
 241
 242         void            (*pre_handler)(unsigned int, void *, void *);
 243         void            *arg1;
 244         void            *arg2;
 245 };
 246
 247 #ifdef CONFIG_SMP
 248 static int irq_choose_cpu(unsigned int virt_irq)
 249 {
 250         cpumask_t mask = irq_desc[virt_irq].affinity;
 251         int cpuid;
 252
 253         if (cpus_equal(mask, CPU_MASK_ALL)) {
 254                 static int irq_rover;
 255                 static DEFINE_SPINLOCK(irq_rover_lock);
 256                 unsigned long flags;
 257
 258                 /* Round-robin distribution... */
 259         do_round_robin:
 260                 spin_lock_irqsave(&irq_rover_lock, flags);
 261
 262                 while (!cpu_online(irq_rover)) {
 263                         if (++irq_rover >= NR_CPUS)
 264                                 irq_rover = 0;
 265                 }
 266                 cpuid = irq_rover;
 267                 do {
 268                         if (++irq_rover >= NR_CPUS)
 269                                 irq_rover = 0;
 270                 } while (!cpu_online(irq_rover));
 271
 272                 spin_unlock_irqrestore(&irq_rover_lock, flags);
 273         } else {
 274                 cpumask_t tmp;
 275
 276                 cpus_and(tmp, cpu_online_map, mask);
 277
 278                 if (cpus_empty(tmp))
 279                         goto do_round_robin;
 280
 281                 cpuid = first_cpu(tmp);
 282         }
 283
 284         return cpuid;
 285 }
 286 #else
 287 static int irq_choose_cpu(unsigned int virt_irq)
 288 {
 289         return real_hard_smp_processor_id();
 290 }
 291 #endif
 292
 293 static void sun4u_irq_enable(unsigned int virt_irq)
 294 {
 295         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 296
 297         if (likely(data)) {
 298                 unsigned long cpuid, imap, val;
 299                 unsigned int tid;
 300
 301                 cpuid = irq_choose_cpu(virt_irq);
 302                 imap = data->imap;
 303
 304                 tid = sun4u_compute_tid(imap, cpuid);
 305
 306                 val = upa_readq(imap);
 307                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 308                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 309                 val |= tid | IMAP_VALID;
 310                 upa_writeq(val, imap);
 311                 upa_writeq(ICLR_IDLE, data->iclr);
 312         }
 313 }
 314
 315 static void sun4u_set_affinity(unsigned int virt_irq,
 316                                const struct cpumask *mask)
 317 {
 318         sun4u_irq_enable(virt_irq);
 319 }
 320
 321 static void sun4u_irq_disable(unsigned int virt_irq)
 322 {
 323         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 324
 325         if (likely(data)) {
 326                 unsigned long imap = data->imap;
 327                 unsigned long tmp = upa_readq(imap);
 328
 329                 tmp &= ~IMAP_VALID;
 330                 upa_writeq(tmp, imap);
 331         }
 332 }
 333
 334 static void sun4u_irq_eoi(unsigned int virt_irq)
 335 {
 336         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 337         struct irq_desc *desc = irq_desc + virt_irq;
 338
 339         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 340                 return;
 341
 342         if (likely(data))
 343                 upa_writeq(ICLR_IDLE, data->iclr);
 344 }
 345
 346 static void sun4v_irq_enable(unsigned int virt_irq)
 347 {
 348         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 349         unsigned long cpuid = irq_choose_cpu(virt_irq);
 350         int err;
 351
 352         err = sun4v_intr_settarget(ino, cpuid);
 353         if (err != HV_EOK)
 354                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 355                        "err(%d)\n", ino, cpuid, err);
 356         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 357         if (err != HV_EOK)
 358                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 359                        "err(%d)\n", ino, err);
 360         err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 361         if (err != HV_EOK)
 362                 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
 363                        ino, err);
 364 }
 365
 366 static void sun4v_set_affinity(unsigned int virt_irq,
 367                                const struct cpumask *mask)
 368 {
 369         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 370         unsigned long cpuid = irq_choose_cpu(virt_irq);
 371         int err;
 372
 373         err = sun4v_intr_settarget(ino, cpuid);
 374         if (err != HV_EOK)
 375                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 376                        "err(%d)\n", ino, cpuid, err);
 377 }
 378
 379 static void sun4v_irq_disable(unsigned int virt_irq)
 380 {
 381         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 382         int err;
 383
 384         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 385         if (err != HV_EOK)
 386                 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
 387                        "err(%d)\n", ino, err);
 388 }
 389
 390 static void sun4v_irq_eoi(unsigned int virt_irq)
 391 {
 392         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 393         struct irq_desc *desc = irq_desc + virt_irq;
 394         int err;
 395
 396         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 397                 return;
 398
 399         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 400         if (err != HV_EOK)
 401                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 402                        "err(%d)\n", ino, err);
 403 }
 404
 405 static void sun4v_virq_enable(unsigned int virt_irq)
 406 {
 407         unsigned long cpuid, dev_handle, dev_ino;
 408         int err;
 409
 410         cpuid = irq_choose_cpu(virt_irq);
 411
 412         dev_handle = virt_irq_table[virt_irq].dev_handle;
 413         dev_ino = virt_irq_table[virt_irq].dev_ino;
 414
 415         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 416         if (err != HV_EOK)
 417                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 418                        "err(%d)\n",
 419                        dev_handle, dev_ino, cpuid, err);
 420         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 421                                     HV_INTR_STATE_IDLE);
 422         if (err != HV_EOK)
 423                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 424                        "HV_INTR_STATE_IDLE): err(%d)\n",
 425                        dev_handle, dev_ino, err);
 426         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 427                                     HV_INTR_ENABLED);
 428         if (err != HV_EOK)
 429                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 430                        "HV_INTR_ENABLED): err(%d)\n",
 431                        dev_handle, dev_ino, err);
 432 }
 433
 434 static void sun4v_virt_set_affinity(unsigned int virt_irq,
 435                                     const struct cpumask *mask)
 436 {
 437         unsigned long cpuid, dev_handle, dev_ino;
 438         int err;
 439
 440         cpuid = irq_choose_cpu(virt_irq);
 441
 442         dev_handle = virt_irq_table[virt_irq].dev_handle;
 443         dev_ino = virt_irq_table[virt_irq].dev_ino;
 444
 445         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 446         if (err != HV_EOK)
 447                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 448                        "err(%d)\n",
 449                        dev_handle, dev_ino, cpuid, err);
 450 }
 451
 452 static void sun4v_virq_disable(unsigned int virt_irq)
 453 {
 454         unsigned long dev_handle, dev_ino;
 455         int err;
 456
 457         dev_handle = virt_irq_table[virt_irq].dev_handle;
 458         dev_ino = virt_irq_table[virt_irq].dev_ino;
 459
 460         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 461                                     HV_INTR_DISABLED);
 462         if (err != HV_EOK)
 463                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 464                        "HV_INTR_DISABLED): err(%d)\n",
 465                        dev_handle, dev_ino, err);
 466 }
 467
 468 static void sun4v_virq_eoi(unsigned int virt_irq)
 469 {
 470         struct irq_desc *desc = irq_desc + virt_irq;
 471         unsigned long dev_handle, dev_ino;
 472         int err;
 473
 474         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 475                 return;
 476
 477         dev_handle = virt_irq_table[virt_irq].dev_handle;
 478         dev_ino = virt_irq_table[virt_irq].dev_ino;
 479
 480         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 481                                     HV_INTR_STATE_IDLE);
 482         if (err != HV_EOK)
 483                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 484                        "HV_INTR_STATE_IDLE): err(%d)\n",
 485                        dev_handle, dev_ino, err);
 486 }
 487
 488 static struct irq_chip sun4u_irq = {
 489         .typename       = "sun4u",
 490         .enable         = sun4u_irq_enable,
 491         .disable        = sun4u_irq_disable,
 492         .eoi            = sun4u_irq_eoi,
 493         .set_affinity   = sun4u_set_affinity,
 494 };
 495
 496 static struct irq_chip sun4v_irq = {
 497         .typename       = "sun4v",
 498         .enable         = sun4v_irq_enable,
 499         .disable        = sun4v_irq_disable,
 500         .eoi            = sun4v_irq_eoi,
 501         .set_affinity   = sun4v_set_affinity,
 502 };
 503
 504 static struct irq_chip sun4v_virq = {
 505         .typename       = "vsun4v",
 506         .enable         = sun4v_virq_enable,
 507         .disable        = sun4v_virq_disable,
 508         .eoi            = sun4v_virq_eoi,
 509         .set_affinity   = sun4v_virt_set_affinity,
 510 };
 511
 512 static void pre_flow_handler(unsigned int virt_irq,
 513                                       struct irq_desc *desc)
 514 {
 515         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 516         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 517
 518         data->pre_handler(ino, data->arg1, data->arg2);
 519
 520         handle_fasteoi_irq(virt_irq, desc);
 521 }
 522
 523 void irq_install_pre_handler(int virt_irq,
 524                              void (*func)(unsigned int, void *, void *),
 525                              void *arg1, void *arg2)
 526 {
 527         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 528         struct irq_desc *desc = irq_desc + virt_irq;
 529
 530         data->pre_handler = func;
 531         data->arg1 = arg1;
 532         data->arg2 = arg2;
 533
 534         desc->handle_irq = pre_flow_handler;
 535 }
 536
 537 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
 538 {
 539         struct ino_bucket *bucket;
 540         struct irq_handler_data *data;
 541         unsigned int virt_irq;
 542         int ino;
 543
 544         BUG_ON(tlb_type == hypervisor);
 545
 546         ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 547         bucket = &ivector_table[ino];
 548         virt_irq = bucket_get_virt_irq(__pa(bucket));
 549         if (!virt_irq) {
 550                 virt_irq = virt_irq_alloc(0, ino);
 551                 bucket_set_virt_irq(__pa(bucket), virt_irq);
 552                 set_irq_chip_and_handler_name(virt_irq,
 553                                               &sun4u_irq,
 554                                               handle_fasteoi_irq,
 555                                               "IVEC");
 556         }
 557
 558         data = get_irq_chip_data(virt_irq);
 559         if (unlikely(data))
 560                 goto out;
 561
 562         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 563         if (unlikely(!data)) {
 564                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 565                 prom_halt();
 566         }
 567         set_irq_chip_data(virt_irq, data);
 568
 569         data->imap  = imap;
 570         data->iclr  = iclr;
 571
 572 out:
 573         return virt_irq;
 574 }
 575
 576 static unsigned int sun4v_build_common(unsigned long sysino,
 577                                        struct irq_chip *chip)
 578 {
 579         struct ino_bucket *bucket;
 580         struct irq_handler_data *data;
 581         unsigned int virt_irq;
 582
 583         BUG_ON(tlb_type != hypervisor);
 584
 585         bucket = &ivector_table[sysino];
 586         virt_irq = bucket_get_virt_irq(__pa(bucket));
 587         if (!virt_irq) {
 588                 virt_irq = virt_irq_alloc(0, sysino);
 589                 bucket_set_virt_irq(__pa(bucket), virt_irq);
 590                 set_irq_chip_and_handler_name(virt_irq, chip,
 591                                               handle_fasteoi_irq,
 592                                               "IVEC");
 593         }
 594
 595         data = get_irq_chip_data(virt_irq);
 596         if (unlikely(data))
 597                 goto out;
 598
 599         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 600         if (unlikely(!data)) {
 601                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 602                 prom_halt();
 603         }
 604         set_irq_chip_data(virt_irq, data);
 605
 606         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 607          * is done by hypervisor calls on sun4v platforms, not by direct
 608          * register accesses.
 609          */
 610         data->imap = ~0UL;
 611         data->iclr = ~0UL;
 612
 613 out:
 614         return virt_irq;
 615 }
 616
 617 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
 618 {
 619         unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
 620
 621         return sun4v_build_common(sysino, &sun4v_irq);
 622 }
 623
 624 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
 625 {
 626         struct irq_handler_data *data;
 627         unsigned long hv_err, cookie;
 628         struct ino_bucket *bucket;
 629         struct irq_desc *desc;
 630         unsigned int virt_irq;
 631
 632         bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
 633         if (unlikely(!bucket))
 634                 return 0;
 635         __flush_dcache_range((unsigned long) bucket,
 636                              ((unsigned long) bucket +
 637                               sizeof(struct ino_bucket)));
 638
 639         virt_irq = virt_irq_alloc(devhandle, devino);
 640         bucket_set_virt_irq(__pa(bucket), virt_irq);
 641
 642         set_irq_chip_and_handler_name(virt_irq, &sun4v_virq,
 643                                       handle_fasteoi_irq,
 644                                       "IVEC");
 645
 646         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 647         if (unlikely(!data))
 648                 return 0;
 649
 650         /* In order to make the LDC channel startup sequence easier,
 651          * especially wrt. locking, we do not let request_irq() enable
 652          * the interrupt.
 653          */
 654         desc = irq_desc + virt_irq;
 655         desc->status |= IRQ_NOAUTOEN;
 656
 657         set_irq_chip_data(virt_irq, data);
 658
 659         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 660          * is done by hypervisor calls on sun4v platforms, not by direct
 661          * register accesses.
 662          */
 663         data->imap = ~0UL;
 664         data->iclr = ~0UL;
 665
 666         cookie = ~__pa(bucket);
 667         hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
 668         if (hv_err) {
 669                 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
 670                             "err=%lu\n", devhandle, devino, hv_err);
 671                 prom_halt();
 672         }
 673
 674         return virt_irq;
 675 }
 676
 677 void ack_bad_irq(unsigned int virt_irq)
 678 {
 679         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 680
 681         if (!ino)
 682                 ino = 0xdeadbeef;
 683
 684         printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
 685                ino, virt_irq);
 686 }
 687
 688 void *hardirq_stack[NR_CPUS];
 689 void *softirq_stack[NR_CPUS];
 690
 691 static __attribute__((always_inline)) void *set_hardirq_stack(void)
 692 {
 693         void *orig_sp, *sp = hardirq_stack[smp_processor_id()];
 694
 695         __asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp));
 696         if (orig_sp < sp ||
 697             orig_sp > (sp + THREAD_SIZE)) {
 698                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 699                 __asm__ __volatile__("mov %0, %%sp" : : "r" (sp));
 700         }
 701
 702         return orig_sp;
 703 }
 704 static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp)
 705 {
 706         __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp));
 707 }
 708
 709 void handler_irq(int irq, struct pt_regs *regs)
 710 {
 711         unsigned long pstate, bucket_pa;
 712         struct pt_regs *old_regs;
 713         void *orig_sp;
 714
 715         clear_softint(1 << irq);
 716
 717         old_regs = set_irq_regs(regs);
 718         irq_enter();
 719
 720         /* Grab an atomic snapshot of the pending IVECs.  */
 721         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
 722                              "wrpr      %0, %3, %%pstate\n\t"
 723                              "ldx       [%2], %1\n\t"
 724                              "stx       %%g0, [%2]\n\t"
 725                              "wrpr      %0, 0x0, %%pstate\n\t"
 726                              : "=&r" (pstate), "=&r" (bucket_pa)
 727                              : "r" (irq_work_pa(smp_processor_id())),
 728                                "i" (PSTATE_IE)
 729                              : "memory");
 730
 731         orig_sp = set_hardirq_stack();
 732
 733         while (bucket_pa) {
 734                 struct irq_desc *desc;
 735                 unsigned long next_pa;
 736                 unsigned int virt_irq;
 737
 738                 next_pa = bucket_get_chain_pa(bucket_pa);
 739                 virt_irq = bucket_get_virt_irq(bucket_pa);
 740                 bucket_clear_chain_pa(bucket_pa);
 741
 742                 desc = irq_desc + virt_irq;
 743
 744                 desc->handle_irq(virt_irq, desc);
 745
 746                 bucket_pa = next_pa;
 747         }
 748
 749         restore_hardirq_stack(orig_sp);
 750
 751         irq_exit();
 752         set_irq_regs(old_regs);
 753 }
 754
 755 void do_softirq(void)
 756 {
 757         unsigned long flags;
 758
 759         if (in_interrupt())
 760                 return;
 761
 762         local_irq_save(flags);
 763
 764         if (local_softirq_pending()) {
 765                 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
 766
 767                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 768
 769                 __asm__ __volatile__("mov %%sp, %0\n\t"
 770                                      "mov %1, %%sp"
 771                                      : "=&r" (orig_sp)
 772                                      : "r" (sp));
 773                 __do_softirq();
 774                 __asm__ __volatile__("mov %0, %%sp"
 775                                      : : "r" (orig_sp));
 776         }
 777
 778         local_irq_restore(flags);
 779 }
 780
 781 static void unhandled_perf_irq(struct pt_regs *regs)
 782 {
 783         unsigned long pcr, pic;
 784
 785         read_pcr(pcr);
 786         read_pic(pic);
 787
 788         write_pcr(0);
 789
 790         printk(KERN_EMERG "CPU %d: Got unexpected perf counter IRQ.\n",
 791                smp_processor_id());
 792         printk(KERN_EMERG "CPU %d: PCR[%016lx] PIC[%016lx]\n",
 793                smp_processor_id(), pcr, pic);
 794 }
 795
 796 /* Almost a direct copy of the powerpc PMC code.  */
 797 static DEFINE_SPINLOCK(perf_irq_lock);
 798 static void *perf_irq_owner_caller; /* mostly for debugging */
 799 static void (*perf_irq)(struct pt_regs *regs) = unhandled_perf_irq;
 800
 801 /* Invoked from level 15 PIL handler in trap table.  */
 802 void perfctr_irq(int irq, struct pt_regs *regs)
 803 {
 804         clear_softint(1 << irq);
 805         perf_irq(regs);
 806 }
 807
 808 int register_perfctr_intr(void (*handler)(struct pt_regs *))
 809 {
 810         int ret;
 811
 812         if (!handler)
 813                 return -EINVAL;
 814
 815         spin_lock(&perf_irq_lock);
 816         if (perf_irq != unhandled_perf_irq) {
 817                 printk(KERN_WARNING "register_perfctr_intr: "
 818                        "perf IRQ busy (reserved by caller %p)\n",
 819                        perf_irq_owner_caller);
 820                 ret = -EBUSY;
 821                 goto out;
 822         }
 823
 824         perf_irq_owner_caller = __builtin_return_address(0);
 825         perf_irq = handler;
 826
 827         ret = 0;
 828 out:
 829         spin_unlock(&perf_irq_lock);
 830
 831         return ret;
 832 }
 833 EXPORT_SYMBOL_GPL(register_perfctr_intr);
 834
 835 void release_perfctr_intr(void (*handler)(struct pt_regs *))
 836 {
 837         spin_lock(&perf_irq_lock);
 838         perf_irq_owner_caller = NULL;
 839         perf_irq = unhandled_perf_irq;
 840         spin_unlock(&perf_irq_lock);
 841 }
 842 EXPORT_SYMBOL_GPL(release_perfctr_intr);
 843
 844 #ifdef CONFIG_HOTPLUG_CPU
 845 void fixup_irqs(void)
 846 {
 847         unsigned int irq;
 848
 849         for (irq = 0; irq < NR_IRQS; irq++) {
 850                 unsigned long flags;
 851
 852                 spin_lock_irqsave(&irq_desc[irq].lock, flags);
 853                 if (irq_desc[irq].action &&
 854                     !(irq_desc[irq].status & IRQ_PER_CPU)) {
 855                         if (irq_desc[irq].chip->set_affinity)
 856                                 irq_desc[irq].chip->set_affinity(irq,
 857                                         &irq_desc[irq].affinity);
 858                 }
 859                 spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
 860         }
 861
 862         tick_ops->disable_irq();
 863 }
 864 #endif
 865
 866 struct sun5_timer {
 867         u64     count0;
 868         u64     limit0;
 869         u64     count1;
 870         u64     limit1;
 871 };
 872
 873 static struct sun5_timer *prom_timers;
 874 static u64 prom_limit0, prom_limit1;
 875
 876 static void map_prom_timers(void)
 877 {
 878         struct device_node *dp;
 879         const unsigned int *addr;
 880
 881         /* PROM timer node hangs out in the top level of device siblings... */
 882         dp = of_find_node_by_path("/");
 883         dp = dp->child;
 884         while (dp) {
 885                 if (!strcmp(dp->name, "counter-timer"))
 886                         break;
 887                 dp = dp->sibling;
 888         }
 889
 890         /* Assume if node is not present, PROM uses different tick mechanism
 891          * which we should not care about.
 892          */
 893         if (!dp) {
 894                 prom_timers = (struct sun5_timer *) 0;
 895                 return;
 896         }
 897
 898         /* If PROM is really using this, it must be mapped by him. */
 899         addr = of_get_property(dp, "address", NULL);
 900         if (!addr) {
 901                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 902                 prom_timers = (struct sun5_timer *) 0;
 903                 return;
 904         }
 905         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 906 }
 907
 908 static void kill_prom_timer(void)
 909 {
 910         if (!prom_timers)
 911                 return;
 912
 913         /* Save them away for later. */
 914         prom_limit0 = prom_timers->limit0;
 915         prom_limit1 = prom_timers->limit1;
 916
 917         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 918          * We turn both off here just to be paranoid.
 919          */
 920         prom_timers->limit0 = 0;
 921         prom_timers->limit1 = 0;
 922
 923         /* Wheee, eat the interrupt packet too... */
 924         __asm__ __volatile__(
 925 "       mov     0x40, %%g2\n"
 926 "       ldxa    [%%g0] %0, %%g1\n"
 927 "       ldxa    [%%g2] %1, %%g1\n"
 928 "       stxa    %%g0, [%%g0] %0\n"
 929 "       membar  #Sync\n"
 930         : /* no outputs */
 931         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 932         : "g1", "g2");
 933 }
 934
 935 void notrace init_irqwork_curcpu(void)
 936 {
 937         int cpu = hard_smp_processor_id();
 938
 939         trap_block[cpu].irq_worklist_pa = 0UL;
 940 }
 941
 942 /* Please be very careful with register_one_mondo() and
 943  * sun4v_register_mondo_queues().
 944  *
 945  * On SMP this gets invoked from the CPU trampoline before
 946  * the cpu has fully taken over the trap table from OBP,
 947  * and it's kernel stack + %g6 thread register state is
 948  * not fully cooked yet.
 949  *
 950  * Therefore you cannot make any OBP calls, not even prom_printf,
 951  * from these two routines.
 952  */
 953 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
 954 {
 955         unsigned long num_entries = (qmask + 1) / 64;
 956         unsigned long status;
 957
 958         status = sun4v_cpu_qconf(type, paddr, num_entries);
 959         if (status != HV_EOK) {
 960                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 961                             "err %lu\n", type, paddr, num_entries, status);
 962                 prom_halt();
 963         }
 964 }
 965
 966 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
 967 {
 968         struct trap_per_cpu *tb = &trap_block[this_cpu];
 969
 970         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
 971                            tb->cpu_mondo_qmask);
 972         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
 973                            tb->dev_mondo_qmask);
 974         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
 975                            tb->resum_qmask);
 976         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
 977                            tb->nonresum_qmask);
 978 }
 979
 980 static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask)
 981 {
 982         unsigned long size = PAGE_ALIGN(qmask + 1);
 983         void *p = __alloc_bootmem(size, size, 0);
 984         if (!p) {
 985                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 986                 prom_halt();
 987         }
 988
 989         *pa_ptr = __pa(p);
 990 }
 991
 992 static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask)
 993 {
 994         unsigned long size = PAGE_ALIGN(qmask + 1);
 995         void *p = __alloc_bootmem(size, size, 0);
 996
 997         if (!p) {
 998                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
 999                 prom_halt();
1000         }
1001
1002         *pa_ptr = __pa(p);
1003 }
1004
1005 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
1006 {
1007 #ifdef CONFIG_SMP
1008         void *page;
1009
1010         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
1011
1012         page = alloc_bootmem_pages(PAGE_SIZE);
1013         if (!page) {
1014                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1015                 prom_halt();
1016         }
1017
1018         tb->cpu_mondo_block_pa = __pa(page);
1019         tb->cpu_list_pa = __pa(page + 64);
1020 #endif
1021 }
1022
1023 /* Allocate mondo and error queues for all possible cpus.  */
1024 static void __init sun4v_init_mondo_queues(void)
1025 {
1026         int cpu;
1027
1028         for_each_possible_cpu(cpu) {
1029                 struct trap_per_cpu *tb = &trap_block[cpu];
1030
1031                 alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
1032                 alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
1033                 alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask);
1034                 alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask);
1035                 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
1036                 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa,
1037                                tb->nonresum_qmask);
1038         }
1039 }
1040
1041 static void __init init_send_mondo_info(void)
1042 {
1043         int cpu;
1044
1045         for_each_possible_cpu(cpu) {
1046                 struct trap_per_cpu *tb = &trap_block[cpu];
1047
1048                 init_cpu_send_mondo_info(tb);
1049         }
1050 }
1051
1052 static struct irqaction timer_irq_action = {
1053         .name = "timer",
1054 };
1055
1056 /* Only invoked on boot processor. */
1057 void __init init_IRQ(void)
1058 {
1059         unsigned long size;
1060
1061         map_prom_timers();
1062         kill_prom_timer();
1063
1064         size = sizeof(struct ino_bucket) * NUM_IVECS;
1065         ivector_table = alloc_bootmem(size);
1066         if (!ivector_table) {
1067                 prom_printf("Fatal error, cannot allocate ivector_table\n");
1068                 prom_halt();
1069         }
1070         __flush_dcache_range((unsigned long) ivector_table,
1071                              ((unsigned long) ivector_table) + size);
1072
1073         ivector_table_pa = __pa(ivector_table);
1074
1075         if (tlb_type == hypervisor)
1076                 sun4v_init_mondo_queues();
1077
1078         init_send_mondo_info();
1079
1080         if (tlb_type == hypervisor) {
1081                 /* Load up the boot cpu's entries.  */
1082                 sun4v_register_mondo_queues(hard_smp_processor_id());
1083         }
1084
1085         /* We need to clear any IRQ's pending in the soft interrupt
1086          * registers, a spurious one could be left around from the
1087          * PROM timer which we just disabled.
1088          */
1089         clear_softint(get_softint());
1090
1091         /* Now that ivector table is initialized, it is safe
1092          * to receive IRQ vector traps.  We will normally take
1093          * one or two right now, in case some device PROM used
1094          * to boot us wants to speak to us.  We just ignore them.
1095          */
1096         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1097                              "or        %%g1, %0, %%g1\n\t"
1098                              "wrpr      %%g1, 0x0, %%pstate"
1099                              : /* No outputs */
1100                              : "i" (PSTATE_IE)
1101                              : "g1");
1102
1103         irq_desc[0].action = &timer_irq_action;
1104 }