git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39
  40 #include <ib_verbs.h>
  41 #include <ib_cache.h>
  42 #include <ib_pack.h>
  43
  44 #include "mthca_dev.h"
  45 #include "mthca_cmd.h"
  46 #include "mthca_memfree.h"
  47
  48 enum {
  49         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  50         MTHCA_ACK_REQ_FREQ       = 10,
  51         MTHCA_FLIGHT_LIMIT       = 9,
  52         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  53         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  54         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  55 };
  56
  57 enum {
  58         MTHCA_QP_STATE_RST  = 0,
  59         MTHCA_QP_STATE_INIT = 1,
  60         MTHCA_QP_STATE_RTR  = 2,
  61         MTHCA_QP_STATE_RTS  = 3,
  62         MTHCA_QP_STATE_SQE  = 4,
  63         MTHCA_QP_STATE_SQD  = 5,
  64         MTHCA_QP_STATE_ERR  = 6,
  65         MTHCA_QP_STATE_DRAINING = 7
  66 };
  67
  68 enum {
  69         MTHCA_QP_ST_RC  = 0x0,
  70         MTHCA_QP_ST_UC  = 0x1,
  71         MTHCA_QP_ST_RD  = 0x2,
  72         MTHCA_QP_ST_UD  = 0x3,
  73         MTHCA_QP_ST_MLX = 0x7
  74 };
  75
  76 enum {
  77         MTHCA_QP_PM_MIGRATED = 0x3,
  78         MTHCA_QP_PM_ARMED    = 0x0,
  79         MTHCA_QP_PM_REARM    = 0x1
  80 };
  81
  82 enum {
  83         /* qp_context flags */
  84         MTHCA_QP_BIT_DE  = 1 <<  8,
  85         /* params1 */
  86         MTHCA_QP_BIT_SRE = 1 << 15,
  87         MTHCA_QP_BIT_SWE = 1 << 14,
  88         MTHCA_QP_BIT_SAE = 1 << 13,
  89         MTHCA_QP_BIT_SIC = 1 <<  4,
  90         MTHCA_QP_BIT_SSC = 1 <<  3,
  91         /* params2 */
  92         MTHCA_QP_BIT_RRE = 1 << 15,
  93         MTHCA_QP_BIT_RWE = 1 << 14,
  94         MTHCA_QP_BIT_RAE = 1 << 13,
  95         MTHCA_QP_BIT_RIC = 1 <<  4,
  96         MTHCA_QP_BIT_RSC = 1 <<  3
  97 };
  98
  99 struct mthca_qp_path {
 100         u32 port_pkey;
 101         u8  rnr_retry;
 102         u8  g_mylmc;
 103         u16 rlid;
 104         u8  ackto;
 105         u8  mgid_index;
 106         u8  static_rate;
 107         u8  hop_limit;
 108         u32 sl_tclass_flowlabel;
 109         u8  rgid[16];
 110 } __attribute__((packed));
 111
 112 struct mthca_qp_context {
 113         u32 flags;
 114         u32 tavor_sched_queue;  /* Reserved on Arbel */
 115         u8  mtu_msgmax;
 116         u8  rq_size_stride;     /* Reserved on Tavor */
 117         u8  sq_size_stride;     /* Reserved on Tavor */
 118         u8  rlkey_arbel_sched_queue;    /* Reserved on Tavor */
 119         u32 usr_page;
 120         u32 local_qpn;
 121         u32 remote_qpn;
 122         u32 reserved1[2];
 123         struct mthca_qp_path pri_path;
 124         struct mthca_qp_path alt_path;
 125         u32 rdd;
 126         u32 pd;
 127         u32 wqe_base;
 128         u32 wqe_lkey;
 129         u32 params1;
 130         u32 reserved2;
 131         u32 next_send_psn;
 132         u32 cqn_snd;
 133         u32 snd_wqe_base_l;     /* Next send WQE on Tavor */
 134         u32 snd_db_index;       /* (debugging only entries) */
 135         u32 last_acked_psn;
 136         u32 ssn;
 137         u32 params2;
 138         u32 rnr_nextrecvpsn;
 139         u32 ra_buff_indx;
 140         u32 cqn_rcv;
 141         u32 rcv_wqe_base_l;     /* Next recv WQE on Tavor */
 142         u32 rcv_db_index;       /* (debugging only entries) */
 143         u32 qkey;
 144         u32 srqn;
 145         u32 rmsn;
 146         u16 rq_wqe_counter;     /* reserved on Tavor */
 147         u16 sq_wqe_counter;     /* reserved on Tavor */
 148         u32 reserved3[18];
 149 } __attribute__((packed));
 150
 151 struct mthca_qp_param {
 152         u32 opt_param_mask;
 153         u32 reserved1;
 154         struct mthca_qp_context context;
 155         u32 reserved2[62];
 156 } __attribute__((packed));
 157
 158 enum {
 159         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 160         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 161         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 162         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 163         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 164         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 165         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 166         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 167         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 168         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 169         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 170         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 171         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 172         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 173         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 174         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 175         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 176 };
 177
 178 enum {
 179         MTHCA_NEXT_DBD       = 1 << 7,
 180         MTHCA_NEXT_FENCE     = 1 << 6,
 181         MTHCA_NEXT_CQ_UPDATE = 1 << 3,
 182         MTHCA_NEXT_EVENT_GEN = 1 << 2,
 183         MTHCA_NEXT_SOLICIT   = 1 << 1,
 184
 185         MTHCA_MLX_VL15       = 1 << 17,
 186         MTHCA_MLX_SLR        = 1 << 16
 187 };
 188
 189 enum {
 190         MTHCA_INVAL_LKEY = 0x100
 191 };
 192
 193 struct mthca_next_seg {
 194         u32 nda_op;             /* [31:6] next WQE [4:0] next opcode */
 195         u32 ee_nds;             /* [31:8] next EE  [7] DBD [6] F [5:0] next WQE size */
 196         u32 flags;              /* [3] CQ [2] Event [1] Solicit */
 197         u32 imm;                /* immediate data */
 198 };
 199
 200 struct mthca_tavor_ud_seg {
 201         u32 reserved1;
 202         u32 lkey;
 203         u64 av_addr;
 204         u32 reserved2[4];
 205         u32 dqpn;
 206         u32 qkey;
 207         u32 reserved3[2];
 208 };
 209
 210 struct mthca_arbel_ud_seg {
 211         u32 av[8];
 212         u32 dqpn;
 213         u32 qkey;
 214         u32 reserved[2];
 215 };
 216
 217 struct mthca_bind_seg {
 218         u32 flags;              /* [31] Atomic [30] rem write [29] rem read */
 219         u32 reserved;
 220         u32 new_rkey;
 221         u32 lkey;
 222         u64 addr;
 223         u64 length;
 224 };
 225
 226 struct mthca_raddr_seg {
 227         u64 raddr;
 228         u32 rkey;
 229         u32 reserved;
 230 };
 231
 232 struct mthca_atomic_seg {
 233         u64 swap_add;
 234         u64 compare;
 235 };
 236
 237 struct mthca_data_seg {
 238         u32 byte_count;
 239         u32 lkey;
 240         u64 addr;
 241 };
 242
 243 struct mthca_mlx_seg {
 244         u32 nda_op;
 245         u32 nds;
 246         u32 flags;              /* [17] VL15 [16] SLR [14:12] static rate
 247                                    [11:8] SL [3] C [2] E */
 248         u16 rlid;
 249         u16 vcrc;
 250 };
 251
 252 static const u8 mthca_opcode[] = {
 253         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 254         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 255         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 256         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 257         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 258         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 259         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 260 };
 261
 262 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 263 {
 264         return qp->qpn >= dev->qp_table.sqp_start &&
 265                 qp->qpn <= dev->qp_table.sqp_start + 3;
 266 }
 267
 268 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 269 {
 270         return qp->qpn >= dev->qp_table.sqp_start &&
 271                 qp->qpn <= dev->qp_table.sqp_start + 1;
 272 }
 273
 274 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 275 {
 276         if (qp->is_direct)
 277                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 278         else
 279                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 280                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 281 }
 282
 283 static void *get_send_wqe(struct mthca_qp *qp, int n)
 284 {
 285         if (qp->is_direct)
 286                 return qp->queue.direct.buf + qp->send_wqe_offset +
 287                         (n << qp->sq.wqe_shift);
 288         else
 289                 return qp->queue.page_list[(qp->send_wqe_offset +
 290                                             (n << qp->sq.wqe_shift)) >>
 291                                            PAGE_SHIFT].buf +
 292                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 293                          (PAGE_SIZE - 1));
 294 }
 295
 296 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 297                     enum ib_event_type event_type)
 298 {
 299         struct mthca_qp *qp;
 300         struct ib_event event;
 301
 302         spin_lock(&dev->qp_table.lock);
 303         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 304         if (qp)
 305                 atomic_inc(&qp->refcount);
 306         spin_unlock(&dev->qp_table.lock);
 307
 308         if (!qp) {
 309                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 310                 return;
 311         }
 312
 313         event.device      = &dev->ib_dev;
 314         event.event       = event_type;
 315         event.element.qp  = &qp->ibqp;
 316         if (qp->ibqp.event_handler)
 317                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 318
 319         if (atomic_dec_and_test(&qp->refcount))
 320                 wake_up(&qp->wait);
 321 }
 322
 323 static int to_mthca_state(enum ib_qp_state ib_state)
 324 {
 325         switch (ib_state) {
 326         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 327         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 328         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 329         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 330         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 331         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 332         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 333         default:                return -1;
 334         }
 335 }
 336
 337 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 338
 339 static int to_mthca_st(int transport)
 340 {
 341         switch (transport) {
 342         case RC:  return MTHCA_QP_ST_RC;
 343         case UC:  return MTHCA_QP_ST_UC;
 344         case UD:  return MTHCA_QP_ST_UD;
 345         case RD:  return MTHCA_QP_ST_RD;
 346         case MLX: return MTHCA_QP_ST_MLX;
 347         default:  return -1;
 348         }
 349 }
 350
 351 static const struct {
 352         int trans;
 353         u32 req_param[NUM_TRANS];
 354         u32 opt_param[NUM_TRANS];
 355 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 356         [IB_QPS_RESET] = {
 357                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 358                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 359                 [IB_QPS_INIT]  = {
 360                         .trans = MTHCA_TRANS_RST2INIT,
 361                         .req_param = {
 362                                 [UD]  = (IB_QP_PKEY_INDEX |
 363                                          IB_QP_PORT       |
 364                                          IB_QP_QKEY),
 365                                 [UC]  = (IB_QP_PKEY_INDEX |
 366                                          IB_QP_PORT       |
 367                                          IB_QP_ACCESS_FLAGS),
 368                                 [RC]  = (IB_QP_PKEY_INDEX |
 369                                          IB_QP_PORT       |
 370                                          IB_QP_ACCESS_FLAGS),
 371                                 [MLX] = (IB_QP_PKEY_INDEX |
 372                                          IB_QP_QKEY),
 373                         },
 374                         /* bug-for-bug compatibility with VAPI: */
 375                         .opt_param = {
 376                                 [MLX] = IB_QP_PORT
 377                         }
 378                 },
 379         },
 380         [IB_QPS_INIT]  = {
 381                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 382                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 383                 [IB_QPS_INIT]  = {
 384                         .trans = MTHCA_TRANS_INIT2INIT,
 385                         .opt_param = {
 386                                 [UD]  = (IB_QP_PKEY_INDEX |
 387                                          IB_QP_PORT       |
 388                                          IB_QP_QKEY),
 389                                 [UC]  = (IB_QP_PKEY_INDEX |
 390                                          IB_QP_PORT       |
 391                                          IB_QP_ACCESS_FLAGS),
 392                                 [RC]  = (IB_QP_PKEY_INDEX |
 393                                          IB_QP_PORT       |
 394                                          IB_QP_ACCESS_FLAGS),
 395                                 [MLX] = (IB_QP_PKEY_INDEX |
 396                                          IB_QP_QKEY),
 397                         }
 398                 },
 399                 [IB_QPS_RTR]   = {
 400                         .trans = MTHCA_TRANS_INIT2RTR,
 401                         .req_param = {
 402                                 [UC]  = (IB_QP_AV                  |
 403                                          IB_QP_PATH_MTU            |
 404                                          IB_QP_DEST_QPN            |
 405                                          IB_QP_RQ_PSN              |
 406                                          IB_QP_MAX_DEST_RD_ATOMIC),
 407                                 [RC]  = (IB_QP_AV                  |
 408                                          IB_QP_PATH_MTU            |
 409                                          IB_QP_DEST_QPN            |
 410                                          IB_QP_RQ_PSN              |
 411                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 412                                          IB_QP_MIN_RNR_TIMER),
 413                         },
 414                         .opt_param = {
 415                                 [UD]  = (IB_QP_PKEY_INDEX |
 416                                          IB_QP_QKEY),
 417                                 [UC]  = (IB_QP_ALT_PATH     |
 418                                          IB_QP_ACCESS_FLAGS |
 419                                          IB_QP_PKEY_INDEX),
 420                                 [RC]  = (IB_QP_ALT_PATH     |
 421                                          IB_QP_ACCESS_FLAGS |
 422                                          IB_QP_PKEY_INDEX),
 423                                 [MLX] = (IB_QP_PKEY_INDEX |
 424                                          IB_QP_QKEY),
 425                         }
 426                 }
 427         },
 428         [IB_QPS_RTR]   = {
 429                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 430                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 431                 [IB_QPS_RTS]   = {
 432                         .trans = MTHCA_TRANS_RTR2RTS,
 433                         .req_param = {
 434                                 [UD]  = IB_QP_SQ_PSN,
 435                                 [UC]  = (IB_QP_SQ_PSN            |
 436                                          IB_QP_MAX_QP_RD_ATOMIC),
 437                                 [RC]  = (IB_QP_TIMEOUT           |
 438                                          IB_QP_RETRY_CNT         |
 439                                          IB_QP_RNR_RETRY         |
 440                                          IB_QP_SQ_PSN            |
 441                                          IB_QP_MAX_QP_RD_ATOMIC),
 442                                 [MLX] = IB_QP_SQ_PSN,
 443                         },
 444                         .opt_param = {
 445                                 [UD]  = (IB_QP_CUR_STATE             |
 446                                          IB_QP_QKEY),
 447                                 [UC]  = (IB_QP_CUR_STATE             |
 448                                          IB_QP_ALT_PATH              |
 449                                          IB_QP_ACCESS_FLAGS          |
 450                                          IB_QP_PKEY_INDEX            |
 451                                          IB_QP_PATH_MIG_STATE),
 452                                 [RC]  = (IB_QP_CUR_STATE             |
 453                                          IB_QP_ALT_PATH              |
 454                                          IB_QP_ACCESS_FLAGS          |
 455                                          IB_QP_PKEY_INDEX            |
 456                                          IB_QP_MIN_RNR_TIMER         |
 457                                          IB_QP_PATH_MIG_STATE),
 458                                 [MLX] = (IB_QP_CUR_STATE             |
 459                                          IB_QP_QKEY),
 460                         }
 461                 }
 462         },
 463         [IB_QPS_RTS]   = {
 464                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 465                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 466                 [IB_QPS_RTS]   = {
 467                         .trans = MTHCA_TRANS_RTS2RTS,
 468                         .opt_param = {
 469                                 [UD]  = (IB_QP_CUR_STATE             |
 470                                          IB_QP_QKEY),
 471                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 472                                          IB_QP_ALT_PATH              |
 473                                          IB_QP_PATH_MIG_STATE),
 474                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 475                                          IB_QP_ALT_PATH              |
 476                                          IB_QP_PATH_MIG_STATE        |
 477                                          IB_QP_MIN_RNR_TIMER),
 478                                 [MLX] = (IB_QP_CUR_STATE             |
 479                                          IB_QP_QKEY),
 480                         }
 481                 },
 482                 [IB_QPS_SQD]   = {
 483                         .trans = MTHCA_TRANS_RTS2SQD,
 484                 },
 485         },
 486         [IB_QPS_SQD]   = {
 487                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 488                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 489                 [IB_QPS_RTS]   = {
 490                         .trans = MTHCA_TRANS_SQD2RTS,
 491                         .opt_param = {
 492                                 [UD]  = (IB_QP_CUR_STATE             |
 493                                          IB_QP_QKEY),
 494                                 [UC]  = (IB_QP_CUR_STATE             |
 495                                          IB_QP_ALT_PATH              |
 496                                          IB_QP_ACCESS_FLAGS          |
 497                                          IB_QP_PATH_MIG_STATE),
 498                                 [RC]  = (IB_QP_CUR_STATE             |
 499                                          IB_QP_ALT_PATH              |
 500                                          IB_QP_ACCESS_FLAGS          |
 501                                          IB_QP_MIN_RNR_TIMER         |
 502                                          IB_QP_PATH_MIG_STATE),
 503                                 [MLX] = (IB_QP_CUR_STATE             |
 504                                          IB_QP_QKEY),
 505                         }
 506                 },
 507                 [IB_QPS_SQD]   = {
 508                         .trans = MTHCA_TRANS_SQD2SQD,
 509                         .opt_param = {
 510                                 [UD]  = (IB_QP_PKEY_INDEX            |
 511                                          IB_QP_QKEY),
 512                                 [UC]  = (IB_QP_AV                    |
 513                                          IB_QP_MAX_QP_RD_ATOMIC      |
 514                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 515                                          IB_QP_CUR_STATE             |
 516                                          IB_QP_ALT_PATH              |
 517                                          IB_QP_ACCESS_FLAGS          |
 518                                          IB_QP_PKEY_INDEX            |
 519                                          IB_QP_PATH_MIG_STATE),
 520                                 [RC]  = (IB_QP_AV                    |
 521                                          IB_QP_TIMEOUT               |
 522                                          IB_QP_RETRY_CNT             |
 523                                          IB_QP_RNR_RETRY             |
 524                                          IB_QP_MAX_QP_RD_ATOMIC      |
 525                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 526                                          IB_QP_CUR_STATE             |
 527                                          IB_QP_ALT_PATH              |
 528                                          IB_QP_ACCESS_FLAGS          |
 529                                          IB_QP_PKEY_INDEX            |
 530                                          IB_QP_MIN_RNR_TIMER         |
 531                                          IB_QP_PATH_MIG_STATE),
 532                                 [MLX] = (IB_QP_PKEY_INDEX            |
 533                                          IB_QP_QKEY),
 534                         }
 535                 }
 536         },
 537         [IB_QPS_SQE]   = {
 538                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 539                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 540                 [IB_QPS_RTS]   = {
 541                         .trans = MTHCA_TRANS_SQERR2RTS,
 542                         .opt_param = {
 543                                 [UD]  = (IB_QP_CUR_STATE             |
 544                                          IB_QP_QKEY),
 545                                 [UC]  = (IB_QP_CUR_STATE),
 546                                 [RC]  = (IB_QP_CUR_STATE             |
 547                                          IB_QP_MIN_RNR_TIMER),
 548                                 [MLX] = (IB_QP_CUR_STATE             |
 549                                          IB_QP_QKEY),
 550                         }
 551                 }
 552         },
 553         [IB_QPS_ERR] = {
 554                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 555                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 556         }
 557 };
 558
 559 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 560                         int attr_mask)
 561 {
 562         if (attr_mask & IB_QP_PKEY_INDEX)
 563                 sqp->pkey_index = attr->pkey_index;
 564         if (attr_mask & IB_QP_QKEY)
 565                 sqp->qkey = attr->qkey;
 566         if (attr_mask & IB_QP_SQ_PSN)
 567                 sqp->send_psn = attr->sq_psn;
 568 }
 569
 570 static void init_port(struct mthca_dev *dev, int port)
 571 {
 572         int err;
 573         u8 status;
 574         struct mthca_init_ib_param param;
 575
 576         memset(&param, 0, sizeof param);
 577
 578         param.enable_1x = 1;
 579         param.enable_4x = 1;
 580         param.vl_cap    = dev->limits.vl_cap;
 581         param.mtu_cap   = dev->limits.mtu_cap;
 582         param.gid_cap   = dev->limits.gid_table_len;
 583         param.pkey_cap  = dev->limits.pkey_table_len;
 584
 585         err = mthca_INIT_IB(dev, &param, port, &status);
 586         if (err)
 587                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 588         if (status)
 589                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 590 }
 591
 592 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 593 {
 594         struct mthca_dev *dev = to_mdev(ibqp->device);
 595         struct mthca_qp *qp = to_mqp(ibqp);
 596         enum ib_qp_state cur_state, new_state;
 597         struct mthca_mailbox *mailbox;
 598         struct mthca_qp_param *qp_param;
 599         struct mthca_qp_context *qp_context;
 600         u32 req_param, opt_param;
 601         u8 status;
 602         int err;
 603
 604         if (attr_mask & IB_QP_CUR_STATE) {
 605                 if (attr->cur_qp_state != IB_QPS_RTR &&
 606                     attr->cur_qp_state != IB_QPS_RTS &&
 607                     attr->cur_qp_state != IB_QPS_SQD &&
 608                     attr->cur_qp_state != IB_QPS_SQE)
 609                         return -EINVAL;
 610                 else
 611                         cur_state = attr->cur_qp_state;
 612         } else {
 613                 spin_lock_irq(&qp->sq.lock);
 614                 spin_lock(&qp->rq.lock);
 615                 cur_state = qp->state;
 616                 spin_unlock(&qp->rq.lock);
 617                 spin_unlock_irq(&qp->sq.lock);
 618         }
 619
 620         if (attr_mask & IB_QP_STATE) {
 621                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 622                         return -EINVAL;
 623                 new_state = attr->qp_state;
 624         } else
 625                 new_state = cur_state;
 626
 627         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 628                 mthca_dbg(dev, "Illegal QP transition "
 629                           "%d->%d\n", cur_state, new_state);
 630                 return -EINVAL;
 631         }
 632
 633         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 634         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 635
 636         if ((req_param & attr_mask) != req_param) {
 637                 mthca_dbg(dev, "QP transition "
 638                           "%d->%d missing req attr 0x%08x\n",
 639                           cur_state, new_state,
 640                           req_param & ~attr_mask);
 641                 return -EINVAL;
 642         }
 643
 644         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 645                 mthca_dbg(dev, "QP transition (transport %d) "
 646                           "%d->%d has extra attr 0x%08x\n",
 647                           qp->transport,
 648                           cur_state, new_state,
 649                           attr_mask & ~(req_param | opt_param |
 650                                                  IB_QP_STATE));
 651                 return -EINVAL;
 652         }
 653
 654         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 655         if (IS_ERR(mailbox))
 656                 return PTR_ERR(mailbox);
 657         qp_param = mailbox->buf;
 658         qp_context = &qp_param->context;
 659         memset(qp_param, 0, sizeof *qp_param);
 660
 661         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 662                                              (to_mthca_st(qp->transport) << 16));
 663         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 664         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 665                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 666         else {
 667                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 668                 switch (attr->path_mig_state) {
 669                 case IB_MIG_MIGRATED:
 670                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 671                         break;
 672                 case IB_MIG_REARM:
 673                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 674                         break;
 675                 case IB_MIG_ARMED:
 676                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 677                         break;
 678                 }
 679         }
 680
 681         /* leave tavor_sched_queue as 0 */
 682
 683         if (qp->transport == MLX || qp->transport == UD)
 684                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 685         else if (attr_mask & IB_QP_PATH_MTU)
 686                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 687
 688         if (mthca_is_memfree(dev)) {
 689                 qp_context->rq_size_stride =
 690                         ((ffs(qp->rq.max) - 1) << 3) | (qp->rq.wqe_shift - 4);
 691                 qp_context->sq_size_stride =
 692                         ((ffs(qp->sq.max) - 1) << 3) | (qp->sq.wqe_shift - 4);
 693         }
 694
 695         /* leave arbel_sched_queue as 0 */
 696
 697         if (qp->ibqp.uobject)
 698                 qp_context->usr_page =
 699                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 700         else
 701                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 702         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 703         if (attr_mask & IB_QP_DEST_QPN) {
 704                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 705         }
 706
 707         if (qp->transport == MLX)
 708                 qp_context->pri_path.port_pkey |=
 709                         cpu_to_be32(to_msqp(qp)->port << 24);
 710         else {
 711                 if (attr_mask & IB_QP_PORT) {
 712                         qp_context->pri_path.port_pkey |=
 713                                 cpu_to_be32(attr->port_num << 24);
 714                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 715                 }
 716         }
 717
 718         if (attr_mask & IB_QP_PKEY_INDEX) {
 719                 qp_context->pri_path.port_pkey |=
 720                         cpu_to_be32(attr->pkey_index);
 721                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 722         }
 723
 724         if (attr_mask & IB_QP_RNR_RETRY) {
 725                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 726                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 727         }
 728
 729         if (attr_mask & IB_QP_AV) {
 730                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 731                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 732                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 733                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 734                         qp_context->pri_path.g_mylmc |= 1 << 7;
 735                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 736                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 737                         qp_context->pri_path.sl_tclass_flowlabel =
 738                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 739                                             (attr->ah_attr.grh.traffic_class << 20) |
 740                                             (attr->ah_attr.grh.flow_label));
 741                         memcpy(qp_context->pri_path.rgid,
 742                                attr->ah_attr.grh.dgid.raw, 16);
 743                 } else {
 744                         qp_context->pri_path.sl_tclass_flowlabel =
 745                                 cpu_to_be32(attr->ah_attr.sl << 28);
 746                 }
 747                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 748         }
 749
 750         if (attr_mask & IB_QP_TIMEOUT) {
 751                 qp_context->pri_path.ackto = attr->timeout;
 752                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 753         }
 754
 755         /* XXX alt_path */
 756
 757         /* leave rdd as 0 */
 758         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 759         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 760         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 761         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 762                                              (MTHCA_FLIGHT_LIMIT << 24) |
 763                                              MTHCA_QP_BIT_SRE           |
 764                                              MTHCA_QP_BIT_SWE           |
 765                                              MTHCA_QP_BIT_SAE);
 766         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 767                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 768         if (attr_mask & IB_QP_RETRY_CNT) {
 769                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 770                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 771         }
 772
 773         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 774                 qp_context->params1 |= cpu_to_be32(min(attr->max_rd_atomic ?
 775                                                        ffs(attr->max_rd_atomic) - 1 : 0,
 776                                                        7) << 21);
 777                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 778         }
 779
 780         if (attr_mask & IB_QP_SQ_PSN)
 781                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 782         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 783
 784         if (mthca_is_memfree(dev)) {
 785                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 786                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 787         }
 788
 789         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 790                 /*
 791                  * Only enable RDMA/atomics if we have responder
 792                  * resources set to a non-zero value.
 793                  */
 794                 if (qp->resp_depth) {
 795                         qp_context->params2 |=
 796                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 797                                             MTHCA_QP_BIT_RWE : 0);
 798                         qp_context->params2 |=
 799                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 800                                             MTHCA_QP_BIT_RRE : 0);
 801                         qp_context->params2 |=
 802                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 803                                             MTHCA_QP_BIT_RAE : 0);
 804                 }
 805
 806                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 807                                                         MTHCA_QP_OPTPAR_RRE |
 808                                                         MTHCA_QP_OPTPAR_RAE);
 809
 810                 qp->atomic_rd_en = attr->qp_access_flags;
 811         }
 812
 813         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 814                 u8 rra_max;
 815
 816                 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
 817                         /*
 818                          * Lowering our responder resources to zero.
 819                          * Turn off RDMA/atomics as responder.
 820                          * (RWE/RRE/RAE in params2 already zero)
 821                          */
 822                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 823                                                                 MTHCA_QP_OPTPAR_RRE |
 824                                                                 MTHCA_QP_OPTPAR_RAE);
 825                 }
 826
 827                 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
 828                         /*
 829                          * Increasing our responder resources from
 830                          * zero.  Turn on RDMA/atomics as appropriate.
 831                          */
 832                         qp_context->params2 |=
 833                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
 834                                             MTHCA_QP_BIT_RWE : 0);
 835                         qp_context->params2 |=
 836                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 837                                             MTHCA_QP_BIT_RRE : 0);
 838                         qp_context->params2 |=
 839                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 840                                             MTHCA_QP_BIT_RAE : 0);
 841
 842                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 843                                                                 MTHCA_QP_OPTPAR_RRE |
 844                                                                 MTHCA_QP_OPTPAR_RAE);
 845                 }
 846
 847                 for (rra_max = 0;
 848                      1 << rra_max < attr->max_dest_rd_atomic &&
 849                              rra_max < dev->qp_table.rdb_shift;
 850                      ++rra_max)
 851                         ; /* nothing */
 852
 853                 qp_context->params2      |= cpu_to_be32(rra_max << 21);
 854                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 855
 856                 qp->resp_depth = attr->max_dest_rd_atomic;
 857         }
 858
 859         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 860
 861         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 862                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 863                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 864         }
 865         if (attr_mask & IB_QP_RQ_PSN)
 866                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 867
 868         qp_context->ra_buff_indx =
 869                 cpu_to_be32(dev->qp_table.rdb_base +
 870                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 871                              dev->qp_table.rdb_shift));
 872
 873         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 874
 875         if (mthca_is_memfree(dev))
 876                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 877
 878         if (attr_mask & IB_QP_QKEY) {
 879                 qp_context->qkey = cpu_to_be32(attr->qkey);
 880                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 881         }
 882
 883         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 884                               qp->qpn, 0, mailbox, 0, &status);
 885         if (status) {
 886                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 887                            state_table[cur_state][new_state].trans, status);
 888                 err = -EINVAL;
 889         }
 890
 891         if (!err)
 892                 qp->state = new_state;
 893
 894         mthca_free_mailbox(dev, mailbox);
 895
 896         if (is_sqp(dev, qp))
 897                 store_attrs(to_msqp(qp), attr, attr_mask);
 898
 899         /*
 900          * If we are moving QP0 to RTR, bring the IB link up; if we
 901          * are moving QP0 to RESET or ERROR, bring the link back down.
 902          */
 903         if (is_qp0(dev, qp)) {
 904                 if (cur_state != IB_QPS_RTR &&
 905                     new_state == IB_QPS_RTR)
 906                         init_port(dev, to_msqp(qp)->port);
 907
 908                 if (cur_state != IB_QPS_RESET &&
 909                     cur_state != IB_QPS_ERR &&
 910                     (new_state == IB_QPS_RESET ||
 911                      new_state == IB_QPS_ERR))
 912                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 913         }
 914
 915         return err;
 916 }
 917
 918 /*
 919  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 920  * rq.max_gs and sq.max_gs must all be assigned.
 921  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 922  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 923  * queue)
 924  */
 925 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 926                                struct mthca_pd *pd,
 927                                struct mthca_qp *qp)
 928 {
 929         int size;
 930         int i;
 931         int npages, shift;
 932         dma_addr_t t;
 933         u64 *dma_list = NULL;
 934         int err = -ENOMEM;
 935
 936         size = sizeof (struct mthca_next_seg) +
 937                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 938
 939         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 940              qp->rq.wqe_shift++)
 941                 ; /* nothing */
 942
 943         size = sizeof (struct mthca_next_seg) +
 944                 qp->sq.max_gs * sizeof (struct mthca_data_seg);
 945         switch (qp->transport) {
 946         case MLX:
 947                 size += 2 * sizeof (struct mthca_data_seg);
 948                 break;
 949         case UD:
 950                 if (mthca_is_memfree(dev))
 951                         size += sizeof (struct mthca_arbel_ud_seg);
 952                 else
 953                         size += sizeof (struct mthca_tavor_ud_seg);
 954                 break;
 955         default:
 956                 /* bind seg is as big as atomic + raddr segs */
 957                 size += sizeof (struct mthca_bind_seg);
 958         }
 959
 960         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 961              qp->sq.wqe_shift++)
 962                 ; /* nothing */
 963
 964         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 965                                     1 << qp->sq.wqe_shift);
 966
 967         /*
 968          * If this is a userspace QP, we don't actually have to
 969          * allocate anything.  All we need is to calculate the WQE
 970          * sizes and the send_wqe_offset, so we're done now.
 971          */
 972         if (pd->ibpd.uobject)
 973                 return 0;
 974
 975         size = PAGE_ALIGN(qp->send_wqe_offset +
 976                           (qp->sq.max << qp->sq.wqe_shift));
 977
 978         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 979                            GFP_KERNEL);
 980         if (!qp->wrid)
 981                 goto err_out;
 982
 983         if (size <= MTHCA_MAX_DIRECT_QP_SIZE) {
 984                 qp->is_direct = 1;
 985                 npages = 1;
 986                 shift = get_order(size) + PAGE_SHIFT;
 987
 988                 if (0)
 989                         mthca_dbg(dev, "Creating direct QP of size %d (shift %d)\n",
 990                                   size, shift);
 991
 992                 qp->queue.direct.buf = dma_alloc_coherent(&dev->pdev->dev, size,
 993                                                           &t, GFP_KERNEL);
 994                 if (!qp->queue.direct.buf)
 995                         goto err_out;
 996
 997                 pci_unmap_addr_set(&qp->queue.direct, mapping, t);
 998
 999                 memset(qp->queue.direct.buf, 0, size);
1000
1001                 while (t & ((1 << shift) - 1)) {
1002                         --shift;
1003                         npages *= 2;
1004                 }
1005
1006                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
1007                 if (!dma_list)
1008                         goto err_out_free;
1009
1010                 for (i = 0; i < npages; ++i)
1011                         dma_list[i] = t + i * (1 << shift);
1012         } else {
1013                 qp->is_direct = 0;
1014                 npages = size / PAGE_SIZE;
1015                 shift = PAGE_SHIFT;
1016
1017                 if (0)
1018                         mthca_dbg(dev, "Creating indirect QP with %d pages\n", npages);
1019
1020                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
1021                 if (!dma_list)
1022                         goto err_out;
1023
1024                 qp->queue.page_list = kmalloc(npages *
1025                                               sizeof *qp->queue.page_list,
1026                                               GFP_KERNEL);
1027                 if (!qp->queue.page_list)
1028                         goto err_out;
1029
1030                 for (i = 0; i < npages; ++i) {
1031                         qp->queue.page_list[i].buf =
1032                                 dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE,
1033                                                    &t, GFP_KERNEL);
1034                         if (!qp->queue.page_list[i].buf)
1035                                 goto err_out_free;
1036
1037                         memset(qp->queue.page_list[i].buf, 0, PAGE_SIZE);
1038
1039                         pci_unmap_addr_set(&qp->queue.page_list[i], mapping, t);
1040                         dma_list[i] = t;
1041                 }
1042         }
1043
1044         err = mthca_mr_alloc_phys(dev, pd->pd_num, dma_list, shift,
1045                                   npages, 0, size,
1046                                   MTHCA_MPT_FLAG_LOCAL_READ,
1047                                   &qp->mr);
1048         if (err)
1049                 goto err_out_free;
1050
1051         kfree(dma_list);
1052         return 0;
1053
1054  err_out_free:
1055         if (qp->is_direct) {
1056                 dma_free_coherent(&dev->pdev->dev, size, qp->queue.direct.buf,
1057                                   pci_unmap_addr(&qp->queue.direct, mapping));
1058         } else
1059                 for (i = 0; i < npages; ++i) {
1060                         if (qp->queue.page_list[i].buf)
1061                                 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
1062                                                   qp->queue.page_list[i].buf,
1063                                                   pci_unmap_addr(&qp->queue.page_list[i],
1064                                                                  mapping));
1065
1066                 }
1067
1068  err_out:
1069         kfree(qp->wrid);
1070         kfree(dma_list);
1071         return err;
1072 }
1073
1074 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1075                                struct mthca_qp *qp)
1076 {
1077         int i;
1078         int size = PAGE_ALIGN(qp->send_wqe_offset +
1079                               (qp->sq.max << qp->sq.wqe_shift));
1080
1081         if (qp->is_direct) {
1082                 dma_free_coherent(&dev->pdev->dev, size, qp->queue.direct.buf,
1083                                   pci_unmap_addr(&qp->queue.direct, mapping));
1084         } else {
1085                 for (i = 0; i < size / PAGE_SIZE; ++i) {
1086                         dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
1087                                           qp->queue.page_list[i].buf,
1088                                           pci_unmap_addr(&qp->queue.page_list[i],
1089                                                          mapping));
1090                 }
1091         }
1092
1093         kfree(qp->wrid);
1094 }
1095
1096 static int mthca_map_memfree(struct mthca_dev *dev,
1097                              struct mthca_qp *qp)
1098 {
1099         int ret;
1100
1101         if (mthca_is_memfree(dev)) {
1102                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1103                 if (ret)
1104                         return ret;
1105
1106                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1107                 if (ret)
1108                         goto err_qpc;
1109
1110                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1111                                       qp->qpn << dev->qp_table.rdb_shift);
1112                 if (ret)
1113                         goto err_eqpc;
1114
1115         }
1116
1117         return 0;
1118
1119 err_eqpc:
1120         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1121
1122 err_qpc:
1123         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1124
1125         return ret;
1126 }
1127
1128 static void mthca_unmap_memfree(struct mthca_dev *dev,
1129                                 struct mthca_qp *qp)
1130 {
1131         mthca_table_put(dev, dev->qp_table.rdb_table,
1132                         qp->qpn << dev->qp_table.rdb_shift);
1133         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1134         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1135 }
1136
1137 static int mthca_alloc_memfree(struct mthca_dev *dev,
1138                                struct mthca_qp *qp)
1139 {
1140         int ret = 0;
1141
1142         if (mthca_is_memfree(dev)) {
1143                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1144                                                  qp->qpn, &qp->rq.db);
1145                 if (qp->rq.db_index < 0)
1146                         return ret;
1147
1148                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1149                                                  qp->qpn, &qp->sq.db);
1150                 if (qp->sq.db_index < 0)
1151                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1152         }
1153
1154         return ret;
1155 }
1156
1157 static void mthca_free_memfree(struct mthca_dev *dev,
1158                                struct mthca_qp *qp)
1159 {
1160         if (mthca_is_memfree(dev)) {
1161                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1162                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1163         }
1164 }
1165
1166 static void mthca_wq_init(struct mthca_wq* wq)
1167 {
1168         spin_lock_init(&wq->lock);
1169         wq->next_ind  = 0;
1170         wq->last_comp = wq->max - 1;
1171         wq->head      = 0;
1172         wq->tail      = 0;
1173         wq->last      = NULL;
1174 }
1175
1176 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1177                                  struct mthca_pd *pd,
1178                                  struct mthca_cq *send_cq,
1179                                  struct mthca_cq *recv_cq,
1180                                  enum ib_sig_type send_policy,
1181                                  struct mthca_qp *qp)
1182 {
1183         int ret;
1184         int i;
1185
1186         atomic_set(&qp->refcount, 1);
1187         qp->state        = IB_QPS_RESET;
1188         qp->atomic_rd_en = 0;
1189         qp->resp_depth   = 0;
1190         qp->sq_policy    = send_policy;
1191         mthca_wq_init(&qp->sq);
1192         mthca_wq_init(&qp->rq);
1193
1194         ret = mthca_map_memfree(dev, qp);
1195         if (ret)
1196                 return ret;
1197
1198         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1199         if (ret) {
1200                 mthca_unmap_memfree(dev, qp);
1201                 return ret;
1202         }
1203
1204         /*
1205          * If this is a userspace QP, we're done now.  The doorbells
1206          * will be allocated and buffers will be initialized in
1207          * userspace.
1208          */
1209         if (pd->ibpd.uobject)
1210                 return 0;
1211
1212         ret = mthca_alloc_memfree(dev, qp);
1213         if (ret) {
1214                 mthca_free_wqe_buf(dev, qp);
1215                 mthca_unmap_memfree(dev, qp);
1216                 return ret;
1217         }
1218
1219         if (mthca_is_memfree(dev)) {
1220                 struct mthca_next_seg *next;
1221                 struct mthca_data_seg *scatter;
1222                 int size = (sizeof (struct mthca_next_seg) +
1223                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1224
1225                 for (i = 0; i < qp->rq.max; ++i) {
1226                         next = get_recv_wqe(qp, i);
1227                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1228                                                    qp->rq.wqe_shift);
1229                         next->ee_nds = cpu_to_be32(size);
1230
1231                         for (scatter = (void *) (next + 1);
1232                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1233                              ++scatter)
1234                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1235                 }
1236
1237                 for (i = 0; i < qp->sq.max; ++i) {
1238                         next = get_send_wqe(qp, i);
1239                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1240                                                     qp->sq.wqe_shift) +
1241                                                    qp->send_wqe_offset);
1242                 }
1243         }
1244
1245         return 0;
1246 }
1247
1248 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1249                              struct mthca_qp *qp)
1250 {
1251         /* Sanity check QP size before proceeding */
1252         if (cap->max_send_wr  > 65536 || cap->max_recv_wr  > 65536 ||
1253             cap->max_send_sge > 64    || cap->max_recv_sge > 64)
1254                 return -EINVAL;
1255
1256         if (mthca_is_memfree(dev)) {
1257                 qp->rq.max = cap->max_recv_wr ?
1258                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1259                 qp->sq.max = cap->max_send_wr ?
1260                         roundup_pow_of_two(cap->max_send_wr) : 0;
1261         } else {
1262                 qp->rq.max = cap->max_recv_wr;
1263                 qp->sq.max = cap->max_send_wr;
1264         }
1265
1266         qp->rq.max_gs = cap->max_recv_sge;
1267         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1268                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1269                                     MTHCA_INLINE_CHUNK_SIZE) /
1270                               sizeof (struct mthca_data_seg));
1271
1272         /*
1273          * For MLX transport we need 2 extra S/G entries:
1274          * one for the header and one for the checksum at the end
1275          */
1276         if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1277             qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1278                 return -EINVAL;
1279
1280         return 0;
1281 }
1282
1283 int mthca_alloc_qp(struct mthca_dev *dev,
1284                    struct mthca_pd *pd,
1285                    struct mthca_cq *send_cq,
1286                    struct mthca_cq *recv_cq,
1287                    enum ib_qp_type type,
1288                    enum ib_sig_type send_policy,
1289                    struct ib_qp_cap *cap,
1290                    struct mthca_qp *qp)
1291 {
1292         int err;
1293
1294         err = mthca_set_qp_size(dev, cap, qp);
1295         if (err)
1296                 return err;
1297
1298         switch (type) {
1299         case IB_QPT_RC: qp->transport = RC; break;
1300         case IB_QPT_UC: qp->transport = UC; break;
1301         case IB_QPT_UD: qp->transport = UD; break;
1302         default: return -EINVAL;
1303         }
1304
1305         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1306         if (qp->qpn == -1)
1307                 return -ENOMEM;
1308
1309         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1310                                     send_policy, qp);
1311         if (err) {
1312                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1313                 return err;
1314         }
1315
1316         spin_lock_irq(&dev->qp_table.lock);
1317         mthca_array_set(&dev->qp_table.qp,
1318                         qp->qpn & (dev->limits.num_qps - 1), qp);
1319         spin_unlock_irq(&dev->qp_table.lock);
1320
1321         return 0;
1322 }
1323
1324 int mthca_alloc_sqp(struct mthca_dev *dev,
1325                     struct mthca_pd *pd,
1326                     struct mthca_cq *send_cq,
1327                     struct mthca_cq *recv_cq,
1328                     enum ib_sig_type send_policy,
1329                     struct ib_qp_cap *cap,
1330                     int qpn,
1331                     int port,
1332                     struct mthca_sqp *sqp)
1333 {
1334         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1335         int err;
1336
1337         err = mthca_set_qp_size(dev, cap, &sqp->qp);
1338         if (err)
1339                 return err;
1340
1341         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1342         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1343                                              &sqp->header_dma, GFP_KERNEL);
1344         if (!sqp->header_buf)
1345                 return -ENOMEM;
1346
1347         spin_lock_irq(&dev->qp_table.lock);
1348         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1349                 err = -EBUSY;
1350         else
1351                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1352         spin_unlock_irq(&dev->qp_table.lock);
1353
1354         if (err)
1355                 goto err_out;
1356
1357         sqp->port = port;
1358         sqp->qp.qpn       = mqpn;
1359         sqp->qp.transport = MLX;
1360
1361         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1362                                     send_policy, &sqp->qp);
1363         if (err)
1364                 goto err_out_free;
1365
1366         atomic_inc(&pd->sqp_count);
1367
1368         return 0;
1369
1370  err_out_free:
1371         /*
1372          * Lock CQs here, so that CQ polling code can do QP lookup
1373          * without taking a lock.
1374          */
1375         spin_lock_irq(&send_cq->lock);
1376         if (send_cq != recv_cq)
1377                 spin_lock(&recv_cq->lock);
1378
1379         spin_lock(&dev->qp_table.lock);
1380         mthca_array_clear(&dev->qp_table.qp, mqpn);
1381         spin_unlock(&dev->qp_table.lock);
1382
1383         if (send_cq != recv_cq)
1384                 spin_unlock(&recv_cq->lock);
1385         spin_unlock_irq(&send_cq->lock);
1386
1387  err_out:
1388         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1389                           sqp->header_buf, sqp->header_dma);
1390
1391         return err;
1392 }
1393
1394 void mthca_free_qp(struct mthca_dev *dev,
1395                    struct mthca_qp *qp)
1396 {
1397         u8 status;
1398         struct mthca_cq *send_cq;
1399         struct mthca_cq *recv_cq;
1400
1401         send_cq = to_mcq(qp->ibqp.send_cq);
1402         recv_cq = to_mcq(qp->ibqp.recv_cq);
1403
1404         /*
1405          * Lock CQs here, so that CQ polling code can do QP lookup
1406          * without taking a lock.
1407          */
1408         spin_lock_irq(&send_cq->lock);
1409         if (send_cq != recv_cq)
1410                 spin_lock(&recv_cq->lock);
1411
1412         spin_lock(&dev->qp_table.lock);
1413         mthca_array_clear(&dev->qp_table.qp,
1414                           qp->qpn & (dev->limits.num_qps - 1));
1415         spin_unlock(&dev->qp_table.lock);
1416
1417         if (send_cq != recv_cq)
1418                 spin_unlock(&recv_cq->lock);
1419         spin_unlock_irq(&send_cq->lock);
1420
1421         atomic_dec(&qp->refcount);
1422         wait_event(qp->wait, !atomic_read(&qp->refcount));
1423
1424         if (qp->state != IB_QPS_RESET)
1425                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1426
1427         /*
1428          * If this is a userspace QP, the buffers, MR, CQs and so on
1429          * will be cleaned up in userspace, so all we have to do is
1430          * unref the mem-free tables and free the QPN in our table.
1431          */
1432         if (!qp->ibqp.uobject) {
1433                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn);
1434                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1435                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn);
1436
1437                 mthca_free_mr(dev, &qp->mr);
1438                 mthca_free_memfree(dev, qp);
1439                 mthca_free_wqe_buf(dev, qp);
1440         }
1441
1442         mthca_unmap_memfree(dev, qp);
1443
1444         if (is_sqp(dev, qp)) {
1445                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1446                 dma_free_coherent(&dev->pdev->dev,
1447                                   to_msqp(qp)->header_buf_size,
1448                                   to_msqp(qp)->header_buf,
1449                                   to_msqp(qp)->header_dma);
1450         } else
1451                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1452 }
1453
1454 /* Create UD header for an MLX send and build a data segment for it */
1455 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1456                             int ind, struct ib_send_wr *wr,
1457                             struct mthca_mlx_seg *mlx,
1458                             struct mthca_data_seg *data)
1459 {
1460         int header_size;
1461         int err;
1462
1463         ib_ud_header_init(256, /* assume a MAD */
1464                           sqp->ud_header.grh_present,
1465                           &sqp->ud_header);
1466
1467         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1468         if (err)
1469                 return err;
1470         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1471         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1472                                   (sqp->ud_header.lrh.destination_lid == 0xffff ?
1473                                    MTHCA_MLX_SLR : 0) |
1474                                   (sqp->ud_header.lrh.service_level << 8));
1475         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1476         mlx->vcrc = 0;
1477
1478         switch (wr->opcode) {
1479         case IB_WR_SEND:
1480                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1481                 sqp->ud_header.immediate_present = 0;
1482                 break;
1483         case IB_WR_SEND_WITH_IMM:
1484                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1485                 sqp->ud_header.immediate_present = 1;
1486                 sqp->ud_header.immediate_data = wr->imm_data;
1487                 break;
1488         default:
1489                 return -EINVAL;
1490         }
1491
1492         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1493         if (sqp->ud_header.lrh.destination_lid == 0xffff)
1494                 sqp->ud_header.lrh.source_lid = 0xffff;
1495         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1496         if (!sqp->qp.ibqp.qp_num)
1497                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1498                                    sqp->pkey_index,
1499                                    &sqp->ud_header.bth.pkey);
1500         else
1501                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1502                                    wr->wr.ud.pkey_index,
1503                                    &sqp->ud_header.bth.pkey);
1504         cpu_to_be16s(&sqp->ud_header.bth.pkey);
1505         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1506         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1507         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1508                                                sqp->qkey : wr->wr.ud.remote_qkey);
1509         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1510
1511         header_size = ib_ud_header_pack(&sqp->ud_header,
1512                                         sqp->header_buf +
1513                                         ind * MTHCA_UD_HEADER_SIZE);
1514
1515         data->byte_count = cpu_to_be32(header_size);
1516         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1517         data->addr       = cpu_to_be64(sqp->header_dma +
1518                                        ind * MTHCA_UD_HEADER_SIZE);
1519
1520         return 0;
1521 }
1522
1523 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1524                                     struct ib_cq *ib_cq)
1525 {
1526         unsigned cur;
1527         struct mthca_cq *cq;
1528
1529         cur = wq->head - wq->tail;
1530         if (likely(cur + nreq < wq->max))
1531                 return 0;
1532
1533         cq = to_mcq(ib_cq);
1534         spin_lock(&cq->lock);
1535         cur = wq->head - wq->tail;
1536         spin_unlock(&cq->lock);
1537
1538         return cur + nreq >= wq->max;
1539 }
1540
1541 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1542                           struct ib_send_wr **bad_wr)
1543 {
1544         struct mthca_dev *dev = to_mdev(ibqp->device);
1545         struct mthca_qp *qp = to_mqp(ibqp);
1546         void *wqe;
1547         void *prev_wqe;
1548         unsigned long flags;
1549         int err = 0;
1550         int nreq;
1551         int i;
1552         int size;
1553         int size0 = 0;
1554         u32 f0 = 0;
1555         int ind;
1556         u8 op0 = 0;
1557
1558         spin_lock_irqsave(&qp->sq.lock, flags);
1559
1560         /* XXX check that state is OK to post send */
1561
1562         ind = qp->sq.next_ind;
1563
1564         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1565                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1566                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1567                                         " %d max, %d nreq)\n", qp->qpn,
1568                                         qp->sq.head, qp->sq.tail,
1569                                         qp->sq.max, nreq);
1570                         err = -ENOMEM;
1571                         *bad_wr = wr;
1572                         goto out;
1573                 }
1574
1575                 wqe = get_send_wqe(qp, ind);
1576                 prev_wqe = qp->sq.last;
1577                 qp->sq.last = wqe;
1578
1579                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1580                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1581                 ((struct mthca_next_seg *) wqe)->flags =
1582                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1583                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1584                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1585                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1586                         cpu_to_be32(1);
1587                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1588                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1589                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1590
1591                 wqe += sizeof (struct mthca_next_seg);
1592                 size = sizeof (struct mthca_next_seg) / 16;
1593
1594                 switch (qp->transport) {
1595                 case RC:
1596                         switch (wr->opcode) {
1597                         case IB_WR_ATOMIC_CMP_AND_SWP:
1598                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1599                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1600                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1601                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1602                                         cpu_to_be32(wr->wr.atomic.rkey);
1603                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1604
1605                                 wqe += sizeof (struct mthca_raddr_seg);
1606
1607                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1608                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1609                                                 cpu_to_be64(wr->wr.atomic.swap);
1610                                         ((struct mthca_atomic_seg *) wqe)->compare =
1611                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1612                                 } else {
1613                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1614                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1615                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1616                                 }
1617
1618                                 wqe += sizeof (struct mthca_atomic_seg);
1619                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1620                                         sizeof (struct mthca_atomic_seg);
1621                                 break;
1622
1623                         case IB_WR_RDMA_WRITE:
1624                         case IB_WR_RDMA_WRITE_WITH_IMM:
1625                         case IB_WR_RDMA_READ:
1626                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1627                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1628                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1629                                         cpu_to_be32(wr->wr.rdma.rkey);
1630                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1631                                 wqe += sizeof (struct mthca_raddr_seg);
1632                                 size += sizeof (struct mthca_raddr_seg) / 16;
1633                                 break;
1634
1635                         default:
1636                                 /* No extra segments required for sends */
1637                                 break;
1638                         }
1639
1640                         break;
1641
1642                 case UC:
1643                         switch (wr->opcode) {
1644                         case IB_WR_RDMA_WRITE:
1645                         case IB_WR_RDMA_WRITE_WITH_IMM:
1646                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1647                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1648                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1649                                         cpu_to_be32(wr->wr.rdma.rkey);
1650                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1651                                 wqe += sizeof (struct mthca_raddr_seg);
1652                                 size += sizeof (struct mthca_raddr_seg) / 16;
1653                                 break;
1654
1655                         default:
1656                                 /* No extra segments required for sends */
1657                                 break;
1658                         }
1659
1660                         break;
1661
1662                 case UD:
1663                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1664                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1665                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1666                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1667                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1668                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1669                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1670                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1671
1672                         wqe += sizeof (struct mthca_tavor_ud_seg);
1673                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1674                         break;
1675
1676                 case MLX:
1677                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1678                                                wqe - sizeof (struct mthca_next_seg),
1679                                                wqe);
1680                         if (err) {
1681                                 *bad_wr = wr;
1682                                 goto out;
1683                         }
1684                         wqe += sizeof (struct mthca_data_seg);
1685                         size += sizeof (struct mthca_data_seg) / 16;
1686                         break;
1687                 }
1688
1689                 if (wr->num_sge > qp->sq.max_gs) {
1690                         mthca_err(dev, "too many gathers\n");
1691                         err = -EINVAL;
1692                         *bad_wr = wr;
1693                         goto out;
1694                 }
1695
1696                 for (i = 0; i < wr->num_sge; ++i) {
1697                         ((struct mthca_data_seg *) wqe)->byte_count =
1698                                 cpu_to_be32(wr->sg_list[i].length);
1699                         ((struct mthca_data_seg *) wqe)->lkey =
1700                                 cpu_to_be32(wr->sg_list[i].lkey);
1701                         ((struct mthca_data_seg *) wqe)->addr =
1702                                 cpu_to_be64(wr->sg_list[i].addr);
1703                         wqe += sizeof (struct mthca_data_seg);
1704                         size += sizeof (struct mthca_data_seg) / 16;
1705                 }
1706
1707                 /* Add one more inline data segment for ICRC */
1708                 if (qp->transport == MLX) {
1709                         ((struct mthca_data_seg *) wqe)->byte_count =
1710                                 cpu_to_be32((1 << 31) | 4);
1711                         ((u32 *) wqe)[1] = 0;
1712                         wqe += sizeof (struct mthca_data_seg);
1713                         size += sizeof (struct mthca_data_seg) / 16;
1714                 }
1715
1716                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1717
1718                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1719                         mthca_err(dev, "opcode invalid\n");
1720                         err = -EINVAL;
1721                         *bad_wr = wr;
1722                         goto out;
1723                 }
1724
1725                 if (prev_wqe) {
1726                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1727                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1728                                              qp->send_wqe_offset) |
1729                                             mthca_opcode[wr->opcode]);
1730                         wmb();
1731                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1732                                 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1733                 }
1734
1735                 if (!size0) {
1736                         size0 = size;
1737                         op0   = mthca_opcode[wr->opcode];
1738                 }
1739
1740                 ++ind;
1741                 if (unlikely(ind >= qp->sq.max))
1742                         ind -= qp->sq.max;
1743         }
1744
1745 out:
1746         if (likely(nreq)) {
1747                 u32 doorbell[2];
1748
1749                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1750                                            qp->send_wqe_offset) | f0 | op0);
1751                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1752
1753                 wmb();
1754
1755                 mthca_write64(doorbell,
1756                               dev->kar + MTHCA_SEND_DOORBELL,
1757                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1758         }
1759
1760         qp->sq.next_ind = ind;
1761         qp->sq.head    += nreq;
1762
1763         spin_unlock_irqrestore(&qp->sq.lock, flags);
1764         return err;
1765 }
1766
1767 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1768                              struct ib_recv_wr **bad_wr)
1769 {
1770         struct mthca_dev *dev = to_mdev(ibqp->device);
1771         struct mthca_qp *qp = to_mqp(ibqp);
1772         unsigned long flags;
1773         int err = 0;
1774         int nreq;
1775         int i;
1776         int size;
1777         int size0 = 0;
1778         int ind;
1779         void *wqe;
1780         void *prev_wqe;
1781
1782         spin_lock_irqsave(&qp->rq.lock, flags);
1783
1784         /* XXX check that state is OK to post receive */
1785
1786         ind = qp->rq.next_ind;
1787
1788         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1789                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1790                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1791                                         " %d max, %d nreq)\n", qp->qpn,
1792                                         qp->rq.head, qp->rq.tail,
1793                                         qp->rq.max, nreq);
1794                         err = -ENOMEM;
1795                         *bad_wr = wr;
1796                         goto out;
1797                 }
1798
1799                 wqe = get_recv_wqe(qp, ind);
1800                 prev_wqe = qp->rq.last;
1801                 qp->rq.last = wqe;
1802
1803                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1804                 ((struct mthca_next_seg *) wqe)->ee_nds =
1805                         cpu_to_be32(MTHCA_NEXT_DBD);
1806                 ((struct mthca_next_seg *) wqe)->flags = 0;
1807
1808                 wqe += sizeof (struct mthca_next_seg);
1809                 size = sizeof (struct mthca_next_seg) / 16;
1810
1811                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1812                         err = -EINVAL;
1813                         *bad_wr = wr;
1814                         goto out;
1815                 }
1816
1817                 for (i = 0; i < wr->num_sge; ++i) {
1818                         ((struct mthca_data_seg *) wqe)->byte_count =
1819                                 cpu_to_be32(wr->sg_list[i].length);
1820                         ((struct mthca_data_seg *) wqe)->lkey =
1821                                 cpu_to_be32(wr->sg_list[i].lkey);
1822                         ((struct mthca_data_seg *) wqe)->addr =
1823                                 cpu_to_be64(wr->sg_list[i].addr);
1824                         wqe += sizeof (struct mthca_data_seg);
1825                         size += sizeof (struct mthca_data_seg) / 16;
1826                 }
1827
1828                 qp->wrid[ind] = wr->wr_id;
1829
1830                 if (likely(prev_wqe)) {
1831                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1832                                 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1833                         wmb();
1834                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1835                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1836                 }
1837
1838                 if (!size0)
1839                         size0 = size;
1840
1841                 ++ind;
1842                 if (unlikely(ind >= qp->rq.max))
1843                         ind -= qp->rq.max;
1844         }
1845
1846 out:
1847         if (likely(nreq)) {
1848                 u32 doorbell[2];
1849
1850                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1851                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1852
1853                 wmb();
1854
1855                 mthca_write64(doorbell,
1856                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1857                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1858         }
1859
1860         qp->rq.next_ind = ind;
1861         qp->rq.head    += nreq;
1862
1863         spin_unlock_irqrestore(&qp->rq.lock, flags);
1864         return err;
1865 }
1866
1867 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1868                           struct ib_send_wr **bad_wr)
1869 {
1870         struct mthca_dev *dev = to_mdev(ibqp->device);
1871         struct mthca_qp *qp = to_mqp(ibqp);
1872         void *wqe;
1873         void *prev_wqe;
1874         unsigned long flags;
1875         int err = 0;
1876         int nreq;
1877         int i;
1878         int size;
1879         int size0 = 0;
1880         u32 f0 = 0;
1881         int ind;
1882         u8 op0 = 0;
1883
1884         spin_lock_irqsave(&qp->sq.lock, flags);
1885
1886         /* XXX check that state is OK to post send */
1887
1888         ind = qp->sq.head & (qp->sq.max - 1);
1889
1890         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1891                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1892                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1893                                         " %d max, %d nreq)\n", qp->qpn,
1894                                         qp->sq.head, qp->sq.tail,
1895                                         qp->sq.max, nreq);
1896                         err = -ENOMEM;
1897                         *bad_wr = wr;
1898                         goto out;
1899                 }
1900
1901                 wqe = get_send_wqe(qp, ind);
1902                 prev_wqe = qp->sq.last;
1903                 qp->sq.last = wqe;
1904
1905                 ((struct mthca_next_seg *) wqe)->flags =
1906                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1907                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1908                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1909                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1910                         cpu_to_be32(1);
1911                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1912                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1913                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1914
1915                 wqe += sizeof (struct mthca_next_seg);
1916                 size = sizeof (struct mthca_next_seg) / 16;
1917
1918                 switch (qp->transport) {
1919                 case RC:
1920                         switch (wr->opcode) {
1921                         case IB_WR_ATOMIC_CMP_AND_SWP:
1922                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1923                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1924                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1925                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1926                                         cpu_to_be32(wr->wr.atomic.rkey);
1927                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1928
1929                                 wqe += sizeof (struct mthca_raddr_seg);
1930
1931                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1932                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1933                                                 cpu_to_be64(wr->wr.atomic.swap);
1934                                         ((struct mthca_atomic_seg *) wqe)->compare =
1935                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1936                                 } else {
1937                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1938                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1939                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1940                                 }
1941
1942                                 wqe += sizeof (struct mthca_atomic_seg);
1943                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1944                                         sizeof (struct mthca_atomic_seg);
1945                                 break;
1946
1947                         case IB_WR_RDMA_READ:
1948                         case IB_WR_RDMA_WRITE:
1949                         case IB_WR_RDMA_WRITE_WITH_IMM:
1950                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1951                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1952                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1953                                         cpu_to_be32(wr->wr.rdma.rkey);
1954                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1955                                 wqe += sizeof (struct mthca_raddr_seg);
1956                                 size += sizeof (struct mthca_raddr_seg) / 16;
1957                                 break;
1958
1959                         default:
1960                                 /* No extra segments required for sends */
1961                                 break;
1962                         }
1963
1964                         break;
1965
1966                 case UC:
1967                         switch (wr->opcode) {
1968                         case IB_WR_RDMA_WRITE:
1969                         case IB_WR_RDMA_WRITE_WITH_IMM:
1970                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1971                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1972                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1973                                         cpu_to_be32(wr->wr.rdma.rkey);
1974                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1975                                 wqe += sizeof (struct mthca_raddr_seg);
1976                                 size += sizeof (struct mthca_raddr_seg) / 16;
1977                                 break;
1978
1979                         default:
1980                                 /* No extra segments required for sends */
1981                                 break;
1982                         }
1983
1984                         break;
1985
1986                 case UD:
1987                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1988                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1989                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1990                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1991                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1992                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1993
1994                         wqe += sizeof (struct mthca_arbel_ud_seg);
1995                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1996                         break;
1997
1998                 case MLX:
1999                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
2000                                                wqe - sizeof (struct mthca_next_seg),
2001                                                wqe);
2002                         if (err) {
2003                                 *bad_wr = wr;
2004                                 goto out;
2005                         }
2006                         wqe += sizeof (struct mthca_data_seg);
2007                         size += sizeof (struct mthca_data_seg) / 16;
2008                         break;
2009                 }
2010
2011                 if (wr->num_sge > qp->sq.max_gs) {
2012                         mthca_err(dev, "too many gathers\n");
2013                         err = -EINVAL;
2014                         *bad_wr = wr;
2015                         goto out;
2016                 }
2017
2018                 for (i = 0; i < wr->num_sge; ++i) {
2019                         ((struct mthca_data_seg *) wqe)->byte_count =
2020                                 cpu_to_be32(wr->sg_list[i].length);
2021                         ((struct mthca_data_seg *) wqe)->lkey =
2022                                 cpu_to_be32(wr->sg_list[i].lkey);
2023                         ((struct mthca_data_seg *) wqe)->addr =
2024                                 cpu_to_be64(wr->sg_list[i].addr);
2025                         wqe += sizeof (struct mthca_data_seg);
2026                         size += sizeof (struct mthca_data_seg) / 16;
2027                 }
2028
2029                 /* Add one more inline data segment for ICRC */
2030                 if (qp->transport == MLX) {
2031                         ((struct mthca_data_seg *) wqe)->byte_count =
2032                                 cpu_to_be32((1 << 31) | 4);
2033                         ((u32 *) wqe)[1] = 0;
2034                         wqe += sizeof (struct mthca_data_seg);
2035                         size += sizeof (struct mthca_data_seg) / 16;
2036                 }
2037
2038                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2039
2040                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2041                         mthca_err(dev, "opcode invalid\n");
2042                         err = -EINVAL;
2043                         *bad_wr = wr;
2044                         goto out;
2045                 }
2046
2047                 if (likely(prev_wqe)) {
2048                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
2049                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2050                                              qp->send_wqe_offset) |
2051                                             mthca_opcode[wr->opcode]);
2052                         wmb();
2053                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2054                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
2055                 }
2056
2057                 if (!size0) {
2058                         size0 = size;
2059                         op0   = mthca_opcode[wr->opcode];
2060                 }
2061
2062                 ++ind;
2063                 if (unlikely(ind >= qp->sq.max))
2064                         ind -= qp->sq.max;
2065         }
2066
2067 out:
2068         if (likely(nreq)) {
2069                 u32 doorbell[2];
2070
2071                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2072                                           ((qp->sq.head & 0xffff) << 8) |
2073                                           f0 | op0);
2074                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2075
2076                 qp->sq.head += nreq;
2077
2078                 /*
2079                  * Make sure that descriptors are written before
2080                  * doorbell record.
2081                  */
2082                 wmb();
2083                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2084
2085                 /*
2086                  * Make sure doorbell record is written before we
2087                  * write MMIO send doorbell.
2088                  */
2089                 wmb();
2090                 mthca_write64(doorbell,
2091                               dev->kar + MTHCA_SEND_DOORBELL,
2092                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2093         }
2094
2095         spin_unlock_irqrestore(&qp->sq.lock, flags);
2096         return err;
2097 }
2098
2099 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2100                              struct ib_recv_wr **bad_wr)
2101 {
2102         struct mthca_dev *dev = to_mdev(ibqp->device);
2103         struct mthca_qp *qp = to_mqp(ibqp);
2104         unsigned long flags;
2105         int err = 0;
2106         int nreq;
2107         int ind;
2108         int i;
2109         void *wqe;
2110
2111         spin_lock_irqsave(&qp->rq.lock, flags);
2112
2113         /* XXX check that state is OK to post receive */
2114
2115         ind = qp->rq.head & (qp->rq.max - 1);
2116
2117         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2118                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2119                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2120                                         " %d max, %d nreq)\n", qp->qpn,
2121                                         qp->rq.head, qp->rq.tail,
2122                                         qp->rq.max, nreq);
2123                         err = -ENOMEM;
2124                         *bad_wr = wr;
2125                         goto out;
2126                 }
2127
2128                 wqe = get_recv_wqe(qp, ind);
2129
2130                 ((struct mthca_next_seg *) wqe)->flags = 0;
2131
2132                 wqe += sizeof (struct mthca_next_seg);
2133
2134                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2135                         err = -EINVAL;
2136                         *bad_wr = wr;
2137                         goto out;
2138                 }
2139
2140                 for (i = 0; i < wr->num_sge; ++i) {
2141                         ((struct mthca_data_seg *) wqe)->byte_count =
2142                                 cpu_to_be32(wr->sg_list[i].length);
2143                         ((struct mthca_data_seg *) wqe)->lkey =
2144                                 cpu_to_be32(wr->sg_list[i].lkey);
2145                         ((struct mthca_data_seg *) wqe)->addr =
2146                                 cpu_to_be64(wr->sg_list[i].addr);
2147                         wqe += sizeof (struct mthca_data_seg);
2148                 }
2149
2150                 if (i < qp->rq.max_gs) {
2151                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2152                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2153                         ((struct mthca_data_seg *) wqe)->addr = 0;
2154                 }
2155
2156                 qp->wrid[ind] = wr->wr_id;
2157
2158                 ++ind;
2159                 if (unlikely(ind >= qp->rq.max))
2160                         ind -= qp->rq.max;
2161         }
2162 out:
2163         if (likely(nreq)) {
2164                 qp->rq.head += nreq;
2165
2166                 /*
2167                  * Make sure that descriptors are written before
2168                  * doorbell record.
2169                  */
2170                 wmb();
2171                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2172         }
2173
2174         spin_unlock_irqrestore(&qp->rq.lock, flags);
2175         return err;
2176 }
2177
2178 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2179                        int index, int *dbd, u32 *new_wqe)
2180 {
2181         struct mthca_next_seg *next;
2182
2183         if (is_send)
2184                 next = get_send_wqe(qp, index);
2185         else
2186                 next = get_recv_wqe(qp, index);
2187
2188         if (mthca_is_memfree(dev))
2189                 *dbd = 1;
2190         else
2191                 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2192         if (next->ee_nds & cpu_to_be32(0x3f))
2193                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2194                         (next->ee_nds & cpu_to_be32(0x3f));
2195         else
2196                 *new_wqe = 0;
2197
2198         return 0;
2199 }
2200
2201 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2202 {
2203         int err;
2204         u8 status;
2205         int i;
2206
2207         spin_lock_init(&dev->qp_table.lock);
2208
2209         /*
2210          * We reserve 2 extra QPs per port for the special QPs.  The
2211          * special QP for port 1 has to be even, so round up.
2212          */
2213         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2214         err = mthca_alloc_init(&dev->qp_table.alloc,
2215                                dev->limits.num_qps,
2216                                (1 << 24) - 1,
2217                                dev->qp_table.sqp_start +
2218                                MTHCA_MAX_PORTS * 2);
2219         if (err)
2220                 return err;
2221
2222         err = mthca_array_init(&dev->qp_table.qp,
2223                                dev->limits.num_qps);
2224         if (err) {
2225                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2226                 return err;
2227         }
2228
2229         for (i = 0; i < 2; ++i) {
2230                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2231                                             dev->qp_table.sqp_start + i * 2,
2232                                             &status);
2233                 if (err)
2234                         goto err_out;
2235                 if (status) {
2236                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2237                                    "status %02x, aborting.\n",
2238                                    status);
2239                         err = -EINVAL;
2240                         goto err_out;
2241                 }
2242         }
2243         return 0;
2244
2245  err_out:
2246         for (i = 0; i < 2; ++i)
2247                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2248
2249         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2250         mthca_alloc_cleanup(&dev->qp_table.alloc);
2251
2252         return err;
2253 }
2254
2255 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2256 {
2257         int i;
2258         u8 status;
2259
2260         for (i = 0; i < 2; ++i)
2261                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2262
2263         mthca_alloc_cleanup(&dev->qp_table.alloc);
2264 }