git.oblomov.eu Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/io.h>
  46 #include <asm/byteorder.h>
  47 #include <asm/uaccess.h>
  48
  49 #ifdef CONFIG_SPARC64
  50 #include <asm/idprom.h>
  51 #include <asm/oplib.h>
  52 #include <asm/pbm.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #ifdef NETIF_F_TSO
  62 #define TG3_TSO_SUPPORT 1
  63 #else
  64 #define TG3_TSO_SUPPORT 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.45"
  72 #define DRV_MODULE_RELDATE      "Dec 13, 2005"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define TX_BUFFS_AVAIL(TP)                                              \
 127         ((TP)->tx_pending -                                             \
 128          (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
 129 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 130
 131 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 132 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 133
 134 /* minimum number of free TX descriptors required to wake up TX process */
 135 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 136
 137 /* number of ETHTOOL_GSTATS u64's */
 138 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 139
 140 #define TG3_NUM_TEST            6
 141
 142 static char version[] __devinitdata =
 143         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 144
 145 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 146 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 147 MODULE_LICENSE("GPL");
 148 MODULE_VERSION(DRV_MODULE_VERSION);
 149
 150 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 151 module_param(tg3_debug, int, 0);
 152 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 153
 154 static struct pci_device_id tg3_pci_tbl[] = {
 155         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 156           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 157         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 158           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 159         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 160           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 161         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 162           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 163         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 164           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 165         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 166           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 167         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 168           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 169         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 170           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 171         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 172           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 173         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 174           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 175         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 176           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 177         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 178           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 179         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 180           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 181         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 182           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 183         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 184           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 185         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 186           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 187         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 188           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 189         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 190           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 191         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 192           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 193         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 194           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 195         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 196           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 197         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 198           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 199         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 200           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 201         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 202           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 203         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 204           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 205         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 206           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 207         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 208           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 209         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 210           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 211         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 212           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 213         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 214           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 215         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 216           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 217         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 218           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 219         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 220           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 221         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 222           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 223         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
 224           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 225         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
 226           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 227         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
 228           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 229         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
 230           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 231         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 232           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 233         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 234           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 235         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 236           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 237         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 239         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 241         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 242           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 243         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 244           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 245         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 246           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 247         { 0, }
 248 };
 249
 250 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 251
 252 static struct {
 253         const char string[ETH_GSTRING_LEN];
 254 } ethtool_stats_keys[TG3_NUM_STATS] = {
 255         { "rx_octets" },
 256         { "rx_fragments" },
 257         { "rx_ucast_packets" },
 258         { "rx_mcast_packets" },
 259         { "rx_bcast_packets" },
 260         { "rx_fcs_errors" },
 261         { "rx_align_errors" },
 262         { "rx_xon_pause_rcvd" },
 263         { "rx_xoff_pause_rcvd" },
 264         { "rx_mac_ctrl_rcvd" },
 265         { "rx_xoff_entered" },
 266         { "rx_frame_too_long_errors" },
 267         { "rx_jabbers" },
 268         { "rx_undersize_packets" },
 269         { "rx_in_length_errors" },
 270         { "rx_out_length_errors" },
 271         { "rx_64_or_less_octet_packets" },
 272         { "rx_65_to_127_octet_packets" },
 273         { "rx_128_to_255_octet_packets" },
 274         { "rx_256_to_511_octet_packets" },
 275         { "rx_512_to_1023_octet_packets" },
 276         { "rx_1024_to_1522_octet_packets" },
 277         { "rx_1523_to_2047_octet_packets" },
 278         { "rx_2048_to_4095_octet_packets" },
 279         { "rx_4096_to_8191_octet_packets" },
 280         { "rx_8192_to_9022_octet_packets" },
 281
 282         { "tx_octets" },
 283         { "tx_collisions" },
 284
 285         { "tx_xon_sent" },
 286         { "tx_xoff_sent" },
 287         { "tx_flow_control" },
 288         { "tx_mac_errors" },
 289         { "tx_single_collisions" },
 290         { "tx_mult_collisions" },
 291         { "tx_deferred" },
 292         { "tx_excessive_collisions" },
 293         { "tx_late_collisions" },
 294         { "tx_collide_2times" },
 295         { "tx_collide_3times" },
 296         { "tx_collide_4times" },
 297         { "tx_collide_5times" },
 298         { "tx_collide_6times" },
 299         { "tx_collide_7times" },
 300         { "tx_collide_8times" },
 301         { "tx_collide_9times" },
 302         { "tx_collide_10times" },
 303         { "tx_collide_11times" },
 304         { "tx_collide_12times" },
 305         { "tx_collide_13times" },
 306         { "tx_collide_14times" },
 307         { "tx_collide_15times" },
 308         { "tx_ucast_packets" },
 309         { "tx_mcast_packets" },
 310         { "tx_bcast_packets" },
 311         { "tx_carrier_sense_errors" },
 312         { "tx_discards" },
 313         { "tx_errors" },
 314
 315         { "dma_writeq_full" },
 316         { "dma_write_prioq_full" },
 317         { "rxbds_empty" },
 318         { "rx_discards" },
 319         { "rx_errors" },
 320         { "rx_threshold_hit" },
 321
 322         { "dma_readq_full" },
 323         { "dma_read_prioq_full" },
 324         { "tx_comp_queue_full" },
 325
 326         { "ring_set_send_prod_index" },
 327         { "ring_status_update" },
 328         { "nic_irqs" },
 329         { "nic_avoided_irqs" },
 330         { "nic_tx_threshold_hit" }
 331 };
 332
 333 static struct {
 334         const char string[ETH_GSTRING_LEN];
 335 } ethtool_test_keys[TG3_NUM_TEST] = {
 336         { "nvram test     (online) " },
 337         { "link test      (online) " },
 338         { "register test  (offline)" },
 339         { "memory test    (offline)" },
 340         { "loopback test  (offline)" },
 341         { "interrupt test (offline)" },
 342 };
 343
 344 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 345 {
 346         unsigned long flags;
 347
 348         spin_lock_irqsave(&tp->indirect_lock, flags);
 349         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 350         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 351         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 352 }
 353
 354 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 355 {
 356         writel(val, tp->regs + off);
 357         readl(tp->regs + off);
 358 }
 359
 360 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 361 {
 362         unsigned long flags;
 363         u32 val;
 364
 365         spin_lock_irqsave(&tp->indirect_lock, flags);
 366         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 367         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 368         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 369         return val;
 370 }
 371
 372 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         unsigned long flags;
 375
 376         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 377                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 378                                        TG3_64BIT_REG_LOW, val);
 379                 return;
 380         }
 381         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 382                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 383                                        TG3_64BIT_REG_LOW, val);
 384                 return;
 385         }
 386
 387         spin_lock_irqsave(&tp->indirect_lock, flags);
 388         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 389         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 390         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 391
 392         /* In indirect mode when disabling interrupts, we also need
 393          * to clear the interrupt bit in the GRC local ctrl register.
 394          */
 395         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 396             (val == 0x1)) {
 397                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 398                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 399         }
 400 }
 401
 402 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 403 {
 404         unsigned long flags;
 405         u32 val;
 406
 407         spin_lock_irqsave(&tp->indirect_lock, flags);
 408         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 409         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 410         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 411         return val;
 412 }
 413
 414 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
 415 {
 416         tp->write32(tp, off, val);
 417         if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) &&
 418             !(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) &&
 419             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 420                 tp->read32(tp, off);    /* flush */
 421 }
 422
 423 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 424 {
 425         tp->write32_mbox(tp, off, val);
 426         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 427             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 428                 tp->read32_mbox(tp, off);
 429 }
 430
 431 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 432 {
 433         void __iomem *mbox = tp->regs + off;
 434         writel(val, mbox);
 435         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 436                 writel(val, mbox);
 437         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 438                 readl(mbox);
 439 }
 440
 441 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 442 {
 443         writel(val, tp->regs + off);
 444 }
 445
 446 static u32 tg3_read32(struct tg3 *tp, u32 off)
 447 {
 448         return (readl(tp->regs + off));
 449 }
 450
 451 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 452 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 453 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 454 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 455 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 456
 457 #define tw32(reg,val)           tp->write32(tp, reg, val)
 458 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val))
 459 #define tr32(reg)               tp->read32(tp, reg)
 460
 461 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 462 {
 463         unsigned long flags;
 464
 465         spin_lock_irqsave(&tp->indirect_lock, flags);
 466         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 467         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 468
 469         /* Always leave this as zero. */
 470         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 472 }
 473
 474 static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
 475 {
 476         /* If no workaround is needed, write to mem space directly */
 477         if (tp->write32 != tg3_write_indirect_reg32)
 478                 tw32(NIC_SRAM_WIN_BASE + off, val);
 479         else
 480                 tg3_write_mem(tp, off, val);
 481 }
 482
 483 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 484 {
 485         unsigned long flags;
 486
 487         spin_lock_irqsave(&tp->indirect_lock, flags);
 488         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 489         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 490
 491         /* Always leave this as zero. */
 492         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 493         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 494 }
 495
 496 static void tg3_disable_ints(struct tg3 *tp)
 497 {
 498         tw32(TG3PCI_MISC_HOST_CTRL,
 499              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 500         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 501 }
 502
 503 static inline void tg3_cond_int(struct tg3 *tp)
 504 {
 505         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 506             (tp->hw_status->status & SD_STATUS_UPDATED))
 507                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 508 }
 509
 510 static void tg3_enable_ints(struct tg3 *tp)
 511 {
 512         tp->irq_sync = 0;
 513         wmb();
 514
 515         tw32(TG3PCI_MISC_HOST_CTRL,
 516              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 517         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 518                        (tp->last_tag << 24));
 519         tg3_cond_int(tp);
 520 }
 521
 522 static inline unsigned int tg3_has_work(struct tg3 *tp)
 523 {
 524         struct tg3_hw_status *sblk = tp->hw_status;
 525         unsigned int work_exists = 0;
 526
 527         /* check for phy events */
 528         if (!(tp->tg3_flags &
 529               (TG3_FLAG_USE_LINKCHG_REG |
 530                TG3_FLAG_POLL_SERDES))) {
 531                 if (sblk->status & SD_STATUS_LINK_CHG)
 532                         work_exists = 1;
 533         }
 534         /* check for RX/TX work to do */
 535         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 536             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 537                 work_exists = 1;
 538
 539         return work_exists;
 540 }
 541
 542 /* tg3_restart_ints
 543  *  similar to tg3_enable_ints, but it accurately determines whether there
 544  *  is new work pending and can return without flushing the PIO write
 545  *  which reenables interrupts
 546  */
 547 static void tg3_restart_ints(struct tg3 *tp)
 548 {
 549         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 550                      tp->last_tag << 24);
 551         mmiowb();
 552
 553         /* When doing tagged status, this work check is unnecessary.
 554          * The last_tag we write above tells the chip which piece of
 555          * work we've completed.
 556          */
 557         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 558             tg3_has_work(tp))
 559                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 560                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 561 }
 562
 563 static inline void tg3_netif_stop(struct tg3 *tp)
 564 {
 565         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 566         netif_poll_disable(tp->dev);
 567         netif_tx_disable(tp->dev);
 568 }
 569
 570 static inline void tg3_netif_start(struct tg3 *tp)
 571 {
 572         netif_wake_queue(tp->dev);
 573         /* NOTE: unconditional netif_wake_queue is only appropriate
 574          * so long as all callers are assured to have free tx slots
 575          * (such as after tg3_init_hw)
 576          */
 577         netif_poll_enable(tp->dev);
 578         tp->hw_status->status |= SD_STATUS_UPDATED;
 579         tg3_enable_ints(tp);
 580 }
 581
 582 static void tg3_switch_clocks(struct tg3 *tp)
 583 {
 584         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 585         u32 orig_clock_ctrl;
 586
 587         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 588                 return;
 589
 590         orig_clock_ctrl = clock_ctrl;
 591         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 592                        CLOCK_CTRL_CLKRUN_OENABLE |
 593                        0x1f);
 594         tp->pci_clock_ctrl = clock_ctrl;
 595
 596         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 597                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 598                         tw32_f(TG3PCI_CLOCK_CTRL,
 599                                clock_ctrl | CLOCK_CTRL_625_CORE);
 600                         udelay(40);
 601                 }
 602         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 603                 tw32_f(TG3PCI_CLOCK_CTRL,
 604                      clock_ctrl |
 605                      (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
 606                 udelay(40);
 607                 tw32_f(TG3PCI_CLOCK_CTRL,
 608                      clock_ctrl | (CLOCK_CTRL_ALTCLK));
 609                 udelay(40);
 610         }
 611         tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
 612         udelay(40);
 613 }
 614
 615 #define PHY_BUSY_LOOPS  5000
 616
 617 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 618 {
 619         u32 frame_val;
 620         unsigned int loops;
 621         int ret;
 622
 623         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 624                 tw32_f(MAC_MI_MODE,
 625                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 626                 udelay(80);
 627         }
 628
 629         *val = 0x0;
 630
 631         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 632                       MI_COM_PHY_ADDR_MASK);
 633         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 634                       MI_COM_REG_ADDR_MASK);
 635         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 636
 637         tw32_f(MAC_MI_COM, frame_val);
 638
 639         loops = PHY_BUSY_LOOPS;
 640         while (loops != 0) {
 641                 udelay(10);
 642                 frame_val = tr32(MAC_MI_COM);
 643
 644                 if ((frame_val & MI_COM_BUSY) == 0) {
 645                         udelay(5);
 646                         frame_val = tr32(MAC_MI_COM);
 647                         break;
 648                 }
 649                 loops -= 1;
 650         }
 651
 652         ret = -EBUSY;
 653         if (loops != 0) {
 654                 *val = frame_val & MI_COM_DATA_MASK;
 655                 ret = 0;
 656         }
 657
 658         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 659                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 660                 udelay(80);
 661         }
 662
 663         return ret;
 664 }
 665
 666 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 667 {
 668         u32 frame_val;
 669         unsigned int loops;
 670         int ret;
 671
 672         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 673                 tw32_f(MAC_MI_MODE,
 674                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 675                 udelay(80);
 676         }
 677
 678         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 679                       MI_COM_PHY_ADDR_MASK);
 680         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 681                       MI_COM_REG_ADDR_MASK);
 682         frame_val |= (val & MI_COM_DATA_MASK);
 683         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 684
 685         tw32_f(MAC_MI_COM, frame_val);
 686
 687         loops = PHY_BUSY_LOOPS;
 688         while (loops != 0) {
 689                 udelay(10);
 690                 frame_val = tr32(MAC_MI_COM);
 691                 if ((frame_val & MI_COM_BUSY) == 0) {
 692                         udelay(5);
 693                         frame_val = tr32(MAC_MI_COM);
 694                         break;
 695                 }
 696                 loops -= 1;
 697         }
 698
 699         ret = -EBUSY;
 700         if (loops != 0)
 701                 ret = 0;
 702
 703         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 704                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 705                 udelay(80);
 706         }
 707
 708         return ret;
 709 }
 710
 711 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 712 {
 713         u32 val;
 714
 715         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 716                 return;
 717
 718         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 719             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 720                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 721                              (val | (1 << 15) | (1 << 4)));
 722 }
 723
 724 static int tg3_bmcr_reset(struct tg3 *tp)
 725 {
 726         u32 phy_control;
 727         int limit, err;
 728
 729         /* OK, reset it, and poll the BMCR_RESET bit until it
 730          * clears or we time out.
 731          */
 732         phy_control = BMCR_RESET;
 733         err = tg3_writephy(tp, MII_BMCR, phy_control);
 734         if (err != 0)
 735                 return -EBUSY;
 736
 737         limit = 5000;
 738         while (limit--) {
 739                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 740                 if (err != 0)
 741                         return -EBUSY;
 742
 743                 if ((phy_control & BMCR_RESET) == 0) {
 744                         udelay(40);
 745                         break;
 746                 }
 747                 udelay(10);
 748         }
 749         if (limit <= 0)
 750                 return -EBUSY;
 751
 752         return 0;
 753 }
 754
 755 static int tg3_wait_macro_done(struct tg3 *tp)
 756 {
 757         int limit = 100;
 758
 759         while (limit--) {
 760                 u32 tmp32;
 761
 762                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 763                         if ((tmp32 & 0x1000) == 0)
 764                                 break;
 765                 }
 766         }
 767         if (limit <= 0)
 768                 return -EBUSY;
 769
 770         return 0;
 771 }
 772
 773 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 774 {
 775         static const u32 test_pat[4][6] = {
 776         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 777         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 778         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 779         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 780         };
 781         int chan;
 782
 783         for (chan = 0; chan < 4; chan++) {
 784                 int i;
 785
 786                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 787                              (chan * 0x2000) | 0x0200);
 788                 tg3_writephy(tp, 0x16, 0x0002);
 789
 790                 for (i = 0; i < 6; i++)
 791                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 792                                      test_pat[chan][i]);
 793
 794                 tg3_writephy(tp, 0x16, 0x0202);
 795                 if (tg3_wait_macro_done(tp)) {
 796                         *resetp = 1;
 797                         return -EBUSY;
 798                 }
 799
 800                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 801                              (chan * 0x2000) | 0x0200);
 802                 tg3_writephy(tp, 0x16, 0x0082);
 803                 if (tg3_wait_macro_done(tp)) {
 804                         *resetp = 1;
 805                         return -EBUSY;
 806                 }
 807
 808                 tg3_writephy(tp, 0x16, 0x0802);
 809                 if (tg3_wait_macro_done(tp)) {
 810                         *resetp = 1;
 811                         return -EBUSY;
 812                 }
 813
 814                 for (i = 0; i < 6; i += 2) {
 815                         u32 low, high;
 816
 817                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 818                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 819                             tg3_wait_macro_done(tp)) {
 820                                 *resetp = 1;
 821                                 return -EBUSY;
 822                         }
 823                         low &= 0x7fff;
 824                         high &= 0x000f;
 825                         if (low != test_pat[chan][i] ||
 826                             high != test_pat[chan][i+1]) {
 827                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 828                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 829                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 830
 831                                 return -EBUSY;
 832                         }
 833                 }
 834         }
 835
 836         return 0;
 837 }
 838
 839 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 840 {
 841         int chan;
 842
 843         for (chan = 0; chan < 4; chan++) {
 844                 int i;
 845
 846                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 847                              (chan * 0x2000) | 0x0200);
 848                 tg3_writephy(tp, 0x16, 0x0002);
 849                 for (i = 0; i < 6; i++)
 850                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 851                 tg3_writephy(tp, 0x16, 0x0202);
 852                 if (tg3_wait_macro_done(tp))
 853                         return -EBUSY;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 860 {
 861         u32 reg32, phy9_orig;
 862         int retries, do_phy_reset, err;
 863
 864         retries = 10;
 865         do_phy_reset = 1;
 866         do {
 867                 if (do_phy_reset) {
 868                         err = tg3_bmcr_reset(tp);
 869                         if (err)
 870                                 return err;
 871                         do_phy_reset = 0;
 872                 }
 873
 874                 /* Disable transmitter and interrupt.  */
 875                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 876                         continue;
 877
 878                 reg32 |= 0x3000;
 879                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 880
 881                 /* Set full-duplex, 1000 mbps.  */
 882                 tg3_writephy(tp, MII_BMCR,
 883                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 884
 885                 /* Set to master mode.  */
 886                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 887                         continue;
 888
 889                 tg3_writephy(tp, MII_TG3_CTRL,
 890                              (MII_TG3_CTRL_AS_MASTER |
 891                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 892
 893                 /* Enable SM_DSP_CLOCK and 6dB.  */
 894                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 895
 896                 /* Block the PHY control access.  */
 897                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 898                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 899
 900                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 901                 if (!err)
 902                         break;
 903         } while (--retries);
 904
 905         err = tg3_phy_reset_chanpat(tp);
 906         if (err)
 907                 return err;
 908
 909         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 910         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 911
 912         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 913         tg3_writephy(tp, 0x16, 0x0000);
 914
 915         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 916             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 917                 /* Set Extended packet length bit for jumbo frames */
 918                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 919         }
 920         else {
 921                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 922         }
 923
 924         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 925
 926         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 927                 reg32 &= ~0x3000;
 928                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 929         } else if (!err)
 930                 err = -EBUSY;
 931
 932         return err;
 933 }
 934
 935 /* This will reset the tigon3 PHY if there is no valid
 936  * link unless the FORCE argument is non-zero.
 937  */
 938 static int tg3_phy_reset(struct tg3 *tp)
 939 {
 940         u32 phy_status;
 941         int err;
 942
 943         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 944         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 945         if (err != 0)
 946                 return -EBUSY;
 947
 948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 949             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 950             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 951                 err = tg3_phy_reset_5703_4_5(tp);
 952                 if (err)
 953                         return err;
 954                 goto out;
 955         }
 956
 957         err = tg3_bmcr_reset(tp);
 958         if (err)
 959                 return err;
 960
 961 out:
 962         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 964                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 965                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 966                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 967                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 969         }
 970         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 971                 tg3_writephy(tp, 0x1c, 0x8d68);
 972                 tg3_writephy(tp, 0x1c, 0x8d68);
 973         }
 974         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 975                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 976                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 977                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
 978                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 979                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
 980                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
 981                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
 982                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 983         }
 984         /* Set Extended packet length bit (bit 14) on all chips that */
 985         /* support jumbo frames */
 986         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 987                 /* Cannot do read-modify-write on 5401 */
 988                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 989         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
 990                 u32 phy_reg;
 991
 992                 /* Set bit 14 with read-modify-write to preserve other bits */
 993                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
 994                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
 995                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
 996         }
 997
 998         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
 999          * jumbo frames transmission.
1000          */
1001         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1002                 u32 phy_reg;
1003
1004                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1005                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1006                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1007         }
1008
1009         tg3_phy_set_wirespeed(tp);
1010         return 0;
1011 }
1012
1013 static void tg3_frob_aux_power(struct tg3 *tp)
1014 {
1015         struct tg3 *tp_peer = tp;
1016
1017         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1018                 return;
1019
1020         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1021                 tp_peer = pci_get_drvdata(tp->pdev_peer);
1022                 if (!tp_peer)
1023                         BUG();
1024         }
1025
1026
1027         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1028             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1029             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1030             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1031                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1032                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1033                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1034                              (GRC_LCLCTRL_GPIO_OE0 |
1035                               GRC_LCLCTRL_GPIO_OE1 |
1036                               GRC_LCLCTRL_GPIO_OE2 |
1037                               GRC_LCLCTRL_GPIO_OUTPUT0 |
1038                               GRC_LCLCTRL_GPIO_OUTPUT1));
1039                         udelay(100);
1040                 } else {
1041                         u32 no_gpio2;
1042                         u32 grc_local_ctrl;
1043
1044                         if (tp_peer != tp &&
1045                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1046                                 return;
1047
1048                         /* On 5753 and variants, GPIO2 cannot be used. */
1049                         no_gpio2 = tp->nic_sram_data_cfg &
1050                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1051
1052                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1053                                          GRC_LCLCTRL_GPIO_OE1 |
1054                                          GRC_LCLCTRL_GPIO_OE2 |
1055                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1056                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1057                         if (no_gpio2) {
1058                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1059                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1060                         }
1061                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1062                                                 grc_local_ctrl);
1063                         udelay(100);
1064
1065                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1066
1067                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1068                                                 grc_local_ctrl);
1069                         udelay(100);
1070
1071                         if (!no_gpio2) {
1072                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1073                                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1074                                        grc_local_ctrl);
1075                                 udelay(100);
1076                         }
1077                 }
1078         } else {
1079                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1080                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1081                         if (tp_peer != tp &&
1082                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1083                                 return;
1084
1085                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1086                              (GRC_LCLCTRL_GPIO_OE1 |
1087                               GRC_LCLCTRL_GPIO_OUTPUT1));
1088                         udelay(100);
1089
1090                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1091                              (GRC_LCLCTRL_GPIO_OE1));
1092                         udelay(100);
1093
1094                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095                              (GRC_LCLCTRL_GPIO_OE1 |
1096                               GRC_LCLCTRL_GPIO_OUTPUT1));
1097                         udelay(100);
1098                 }
1099         }
1100 }
1101
1102 static int tg3_setup_phy(struct tg3 *, int);
1103
1104 #define RESET_KIND_SHUTDOWN     0
1105 #define RESET_KIND_INIT         1
1106 #define RESET_KIND_SUSPEND      2
1107
1108 static void tg3_write_sig_post_reset(struct tg3 *, int);
1109 static int tg3_halt_cpu(struct tg3 *, u32);
1110 static int tg3_nvram_lock(struct tg3 *);
1111 static void tg3_nvram_unlock(struct tg3 *);
1112
1113 static int tg3_set_power_state(struct tg3 *tp, int state)
1114 {
1115         u32 misc_host_ctrl;
1116         u16 power_control, power_caps;
1117         int pm = tp->pm_cap;
1118
1119         /* Make sure register accesses (indirect or otherwise)
1120          * will function correctly.
1121          */
1122         pci_write_config_dword(tp->pdev,
1123                                TG3PCI_MISC_HOST_CTRL,
1124                                tp->misc_host_ctrl);
1125
1126         pci_read_config_word(tp->pdev,
1127                              pm + PCI_PM_CTRL,
1128                              &power_control);
1129         power_control |= PCI_PM_CTRL_PME_STATUS;
1130         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1131         switch (state) {
1132         case 0:
1133                 power_control |= 0;
1134                 pci_write_config_word(tp->pdev,
1135                                       pm + PCI_PM_CTRL,
1136                                       power_control);
1137                 udelay(100);    /* Delay after power state change */
1138
1139                 /* Switch out of Vaux if it is not a LOM */
1140                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1141                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1142                         udelay(100);
1143                 }
1144
1145                 return 0;
1146
1147         case 1:
1148                 power_control |= 1;
1149                 break;
1150
1151         case 2:
1152                 power_control |= 2;
1153                 break;
1154
1155         case 3:
1156                 power_control |= 3;
1157                 break;
1158
1159         default:
1160                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1161                        "requested.\n",
1162                        tp->dev->name, state);
1163                 return -EINVAL;
1164         };
1165
1166         power_control |= PCI_PM_CTRL_PME_ENABLE;
1167
1168         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1169         tw32(TG3PCI_MISC_HOST_CTRL,
1170              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1171
1172         if (tp->link_config.phy_is_low_power == 0) {
1173                 tp->link_config.phy_is_low_power = 1;
1174                 tp->link_config.orig_speed = tp->link_config.speed;
1175                 tp->link_config.orig_duplex = tp->link_config.duplex;
1176                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1177         }
1178
1179         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1180                 tp->link_config.speed = SPEED_10;
1181                 tp->link_config.duplex = DUPLEX_HALF;
1182                 tp->link_config.autoneg = AUTONEG_ENABLE;
1183                 tg3_setup_phy(tp, 0);
1184         }
1185
1186         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1187                 int i;
1188                 u32 val;
1189
1190                 for (i = 0; i < 200; i++) {
1191                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1192                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1193                                 break;
1194                         msleep(1);
1195                 }
1196         }
1197         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1198                                              WOL_DRV_STATE_SHUTDOWN |
1199                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1200
1201         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1202
1203         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1204                 u32 mac_mode;
1205
1206                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1207                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1208                         udelay(40);
1209
1210                         mac_mode = MAC_MODE_PORT_MODE_MII;
1211
1212                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1213                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1214                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1215                 } else {
1216                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1217                 }
1218
1219                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1220                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1221
1222                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1223                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1224                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1225
1226                 tw32_f(MAC_MODE, mac_mode);
1227                 udelay(100);
1228
1229                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1230                 udelay(10);
1231         }
1232
1233         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1234             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1235              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1236                 u32 base_val;
1237
1238                 base_val = tp->pci_clock_ctrl;
1239                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1240                              CLOCK_CTRL_TXCLK_DISABLE);
1241
1242                 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1243                      CLOCK_CTRL_ALTCLK |
1244                      CLOCK_CTRL_PWRDOWN_PLL133);
1245                 udelay(40);
1246         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1247                 /* do nothing */
1248         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1249                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1250                 u32 newbits1, newbits2;
1251
1252                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1253                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1254                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1255                                     CLOCK_CTRL_TXCLK_DISABLE |
1256                                     CLOCK_CTRL_ALTCLK);
1257                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1258                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1259                         newbits1 = CLOCK_CTRL_625_CORE;
1260                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1261                 } else {
1262                         newbits1 = CLOCK_CTRL_ALTCLK;
1263                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1264                 }
1265
1266                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1267                 udelay(40);
1268
1269                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1270                 udelay(40);
1271
1272                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1273                         u32 newbits3;
1274
1275                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1276                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1277                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1278                                             CLOCK_CTRL_TXCLK_DISABLE |
1279                                             CLOCK_CTRL_44MHZ_CORE);
1280                         } else {
1281                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1282                         }
1283
1284                         tw32_f(TG3PCI_CLOCK_CTRL,
1285                                          tp->pci_clock_ctrl | newbits3);
1286                         udelay(40);
1287                 }
1288         }
1289
1290         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1291             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1292                 /* Turn off the PHY */
1293                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1294                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1295                                      MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1296                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1297                         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1298                 }
1299         }
1300
1301         tg3_frob_aux_power(tp);
1302
1303         /* Workaround for unstable PLL clock */
1304         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1305             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1306                 u32 val = tr32(0x7d00);
1307
1308                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1309                 tw32(0x7d00, val);
1310                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1311                         tg3_nvram_lock(tp);
1312                         tg3_halt_cpu(tp, RX_CPU_BASE);
1313                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR0);
1314                         tg3_nvram_unlock(tp);
1315                 }
1316         }
1317
1318         /* Finally, set the new power state. */
1319         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1320         udelay(100);    /* Delay after power state change */
1321
1322         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1323
1324         return 0;
1325 }
1326
1327 static void tg3_link_report(struct tg3 *tp)
1328 {
1329         if (!netif_carrier_ok(tp->dev)) {
1330                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1331         } else {
1332                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1333                        tp->dev->name,
1334                        (tp->link_config.active_speed == SPEED_1000 ?
1335                         1000 :
1336                         (tp->link_config.active_speed == SPEED_100 ?
1337                          100 : 10)),
1338                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1339                         "full" : "half"));
1340
1341                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1342                        "%s for RX.\n",
1343                        tp->dev->name,
1344                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1345                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1346         }
1347 }
1348
1349 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1350 {
1351         u32 new_tg3_flags = 0;
1352         u32 old_rx_mode = tp->rx_mode;
1353         u32 old_tx_mode = tp->tx_mode;
1354
1355         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1356
1357                 /* Convert 1000BaseX flow control bits to 1000BaseT
1358                  * bits before resolving flow control.
1359                  */
1360                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1361                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1362                                        ADVERTISE_PAUSE_ASYM);
1363                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1364
1365                         if (local_adv & ADVERTISE_1000XPAUSE)
1366                                 local_adv |= ADVERTISE_PAUSE_CAP;
1367                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1368                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1369                         if (remote_adv & LPA_1000XPAUSE)
1370                                 remote_adv |= LPA_PAUSE_CAP;
1371                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1372                                 remote_adv |= LPA_PAUSE_ASYM;
1373                 }
1374
1375                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1376                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1377                                 if (remote_adv & LPA_PAUSE_CAP)
1378                                         new_tg3_flags |=
1379                                                 (TG3_FLAG_RX_PAUSE |
1380                                                 TG3_FLAG_TX_PAUSE);
1381                                 else if (remote_adv & LPA_PAUSE_ASYM)
1382                                         new_tg3_flags |=
1383                                                 (TG3_FLAG_RX_PAUSE);
1384                         } else {
1385                                 if (remote_adv & LPA_PAUSE_CAP)
1386                                         new_tg3_flags |=
1387                                                 (TG3_FLAG_RX_PAUSE |
1388                                                 TG3_FLAG_TX_PAUSE);
1389                         }
1390                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1391                         if ((remote_adv & LPA_PAUSE_CAP) &&
1392                         (remote_adv & LPA_PAUSE_ASYM))
1393                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1394                 }
1395
1396                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1397                 tp->tg3_flags |= new_tg3_flags;
1398         } else {
1399                 new_tg3_flags = tp->tg3_flags;
1400         }
1401
1402         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1403                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1404         else
1405                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1406
1407         if (old_rx_mode != tp->rx_mode) {
1408                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1409         }
1410
1411         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1412                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1413         else
1414                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1415
1416         if (old_tx_mode != tp->tx_mode) {
1417                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1418         }
1419 }
1420
1421 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1422 {
1423         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1424         case MII_TG3_AUX_STAT_10HALF:
1425                 *speed = SPEED_10;
1426                 *duplex = DUPLEX_HALF;
1427                 break;
1428
1429         case MII_TG3_AUX_STAT_10FULL:
1430                 *speed = SPEED_10;
1431                 *duplex = DUPLEX_FULL;
1432                 break;
1433
1434         case MII_TG3_AUX_STAT_100HALF:
1435                 *speed = SPEED_100;
1436                 *duplex = DUPLEX_HALF;
1437                 break;
1438
1439         case MII_TG3_AUX_STAT_100FULL:
1440                 *speed = SPEED_100;
1441                 *duplex = DUPLEX_FULL;
1442                 break;
1443
1444         case MII_TG3_AUX_STAT_1000HALF:
1445                 *speed = SPEED_1000;
1446                 *duplex = DUPLEX_HALF;
1447                 break;
1448
1449         case MII_TG3_AUX_STAT_1000FULL:
1450                 *speed = SPEED_1000;
1451                 *duplex = DUPLEX_FULL;
1452                 break;
1453
1454         default:
1455                 *speed = SPEED_INVALID;
1456                 *duplex = DUPLEX_INVALID;
1457                 break;
1458         };
1459 }
1460
1461 static void tg3_phy_copper_begin(struct tg3 *tp)
1462 {
1463         u32 new_adv;
1464         int i;
1465
1466         if (tp->link_config.phy_is_low_power) {
1467                 /* Entering low power mode.  Disable gigabit and
1468                  * 100baseT advertisements.
1469                  */
1470                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1471
1472                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1473                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1474                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1475                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1476
1477                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1478         } else if (tp->link_config.speed == SPEED_INVALID) {
1479                 tp->link_config.advertising =
1480                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1481                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1482                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1483                          ADVERTISED_Autoneg | ADVERTISED_MII);
1484
1485                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1486                         tp->link_config.advertising &=
1487                                 ~(ADVERTISED_1000baseT_Half |
1488                                   ADVERTISED_1000baseT_Full);
1489
1490                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1491                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1492                         new_adv |= ADVERTISE_10HALF;
1493                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1494                         new_adv |= ADVERTISE_10FULL;
1495                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1496                         new_adv |= ADVERTISE_100HALF;
1497                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1498                         new_adv |= ADVERTISE_100FULL;
1499                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1500
1501                 if (tp->link_config.advertising &
1502                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1503                         new_adv = 0;
1504                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1505                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1506                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1507                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1508                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1509                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1510                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1511                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1512                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1513                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1514                 } else {
1515                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1516                 }
1517         } else {
1518                 /* Asking for a specific link mode. */
1519                 if (tp->link_config.speed == SPEED_1000) {
1520                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1521                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1522
1523                         if (tp->link_config.duplex == DUPLEX_FULL)
1524                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1525                         else
1526                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1527                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1528                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1529                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1530                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1531                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1532                 } else {
1533                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1534
1535                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1536                         if (tp->link_config.speed == SPEED_100) {
1537                                 if (tp->link_config.duplex == DUPLEX_FULL)
1538                                         new_adv |= ADVERTISE_100FULL;
1539                                 else
1540                                         new_adv |= ADVERTISE_100HALF;
1541                         } else {
1542                                 if (tp->link_config.duplex == DUPLEX_FULL)
1543                                         new_adv |= ADVERTISE_10FULL;
1544                                 else
1545                                         new_adv |= ADVERTISE_10HALF;
1546                         }
1547                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1548                 }
1549         }
1550
1551         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1552             tp->link_config.speed != SPEED_INVALID) {
1553                 u32 bmcr, orig_bmcr;
1554
1555                 tp->link_config.active_speed = tp->link_config.speed;
1556                 tp->link_config.active_duplex = tp->link_config.duplex;
1557
1558                 bmcr = 0;
1559                 switch (tp->link_config.speed) {
1560                 default:
1561                 case SPEED_10:
1562                         break;
1563
1564                 case SPEED_100:
1565                         bmcr |= BMCR_SPEED100;
1566                         break;
1567
1568                 case SPEED_1000:
1569                         bmcr |= TG3_BMCR_SPEED1000;
1570                         break;
1571                 };
1572
1573                 if (tp->link_config.duplex == DUPLEX_FULL)
1574                         bmcr |= BMCR_FULLDPLX;
1575
1576                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1577                     (bmcr != orig_bmcr)) {
1578                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1579                         for (i = 0; i < 1500; i++) {
1580                                 u32 tmp;
1581
1582                                 udelay(10);
1583                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1584                                     tg3_readphy(tp, MII_BMSR, &tmp))
1585                                         continue;
1586                                 if (!(tmp & BMSR_LSTATUS)) {
1587                                         udelay(40);
1588                                         break;
1589                                 }
1590                         }
1591                         tg3_writephy(tp, MII_BMCR, bmcr);
1592                         udelay(40);
1593                 }
1594         } else {
1595                 tg3_writephy(tp, MII_BMCR,
1596                              BMCR_ANENABLE | BMCR_ANRESTART);
1597         }
1598 }
1599
1600 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1601 {
1602         int err;
1603
1604         /* Turn off tap power management. */
1605         /* Set Extended packet length bit */
1606         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1607
1608         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1609         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1610
1611         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1612         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1613
1614         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1615         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1616
1617         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1618         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1619
1620         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1621         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1622
1623         udelay(40);
1624
1625         return err;
1626 }
1627
1628 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1629 {
1630         u32 adv_reg, all_mask;
1631
1632         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1633                 return 0;
1634
1635         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1636                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1637         if ((adv_reg & all_mask) != all_mask)
1638                 return 0;
1639         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1640                 u32 tg3_ctrl;
1641
1642                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1643                         return 0;
1644
1645                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1646                             MII_TG3_CTRL_ADV_1000_FULL);
1647                 if ((tg3_ctrl & all_mask) != all_mask)
1648                         return 0;
1649         }
1650         return 1;
1651 }
1652
1653 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1654 {
1655         int current_link_up;
1656         u32 bmsr, dummy;
1657         u16 current_speed;
1658         u8 current_duplex;
1659         int i, err;
1660
1661         tw32(MAC_EVENT, 0);
1662
1663         tw32_f(MAC_STATUS,
1664              (MAC_STATUS_SYNC_CHANGED |
1665               MAC_STATUS_CFG_CHANGED |
1666               MAC_STATUS_MI_COMPLETION |
1667               MAC_STATUS_LNKSTATE_CHANGED));
1668         udelay(40);
1669
1670         tp->mi_mode = MAC_MI_MODE_BASE;
1671         tw32_f(MAC_MI_MODE, tp->mi_mode);
1672         udelay(80);
1673
1674         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1675
1676         /* Some third-party PHYs need to be reset on link going
1677          * down.
1678          */
1679         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1680              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1681              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1682             netif_carrier_ok(tp->dev)) {
1683                 tg3_readphy(tp, MII_BMSR, &bmsr);
1684                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1685                     !(bmsr & BMSR_LSTATUS))
1686                         force_reset = 1;
1687         }
1688         if (force_reset)
1689                 tg3_phy_reset(tp);
1690
1691         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1692                 tg3_readphy(tp, MII_BMSR, &bmsr);
1693                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1694                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1695                         bmsr = 0;
1696
1697                 if (!(bmsr & BMSR_LSTATUS)) {
1698                         err = tg3_init_5401phy_dsp(tp);
1699                         if (err)
1700                                 return err;
1701
1702                         tg3_readphy(tp, MII_BMSR, &bmsr);
1703                         for (i = 0; i < 1000; i++) {
1704                                 udelay(10);
1705                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1706                                     (bmsr & BMSR_LSTATUS)) {
1707                                         udelay(40);
1708                                         break;
1709                                 }
1710                         }
1711
1712                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1713                             !(bmsr & BMSR_LSTATUS) &&
1714                             tp->link_config.active_speed == SPEED_1000) {
1715                                 err = tg3_phy_reset(tp);
1716                                 if (!err)
1717                                         err = tg3_init_5401phy_dsp(tp);
1718                                 if (err)
1719                                         return err;
1720                         }
1721                 }
1722         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1723                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1724                 /* 5701 {A0,B0} CRC bug workaround */
1725                 tg3_writephy(tp, 0x15, 0x0a75);
1726                 tg3_writephy(tp, 0x1c, 0x8c68);
1727                 tg3_writephy(tp, 0x1c, 0x8d68);
1728                 tg3_writephy(tp, 0x1c, 0x8c68);
1729         }
1730
1731         /* Clear pending interrupts... */
1732         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1733         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1734
1735         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1736                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1737         else
1738                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1739
1740         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1741             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1742                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1743                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1744                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1745                 else
1746                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1747         }
1748
1749         current_link_up = 0;
1750         current_speed = SPEED_INVALID;
1751         current_duplex = DUPLEX_INVALID;
1752
1753         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1754                 u32 val;
1755
1756                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1757                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1758                 if (!(val & (1 << 10))) {
1759                         val |= (1 << 10);
1760                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1761                         goto relink;
1762                 }
1763         }
1764
1765         bmsr = 0;
1766         for (i = 0; i < 100; i++) {
1767                 tg3_readphy(tp, MII_BMSR, &bmsr);
1768                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1769                     (bmsr & BMSR_LSTATUS))
1770                         break;
1771                 udelay(40);
1772         }
1773
1774         if (bmsr & BMSR_LSTATUS) {
1775                 u32 aux_stat, bmcr;
1776
1777                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1778                 for (i = 0; i < 2000; i++) {
1779                         udelay(10);
1780                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1781                             aux_stat)
1782                                 break;
1783                 }
1784
1785                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1786                                              &current_speed,
1787                                              &current_duplex);
1788
1789                 bmcr = 0;
1790                 for (i = 0; i < 200; i++) {
1791                         tg3_readphy(tp, MII_BMCR, &bmcr);
1792                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1793                                 continue;
1794                         if (bmcr && bmcr != 0x7fff)
1795                                 break;
1796                         udelay(10);
1797                 }
1798
1799                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1800                         if (bmcr & BMCR_ANENABLE) {
1801                                 current_link_up = 1;
1802
1803                                 /* Force autoneg restart if we are exiting
1804                                  * low power mode.
1805                                  */
1806                                 if (!tg3_copper_is_advertising_all(tp))
1807                                         current_link_up = 0;
1808                         } else {
1809                                 current_link_up = 0;
1810                         }
1811                 } else {
1812                         if (!(bmcr & BMCR_ANENABLE) &&
1813                             tp->link_config.speed == current_speed &&
1814                             tp->link_config.duplex == current_duplex) {
1815                                 current_link_up = 1;
1816                         } else {
1817                                 current_link_up = 0;
1818                         }
1819                 }
1820
1821                 tp->link_config.active_speed = current_speed;
1822                 tp->link_config.active_duplex = current_duplex;
1823         }
1824
1825         if (current_link_up == 1 &&
1826             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1827             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1828                 u32 local_adv, remote_adv;
1829
1830                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1831                         local_adv = 0;
1832                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1833
1834                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1835                         remote_adv = 0;
1836
1837                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1838
1839                 /* If we are not advertising full pause capability,
1840                  * something is wrong.  Bring the link down and reconfigure.
1841                  */
1842                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1843                         current_link_up = 0;
1844                 } else {
1845                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1846                 }
1847         }
1848 relink:
1849         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1850                 u32 tmp;
1851
1852                 tg3_phy_copper_begin(tp);
1853
1854                 tg3_readphy(tp, MII_BMSR, &tmp);
1855                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1856                     (tmp & BMSR_LSTATUS))
1857                         current_link_up = 1;
1858         }
1859
1860         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1861         if (current_link_up == 1) {
1862                 if (tp->link_config.active_speed == SPEED_100 ||
1863                     tp->link_config.active_speed == SPEED_10)
1864                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1865                 else
1866                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1867         } else
1868                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1869
1870         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1871         if (tp->link_config.active_duplex == DUPLEX_HALF)
1872                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1873
1874         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1875         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1876                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1877                     (current_link_up == 1 &&
1878                      tp->link_config.active_speed == SPEED_10))
1879                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1880         } else {
1881                 if (current_link_up == 1)
1882                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1883         }
1884
1885         /* ??? Without this setting Netgear GA302T PHY does not
1886          * ??? send/receive packets...
1887          */
1888         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1889             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1890                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1891                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1892                 udelay(80);
1893         }
1894
1895         tw32_f(MAC_MODE, tp->mac_mode);
1896         udelay(40);
1897
1898         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1899                 /* Polled via timer. */
1900                 tw32_f(MAC_EVENT, 0);
1901         } else {
1902                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1903         }
1904         udelay(40);
1905
1906         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1907             current_link_up == 1 &&
1908             tp->link_config.active_speed == SPEED_1000 &&
1909             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1910              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1911                 udelay(120);
1912                 tw32_f(MAC_STATUS,
1913                      (MAC_STATUS_SYNC_CHANGED |
1914                       MAC_STATUS_CFG_CHANGED));
1915                 udelay(40);
1916                 tg3_write_mem(tp,
1917                               NIC_SRAM_FIRMWARE_MBOX,
1918                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1919         }
1920
1921         if (current_link_up != netif_carrier_ok(tp->dev)) {
1922                 if (current_link_up)
1923                         netif_carrier_on(tp->dev);
1924                 else
1925                         netif_carrier_off(tp->dev);
1926                 tg3_link_report(tp);
1927         }
1928
1929         return 0;
1930 }
1931
1932 struct tg3_fiber_aneginfo {
1933         int state;
1934 #define ANEG_STATE_UNKNOWN              0
1935 #define ANEG_STATE_AN_ENABLE            1
1936 #define ANEG_STATE_RESTART_INIT         2
1937 #define ANEG_STATE_RESTART              3
1938 #define ANEG_STATE_DISABLE_LINK_OK      4
1939 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1940 #define ANEG_STATE_ABILITY_DETECT       6
1941 #define ANEG_STATE_ACK_DETECT_INIT      7
1942 #define ANEG_STATE_ACK_DETECT           8
1943 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1944 #define ANEG_STATE_COMPLETE_ACK         10
1945 #define ANEG_STATE_IDLE_DETECT_INIT     11
1946 #define ANEG_STATE_IDLE_DETECT          12
1947 #define ANEG_STATE_LINK_OK              13
1948 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
1949 #define ANEG_STATE_NEXT_PAGE_WAIT       15
1950
1951         u32 flags;
1952 #define MR_AN_ENABLE            0x00000001
1953 #define MR_RESTART_AN           0x00000002
1954 #define MR_AN_COMPLETE          0x00000004
1955 #define MR_PAGE_RX              0x00000008
1956 #define MR_NP_LOADED            0x00000010
1957 #define MR_TOGGLE_TX            0x00000020
1958 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
1959 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
1960 #define MR_LP_ADV_SYM_PAUSE     0x00000100
1961 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
1962 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1963 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1964 #define MR_LP_ADV_NEXT_PAGE     0x00001000
1965 #define MR_TOGGLE_RX            0x00002000
1966 #define MR_NP_RX                0x00004000
1967
1968 #define MR_LINK_OK              0x80000000
1969
1970         unsigned long link_time, cur_time;
1971
1972         u32 ability_match_cfg;
1973         int ability_match_count;
1974
1975         char ability_match, idle_match, ack_match;
1976
1977         u32 txconfig, rxconfig;
1978 #define ANEG_CFG_NP             0x00000080
1979 #define ANEG_CFG_ACK            0x00000040
1980 #define ANEG_CFG_RF2            0x00000020
1981 #define ANEG_CFG_RF1            0x00000010
1982 #define ANEG_CFG_PS2            0x00000001
1983 #define ANEG_CFG_PS1            0x00008000
1984 #define ANEG_CFG_HD             0x00004000
1985 #define ANEG_CFG_FD             0x00002000
1986 #define ANEG_CFG_INVAL          0x00001f06
1987
1988 };
1989 #define ANEG_OK         0
1990 #define ANEG_DONE       1
1991 #define ANEG_TIMER_ENAB 2
1992 #define ANEG_FAILED     -1
1993
1994 #define ANEG_STATE_SETTLE_TIME  10000
1995
1996 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1997                                    struct tg3_fiber_aneginfo *ap)
1998 {
1999         unsigned long delta;
2000         u32 rx_cfg_reg;
2001         int ret;
2002
2003         if (ap->state == ANEG_STATE_UNKNOWN) {
2004                 ap->rxconfig = 0;
2005                 ap->link_time = 0;
2006                 ap->cur_time = 0;
2007                 ap->ability_match_cfg = 0;
2008                 ap->ability_match_count = 0;
2009                 ap->ability_match = 0;
2010                 ap->idle_match = 0;
2011                 ap->ack_match = 0;
2012         }
2013         ap->cur_time++;
2014
2015         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2016                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2017
2018                 if (rx_cfg_reg != ap->ability_match_cfg) {
2019                         ap->ability_match_cfg = rx_cfg_reg;
2020                         ap->ability_match = 0;
2021                         ap->ability_match_count = 0;
2022                 } else {
2023                         if (++ap->ability_match_count > 1) {
2024                                 ap->ability_match = 1;
2025                                 ap->ability_match_cfg = rx_cfg_reg;
2026                         }
2027                 }
2028                 if (rx_cfg_reg & ANEG_CFG_ACK)
2029                         ap->ack_match = 1;
2030                 else
2031                         ap->ack_match = 0;
2032
2033                 ap->idle_match = 0;
2034         } else {
2035                 ap->idle_match = 1;
2036                 ap->ability_match_cfg = 0;
2037                 ap->ability_match_count = 0;
2038                 ap->ability_match = 0;
2039                 ap->ack_match = 0;
2040
2041                 rx_cfg_reg = 0;
2042         }
2043
2044         ap->rxconfig = rx_cfg_reg;
2045         ret = ANEG_OK;
2046
2047         switch(ap->state) {
2048         case ANEG_STATE_UNKNOWN:
2049                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2050                         ap->state = ANEG_STATE_AN_ENABLE;
2051
2052                 /* fallthru */
2053         case ANEG_STATE_AN_ENABLE:
2054                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2055                 if (ap->flags & MR_AN_ENABLE) {
2056                         ap->link_time = 0;
2057                         ap->cur_time = 0;
2058                         ap->ability_match_cfg = 0;
2059                         ap->ability_match_count = 0;
2060                         ap->ability_match = 0;
2061                         ap->idle_match = 0;
2062                         ap->ack_match = 0;
2063
2064                         ap->state = ANEG_STATE_RESTART_INIT;
2065                 } else {
2066                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2067                 }
2068                 break;
2069
2070         case ANEG_STATE_RESTART_INIT:
2071                 ap->link_time = ap->cur_time;
2072                 ap->flags &= ~(MR_NP_LOADED);
2073                 ap->txconfig = 0;
2074                 tw32(MAC_TX_AUTO_NEG, 0);
2075                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2076                 tw32_f(MAC_MODE, tp->mac_mode);
2077                 udelay(40);
2078
2079                 ret = ANEG_TIMER_ENAB;
2080                 ap->state = ANEG_STATE_RESTART;
2081
2082                 /* fallthru */
2083         case ANEG_STATE_RESTART:
2084                 delta = ap->cur_time - ap->link_time;
2085                 if (delta > ANEG_STATE_SETTLE_TIME) {
2086                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2087                 } else {
2088                         ret = ANEG_TIMER_ENAB;
2089                 }
2090                 break;
2091
2092         case ANEG_STATE_DISABLE_LINK_OK:
2093                 ret = ANEG_DONE;
2094                 break;
2095
2096         case ANEG_STATE_ABILITY_DETECT_INIT:
2097                 ap->flags &= ~(MR_TOGGLE_TX);
2098                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2099                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2100                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2101                 tw32_f(MAC_MODE, tp->mac_mode);
2102                 udelay(40);
2103
2104                 ap->state = ANEG_STATE_ABILITY_DETECT;
2105                 break;
2106
2107         case ANEG_STATE_ABILITY_DETECT:
2108                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2109                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2110                 }
2111                 break;
2112
2113         case ANEG_STATE_ACK_DETECT_INIT:
2114                 ap->txconfig |= ANEG_CFG_ACK;
2115                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2116                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2117                 tw32_f(MAC_MODE, tp->mac_mode);
2118                 udelay(40);
2119
2120                 ap->state = ANEG_STATE_ACK_DETECT;
2121
2122                 /* fallthru */
2123         case ANEG_STATE_ACK_DETECT:
2124                 if (ap->ack_match != 0) {
2125                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2126                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2127                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2128                         } else {
2129                                 ap->state = ANEG_STATE_AN_ENABLE;
2130                         }
2131                 } else if (ap->ability_match != 0 &&
2132                            ap->rxconfig == 0) {
2133                         ap->state = ANEG_STATE_AN_ENABLE;
2134                 }
2135                 break;
2136
2137         case ANEG_STATE_COMPLETE_ACK_INIT:
2138                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2139                         ret = ANEG_FAILED;
2140                         break;
2141                 }
2142                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2143                                MR_LP_ADV_HALF_DUPLEX |
2144                                MR_LP_ADV_SYM_PAUSE |
2145                                MR_LP_ADV_ASYM_PAUSE |
2146                                MR_LP_ADV_REMOTE_FAULT1 |
2147                                MR_LP_ADV_REMOTE_FAULT2 |
2148                                MR_LP_ADV_NEXT_PAGE |
2149                                MR_TOGGLE_RX |
2150                                MR_NP_RX);
2151                 if (ap->rxconfig & ANEG_CFG_FD)
2152                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2153                 if (ap->rxconfig & ANEG_CFG_HD)
2154                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2155                 if (ap->rxconfig & ANEG_CFG_PS1)
2156                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2157                 if (ap->rxconfig & ANEG_CFG_PS2)
2158                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2159                 if (ap->rxconfig & ANEG_CFG_RF1)
2160                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2161                 if (ap->rxconfig & ANEG_CFG_RF2)
2162                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2163                 if (ap->rxconfig & ANEG_CFG_NP)
2164                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2165
2166                 ap->link_time = ap->cur_time;
2167
2168                 ap->flags ^= (MR_TOGGLE_TX);
2169                 if (ap->rxconfig & 0x0008)
2170                         ap->flags |= MR_TOGGLE_RX;
2171                 if (ap->rxconfig & ANEG_CFG_NP)
2172                         ap->flags |= MR_NP_RX;
2173                 ap->flags |= MR_PAGE_RX;
2174
2175                 ap->state = ANEG_STATE_COMPLETE_ACK;
2176                 ret = ANEG_TIMER_ENAB;
2177                 break;
2178
2179         case ANEG_STATE_COMPLETE_ACK:
2180                 if (ap->ability_match != 0 &&
2181                     ap->rxconfig == 0) {
2182                         ap->state = ANEG_STATE_AN_ENABLE;
2183                         break;
2184                 }
2185                 delta = ap->cur_time - ap->link_time;
2186                 if (delta > ANEG_STATE_SETTLE_TIME) {
2187                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2188                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2189                         } else {
2190                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2191                                     !(ap->flags & MR_NP_RX)) {
2192                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2193                                 } else {
2194                                         ret = ANEG_FAILED;
2195                                 }
2196                         }
2197                 }
2198                 break;
2199
2200         case ANEG_STATE_IDLE_DETECT_INIT:
2201                 ap->link_time = ap->cur_time;
2202                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2203                 tw32_f(MAC_MODE, tp->mac_mode);
2204                 udelay(40);
2205
2206                 ap->state = ANEG_STATE_IDLE_DETECT;
2207                 ret = ANEG_TIMER_ENAB;
2208                 break;
2209
2210         case ANEG_STATE_IDLE_DETECT:
2211                 if (ap->ability_match != 0 &&
2212                     ap->rxconfig == 0) {
2213                         ap->state = ANEG_STATE_AN_ENABLE;
2214                         break;
2215                 }
2216                 delta = ap->cur_time - ap->link_time;
2217                 if (delta > ANEG_STATE_SETTLE_TIME) {
2218                         /* XXX another gem from the Broadcom driver :( */
2219                         ap->state = ANEG_STATE_LINK_OK;
2220                 }
2221                 break;
2222
2223         case ANEG_STATE_LINK_OK:
2224                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2225                 ret = ANEG_DONE;
2226                 break;
2227
2228         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2229                 /* ??? unimplemented */
2230                 break;
2231
2232         case ANEG_STATE_NEXT_PAGE_WAIT:
2233                 /* ??? unimplemented */
2234                 break;
2235
2236         default:
2237                 ret = ANEG_FAILED;
2238                 break;
2239         };
2240
2241         return ret;
2242 }
2243
2244 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2245 {
2246         int res = 0;
2247         struct tg3_fiber_aneginfo aninfo;
2248         int status = ANEG_FAILED;
2249         unsigned int tick;
2250         u32 tmp;
2251
2252         tw32_f(MAC_TX_AUTO_NEG, 0);
2253
2254         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2255         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2256         udelay(40);
2257
2258         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2259         udelay(40);
2260
2261         memset(&aninfo, 0, sizeof(aninfo));
2262         aninfo.flags |= MR_AN_ENABLE;
2263         aninfo.state = ANEG_STATE_UNKNOWN;
2264         aninfo.cur_time = 0;
2265         tick = 0;
2266         while (++tick < 195000) {
2267                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2268                 if (status == ANEG_DONE || status == ANEG_FAILED)
2269                         break;
2270
2271                 udelay(1);
2272         }
2273
2274         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2275         tw32_f(MAC_MODE, tp->mac_mode);
2276         udelay(40);
2277
2278         *flags = aninfo.flags;
2279
2280         if (status == ANEG_DONE &&
2281             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2282                              MR_LP_ADV_FULL_DUPLEX)))
2283                 res = 1;
2284
2285         return res;
2286 }
2287
2288 static void tg3_init_bcm8002(struct tg3 *tp)
2289 {
2290         u32 mac_status = tr32(MAC_STATUS);
2291         int i;
2292
2293         /* Reset when initting first time or we have a link. */
2294         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2295             !(mac_status & MAC_STATUS_PCS_SYNCED))
2296                 return;
2297
2298         /* Set PLL lock range. */
2299         tg3_writephy(tp, 0x16, 0x8007);
2300
2301         /* SW reset */
2302         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2303
2304         /* Wait for reset to complete. */
2305         /* XXX schedule_timeout() ... */
2306         for (i = 0; i < 500; i++)
2307                 udelay(10);
2308
2309         /* Config mode; select PMA/Ch 1 regs. */
2310         tg3_writephy(tp, 0x10, 0x8411);
2311
2312         /* Enable auto-lock and comdet, select txclk for tx. */
2313         tg3_writephy(tp, 0x11, 0x0a10);
2314
2315         tg3_writephy(tp, 0x18, 0x00a0);
2316         tg3_writephy(tp, 0x16, 0x41ff);
2317
2318         /* Assert and deassert POR. */
2319         tg3_writephy(tp, 0x13, 0x0400);
2320         udelay(40);
2321         tg3_writephy(tp, 0x13, 0x0000);
2322
2323         tg3_writephy(tp, 0x11, 0x0a50);
2324         udelay(40);
2325         tg3_writephy(tp, 0x11, 0x0a10);
2326
2327         /* Wait for signal to stabilize */
2328         /* XXX schedule_timeout() ... */
2329         for (i = 0; i < 15000; i++)
2330                 udelay(10);
2331
2332         /* Deselect the channel register so we can read the PHYID
2333          * later.
2334          */
2335         tg3_writephy(tp, 0x10, 0x8011);
2336 }
2337
2338 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2339 {
2340         u32 sg_dig_ctrl, sg_dig_status;
2341         u32 serdes_cfg, expected_sg_dig_ctrl;
2342         int workaround, port_a;
2343         int current_link_up;
2344
2345         serdes_cfg = 0;
2346         expected_sg_dig_ctrl = 0;
2347         workaround = 0;
2348         port_a = 1;
2349         current_link_up = 0;
2350
2351         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2352             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2353                 workaround = 1;
2354                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2355                         port_a = 0;
2356
2357                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2358                 /* preserve bits 20-23 for voltage regulator */
2359                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2360         }
2361
2362         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2363
2364         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2365                 if (sg_dig_ctrl & (1 << 31)) {
2366                         if (workaround) {
2367                                 u32 val = serdes_cfg;
2368
2369                                 if (port_a)
2370                                         val |= 0xc010000;
2371                                 else
2372                                         val |= 0x4010000;
2373                                 tw32_f(MAC_SERDES_CFG, val);
2374                         }
2375                         tw32_f(SG_DIG_CTRL, 0x01388400);
2376                 }
2377                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2378                         tg3_setup_flow_control(tp, 0, 0);
2379                         current_link_up = 1;
2380                 }
2381                 goto out;
2382         }
2383
2384         /* Want auto-negotiation.  */
2385         expected_sg_dig_ctrl = 0x81388400;
2386
2387         /* Pause capability */
2388         expected_sg_dig_ctrl |= (1 << 11);
2389
2390         /* Asymettric pause */
2391         expected_sg_dig_ctrl |= (1 << 12);
2392
2393         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2394                 if (workaround)
2395                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2396                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2397                 udelay(5);
2398                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2399
2400                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2401         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2402                                  MAC_STATUS_SIGNAL_DET)) {
2403                 int i;
2404
2405                 /* Giver time to negotiate (~200ms) */
2406                 for (i = 0; i < 40000; i++) {
2407                         sg_dig_status = tr32(SG_DIG_STATUS);
2408                         if (sg_dig_status & (0x3))
2409                                 break;
2410                         udelay(5);
2411                 }
2412                 mac_status = tr32(MAC_STATUS);
2413
2414                 if ((sg_dig_status & (1 << 1)) &&
2415                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2416                         u32 local_adv, remote_adv;
2417
2418                         local_adv = ADVERTISE_PAUSE_CAP;
2419                         remote_adv = 0;
2420                         if (sg_dig_status & (1 << 19))
2421                                 remote_adv |= LPA_PAUSE_CAP;
2422                         if (sg_dig_status & (1 << 20))
2423                                 remote_adv |= LPA_PAUSE_ASYM;
2424
2425                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2426                         current_link_up = 1;
2427                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2428                 } else if (!(sg_dig_status & (1 << 1))) {
2429                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2430                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2431                         else {
2432                                 if (workaround) {
2433                                         u32 val = serdes_cfg;
2434
2435                                         if (port_a)
2436                                                 val |= 0xc010000;
2437                                         else
2438                                                 val |= 0x4010000;
2439
2440                                         tw32_f(MAC_SERDES_CFG, val);
2441                                 }
2442
2443                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2444                                 udelay(40);
2445
2446                                 /* Link parallel detection - link is up */
2447                                 /* only if we have PCS_SYNC and not */
2448                                 /* receiving config code words */
2449                                 mac_status = tr32(MAC_STATUS);
2450                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2451                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2452                                         tg3_setup_flow_control(tp, 0, 0);
2453                                         current_link_up = 1;
2454                                 }
2455                         }
2456                 }
2457         }
2458
2459 out:
2460         return current_link_up;
2461 }
2462
2463 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2464 {
2465         int current_link_up = 0;
2466
2467         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2468                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2469                 goto out;
2470         }
2471
2472         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2473                 u32 flags;
2474                 int i;
2475
2476                 if (fiber_autoneg(tp, &flags)) {
2477                         u32 local_adv, remote_adv;
2478
2479                         local_adv = ADVERTISE_PAUSE_CAP;
2480                         remote_adv = 0;
2481                         if (flags & MR_LP_ADV_SYM_PAUSE)
2482                                 remote_adv |= LPA_PAUSE_CAP;
2483                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2484                                 remote_adv |= LPA_PAUSE_ASYM;
2485
2486                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2487
2488                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2489                         current_link_up = 1;
2490                 }
2491                 for (i = 0; i < 30; i++) {
2492                         udelay(20);
2493                         tw32_f(MAC_STATUS,
2494                                (MAC_STATUS_SYNC_CHANGED |
2495                                 MAC_STATUS_CFG_CHANGED));
2496                         udelay(40);
2497                         if ((tr32(MAC_STATUS) &
2498                              (MAC_STATUS_SYNC_CHANGED |
2499                               MAC_STATUS_CFG_CHANGED)) == 0)
2500                                 break;
2501                 }
2502
2503                 mac_status = tr32(MAC_STATUS);
2504                 if (current_link_up == 0 &&
2505                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2506                     !(mac_status & MAC_STATUS_RCVD_CFG))
2507                         current_link_up = 1;
2508         } else {
2509                 /* Forcing 1000FD link up. */
2510                 current_link_up = 1;
2511                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2512
2513                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2514                 udelay(40);
2515         }
2516
2517 out:
2518         return current_link_up;
2519 }
2520
2521 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2522 {
2523         u32 orig_pause_cfg;
2524         u16 orig_active_speed;
2525         u8 orig_active_duplex;
2526         u32 mac_status;
2527         int current_link_up;
2528         int i;
2529
2530         orig_pause_cfg =
2531                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2532                                   TG3_FLAG_TX_PAUSE));
2533         orig_active_speed = tp->link_config.active_speed;
2534         orig_active_duplex = tp->link_config.active_duplex;
2535
2536         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2537             netif_carrier_ok(tp->dev) &&
2538             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2539                 mac_status = tr32(MAC_STATUS);
2540                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2541                                MAC_STATUS_SIGNAL_DET |
2542                                MAC_STATUS_CFG_CHANGED |
2543                                MAC_STATUS_RCVD_CFG);
2544                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2545                                    MAC_STATUS_SIGNAL_DET)) {
2546                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2547                                             MAC_STATUS_CFG_CHANGED));
2548                         return 0;
2549                 }
2550         }
2551
2552         tw32_f(MAC_TX_AUTO_NEG, 0);
2553
2554         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2555         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2556         tw32_f(MAC_MODE, tp->mac_mode);
2557         udelay(40);
2558
2559         if (tp->phy_id == PHY_ID_BCM8002)
2560                 tg3_init_bcm8002(tp);
2561
2562         /* Enable link change event even when serdes polling.  */
2563         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2564         udelay(40);
2565
2566         current_link_up = 0;
2567         mac_status = tr32(MAC_STATUS);
2568
2569         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2570                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2571         else
2572                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2573
2574         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2575         tw32_f(MAC_MODE, tp->mac_mode);
2576         udelay(40);
2577
2578         tp->hw_status->status =
2579                 (SD_STATUS_UPDATED |
2580                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2581
2582         for (i = 0; i < 100; i++) {
2583                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2584                                     MAC_STATUS_CFG_CHANGED));
2585                 udelay(5);
2586                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2587                                          MAC_STATUS_CFG_CHANGED)) == 0)
2588                         break;
2589         }
2590
2591         mac_status = tr32(MAC_STATUS);
2592         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2593                 current_link_up = 0;
2594                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2595                         tw32_f(MAC_MODE, (tp->mac_mode |
2596                                           MAC_MODE_SEND_CONFIGS));
2597                         udelay(1);
2598                         tw32_f(MAC_MODE, tp->mac_mode);
2599                 }
2600         }
2601
2602         if (current_link_up == 1) {
2603                 tp->link_config.active_speed = SPEED_1000;
2604                 tp->link_config.active_duplex = DUPLEX_FULL;
2605                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2606                                     LED_CTRL_LNKLED_OVERRIDE |
2607                                     LED_CTRL_1000MBPS_ON));
2608         } else {
2609                 tp->link_config.active_speed = SPEED_INVALID;
2610                 tp->link_config.active_duplex = DUPLEX_INVALID;
2611                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2612                                     LED_CTRL_LNKLED_OVERRIDE |
2613                                     LED_CTRL_TRAFFIC_OVERRIDE));
2614         }
2615
2616         if (current_link_up != netif_carrier_ok(tp->dev)) {
2617                 if (current_link_up)
2618                         netif_carrier_on(tp->dev);
2619                 else
2620                         netif_carrier_off(tp->dev);
2621                 tg3_link_report(tp);
2622         } else {
2623                 u32 now_pause_cfg =
2624                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2625                                          TG3_FLAG_TX_PAUSE);
2626                 if (orig_pause_cfg != now_pause_cfg ||
2627                     orig_active_speed != tp->link_config.active_speed ||
2628                     orig_active_duplex != tp->link_config.active_duplex)
2629                         tg3_link_report(tp);
2630         }
2631
2632         return 0;
2633 }
2634
2635 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2636 {
2637         int current_link_up, err = 0;
2638         u32 bmsr, bmcr;
2639         u16 current_speed;
2640         u8 current_duplex;
2641
2642         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2643         tw32_f(MAC_MODE, tp->mac_mode);
2644         udelay(40);
2645
2646         tw32(MAC_EVENT, 0);
2647
2648         tw32_f(MAC_STATUS,
2649              (MAC_STATUS_SYNC_CHANGED |
2650               MAC_STATUS_CFG_CHANGED |
2651               MAC_STATUS_MI_COMPLETION |
2652               MAC_STATUS_LNKSTATE_CHANGED));
2653         udelay(40);
2654
2655         if (force_reset)
2656                 tg3_phy_reset(tp);
2657
2658         current_link_up = 0;
2659         current_speed = SPEED_INVALID;
2660         current_duplex = DUPLEX_INVALID;
2661
2662         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2663         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2664
2665         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2666
2667         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2668             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2669                 /* do nothing, just check for link up at the end */
2670         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2671                 u32 adv, new_adv;
2672
2673                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2674                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2675                                   ADVERTISE_1000XPAUSE |
2676                                   ADVERTISE_1000XPSE_ASYM |
2677                                   ADVERTISE_SLCT);
2678
2679                 /* Always advertise symmetric PAUSE just like copper */
2680                 new_adv |= ADVERTISE_1000XPAUSE;
2681
2682                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2683                         new_adv |= ADVERTISE_1000XHALF;
2684                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2685                         new_adv |= ADVERTISE_1000XFULL;
2686
2687                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2688                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2689                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2690                         tg3_writephy(tp, MII_BMCR, bmcr);
2691
2692                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2693                         tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2694                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2695
2696                         return err;
2697                 }
2698         } else {
2699                 u32 new_bmcr;
2700
2701                 bmcr &= ~BMCR_SPEED1000;
2702                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2703
2704                 if (tp->link_config.duplex == DUPLEX_FULL)
2705                         new_bmcr |= BMCR_FULLDPLX;
2706
2707                 if (new_bmcr != bmcr) {
2708                         /* BMCR_SPEED1000 is a reserved bit that needs
2709                          * to be set on write.
2710                          */
2711                         new_bmcr |= BMCR_SPEED1000;
2712
2713                         /* Force a linkdown */
2714                         if (netif_carrier_ok(tp->dev)) {
2715                                 u32 adv;
2716
2717                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2718                                 adv &= ~(ADVERTISE_1000XFULL |
2719                                          ADVERTISE_1000XHALF |
2720                                          ADVERTISE_SLCT);
2721                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2722                                 tg3_writephy(tp, MII_BMCR, bmcr |
2723                                                            BMCR_ANRESTART |
2724                                                            BMCR_ANENABLE);
2725                                 udelay(10);
2726                                 netif_carrier_off(tp->dev);
2727                         }
2728                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2729                         bmcr = new_bmcr;
2730                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2731                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2732                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2733                 }
2734         }
2735
2736         if (bmsr & BMSR_LSTATUS) {
2737                 current_speed = SPEED_1000;
2738                 current_link_up = 1;
2739                 if (bmcr & BMCR_FULLDPLX)
2740                         current_duplex = DUPLEX_FULL;
2741                 else
2742                         current_duplex = DUPLEX_HALF;
2743
2744                 if (bmcr & BMCR_ANENABLE) {
2745                         u32 local_adv, remote_adv, common;
2746
2747                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2748                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2749                         common = local_adv & remote_adv;
2750                         if (common & (ADVERTISE_1000XHALF |
2751                                       ADVERTISE_1000XFULL)) {
2752                                 if (common & ADVERTISE_1000XFULL)
2753                                         current_duplex = DUPLEX_FULL;
2754                                 else
2755                                         current_duplex = DUPLEX_HALF;
2756
2757                                 tg3_setup_flow_control(tp, local_adv,
2758                                                        remote_adv);
2759                         }
2760                         else
2761                                 current_link_up = 0;
2762                 }
2763         }
2764
2765         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2766         if (tp->link_config.active_duplex == DUPLEX_HALF)
2767                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2768
2769         tw32_f(MAC_MODE, tp->mac_mode);
2770         udelay(40);
2771
2772         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2773
2774         tp->link_config.active_speed = current_speed;
2775         tp->link_config.active_duplex = current_duplex;
2776
2777         if (current_link_up != netif_carrier_ok(tp->dev)) {
2778                 if (current_link_up)
2779                         netif_carrier_on(tp->dev);
2780                 else {
2781                         netif_carrier_off(tp->dev);
2782                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2783                 }
2784                 tg3_link_report(tp);
2785         }
2786         return err;
2787 }
2788
2789 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2790 {
2791         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2792                 /* Give autoneg time to complete. */
2793                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2794                 return;
2795         }
2796         if (!netif_carrier_ok(tp->dev) &&
2797             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2798                 u32 bmcr;
2799
2800                 tg3_readphy(tp, MII_BMCR, &bmcr);
2801                 if (bmcr & BMCR_ANENABLE) {
2802                         u32 phy1, phy2;
2803
2804                         /* Select shadow register 0x1f */
2805                         tg3_writephy(tp, 0x1c, 0x7c00);
2806                         tg3_readphy(tp, 0x1c, &phy1);
2807
2808                         /* Select expansion interrupt status register */
2809                         tg3_writephy(tp, 0x17, 0x0f01);
2810                         tg3_readphy(tp, 0x15, &phy2);
2811                         tg3_readphy(tp, 0x15, &phy2);
2812
2813                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2814                                 /* We have signal detect and not receiving
2815                                  * config code words, link is up by parallel
2816                                  * detection.
2817                                  */
2818
2819                                 bmcr &= ~BMCR_ANENABLE;
2820                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2821                                 tg3_writephy(tp, MII_BMCR, bmcr);
2822                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2823                         }
2824                 }
2825         }
2826         else if (netif_carrier_ok(tp->dev) &&
2827                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2828                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2829                 u32 phy2;
2830
2831                 /* Select expansion interrupt status register */
2832                 tg3_writephy(tp, 0x17, 0x0f01);
2833                 tg3_readphy(tp, 0x15, &phy2);
2834                 if (phy2 & 0x20) {
2835                         u32 bmcr;
2836
2837                         /* Config code words received, turn on autoneg. */
2838                         tg3_readphy(tp, MII_BMCR, &bmcr);
2839                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2840
2841                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2842
2843                 }
2844         }
2845 }
2846
2847 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2848 {
2849         int err;
2850
2851         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2852                 err = tg3_setup_fiber_phy(tp, force_reset);
2853         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2854                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2855         } else {
2856                 err = tg3_setup_copper_phy(tp, force_reset);
2857         }
2858
2859         if (tp->link_config.active_speed == SPEED_1000 &&
2860             tp->link_config.active_duplex == DUPLEX_HALF)
2861                 tw32(MAC_TX_LENGTHS,
2862                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2863                       (6 << TX_LENGTHS_IPG_SHIFT) |
2864                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2865         else
2866                 tw32(MAC_TX_LENGTHS,
2867                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2868                       (6 << TX_LENGTHS_IPG_SHIFT) |
2869                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2870
2871         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2872                 if (netif_carrier_ok(tp->dev)) {
2873                         tw32(HOSTCC_STAT_COAL_TICKS,
2874                              tp->coal.stats_block_coalesce_usecs);
2875                 } else {
2876                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2877                 }
2878         }
2879
2880         return err;
2881 }
2882
2883 /* Tigon3 never reports partial packet sends.  So we do not
2884  * need special logic to handle SKBs that have not had all
2885  * of their frags sent yet, like SunGEM does.
2886  */
2887 static void tg3_tx(struct tg3 *tp)
2888 {
2889         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2890         u32 sw_idx = tp->tx_cons;
2891
2892         while (sw_idx != hw_idx) {
2893                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2894                 struct sk_buff *skb = ri->skb;
2895                 int i;
2896
2897                 if (unlikely(skb == NULL))
2898                         BUG();
2899
2900                 pci_unmap_single(tp->pdev,
2901                                  pci_unmap_addr(ri, mapping),
2902                                  skb_headlen(skb),
2903                                  PCI_DMA_TODEVICE);
2904
2905                 ri->skb = NULL;
2906
2907                 sw_idx = NEXT_TX(sw_idx);
2908
2909                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2910                         if (unlikely(sw_idx == hw_idx))
2911                                 BUG();
2912
2913                         ri = &tp->tx_buffers[sw_idx];
2914                         if (unlikely(ri->skb != NULL))
2915                                 BUG();
2916
2917                         pci_unmap_page(tp->pdev,
2918                                        pci_unmap_addr(ri, mapping),
2919                                        skb_shinfo(skb)->frags[i].size,
2920                                        PCI_DMA_TODEVICE);
2921
2922                         sw_idx = NEXT_TX(sw_idx);
2923                 }
2924
2925                 dev_kfree_skb(skb);
2926         }
2927
2928         tp->tx_cons = sw_idx;
2929
2930         if (unlikely(netif_queue_stopped(tp->dev))) {
2931                 spin_lock(&tp->tx_lock);
2932                 if (netif_queue_stopped(tp->dev) &&
2933                     (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2934                         netif_wake_queue(tp->dev);
2935                 spin_unlock(&tp->tx_lock);
2936         }
2937 }
2938
2939 /* Returns size of skb allocated or < 0 on error.
2940  *
2941  * We only need to fill in the address because the other members
2942  * of the RX descriptor are invariant, see tg3_init_rings.
2943  *
2944  * Note the purposeful assymetry of cpu vs. chip accesses.  For
2945  * posting buffers we only dirty the first cache line of the RX
2946  * descriptor (containing the address).  Whereas for the RX status
2947  * buffers the cpu only reads the last cacheline of the RX descriptor
2948  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2949  */
2950 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2951                             int src_idx, u32 dest_idx_unmasked)
2952 {
2953         struct tg3_rx_buffer_desc *desc;
2954         struct ring_info *map, *src_map;
2955         struct sk_buff *skb;
2956         dma_addr_t mapping;
2957         int skb_size, dest_idx;
2958
2959         src_map = NULL;
2960         switch (opaque_key) {
2961         case RXD_OPAQUE_RING_STD:
2962                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2963                 desc = &tp->rx_std[dest_idx];
2964                 map = &tp->rx_std_buffers[dest_idx];
2965                 if (src_idx >= 0)
2966                         src_map = &tp->rx_std_buffers[src_idx];
2967                 skb_size = tp->rx_pkt_buf_sz;
2968                 break;
2969
2970         case RXD_OPAQUE_RING_JUMBO:
2971                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2972                 desc = &tp->rx_jumbo[dest_idx];
2973                 map = &tp->rx_jumbo_buffers[dest_idx];
2974                 if (src_idx >= 0)
2975                         src_map = &tp->rx_jumbo_buffers[src_idx];
2976                 skb_size = RX_JUMBO_PKT_BUF_SZ;
2977                 break;
2978
2979         default:
2980                 return -EINVAL;
2981         };
2982
2983         /* Do not overwrite any of the map or rp information
2984          * until we are sure we can commit to a new buffer.
2985          *
2986          * Callers depend upon this behavior and assume that
2987          * we leave everything unchanged if we fail.
2988          */
2989         skb = dev_alloc_skb(skb_size);
2990         if (skb == NULL)
2991                 return -ENOMEM;
2992
2993         skb->dev = tp->dev;
2994         skb_reserve(skb, tp->rx_offset);
2995
2996         mapping = pci_map_single(tp->pdev, skb->data,
2997                                  skb_size - tp->rx_offset,
2998                                  PCI_DMA_FROMDEVICE);
2999
3000         map->skb = skb;
3001         pci_unmap_addr_set(map, mapping, mapping);
3002
3003         if (src_map != NULL)
3004                 src_map->skb = NULL;
3005
3006         desc->addr_hi = ((u64)mapping >> 32);
3007         desc->addr_lo = ((u64)mapping & 0xffffffff);
3008
3009         return skb_size;
3010 }
3011
3012 /* We only need to move over in the address because the other
3013  * members of the RX descriptor are invariant.  See notes above
3014  * tg3_alloc_rx_skb for full details.
3015  */
3016 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3017                            int src_idx, u32 dest_idx_unmasked)
3018 {
3019         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3020         struct ring_info *src_map, *dest_map;
3021         int dest_idx;
3022
3023         switch (opaque_key) {
3024         case RXD_OPAQUE_RING_STD:
3025                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3026                 dest_desc = &tp->rx_std[dest_idx];
3027                 dest_map = &tp->rx_std_buffers[dest_idx];
3028                 src_desc = &tp->rx_std[src_idx];
3029                 src_map = &tp->rx_std_buffers[src_idx];
3030                 break;
3031
3032         case RXD_OPAQUE_RING_JUMBO:
3033                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3034                 dest_desc = &tp->rx_jumbo[dest_idx];
3035                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3036                 src_desc = &tp->rx_jumbo[src_idx];
3037                 src_map = &tp->rx_jumbo_buffers[src_idx];
3038                 break;
3039
3040         default:
3041                 return;
3042         };
3043
3044         dest_map->skb = src_map->skb;
3045         pci_unmap_addr_set(dest_map, mapping,
3046                            pci_unmap_addr(src_map, mapping));
3047         dest_desc->addr_hi = src_desc->addr_hi;
3048         dest_desc->addr_lo = src_desc->addr_lo;
3049
3050         src_map->skb = NULL;
3051 }
3052
3053 #if TG3_VLAN_TAG_USED
3054 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3055 {
3056         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3057 }
3058 #endif
3059
3060 /* The RX ring scheme is composed of multiple rings which post fresh
3061  * buffers to the chip, and one special ring the chip uses to report
3062  * status back to the host.
3063  *
3064  * The special ring reports the status of received packets to the
3065  * host.  The chip does not write into the original descriptor the
3066  * RX buffer was obtained from.  The chip simply takes the original
3067  * descriptor as provided by the host, updates the status and length
3068  * field, then writes this into the next status ring entry.
3069  *
3070  * Each ring the host uses to post buffers to the chip is described
3071  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3072  * it is first placed into the on-chip ram.  When the packet's length
3073  * is known, it walks down the TG3_BDINFO entries to select the ring.
3074  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3075  * which is within the range of the new packet's length is chosen.
3076  *
3077  * The "separate ring for rx status" scheme may sound queer, but it makes
3078  * sense from a cache coherency perspective.  If only the host writes
3079  * to the buffer post rings, and only the chip writes to the rx status
3080  * rings, then cache lines never move beyond shared-modified state.
3081  * If both the host and chip were to write into the same ring, cache line
3082  * eviction could occur since both entities want it in an exclusive state.
3083  */
3084 static int tg3_rx(struct tg3 *tp, int budget)
3085 {
3086         u32 work_mask;
3087         u32 sw_idx = tp->rx_rcb_ptr;
3088         u16 hw_idx;
3089         int received;
3090
3091         hw_idx = tp->hw_status->idx[0].rx_producer;
3092         /*
3093          * We need to order the read of hw_idx and the read of
3094          * the opaque cookie.
3095          */
3096         rmb();
3097         work_mask = 0;
3098         received = 0;
3099         while (sw_idx != hw_idx && budget > 0) {
3100                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3101                 unsigned int len;
3102                 struct sk_buff *skb;
3103                 dma_addr_t dma_addr;
3104                 u32 opaque_key, desc_idx, *post_ptr;
3105
3106                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3107                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3108                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3109                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3110                                                   mapping);
3111                         skb = tp->rx_std_buffers[desc_idx].skb;
3112                         post_ptr = &tp->rx_std_ptr;
3113                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3114                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3115                                                   mapping);
3116                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3117                         post_ptr = &tp->rx_jumbo_ptr;
3118                 }
3119                 else {
3120                         goto next_pkt_nopost;
3121                 }
3122
3123                 work_mask |= opaque_key;
3124
3125                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3126                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3127                 drop_it:
3128                         tg3_recycle_rx(tp, opaque_key,
3129                                        desc_idx, *post_ptr);
3130                 drop_it_no_recycle:
3131                         /* Other statistics kept track of by card. */
3132                         tp->net_stats.rx_dropped++;
3133                         goto next_pkt;
3134                 }
3135
3136                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3137
3138                 if (len > RX_COPY_THRESHOLD
3139                         && tp->rx_offset == 2
3140                         /* rx_offset != 2 iff this is a 5701 card running
3141                          * in PCI-X mode [see tg3_get_invariants()] */
3142                 ) {
3143                         int skb_size;
3144
3145                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3146                                                     desc_idx, *post_ptr);
3147                         if (skb_size < 0)
3148                                 goto drop_it;
3149
3150                         pci_unmap_single(tp->pdev, dma_addr,
3151                                          skb_size - tp->rx_offset,
3152                                          PCI_DMA_FROMDEVICE);
3153
3154                         skb_put(skb, len);
3155                 } else {
3156                         struct sk_buff *copy_skb;
3157
3158                         tg3_recycle_rx(tp, opaque_key,
3159                                        desc_idx, *post_ptr);
3160
3161                         copy_skb = dev_alloc_skb(len + 2);
3162                         if (copy_skb == NULL)
3163                                 goto drop_it_no_recycle;
3164
3165                         copy_skb->dev = tp->dev;
3166                         skb_reserve(copy_skb, 2);
3167                         skb_put(copy_skb, len);
3168                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3169                         memcpy(copy_skb->data, skb->data, len);
3170                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3171
3172                         /* We'll reuse the original ring buffer. */
3173                         skb = copy_skb;
3174                 }
3175
3176                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3177                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3178                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3179                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3180                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3181                 else
3182                         skb->ip_summed = CHECKSUM_NONE;
3183
3184                 skb->protocol = eth_type_trans(skb, tp->dev);
3185 #if TG3_VLAN_TAG_USED
3186                 if (tp->vlgrp != NULL &&
3187                     desc->type_flags & RXD_FLAG_VLAN) {
3188                         tg3_vlan_rx(tp, skb,
3189                                     desc->err_vlan & RXD_VLAN_MASK);
3190                 } else
3191 #endif
3192                         netif_receive_skb(skb);
3193
3194                 tp->dev->last_rx = jiffies;
3195                 received++;
3196                 budget--;
3197
3198 next_pkt:
3199                 (*post_ptr)++;
3200 next_pkt_nopost:
3201                 sw_idx++;
3202                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3203
3204                 /* Refresh hw_idx to see if there is new work */
3205                 if (sw_idx == hw_idx) {
3206                         hw_idx = tp->hw_status->idx[0].rx_producer;
3207                         rmb();
3208                 }
3209         }
3210
3211         /* ACK the status ring. */
3212         tp->rx_rcb_ptr = sw_idx;
3213         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3214
3215         /* Refill RX ring(s). */
3216         if (work_mask & RXD_OPAQUE_RING_STD) {
3217                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3218                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3219                              sw_idx);
3220         }
3221         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3222                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3223                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3224                              sw_idx);
3225         }
3226         mmiowb();
3227
3228         return received;
3229 }
3230
3231 static int tg3_poll(struct net_device *netdev, int *budget)
3232 {
3233         struct tg3 *tp = netdev_priv(netdev);
3234         struct tg3_hw_status *sblk = tp->hw_status;
3235         int done;
3236
3237         /* handle link change and other phy events */
3238         if (!(tp->tg3_flags &
3239               (TG3_FLAG_USE_LINKCHG_REG |
3240                TG3_FLAG_POLL_SERDES))) {
3241                 if (sblk->status & SD_STATUS_LINK_CHG) {
3242                         sblk->status = SD_STATUS_UPDATED |
3243                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3244                         spin_lock(&tp->lock);
3245                         tg3_setup_phy(tp, 0);
3246                         spin_unlock(&tp->lock);
3247                 }
3248         }
3249
3250         /* run TX completion thread */
3251         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3252                 tg3_tx(tp);
3253         }
3254
3255         /* run RX thread, within the bounds set by NAPI.
3256          * All RX "locking" is done by ensuring outside
3257          * code synchronizes with dev->poll()
3258          */
3259         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3260                 int orig_budget = *budget;
3261                 int work_done;
3262
3263                 if (orig_budget > netdev->quota)
3264                         orig_budget = netdev->quota;
3265
3266                 work_done = tg3_rx(tp, orig_budget);
3267
3268                 *budget -= work_done;
3269                 netdev->quota -= work_done;
3270         }
3271
3272         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3273                 tp->last_tag = sblk->status_tag;
3274                 rmb();
3275         } else
3276                 sblk->status &= ~SD_STATUS_UPDATED;
3277
3278         /* if no more work, tell net stack and NIC we're done */
3279         done = !tg3_has_work(tp);
3280         if (done) {
3281                 netif_rx_complete(netdev);
3282                 tg3_restart_ints(tp);
3283         }
3284
3285         return (done ? 0 : 1);
3286 }
3287
3288 static void tg3_irq_quiesce(struct tg3 *tp)
3289 {
3290         BUG_ON(tp->irq_sync);
3291
3292         tp->irq_sync = 1;
3293         smp_mb();
3294
3295         synchronize_irq(tp->pdev->irq);
3296 }
3297
3298 static inline int tg3_irq_sync(struct tg3 *tp)
3299 {
3300         return tp->irq_sync;
3301 }
3302
3303 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3304  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3305  * with as well.  Most of the time, this is not necessary except when
3306  * shutting down the device.
3307  */
3308 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3309 {
3310         if (irq_sync)
3311                 tg3_irq_quiesce(tp);
3312         spin_lock_bh(&tp->lock);
3313         spin_lock(&tp->tx_lock);
3314 }
3315
3316 static inline void tg3_full_unlock(struct tg3 *tp)
3317 {
3318         spin_unlock(&tp->tx_lock);
3319         spin_unlock_bh(&tp->lock);
3320 }
3321
3322 /* MSI ISR - No need to check for interrupt sharing and no need to
3323  * flush status block and interrupt mailbox. PCI ordering rules
3324  * guarantee that MSI will arrive after the status block.
3325  */
3326 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3327 {
3328         struct net_device *dev = dev_id;
3329         struct tg3 *tp = netdev_priv(dev);
3330
3331         prefetch(tp->hw_status);
3332         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3333         /*
3334          * Writing any value to intr-mbox-0 clears PCI INTA# and
3335          * chip-internal interrupt pending events.
3336          * Writing non-zero to intr-mbox-0 additional tells the
3337          * NIC to stop sending us irqs, engaging "in-intr-handler"
3338          * event coalescing.
3339          */
3340         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3341         if (likely(!tg3_irq_sync(tp)))
3342                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3343
3344         return IRQ_RETVAL(1);
3345 }
3346
3347 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3348 {
3349         struct net_device *dev = dev_id;
3350         struct tg3 *tp = netdev_priv(dev);
3351         struct tg3_hw_status *sblk = tp->hw_status;
3352         unsigned int handled = 1;
3353
3354         /* In INTx mode, it is possible for the interrupt to arrive at
3355          * the CPU before the status block posted prior to the interrupt.
3356          * Reading the PCI State register will confirm whether the
3357          * interrupt is ours and will flush the status block.
3358          */
3359         if ((sblk->status & SD_STATUS_UPDATED) ||
3360             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3361                 /*
3362                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3363                  * chip-internal interrupt pending events.
3364                  * Writing non-zero to intr-mbox-0 additional tells the
3365                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3366                  * event coalescing.
3367                  */
3368                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3369                              0x00000001);
3370                 if (tg3_irq_sync(tp))
3371                         goto out;
3372                 sblk->status &= ~SD_STATUS_UPDATED;
3373                 if (likely(tg3_has_work(tp))) {
3374                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3375                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3376                 } else {
3377                         /* No work, shared interrupt perhaps?  re-enable
3378                          * interrupts, and flush that PCI write
3379                          */
3380                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3381                                 0x00000000);
3382                 }
3383         } else {        /* shared interrupt */
3384                 handled = 0;
3385         }
3386 out:
3387         return IRQ_RETVAL(handled);
3388 }
3389
3390 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3391 {
3392         struct net_device *dev = dev_id;
3393         struct tg3 *tp = netdev_priv(dev);
3394         struct tg3_hw_status *sblk = tp->hw_status;
3395         unsigned int handled = 1;
3396
3397         /* In INTx mode, it is possible for the interrupt to arrive at
3398          * the CPU before the status block posted prior to the interrupt.
3399          * Reading the PCI State register will confirm whether the
3400          * interrupt is ours and will flush the status block.
3401          */
3402         if ((sblk->status_tag != tp->last_tag) ||
3403             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3404                 /*
3405                  * writing any value to intr-mbox-0 clears PCI INTA# and
3406                  * chip-internal interrupt pending events.
3407                  * writing non-zero to intr-mbox-0 additional tells the
3408                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3409                  * event coalescing.
3410                  */
3411                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3412                              0x00000001);
3413                 if (tg3_irq_sync(tp))
3414                         goto out;
3415                 if (netif_rx_schedule_prep(dev)) {
3416                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3417                         /* Update last_tag to mark that this status has been
3418                          * seen. Because interrupt may be shared, we may be
3419                          * racing with tg3_poll(), so only update last_tag
3420                          * if tg3_poll() is not scheduled.
3421                          */
3422                         tp->last_tag = sblk->status_tag;
3423                         __netif_rx_schedule(dev);
3424                 }
3425         } else {        /* shared interrupt */
3426                 handled = 0;
3427         }
3428 out:
3429         return IRQ_RETVAL(handled);
3430 }
3431
3432 /* ISR for interrupt test */
3433 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3434                 struct pt_regs *regs)
3435 {
3436         struct net_device *dev = dev_id;
3437         struct tg3 *tp = netdev_priv(dev);
3438         struct tg3_hw_status *sblk = tp->hw_status;
3439
3440         if ((sblk->status & SD_STATUS_UPDATED) ||
3441             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3442                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3443                              0x00000001);
3444                 return IRQ_RETVAL(1);
3445         }
3446         return IRQ_RETVAL(0);
3447 }
3448
3449 static int tg3_init_hw(struct tg3 *);
3450 static int tg3_halt(struct tg3 *, int, int);
3451
3452 #ifdef CONFIG_NET_POLL_CONTROLLER
3453 static void tg3_poll_controller(struct net_device *dev)
3454 {
3455         struct tg3 *tp = netdev_priv(dev);
3456
3457         tg3_interrupt(tp->pdev->irq, dev, NULL);
3458 }
3459 #endif
3460
3461 static void tg3_reset_task(void *_data)
3462 {
3463         struct tg3 *tp = _data;
3464         unsigned int restart_timer;
3465
3466         tg3_netif_stop(tp);
3467
3468         tg3_full_lock(tp, 1);
3469
3470         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3471         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3472
3473         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3474         tg3_init_hw(tp);
3475
3476         tg3_netif_start(tp);
3477
3478         tg3_full_unlock(tp);
3479
3480         if (restart_timer)
3481                 mod_timer(&tp->timer, jiffies + 1);
3482 }
3483
3484 static void tg3_tx_timeout(struct net_device *dev)
3485 {
3486         struct tg3 *tp = netdev_priv(dev);
3487
3488         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3489                dev->name);
3490
3491         schedule_work(&tp->reset_task);
3492 }
3493
3494 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3495 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3496 {
3497         u32 base = (u32) mapping & 0xffffffff;
3498
3499         return ((base > 0xffffdcc0) &&
3500                 (base + len + 8 < base));
3501 }
3502
3503 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3504
3505 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3506                                        u32 last_plus_one, u32 *start,
3507                                        u32 base_flags, u32 mss)
3508 {
3509         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3510         dma_addr_t new_addr = 0;
3511         u32 entry = *start;
3512         int i, ret = 0;
3513
3514         if (!new_skb) {
3515                 ret = -1;
3516         } else {
3517                 /* New SKB is guaranteed to be linear. */
3518                 entry = *start;
3519                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3520                                           PCI_DMA_TODEVICE);
3521                 /* Make sure new skb does not cross any 4G boundaries.
3522                  * Drop the packet if it does.
3523                  */
3524                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3525                         ret = -1;
3526                         dev_kfree_skb(new_skb);
3527                         new_skb = NULL;
3528                 } else {
3529                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3530                                     base_flags, 1 | (mss << 1));
3531                         *start = NEXT_TX(entry);
3532                 }
3533         }
3534
3535         /* Now clean up the sw ring entries. */
3536         i = 0;
3537         while (entry != last_plus_one) {
3538                 int len;
3539
3540                 if (i == 0)
3541                         len = skb_headlen(skb);
3542                 else
3543                         len = skb_shinfo(skb)->frags[i-1].size;
3544                 pci_unmap_single(tp->pdev,
3545                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3546                                  len, PCI_DMA_TODEVICE);
3547                 if (i == 0) {
3548                         tp->tx_buffers[entry].skb = new_skb;
3549                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3550                 } else {
3551                         tp->tx_buffers[entry].skb = NULL;
3552                 }
3553                 entry = NEXT_TX(entry);
3554                 i++;
3555         }
3556
3557         dev_kfree_skb(skb);
3558
3559         return ret;
3560 }
3561
3562 static void tg3_set_txd(struct tg3 *tp, int entry,
3563                         dma_addr_t mapping, int len, u32 flags,
3564                         u32 mss_and_is_end)
3565 {
3566         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3567         int is_end = (mss_and_is_end & 0x1);
3568         u32 mss = (mss_and_is_end >> 1);
3569         u32 vlan_tag = 0;
3570
3571         if (is_end)
3572                 flags |= TXD_FLAG_END;
3573         if (flags & TXD_FLAG_VLAN) {
3574                 vlan_tag = flags >> 16;
3575                 flags &= 0xffff;
3576         }
3577         vlan_tag |= (mss << TXD_MSS_SHIFT);
3578
3579         txd->addr_hi = ((u64) mapping >> 32);
3580         txd->addr_lo = ((u64) mapping & 0xffffffff);
3581         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3582         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3583 }
3584
3585 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3586 {
3587         struct tg3 *tp = netdev_priv(dev);
3588         dma_addr_t mapping;
3589         u32 len, entry, base_flags, mss;
3590         int would_hit_hwbug;
3591
3592         len = skb_headlen(skb);
3593
3594         /* No BH disabling for tx_lock here.  We are running in BH disabled
3595          * context and TX reclaim runs via tp->poll inside of a software
3596          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3597          * no IRQ context deadlocks to worry about either.  Rejoice!
3598          */
3599         if (!spin_trylock(&tp->tx_lock))
3600                 return NETDEV_TX_LOCKED;
3601
3602         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3603                 if (!netif_queue_stopped(dev)) {
3604                         netif_stop_queue(dev);
3605
3606                         /* This is a hard error, log it. */
3607                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3608                                "queue awake!\n", dev->name);
3609                 }
3610                 spin_unlock(&tp->tx_lock);
3611                 return NETDEV_TX_BUSY;
3612         }
3613
3614         entry = tp->tx_prod;
3615         base_flags = 0;
3616         if (skb->ip_summed == CHECKSUM_HW)
3617                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3618 #if TG3_TSO_SUPPORT != 0
3619         mss = 0;
3620         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3621             (mss = skb_shinfo(skb)->tso_size) != 0) {
3622                 int tcp_opt_len, ip_tcp_len;
3623
3624                 if (skb_header_cloned(skb) &&
3625                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3626                         dev_kfree_skb(skb);
3627                         goto out_unlock;
3628                 }
3629
3630                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3631                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3632
3633                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3634                                TXD_FLAG_CPU_POST_DMA);
3635
3636                 skb->nh.iph->check = 0;
3637                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3638                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3639                         skb->h.th->check = 0;
3640                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3641                 }
3642                 else {
3643                         skb->h.th->check =
3644                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3645                                                    skb->nh.iph->daddr,
3646                                                    0, IPPROTO_TCP, 0);
3647                 }
3648
3649                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3650                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3651                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3652                                 int tsflags;
3653
3654                                 tsflags = ((skb->nh.iph->ihl - 5) +
3655                                            (tcp_opt_len >> 2));
3656                                 mss |= (tsflags << 11);
3657                         }
3658                 } else {
3659                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3660                                 int tsflags;
3661
3662                                 tsflags = ((skb->nh.iph->ihl - 5) +
3663                                            (tcp_opt_len >> 2));
3664                                 base_flags |= tsflags << 12;
3665                         }
3666                 }
3667         }
3668 #else
3669         mss = 0;
3670 #endif
3671 #if TG3_VLAN_TAG_USED
3672         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3673                 base_flags |= (TXD_FLAG_VLAN |
3674                                (vlan_tx_tag_get(skb) << 16));
3675 #endif
3676
3677         /* Queue skb data, a.k.a. the main skb fragment. */
3678         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3679
3680         tp->tx_buffers[entry].skb = skb;
3681         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3682
3683         would_hit_hwbug = 0;
3684
3685         if (tg3_4g_overflow_test(mapping, len))
3686                 would_hit_hwbug = 1;
3687
3688         tg3_set_txd(tp, entry, mapping, len, base_flags,
3689                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3690
3691         entry = NEXT_TX(entry);
3692
3693         /* Now loop through additional data fragments, and queue them. */
3694         if (skb_shinfo(skb)->nr_frags > 0) {
3695                 unsigned int i, last;
3696
3697                 last = skb_shinfo(skb)->nr_frags - 1;
3698                 for (i = 0; i <= last; i++) {
3699                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3700
3701                         len = frag->size;
3702                         mapping = pci_map_page(tp->pdev,
3703                                                frag->page,
3704                                                frag->page_offset,
3705                                                len, PCI_DMA_TODEVICE);
3706
3707                         tp->tx_buffers[entry].skb = NULL;
3708                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3709
3710                         if (tg3_4g_overflow_test(mapping, len))
3711                                 would_hit_hwbug = 1;
3712
3713                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3714                                 tg3_set_txd(tp, entry, mapping, len,
3715                                             base_flags, (i == last)|(mss << 1));
3716                         else
3717                                 tg3_set_txd(tp, entry, mapping, len,
3718                                             base_flags, (i == last));
3719
3720                         entry = NEXT_TX(entry);
3721                 }
3722         }
3723
3724         if (would_hit_hwbug) {
3725                 u32 last_plus_one = entry;
3726                 u32 start;
3727
3728                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3729                 start &= (TG3_TX_RING_SIZE - 1);
3730
3731                 /* If the workaround fails due to memory/mapping
3732                  * failure, silently drop this packet.
3733                  */
3734                 if (tigon3_4gb_hwbug_workaround(tp, skb, last_plus_one,
3735                                                 &start, base_flags, mss))
3736                         goto out_unlock;
3737
3738                 entry = start;
3739         }
3740
3741         /* Packets are ready, update Tx producer idx local and on card. */
3742         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3743
3744         tp->tx_prod = entry;
3745         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
3746                 netif_stop_queue(dev);
3747                 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3748                         netif_wake_queue(tp->dev);
3749         }
3750
3751 out_unlock:
3752         mmiowb();
3753         spin_unlock(&tp->tx_lock);
3754
3755         dev->trans_start = jiffies;
3756
3757         return NETDEV_TX_OK;
3758 }
3759
3760 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3761                                int new_mtu)
3762 {
3763         dev->mtu = new_mtu;
3764
3765         if (new_mtu > ETH_DATA_LEN) {
3766                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
3767                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3768                         ethtool_op_set_tso(dev, 0);
3769                 }
3770                 else
3771                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3772         } else {
3773                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
3774                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
3775                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
3776         }
3777 }
3778
3779 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3780 {
3781         struct tg3 *tp = netdev_priv(dev);
3782
3783         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3784                 return -EINVAL;
3785
3786         if (!netif_running(dev)) {
3787                 /* We'll just catch it later when the
3788                  * device is up'd.
3789                  */
3790                 tg3_set_mtu(dev, tp, new_mtu);
3791                 return 0;
3792         }
3793
3794         tg3_netif_stop(tp);
3795
3796         tg3_full_lock(tp, 1);
3797
3798         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3799
3800         tg3_set_mtu(dev, tp, new_mtu);
3801
3802         tg3_init_hw(tp);
3803
3804         tg3_netif_start(tp);
3805
3806         tg3_full_unlock(tp);
3807
3808         return 0;
3809 }
3810
3811 /* Free up pending packets in all rx/tx rings.
3812  *
3813  * The chip has been shut down and the driver detached from
3814  * the networking, so no interrupts or new tx packets will
3815  * end up in the driver.  tp->{tx,}lock is not held and we are not
3816  * in an interrupt context and thus may sleep.
3817  */
3818 static void tg3_free_rings(struct tg3 *tp)
3819 {
3820         struct ring_info *rxp;
3821         int i;
3822
3823         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3824                 rxp = &tp->rx_std_buffers[i];
3825
3826                 if (rxp->skb == NULL)
3827                         continue;
3828                 pci_unmap_single(tp->pdev,
3829                                  pci_unmap_addr(rxp, mapping),
3830                                  tp->rx_pkt_buf_sz - tp->rx_offset,
3831                                  PCI_DMA_FROMDEVICE);
3832                 dev_kfree_skb_any(rxp->skb);
3833                 rxp->skb = NULL;
3834         }
3835
3836         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3837                 rxp = &tp->rx_jumbo_buffers[i];
3838
3839                 if (rxp->skb == NULL)
3840                         continue;
3841                 pci_unmap_single(tp->pdev,
3842                                  pci_unmap_addr(rxp, mapping),
3843                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3844                                  PCI_DMA_FROMDEVICE);
3845                 dev_kfree_skb_any(rxp->skb);
3846                 rxp->skb = NULL;
3847         }
3848
3849         for (i = 0; i < TG3_TX_RING_SIZE; ) {
3850                 struct tx_ring_info *txp;
3851                 struct sk_buff *skb;
3852                 int j;
3853
3854                 txp = &tp->tx_buffers[i];
3855                 skb = txp->skb;
3856
3857                 if (skb == NULL) {
3858                         i++;
3859                         continue;
3860                 }
3861
3862                 pci_unmap_single(tp->pdev,
3863                                  pci_unmap_addr(txp, mapping),
3864                                  skb_headlen(skb),
3865                                  PCI_DMA_TODEVICE);
3866                 txp->skb = NULL;
3867
3868                 i++;
3869
3870                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3871                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3872                         pci_unmap_page(tp->pdev,
3873                                        pci_unmap_addr(txp, mapping),
3874                                        skb_shinfo(skb)->frags[j].size,
3875                                        PCI_DMA_TODEVICE);
3876                         i++;
3877                 }
3878
3879                 dev_kfree_skb_any(skb);
3880         }
3881 }
3882
3883 /* Initialize tx/rx rings for packet processing.
3884  *
3885  * The chip has been shut down and the driver detached from
3886  * the networking, so no interrupts or new tx packets will
3887  * end up in the driver.  tp->{tx,}lock are held and thus
3888  * we may not sleep.
3889  */
3890 static void tg3_init_rings(struct tg3 *tp)
3891 {
3892         u32 i;
3893
3894         /* Free up all the SKBs. */
3895         tg3_free_rings(tp);
3896
3897         /* Zero out all descriptors. */
3898         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3899         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3900         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3901         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3902
3903         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
3904         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
3905             (tp->dev->mtu > ETH_DATA_LEN))
3906                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3907
3908         /* Initialize invariants of the rings, we only set this
3909          * stuff once.  This works because the card does not
3910          * write into the rx buffer posting rings.
3911          */
3912         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3913                 struct tg3_rx_buffer_desc *rxd;
3914
3915                 rxd = &tp->rx_std[i];
3916                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
3917                         << RXD_LEN_SHIFT;
3918                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3919                 rxd->opaque = (RXD_OPAQUE_RING_STD |
3920                                (i << RXD_OPAQUE_INDEX_SHIFT));
3921         }
3922
3923         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3924                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3925                         struct tg3_rx_buffer_desc *rxd;
3926
3927                         rxd = &tp->rx_jumbo[i];
3928                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3929                                 << RXD_LEN_SHIFT;
3930                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3931                                 RXD_FLAG_JUMBO;
3932                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3933                                (i << RXD_OPAQUE_INDEX_SHIFT));
3934                 }
3935         }
3936
3937         /* Now allocate fresh SKBs for each rx ring. */
3938         for (i = 0; i < tp->rx_pending; i++) {
3939                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3940                                      -1, i) < 0)
3941                         break;
3942         }
3943
3944         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3945                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3946                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3947                                              -1, i) < 0)
3948                                 break;
3949                 }
3950         }
3951 }
3952
3953 /*
3954  * Must not be invoked with interrupt sources disabled and
3955  * the hardware shutdown down.
3956  */
3957 static void tg3_free_consistent(struct tg3 *tp)
3958 {
3959         kfree(tp->rx_std_buffers);
3960         tp->rx_std_buffers = NULL;
3961         if (tp->rx_std) {
3962                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3963                                     tp->rx_std, tp->rx_std_mapping);
3964                 tp->rx_std = NULL;
3965         }
3966         if (tp->rx_jumbo) {
3967                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3968                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
3969                 tp->rx_jumbo = NULL;
3970         }
3971         if (tp->rx_rcb) {
3972                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3973                                     tp->rx_rcb, tp->rx_rcb_mapping);
3974                 tp->rx_rcb = NULL;
3975         }
3976         if (tp->tx_ring) {
3977                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3978                         tp->tx_ring, tp->tx_desc_mapping);
3979                 tp->tx_ring = NULL;
3980         }
3981         if (tp->hw_status) {
3982                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3983                                     tp->hw_status, tp->status_mapping);
3984                 tp->hw_status = NULL;
3985         }
3986         if (tp->hw_stats) {
3987                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3988                                     tp->hw_stats, tp->stats_mapping);
3989                 tp->hw_stats = NULL;
3990         }
3991 }
3992
3993 /*
3994  * Must not be invoked with interrupt sources disabled and
3995  * the hardware shutdown down.  Can sleep.
3996  */
3997 static int tg3_alloc_consistent(struct tg3 *tp)
3998 {
3999         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4000                                       (TG3_RX_RING_SIZE +
4001                                        TG3_RX_JUMBO_RING_SIZE)) +
4002                                      (sizeof(struct tx_ring_info) *
4003                                       TG3_TX_RING_SIZE),
4004                                      GFP_KERNEL);
4005         if (!tp->rx_std_buffers)
4006                 return -ENOMEM;
4007
4008         memset(tp->rx_std_buffers, 0,
4009                (sizeof(struct ring_info) *
4010                 (TG3_RX_RING_SIZE +
4011                  TG3_RX_JUMBO_RING_SIZE)) +
4012                (sizeof(struct tx_ring_info) *
4013                 TG3_TX_RING_SIZE));
4014
4015         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4016         tp->tx_buffers = (struct tx_ring_info *)
4017                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4018
4019         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4020                                           &tp->rx_std_mapping);
4021         if (!tp->rx_std)
4022                 goto err_out;
4023
4024         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4025                                             &tp->rx_jumbo_mapping);
4026
4027         if (!tp->rx_jumbo)
4028                 goto err_out;
4029
4030         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4031                                           &tp->rx_rcb_mapping);
4032         if (!tp->rx_rcb)
4033                 goto err_out;
4034
4035         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4036                                            &tp->tx_desc_mapping);
4037         if (!tp->tx_ring)
4038                 goto err_out;
4039
4040         tp->hw_status = pci_alloc_consistent(tp->pdev,
4041                                              TG3_HW_STATUS_SIZE,
4042                                              &tp->status_mapping);
4043         if (!tp->hw_status)
4044                 goto err_out;
4045
4046         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4047                                             sizeof(struct tg3_hw_stats),
4048                                             &tp->stats_mapping);
4049         if (!tp->hw_stats)
4050                 goto err_out;
4051
4052         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4053         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4054
4055         return 0;
4056
4057 err_out:
4058         tg3_free_consistent(tp);
4059         return -ENOMEM;
4060 }
4061
4062 #define MAX_WAIT_CNT 1000
4063
4064 /* To stop a block, clear the enable bit and poll till it
4065  * clears.  tp->lock is held.
4066  */
4067 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4068 {
4069         unsigned int i;
4070         u32 val;
4071
4072         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4073                 switch (ofs) {
4074                 case RCVLSC_MODE:
4075                 case DMAC_MODE:
4076                 case MBFREE_MODE:
4077                 case BUFMGR_MODE:
4078                 case MEMARB_MODE:
4079                         /* We can't enable/disable these bits of the
4080                          * 5705/5750, just say success.
4081                          */
4082                         return 0;
4083
4084                 default:
4085                         break;
4086                 };
4087         }
4088
4089         val = tr32(ofs);
4090         val &= ~enable_bit;
4091         tw32_f(ofs, val);
4092
4093         for (i = 0; i < MAX_WAIT_CNT; i++) {
4094                 udelay(100);
4095                 val = tr32(ofs);
4096                 if ((val & enable_bit) == 0)
4097                         break;
4098         }
4099
4100         if (i == MAX_WAIT_CNT && !silent) {
4101                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4102                        "ofs=%lx enable_bit=%x\n",
4103                        ofs, enable_bit);
4104                 return -ENODEV;
4105         }
4106
4107         return 0;
4108 }
4109
4110 /* tp->lock is held. */
4111 static int tg3_abort_hw(struct tg3 *tp, int silent)
4112 {
4113         int i, err;
4114
4115         tg3_disable_ints(tp);
4116
4117         tp->rx_mode &= ~RX_MODE_ENABLE;
4118         tw32_f(MAC_RX_MODE, tp->rx_mode);
4119         udelay(10);
4120
4121         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4122         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4123         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4124         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4125         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4126         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4127
4128         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4129         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4130         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4131         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4132         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4133         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4134         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4135
4136         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4137         tw32_f(MAC_MODE, tp->mac_mode);
4138         udelay(40);
4139
4140         tp->tx_mode &= ~TX_MODE_ENABLE;
4141         tw32_f(MAC_TX_MODE, tp->tx_mode);
4142
4143         for (i = 0; i < MAX_WAIT_CNT; i++) {
4144                 udelay(100);
4145                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4146                         break;
4147         }
4148         if (i >= MAX_WAIT_CNT) {
4149                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4150                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4151                        tp->dev->name, tr32(MAC_TX_MODE));
4152                 err |= -ENODEV;
4153         }
4154
4155         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4156         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4157         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4158
4159         tw32(FTQ_RESET, 0xffffffff);
4160         tw32(FTQ_RESET, 0x00000000);
4161
4162         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4163         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4164
4165         if (tp->hw_status)
4166                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4167         if (tp->hw_stats)
4168                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4169
4170         return err;
4171 }
4172
4173 /* tp->lock is held. */
4174 static int tg3_nvram_lock(struct tg3 *tp)
4175 {
4176         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4177                 int i;
4178
4179                 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4180                 for (i = 0; i < 8000; i++) {
4181                         if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4182                                 break;
4183                         udelay(20);
4184                 }
4185                 if (i == 8000)
4186                         return -ENODEV;
4187         }
4188         return 0;
4189 }
4190
4191 /* tp->lock is held. */
4192 static void tg3_nvram_unlock(struct tg3 *tp)
4193 {
4194         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4195                 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4196 }
4197
4198 /* tp->lock is held. */
4199 static void tg3_enable_nvram_access(struct tg3 *tp)
4200 {
4201         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4202             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4203                 u32 nvaccess = tr32(NVRAM_ACCESS);
4204
4205                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4206         }
4207 }
4208
4209 /* tp->lock is held. */
4210 static void tg3_disable_nvram_access(struct tg3 *tp)
4211 {
4212         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4213             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4214                 u32 nvaccess = tr32(NVRAM_ACCESS);
4215
4216                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4217         }
4218 }
4219
4220 /* tp->lock is held. */
4221 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4222 {
4223         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4224                 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4225                               NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4226
4227         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4228                 switch (kind) {
4229                 case RESET_KIND_INIT:
4230                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4231                                       DRV_STATE_START);
4232                         break;
4233
4234                 case RESET_KIND_SHUTDOWN:
4235                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4236                                       DRV_STATE_UNLOAD);
4237                         break;
4238
4239                 case RESET_KIND_SUSPEND:
4240                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4241                                       DRV_STATE_SUSPEND);
4242                         break;
4243
4244                 default:
4245                         break;
4246                 };
4247         }
4248 }
4249
4250 /* tp->lock is held. */
4251 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4252 {
4253         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4254                 switch (kind) {
4255                 case RESET_KIND_INIT:
4256                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4257                                       DRV_STATE_START_DONE);
4258                         break;
4259
4260                 case RESET_KIND_SHUTDOWN:
4261                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4262                                       DRV_STATE_UNLOAD_DONE);
4263                         break;
4264
4265                 default:
4266                         break;
4267                 };
4268         }
4269 }
4270
4271 /* tp->lock is held. */
4272 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4273 {
4274         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4275                 switch (kind) {
4276                 case RESET_KIND_INIT:
4277                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4278                                       DRV_STATE_START);
4279                         break;
4280
4281                 case RESET_KIND_SHUTDOWN:
4282                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4283                                       DRV_STATE_UNLOAD);
4284                         break;
4285
4286                 case RESET_KIND_SUSPEND:
4287                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4288                                       DRV_STATE_SUSPEND);
4289                         break;
4290
4291                 default:
4292                         break;
4293                 };
4294         }
4295 }
4296
4297 static void tg3_stop_fw(struct tg3 *);
4298
4299 /* tp->lock is held. */
4300 static int tg3_chip_reset(struct tg3 *tp)
4301 {
4302         u32 val;
4303         void (*write_op)(struct tg3 *, u32, u32);
4304         int i;
4305
4306         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4307                 tg3_nvram_lock(tp);
4308
4309         /*
4310          * We must avoid the readl() that normally takes place.
4311          * It locks machines, causes machine checks, and other
4312          * fun things.  So, temporarily disable the 5701
4313          * hardware workaround, while we do the reset.
4314          */
4315         write_op = tp->write32;
4316         if (write_op == tg3_write_flush_reg32)
4317                 tp->write32 = tg3_write32;
4318
4319         /* do the reset */
4320         val = GRC_MISC_CFG_CORECLK_RESET;
4321
4322         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4323                 if (tr32(0x7e2c) == 0x60) {
4324                         tw32(0x7e2c, 0x20);
4325                 }
4326                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4327                         tw32(GRC_MISC_CFG, (1 << 29));
4328                         val |= (1 << 29);
4329                 }
4330         }
4331
4332         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4333                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4334         tw32(GRC_MISC_CFG, val);
4335
4336         /* restore 5701 hardware bug workaround write method */
4337         tp->write32 = write_op;
4338
4339         /* Unfortunately, we have to delay before the PCI read back.
4340          * Some 575X chips even will not respond to a PCI cfg access
4341          * when the reset command is given to the chip.
4342          *
4343          * How do these hardware designers expect things to work
4344          * properly if the PCI write is posted for a long period
4345          * of time?  It is always necessary to have some method by
4346          * which a register read back can occur to push the write
4347          * out which does the reset.
4348          *
4349          * For most tg3 variants the trick below was working.
4350          * Ho hum...
4351          */
4352         udelay(120);
4353
4354         /* Flush PCI posted writes.  The normal MMIO registers
4355          * are inaccessible at this time so this is the only
4356          * way to make this reliably (actually, this is no longer
4357          * the case, see above).  I tried to use indirect
4358          * register read/write but this upset some 5701 variants.
4359          */
4360         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4361
4362         udelay(120);
4363
4364         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4365                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4366                         int i;
4367                         u32 cfg_val;
4368
4369                         /* Wait for link training to complete.  */
4370                         for (i = 0; i < 5000; i++)
4371                                 udelay(100);
4372
4373                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4374                         pci_write_config_dword(tp->pdev, 0xc4,
4375                                                cfg_val | (1 << 15));
4376                 }
4377                 /* Set PCIE max payload size and clear error status.  */
4378                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4379         }
4380
4381         /* Re-enable indirect register accesses. */
4382         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4383                                tp->misc_host_ctrl);
4384
4385         /* Set MAX PCI retry to zero. */
4386         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4387         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4388             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4389                 val |= PCISTATE_RETRY_SAME_DMA;
4390         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4391
4392         pci_restore_state(tp->pdev);
4393
4394         /* Make sure PCI-X relaxed ordering bit is clear. */
4395         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4396         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4397         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4398
4399         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4400                 u32 val;
4401
4402                 /* Chip reset on 5780 will reset MSI enable bit,
4403                  * so need to restore it.
4404                  */
4405                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4406                         u16 ctrl;
4407
4408                         pci_read_config_word(tp->pdev,
4409                                              tp->msi_cap + PCI_MSI_FLAGS,
4410                                              &ctrl);
4411                         pci_write_config_word(tp->pdev,
4412                                               tp->msi_cap + PCI_MSI_FLAGS,
4413                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4414                         val = tr32(MSGINT_MODE);
4415                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4416                 }
4417
4418                 val = tr32(MEMARB_MODE);
4419                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4420
4421         } else
4422                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4423
4424         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4425                 tg3_stop_fw(tp);
4426                 tw32(0x5000, 0x400);
4427         }
4428
4429         tw32(GRC_MODE, tp->grc_mode);
4430
4431         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4432                 u32 val = tr32(0xc4);
4433
4434                 tw32(0xc4, val | (1 << 15));
4435         }
4436
4437         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4438             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4439                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4440                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4441                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4442                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4443         }
4444
4445         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4446                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4447                 tw32_f(MAC_MODE, tp->mac_mode);
4448         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4449                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4450                 tw32_f(MAC_MODE, tp->mac_mode);
4451         } else
4452                 tw32_f(MAC_MODE, 0);
4453         udelay(40);
4454
4455         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4456                 /* Wait for firmware initialization to complete. */
4457                 for (i = 0; i < 100000; i++) {
4458                         tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4459                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4460                                 break;
4461                         udelay(10);
4462                 }
4463                 if (i >= 100000) {
4464                         printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4465                                "firmware will not restart magic=%08x\n",
4466                                tp->dev->name, val);
4467                         return -ENODEV;
4468                 }
4469         }
4470
4471         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4472             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4473                 u32 val = tr32(0x7c00);
4474
4475                 tw32(0x7c00, val | (1 << 25));
4476         }
4477
4478         /* Reprobe ASF enable state.  */
4479         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4480         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4481         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4482         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4483                 u32 nic_cfg;
4484
4485                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4486                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4487                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4488                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4489                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4490                 }
4491         }
4492
4493         return 0;
4494 }
4495
4496 /* tp->lock is held. */
4497 static void tg3_stop_fw(struct tg3 *tp)
4498 {
4499         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4500                 u32 val;
4501                 int i;
4502
4503                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4504                 val = tr32(GRC_RX_CPU_EVENT);
4505                 val |= (1 << 14);
4506                 tw32(GRC_RX_CPU_EVENT, val);
4507
4508                 /* Wait for RX cpu to ACK the event.  */
4509                 for (i = 0; i < 100; i++) {
4510                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4511                                 break;
4512                         udelay(1);
4513                 }
4514         }
4515 }
4516
4517 /* tp->lock is held. */
4518 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4519 {
4520         int err;
4521
4522         tg3_stop_fw(tp);
4523
4524         tg3_write_sig_pre_reset(tp, kind);
4525
4526         tg3_abort_hw(tp, silent);
4527         err = tg3_chip_reset(tp);
4528
4529         tg3_write_sig_legacy(tp, kind);
4530         tg3_write_sig_post_reset(tp, kind);
4531
4532         if (err)
4533                 return err;
4534
4535         return 0;
4536 }
4537
4538 #define TG3_FW_RELEASE_MAJOR    0x0
4539 #define TG3_FW_RELASE_MINOR     0x0
4540 #define TG3_FW_RELEASE_FIX      0x0
4541 #define TG3_FW_START_ADDR       0x08000000
4542 #define TG3_FW_TEXT_ADDR        0x08000000
4543 #define TG3_FW_TEXT_LEN         0x9c0
4544 #define TG3_FW_RODATA_ADDR      0x080009c0
4545 #define TG3_FW_RODATA_LEN       0x60
4546 #define TG3_FW_DATA_ADDR        0x08000a40
4547 #define TG3_FW_DATA_LEN         0x20
4548 #define TG3_FW_SBSS_ADDR        0x08000a60
4549 #define TG3_FW_SBSS_LEN         0xc
4550 #define TG3_FW_BSS_ADDR         0x08000a70
4551 #define TG3_FW_BSS_LEN          0x10
4552
4553 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4554         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4555         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4556         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4557         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4558         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4559         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4560         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4561         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4562         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4563         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4564         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4565         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4566         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4567         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4568         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4569         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4570         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4571         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4572         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4573         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4574         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4575         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4576         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4577         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4578         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4579         0, 0, 0, 0, 0, 0,
4580         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4581         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4582         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4583         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4584         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4585         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4586         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4587         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4588         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4589         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4590         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4591         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4592         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4593         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4594         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4595         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4596         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4597         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4598         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4599         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4600         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4601         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4602         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4603         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4604         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4605         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4606         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4607         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4608         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4609         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4610         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4611         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4612         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4613         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4614         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4615         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4616         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4617         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4618         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4619         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4620         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4621         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4622         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4623         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4624         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4625         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4626         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4627         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4628         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4629         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4630         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4631         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4632         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4633         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4634         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4635         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4636         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4637         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4638         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4639         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4640         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4641         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4642         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4643         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4644         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4645 };
4646
4647 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4648         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4649         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4650         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4651         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4652         0x00000000
4653 };
4654
4655 #if 0 /* All zeros, don't eat up space with it. */
4656 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4657         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4658         0x00000000, 0x00000000, 0x00000000, 0x00000000
4659 };
4660 #endif
4661
4662 #define RX_CPU_SCRATCH_BASE     0x30000
4663 #define RX_CPU_SCRATCH_SIZE     0x04000
4664 #define TX_CPU_SCRATCH_BASE     0x34000
4665 #define TX_CPU_SCRATCH_SIZE     0x04000
4666
4667 /* tp->lock is held. */
4668 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4669 {
4670         int i;
4671
4672         if (offset == TX_CPU_BASE &&
4673             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4674                 BUG();
4675
4676         if (offset == RX_CPU_BASE) {
4677                 for (i = 0; i < 10000; i++) {
4678                         tw32(offset + CPU_STATE, 0xffffffff);
4679                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4680                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4681                                 break;
4682                 }
4683
4684                 tw32(offset + CPU_STATE, 0xffffffff);
4685                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4686                 udelay(10);
4687         } else {
4688                 for (i = 0; i < 10000; i++) {
4689                         tw32(offset + CPU_STATE, 0xffffffff);
4690                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4691                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4692                                 break;
4693                 }
4694         }
4695
4696         if (i >= 10000) {
4697                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4698                        "and %s CPU\n",
4699                        tp->dev->name,
4700                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4701                 return -ENODEV;
4702         }
4703         return 0;
4704 }
4705
4706 struct fw_info {
4707         unsigned int text_base;
4708         unsigned int text_len;
4709         u32 *text_data;
4710         unsigned int rodata_base;
4711         unsigned int rodata_len;
4712         u32 *rodata_data;
4713         unsigned int data_base;
4714         unsigned int data_len;
4715         u32 *data_data;
4716 };
4717
4718 /* tp->lock is held. */
4719 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4720                                  int cpu_scratch_size, struct fw_info *info)
4721 {
4722         int err, i;
4723         void (*write_op)(struct tg3 *, u32, u32);
4724
4725         if (cpu_base == TX_CPU_BASE &&
4726             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4727                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4728                        "TX cpu firmware on %s which is 5705.\n",
4729                        tp->dev->name);
4730                 return -EINVAL;
4731         }
4732
4733         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4734                 write_op = tg3_write_mem;
4735         else
4736                 write_op = tg3_write_indirect_reg32;
4737
4738         /* It is possible that bootcode is still loading at this point.
4739          * Get the nvram lock first before halting the cpu.
4740          */
4741         tg3_nvram_lock(tp);
4742         err = tg3_halt_cpu(tp, cpu_base);
4743         tg3_nvram_unlock(tp);
4744         if (err)
4745                 goto out;
4746
4747         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4748                 write_op(tp, cpu_scratch_base + i, 0);
4749         tw32(cpu_base + CPU_STATE, 0xffffffff);
4750         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4751         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4752                 write_op(tp, (cpu_scratch_base +
4753                               (info->text_base & 0xffff) +
4754                               (i * sizeof(u32))),
4755                          (info->text_data ?
4756                           info->text_data[i] : 0));
4757         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4758                 write_op(tp, (cpu_scratch_base +
4759                               (info->rodata_base & 0xffff) +
4760                               (i * sizeof(u32))),
4761                          (info->rodata_data ?
4762                           info->rodata_data[i] : 0));
4763         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4764                 write_op(tp, (cpu_scratch_base +
4765                               (info->data_base & 0xffff) +
4766                               (i * sizeof(u32))),
4767                          (info->data_data ?
4768                           info->data_data[i] : 0));
4769
4770         err = 0;
4771
4772 out:
4773         return err;
4774 }
4775
4776 /* tp->lock is held. */
4777 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4778 {
4779         struct fw_info info;
4780         int err, i;
4781
4782         info.text_base = TG3_FW_TEXT_ADDR;
4783         info.text_len = TG3_FW_TEXT_LEN;
4784         info.text_data = &tg3FwText[0];
4785         info.rodata_base = TG3_FW_RODATA_ADDR;
4786         info.rodata_len = TG3_FW_RODATA_LEN;
4787         info.rodata_data = &tg3FwRodata[0];
4788         info.data_base = TG3_FW_DATA_ADDR;
4789         info.data_len = TG3_FW_DATA_LEN;
4790         info.data_data = NULL;
4791
4792         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4793                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4794                                     &info);
4795         if (err)
4796                 return err;
4797
4798         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4799                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4800                                     &info);
4801         if (err)
4802                 return err;
4803
4804         /* Now startup only the RX cpu. */
4805         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4806         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4807
4808         for (i = 0; i < 5; i++) {
4809                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4810                         break;
4811                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4812                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
4813                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4814                 udelay(1000);
4815         }
4816         if (i >= 5) {
4817                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4818                        "to set RX CPU PC, is %08x should be %08x\n",
4819                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4820                        TG3_FW_TEXT_ADDR);
4821                 return -ENODEV;
4822         }
4823         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4824         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
4825
4826         return 0;
4827 }
4828
4829 #if TG3_TSO_SUPPORT != 0
4830
4831 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
4832 #define TG3_TSO_FW_RELASE_MINOR         0x6
4833 #define TG3_TSO_FW_RELEASE_FIX          0x0
4834 #define TG3_TSO_FW_START_ADDR           0x08000000
4835 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
4836 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
4837 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
4838 #define TG3_TSO_FW_RODATA_LEN           0x60
4839 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
4840 #define TG3_TSO_FW_DATA_LEN             0x30
4841 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
4842 #define TG3_TSO_FW_SBSS_LEN             0x2c
4843 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
4844 #define TG3_TSO_FW_BSS_LEN              0x894
4845
4846 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4847         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4848         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4849         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4850         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4851         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4852         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4853         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4854         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4855         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4856         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4857         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4858         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4859         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4860         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4861         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4862         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4863         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4864         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4865         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4866         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4867         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4868         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4869         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4870         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4871         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4872         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4873         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4874         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4875         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4876         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4877         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4878         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4879         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4880         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4881         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4882         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4883         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4884         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4885         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4886         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4887         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4888         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4889         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4890         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4891         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4892         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4893         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4894         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4895         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4896         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4897         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4898         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4899         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4900         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4901         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4902         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4903         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4904         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4905         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4906         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4907         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4908         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4909         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4910         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4911         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4912         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4913         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4914         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4915         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4916         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4917         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4918         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4919         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4920         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4921         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4922         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4923         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4924         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4925         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4926         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4927         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4928         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4929         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4930         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4931         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4932         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4933         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4934         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4935         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4936         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4937         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4938         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4939         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4940         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4941         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4942         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4943         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4944         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4945         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4946         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4947         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4948         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4949         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4950         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4951         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4952         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4953         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4954         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4955         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4956         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4957         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4958         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4959         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4960         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4961         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4962         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4963         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4964         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4965         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4966         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4967         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4968         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4969         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4970         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4971         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4972         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4973         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4974         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4975         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4976         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4977         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4978         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4979         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4980         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4981         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4982         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4983         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4984         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4985         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4986         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4987         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4988         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4989         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4990         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4991         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4992         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4993         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4994         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4995         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4996         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4997         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4998         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4999         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5000         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5001         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5002         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5003         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5004         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5005         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5006         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5007         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5008         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5009         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5010         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5011         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5012         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5013         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5014         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5015         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5016         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5017         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5018         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5019         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5020         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5021         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5022         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5023         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5024         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5025         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5026         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5027         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5028         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5029         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5030         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5031         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5032         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5033         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5034         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5035         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5036         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5037         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5038         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5039         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5040         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5041         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5042         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5043         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5044         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5045         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5046         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5047         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5048         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5049         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5050         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5051         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5052         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5053         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5054         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5055         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5056         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5057         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5058         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5059         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5060         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5061         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5062         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5063         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5064         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5065         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5066         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5067         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5068         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5069         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5070         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5071         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5072         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5073         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5074         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5075         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5076         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5077         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5078         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5079         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5080         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5081         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5082         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5083         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5084         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5085         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5086         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5087         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5088         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5089         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5090         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5091         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5092         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5093         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5094         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5095         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5096         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5097         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5098         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5099         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5100         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5101         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5102         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5103         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5104         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5105         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5106         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5107         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5108         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5109         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5110         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5111         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5112         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5113         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5114         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5115         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5116         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5117         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5118         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5119         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5120         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5121         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5122         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5123         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5124         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5125         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5126         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5127         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5128         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5129         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5130         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5131 };
5132
5133 static u32 tg3TsoFwRodata[] = {
5134         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5135         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5136         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5137         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5138         0x00000000,
5139 };
5140
5141 static u32 tg3TsoFwData[] = {
5142         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5143         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5144         0x00000000,
5145 };
5146
5147 /* 5705 needs a special version of the TSO firmware.  */
5148 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5149 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5150 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5151 #define TG3_TSO5_FW_START_ADDR          0x00010000
5152 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5153 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5154 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5155 #define TG3_TSO5_FW_RODATA_LEN          0x50
5156 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5157 #define TG3_TSO5_FW_DATA_LEN            0x20
5158 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5159 #define TG3_TSO5_FW_SBSS_LEN            0x28
5160 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5161 #define TG3_TSO5_FW_BSS_LEN             0x88
5162
5163 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5164         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5165         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5166         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5167         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5168         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5169         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5170         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5171         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5172         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5173         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5174         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5175         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5176         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5177         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5178         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5179         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5180         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5181         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5182         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5183         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5184         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5185         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5186         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5187         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5188         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5189         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5190         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5191         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5192         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5193         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5194         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5195         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5196         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5197         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5198         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5199         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5200         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5201         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5202         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5203         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5204         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5205         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5206         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5207         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5208         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5209         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5210         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5211         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5212         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5213         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5214         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5215         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5216         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5217         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5218         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5219         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5220         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5221         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5222         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5223         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5224         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5225         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5226         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5227         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5228         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5229         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5230         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5231         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5232         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5233         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5234         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5235         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5236         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5237         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5238         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5239         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5240         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5241         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5242         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5243         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5244         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5245         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5246         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5247         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5248         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5249         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5250         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5251         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5252         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5253         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5254         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5255         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5256         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5257         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5258         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5259         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5260         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5261         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5262         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5263         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5264         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5265         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5266         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5267         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5268         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5269         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5270         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5271         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5272         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5273         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5274         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5275         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5276         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5277         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5278         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5279         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5280         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5281         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5282         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5283         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5284         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5285         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5286         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5287         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5288         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5289         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5290         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5291         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5292         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5293         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5294         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5295         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5296         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5297         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5298         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5299         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5300         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5301         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5302         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5303         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5304         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5305         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5306         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5307         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5308         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5309         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5310         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5311         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5312         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5313         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5314         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5315         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5316         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5317         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5318         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5319         0x00000000, 0x00000000, 0x00000000,
5320 };
5321
5322 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5323         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5324         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5325         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5326         0x00000000, 0x00000000, 0x00000000,
5327 };
5328
5329 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5330         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5331         0x00000000, 0x00000000, 0x00000000,
5332 };
5333
5334 /* tp->lock is held. */
5335 static int tg3_load_tso_firmware(struct tg3 *tp)
5336 {
5337         struct fw_info info;
5338         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5339         int err, i;
5340
5341         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5342                 return 0;
5343
5344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5345                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5346                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5347                 info.text_data = &tg3Tso5FwText[0];
5348                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5349                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5350                 info.rodata_data = &tg3Tso5FwRodata[0];
5351                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5352                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5353                 info.data_data = &tg3Tso5FwData[0];
5354                 cpu_base = RX_CPU_BASE;
5355                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5356                 cpu_scratch_size = (info.text_len +
5357                                     info.rodata_len +
5358                                     info.data_len +
5359                                     TG3_TSO5_FW_SBSS_LEN +
5360                                     TG3_TSO5_FW_BSS_LEN);
5361         } else {
5362                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5363                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5364                 info.text_data = &tg3TsoFwText[0];
5365                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5366                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5367                 info.rodata_data = &tg3TsoFwRodata[0];
5368                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5369                 info.data_len = TG3_TSO_FW_DATA_LEN;
5370                 info.data_data = &tg3TsoFwData[0];
5371                 cpu_base = TX_CPU_BASE;
5372                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5373                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5374         }
5375
5376         err = tg3_load_firmware_cpu(tp, cpu_base,
5377                                     cpu_scratch_base, cpu_scratch_size,
5378                                     &info);
5379         if (err)
5380                 return err;
5381
5382         /* Now startup the cpu. */
5383         tw32(cpu_base + CPU_STATE, 0xffffffff);
5384         tw32_f(cpu_base + CPU_PC,    info.text_base);
5385
5386         for (i = 0; i < 5; i++) {
5387                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5388                         break;
5389                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5390                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5391                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5392                 udelay(1000);
5393         }
5394         if (i >= 5) {
5395                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5396                        "to set CPU PC, is %08x should be %08x\n",
5397                        tp->dev->name, tr32(cpu_base + CPU_PC),
5398                        info.text_base);
5399                 return -ENODEV;
5400         }
5401         tw32(cpu_base + CPU_STATE, 0xffffffff);
5402         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5403         return 0;
5404 }
5405
5406 #endif /* TG3_TSO_SUPPORT != 0 */
5407
5408 /* tp->lock is held. */
5409 static void __tg3_set_mac_addr(struct tg3 *tp)
5410 {
5411         u32 addr_high, addr_low;
5412         int i;
5413
5414         addr_high = ((tp->dev->dev_addr[0] << 8) |
5415                      tp->dev->dev_addr[1]);
5416         addr_low = ((tp->dev->dev_addr[2] << 24) |
5417                     (tp->dev->dev_addr[3] << 16) |
5418                     (tp->dev->dev_addr[4] <<  8) |
5419                     (tp->dev->dev_addr[5] <<  0));
5420         for (i = 0; i < 4; i++) {
5421                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5422                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5423         }
5424
5425         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5426             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5427                 for (i = 0; i < 12; i++) {
5428                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5429                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5430                 }
5431         }
5432
5433         addr_high = (tp->dev->dev_addr[0] +
5434                      tp->dev->dev_addr[1] +
5435                      tp->dev->dev_addr[2] +
5436                      tp->dev->dev_addr[3] +
5437                      tp->dev->dev_addr[4] +
5438                      tp->dev->dev_addr[5]) &
5439                 TX_BACKOFF_SEED_MASK;
5440         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5441 }
5442
5443 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5444 {
5445         struct tg3 *tp = netdev_priv(dev);
5446         struct sockaddr *addr = p;
5447
5448         if (!is_valid_ether_addr(addr->sa_data))
5449                 return -EINVAL;
5450
5451         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5452
5453         spin_lock_bh(&tp->lock);
5454         __tg3_set_mac_addr(tp);
5455         spin_unlock_bh(&tp->lock);
5456
5457         return 0;
5458 }
5459
5460 /* tp->lock is held. */
5461 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5462                            dma_addr_t mapping, u32 maxlen_flags,
5463                            u32 nic_addr)
5464 {
5465         tg3_write_mem(tp,
5466                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5467                       ((u64) mapping >> 32));
5468         tg3_write_mem(tp,
5469                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5470                       ((u64) mapping & 0xffffffff));
5471         tg3_write_mem(tp,
5472                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5473                        maxlen_flags);
5474
5475         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5476                 tg3_write_mem(tp,
5477                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5478                               nic_addr);
5479 }
5480
5481 static void __tg3_set_rx_mode(struct net_device *);
5482 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5483 {
5484         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5485         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5486         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5487         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5488         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5489                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5490                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5491         }
5492         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5493         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5494         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5495                 u32 val = ec->stats_block_coalesce_usecs;
5496
5497                 if (!netif_carrier_ok(tp->dev))
5498                         val = 0;
5499
5500                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5501         }
5502 }
5503
5504 /* tp->lock is held. */
5505 static int tg3_reset_hw(struct tg3 *tp)
5506 {
5507         u32 val, rdmac_mode;
5508         int i, err, limit;
5509
5510         tg3_disable_ints(tp);
5511
5512         tg3_stop_fw(tp);
5513
5514         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5515
5516         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5517                 tg3_abort_hw(tp, 1);
5518         }
5519
5520         err = tg3_chip_reset(tp);
5521         if (err)
5522                 return err;
5523
5524         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5525
5526         /* This works around an issue with Athlon chipsets on
5527          * B3 tigon3 silicon.  This bit has no effect on any
5528          * other revision.  But do not set this on PCI Express
5529          * chips.
5530          */
5531         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5532                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5533         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5534
5535         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5536             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5537                 val = tr32(TG3PCI_PCISTATE);
5538                 val |= PCISTATE_RETRY_SAME_DMA;
5539                 tw32(TG3PCI_PCISTATE, val);
5540         }
5541
5542         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5543                 /* Enable some hw fixes.  */
5544                 val = tr32(TG3PCI_MSI_DATA);
5545                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5546                 tw32(TG3PCI_MSI_DATA, val);
5547         }
5548
5549         /* Descriptor ring init may make accesses to the
5550          * NIC SRAM area to setup the TX descriptors, so we
5551          * can only do this after the hardware has been
5552          * successfully reset.
5553          */
5554         tg3_init_rings(tp);
5555
5556         /* This value is determined during the probe time DMA
5557          * engine test, tg3_test_dma.
5558          */
5559         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5560
5561         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5562                           GRC_MODE_4X_NIC_SEND_RINGS |
5563                           GRC_MODE_NO_TX_PHDR_CSUM |
5564                           GRC_MODE_NO_RX_PHDR_CSUM);
5565         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5566         if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5567                 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5568         if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5569                 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5570
5571         tw32(GRC_MODE,
5572              tp->grc_mode |
5573              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5574
5575         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5576         val = tr32(GRC_MISC_CFG);
5577         val &= ~0xff;
5578         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5579         tw32(GRC_MISC_CFG, val);
5580
5581         /* Initialize MBUF/DESC pool. */
5582         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5583                 /* Do nothing.  */
5584         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5585                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5586                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5587                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5588                 else
5589                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5590                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5591                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5592         }
5593 #if TG3_TSO_SUPPORT != 0
5594         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5595                 int fw_len;
5596
5597                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5598                           TG3_TSO5_FW_RODATA_LEN +
5599                           TG3_TSO5_FW_DATA_LEN +
5600                           TG3_TSO5_FW_SBSS_LEN +
5601                           TG3_TSO5_FW_BSS_LEN);
5602                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5603                 tw32(BUFMGR_MB_POOL_ADDR,
5604                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5605                 tw32(BUFMGR_MB_POOL_SIZE,
5606                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5607         }
5608 #endif
5609
5610         if (tp->dev->mtu <= ETH_DATA_LEN) {
5611                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5612                      tp->bufmgr_config.mbuf_read_dma_low_water);
5613                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5614                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5615                 tw32(BUFMGR_MB_HIGH_WATER,
5616                      tp->bufmgr_config.mbuf_high_water);
5617         } else {
5618                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5619                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5620                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5621                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5622                 tw32(BUFMGR_MB_HIGH_WATER,
5623                      tp->bufmgr_config.mbuf_high_water_jumbo);
5624         }
5625         tw32(BUFMGR_DMA_LOW_WATER,
5626              tp->bufmgr_config.dma_low_water);
5627         tw32(BUFMGR_DMA_HIGH_WATER,
5628              tp->bufmgr_config.dma_high_water);
5629
5630         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5631         for (i = 0; i < 2000; i++) {
5632                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5633                         break;
5634                 udelay(10);
5635         }
5636         if (i >= 2000) {
5637                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5638                        tp->dev->name);
5639                 return -ENODEV;
5640         }
5641
5642         /* Setup replenish threshold. */
5643         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5644
5645         /* Initialize TG3_BDINFO's at:
5646          *  RCVDBDI_STD_BD:     standard eth size rx ring
5647          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5648          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5649          *
5650          * like so:
5651          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5652          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5653          *                              ring attribute flags
5654          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5655          *
5656          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5657          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5658          *
5659          * The size of each ring is fixed in the firmware, but the location is
5660          * configurable.
5661          */
5662         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5663              ((u64) tp->rx_std_mapping >> 32));
5664         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5665              ((u64) tp->rx_std_mapping & 0xffffffff));
5666         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5667              NIC_SRAM_RX_BUFFER_DESC);
5668
5669         /* Don't even try to program the JUMBO/MINI buffer descriptor
5670          * configs on 5705.
5671          */
5672         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5673                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5674                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5675         } else {
5676                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5677                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5678
5679                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5680                      BDINFO_FLAGS_DISABLED);
5681
5682                 /* Setup replenish threshold. */
5683                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5684
5685                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5686                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5687                              ((u64) tp->rx_jumbo_mapping >> 32));
5688                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5689                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5690                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5691                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5692                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5693                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5694                 } else {
5695                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5696                              BDINFO_FLAGS_DISABLED);
5697                 }
5698
5699         }
5700
5701         /* There is only one send ring on 5705/5750, no need to explicitly
5702          * disable the others.
5703          */
5704         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5705                 /* Clear out send RCB ring in SRAM. */
5706                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5707                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5708                                       BDINFO_FLAGS_DISABLED);
5709         }
5710
5711         tp->tx_prod = 0;
5712         tp->tx_cons = 0;
5713         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5714         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5715
5716         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5717                        tp->tx_desc_mapping,
5718                        (TG3_TX_RING_SIZE <<
5719                         BDINFO_FLAGS_MAXLEN_SHIFT),
5720                        NIC_SRAM_TX_BUFFER_DESC);
5721
5722         /* There is only one receive return ring on 5705/5750, no need
5723          * to explicitly disable the others.
5724          */
5725         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5726                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5727                      i += TG3_BDINFO_SIZE) {
5728                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5729                                       BDINFO_FLAGS_DISABLED);
5730                 }
5731         }
5732
5733         tp->rx_rcb_ptr = 0;
5734         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5735
5736         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5737                        tp->rx_rcb_mapping,
5738                        (TG3_RX_RCB_RING_SIZE(tp) <<
5739                         BDINFO_FLAGS_MAXLEN_SHIFT),
5740                        0);
5741
5742         tp->rx_std_ptr = tp->rx_pending;
5743         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5744                      tp->rx_std_ptr);
5745
5746         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
5747                                                 tp->rx_jumbo_pending : 0;
5748         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5749                      tp->rx_jumbo_ptr);
5750
5751         /* Initialize MAC address and backoff seed. */
5752         __tg3_set_mac_addr(tp);
5753
5754         /* MTU + ethernet header + FCS + optional VLAN tag */
5755         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5756
5757         /* The slot time is changed by tg3_setup_phy if we
5758          * run at gigabit with half duplex.
5759          */
5760         tw32(MAC_TX_LENGTHS,
5761              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5762              (6 << TX_LENGTHS_IPG_SHIFT) |
5763              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5764
5765         /* Receive rules. */
5766         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5767         tw32(RCVLPC_CONFIG, 0x0181);
5768
5769         /* Calculate RDMAC_MODE setting early, we need it to determine
5770          * the RCVLPC_STATE_ENABLE mask.
5771          */
5772         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5773                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5774                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5775                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5776                       RDMAC_MODE_LNGREAD_ENAB);
5777         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5778                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5779
5780         /* If statement applies to 5705 and 5750 PCI devices only */
5781         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5782              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5783             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5784                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5785                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5786                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5787                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5788                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5789                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5790                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5791                 }
5792         }
5793
5794         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5795                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5796
5797 #if TG3_TSO_SUPPORT != 0
5798         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5799                 rdmac_mode |= (1 << 27);
5800 #endif
5801
5802         /* Receive/send statistics. */
5803         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5804             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5805                 val = tr32(RCVLPC_STATS_ENABLE);
5806                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5807                 tw32(RCVLPC_STATS_ENABLE, val);
5808         } else {
5809                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5810         }
5811         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5812         tw32(SNDDATAI_STATSENAB, 0xffffff);
5813         tw32(SNDDATAI_STATSCTRL,
5814              (SNDDATAI_SCTRL_ENABLE |
5815               SNDDATAI_SCTRL_FASTUPD));
5816
5817         /* Setup host coalescing engine. */
5818         tw32(HOSTCC_MODE, 0);
5819         for (i = 0; i < 2000; i++) {
5820                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5821                         break;
5822                 udelay(10);
5823         }
5824
5825         __tg3_set_coalesce(tp, &tp->coal);
5826
5827         /* set status block DMA address */
5828         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5829              ((u64) tp->status_mapping >> 32));
5830         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5831              ((u64) tp->status_mapping & 0xffffffff));
5832
5833         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5834                 /* Status/statistics block address.  See tg3_timer,
5835                  * the tg3_periodic_fetch_stats call there, and
5836                  * tg3_get_stats to see how this works for 5705/5750 chips.
5837                  */
5838                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5839                      ((u64) tp->stats_mapping >> 32));
5840                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5841                      ((u64) tp->stats_mapping & 0xffffffff));
5842                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5843                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5844         }
5845
5846         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5847
5848         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5849         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5850         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5851                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5852
5853         /* Clear statistics/status block in chip, and status block in ram. */
5854         for (i = NIC_SRAM_STATS_BLK;
5855              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5856              i += sizeof(u32)) {
5857                 tg3_write_mem(tp, i, 0);
5858                 udelay(40);
5859         }
5860         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5861
5862         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5863                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
5864                 /* reset to prevent losing 1st rx packet intermittently */
5865                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5866                 udelay(10);
5867         }
5868
5869         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5870                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5871         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5872         udelay(40);
5873
5874         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5875          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5876          * register to preserve the GPIO settings for LOMs. The GPIOs,
5877          * whether used as inputs or outputs, are set by boot code after
5878          * reset.
5879          */
5880         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5881                 u32 gpio_mask;
5882
5883                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5884                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5885
5886                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5887                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5888                                      GRC_LCLCTRL_GPIO_OUTPUT3;
5889
5890                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5891
5892                 /* GPIO1 must be driven high for eeprom write protect */
5893                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5894                                        GRC_LCLCTRL_GPIO_OUTPUT1);
5895         }
5896         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5897         udelay(100);
5898
5899         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5900         tp->last_tag = 0;
5901
5902         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5903                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5904                 udelay(40);
5905         }
5906
5907         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5908                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5909                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5910                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5911                WDMAC_MODE_LNGREAD_ENAB);
5912
5913         /* If statement applies to 5705 and 5750 PCI devices only */
5914         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5915              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5916             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5917                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5918                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5919                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5920                         /* nothing */
5921                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5922                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5923                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5924                         val |= WDMAC_MODE_RX_ACCEL;
5925                 }
5926         }
5927
5928         tw32_f(WDMAC_MODE, val);
5929         udelay(40);
5930
5931         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5932                 val = tr32(TG3PCI_X_CAPS);
5933                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5934                         val &= ~PCIX_CAPS_BURST_MASK;
5935                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5936                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5937                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5938                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5939                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5940                                 val |= (tp->split_mode_max_reqs <<
5941                                         PCIX_CAPS_SPLIT_SHIFT);
5942                 }
5943                 tw32(TG3PCI_X_CAPS, val);
5944         }
5945
5946         tw32_f(RDMAC_MODE, rdmac_mode);
5947         udelay(40);
5948
5949         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5950         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5951                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5952         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5953         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5954         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5955         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5956         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5957 #if TG3_TSO_SUPPORT != 0
5958         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5959                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5960 #endif
5961         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5962         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5963
5964         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5965                 err = tg3_load_5701_a0_firmware_fix(tp);
5966                 if (err)
5967                         return err;
5968         }
5969
5970 #if TG3_TSO_SUPPORT != 0
5971         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5972                 err = tg3_load_tso_firmware(tp);
5973                 if (err)
5974                         return err;
5975         }
5976 #endif
5977
5978         tp->tx_mode = TX_MODE_ENABLE;
5979         tw32_f(MAC_TX_MODE, tp->tx_mode);
5980         udelay(100);
5981
5982         tp->rx_mode = RX_MODE_ENABLE;
5983         tw32_f(MAC_RX_MODE, tp->rx_mode);
5984         udelay(10);
5985
5986         if (tp->link_config.phy_is_low_power) {
5987                 tp->link_config.phy_is_low_power = 0;
5988                 tp->link_config.speed = tp->link_config.orig_speed;
5989                 tp->link_config.duplex = tp->link_config.orig_duplex;
5990                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5991         }
5992
5993         tp->mi_mode = MAC_MI_MODE_BASE;
5994         tw32_f(MAC_MI_MODE, tp->mi_mode);
5995         udelay(80);
5996
5997         tw32(MAC_LED_CTRL, tp->led_ctrl);
5998
5999         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6000         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6001                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6002                 udelay(10);
6003         }
6004         tw32_f(MAC_RX_MODE, tp->rx_mode);
6005         udelay(10);
6006
6007         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6008                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6009                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6010                         /* Set drive transmission level to 1.2V  */
6011                         /* only if the signal pre-emphasis bit is not set  */
6012                         val = tr32(MAC_SERDES_CFG);
6013                         val &= 0xfffff000;
6014                         val |= 0x880;
6015                         tw32(MAC_SERDES_CFG, val);
6016                 }
6017                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6018                         tw32(MAC_SERDES_CFG, 0x616000);
6019         }
6020
6021         /* Prevent chip from dropping frames when flow control
6022          * is enabled.
6023          */
6024         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6025
6026         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6027             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6028                 /* Use hardware link auto-negotiation */
6029                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6030         }
6031
6032         err = tg3_setup_phy(tp, 1);
6033         if (err)
6034                 return err;
6035
6036         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6037                 u32 tmp;
6038
6039                 /* Clear CRC stats. */
6040                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6041                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6042                         tg3_readphy(tp, 0x14, &tmp);
6043                 }
6044         }
6045
6046         __tg3_set_rx_mode(tp->dev);
6047
6048         /* Initialize receive rules. */
6049         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6050         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6051         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6052         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6053
6054         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6055             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6056                 limit = 8;
6057         else
6058                 limit = 16;
6059         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6060                 limit -= 4;
6061         switch (limit) {
6062         case 16:
6063                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6064         case 15:
6065                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6066         case 14:
6067                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6068         case 13:
6069                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6070         case 12:
6071                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6072         case 11:
6073                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6074         case 10:
6075                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6076         case 9:
6077                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6078         case 8:
6079                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6080         case 7:
6081                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6082         case 6:
6083                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6084         case 5:
6085                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6086         case 4:
6087                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6088         case 3:
6089                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6090         case 2:
6091         case 1:
6092
6093         default:
6094                 break;
6095         };
6096
6097         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6098
6099         return 0;
6100 }
6101
6102 /* Called at device open time to get the chip ready for
6103  * packet processing.  Invoked with tp->lock held.
6104  */
6105 static int tg3_init_hw(struct tg3 *tp)
6106 {
6107         int err;
6108
6109         /* Force the chip into D0. */
6110         err = tg3_set_power_state(tp, 0);
6111         if (err)
6112                 goto out;
6113
6114         tg3_switch_clocks(tp);
6115
6116         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6117
6118         err = tg3_reset_hw(tp);
6119
6120 out:
6121         return err;
6122 }
6123
6124 #define TG3_STAT_ADD32(PSTAT, REG) \
6125 do {    u32 __val = tr32(REG); \
6126         (PSTAT)->low += __val; \
6127         if ((PSTAT)->low < __val) \
6128                 (PSTAT)->high += 1; \
6129 } while (0)
6130
6131 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6132 {
6133         struct tg3_hw_stats *sp = tp->hw_stats;
6134
6135         if (!netif_carrier_ok(tp->dev))
6136                 return;
6137
6138         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6139         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6140         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6141         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6142         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6143         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6144         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6145         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6146         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6147         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6148         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6149         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6150         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6151
6152         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6153         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6154         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6155         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6156         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6157         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6158         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6159         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6160         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6161         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6162         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6163         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6164         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6165         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6166 }
6167
6168 static void tg3_timer(unsigned long __opaque)
6169 {
6170         struct tg3 *tp = (struct tg3 *) __opaque;
6171
6172         spin_lock(&tp->lock);
6173
6174         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6175                 /* All of this garbage is because when using non-tagged
6176                  * IRQ status the mailbox/status_block protocol the chip
6177                  * uses with the cpu is race prone.
6178                  */
6179                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6180                         tw32(GRC_LOCAL_CTRL,
6181                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6182                 } else {
6183                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6184                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6185                 }
6186
6187                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6188                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6189                         spin_unlock(&tp->lock);
6190                         schedule_work(&tp->reset_task);
6191                         return;
6192                 }
6193         }
6194
6195         /* This part only runs once per second. */
6196         if (!--tp->timer_counter) {
6197                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6198                         tg3_periodic_fetch_stats(tp);
6199
6200                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6201                         u32 mac_stat;
6202                         int phy_event;
6203
6204                         mac_stat = tr32(MAC_STATUS);
6205
6206                         phy_event = 0;
6207                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6208                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6209                                         phy_event = 1;
6210                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6211                                 phy_event = 1;
6212
6213                         if (phy_event)
6214                                 tg3_setup_phy(tp, 0);
6215                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6216                         u32 mac_stat = tr32(MAC_STATUS);
6217                         int need_setup = 0;
6218
6219                         if (netif_carrier_ok(tp->dev) &&
6220                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6221                                 need_setup = 1;
6222                         }
6223                         if (! netif_carrier_ok(tp->dev) &&
6224                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6225                                          MAC_STATUS_SIGNAL_DET))) {
6226                                 need_setup = 1;
6227                         }
6228                         if (need_setup) {
6229                                 tw32_f(MAC_MODE,
6230                                      (tp->mac_mode &
6231                                       ~MAC_MODE_PORT_MODE_MASK));
6232                                 udelay(40);
6233                                 tw32_f(MAC_MODE, tp->mac_mode);
6234                                 udelay(40);
6235                                 tg3_setup_phy(tp, 0);
6236                         }
6237                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6238                         tg3_serdes_parallel_detect(tp);
6239
6240                 tp->timer_counter = tp->timer_multiplier;
6241         }
6242
6243         /* Heartbeat is only sent once every 2 seconds.  */
6244         if (!--tp->asf_counter) {
6245                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6246                         u32 val;
6247
6248                         tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_MBOX,
6249                                            FWCMD_NICDRV_ALIVE2);
6250                         tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6251                         /* 5 seconds timeout */
6252                         tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6253                         val = tr32(GRC_RX_CPU_EVENT);
6254                         val |= (1 << 14);
6255                         tw32(GRC_RX_CPU_EVENT, val);
6256                 }
6257                 tp->asf_counter = tp->asf_multiplier;
6258         }
6259
6260         spin_unlock(&tp->lock);
6261
6262         tp->timer.expires = jiffies + tp->timer_offset;
6263         add_timer(&tp->timer);
6264 }
6265
6266 static int tg3_test_interrupt(struct tg3 *tp)
6267 {
6268         struct net_device *dev = tp->dev;
6269         int err, i;
6270         u32 int_mbox = 0;
6271
6272         if (!netif_running(dev))
6273                 return -ENODEV;
6274
6275         tg3_disable_ints(tp);
6276
6277         free_irq(tp->pdev->irq, dev);
6278
6279         err = request_irq(tp->pdev->irq, tg3_test_isr,
6280                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6281         if (err)
6282                 return err;
6283
6284         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6285         tg3_enable_ints(tp);
6286
6287         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6288                HOSTCC_MODE_NOW);
6289
6290         for (i = 0; i < 5; i++) {
6291                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6292                                         TG3_64BIT_REG_LOW);
6293                 if (int_mbox != 0)
6294                         break;
6295                 msleep(10);
6296         }
6297
6298         tg3_disable_ints(tp);
6299
6300         free_irq(tp->pdev->irq, dev);
6301
6302         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6303                 err = request_irq(tp->pdev->irq, tg3_msi,
6304                                   SA_SAMPLE_RANDOM, dev->name, dev);
6305         else {
6306                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6307                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6308                         fn = tg3_interrupt_tagged;
6309                 err = request_irq(tp->pdev->irq, fn,
6310                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6311         }
6312
6313         if (err)
6314                 return err;
6315
6316         if (int_mbox != 0)
6317                 return 0;
6318
6319         return -EIO;
6320 }
6321
6322 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6323  * successfully restored
6324  */
6325 static int tg3_test_msi(struct tg3 *tp)
6326 {
6327         struct net_device *dev = tp->dev;
6328         int err;
6329         u16 pci_cmd;
6330
6331         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6332                 return 0;
6333
6334         /* Turn off SERR reporting in case MSI terminates with Master
6335          * Abort.
6336          */
6337         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6338         pci_write_config_word(tp->pdev, PCI_COMMAND,
6339                               pci_cmd & ~PCI_COMMAND_SERR);
6340
6341         err = tg3_test_interrupt(tp);
6342
6343         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6344
6345         if (!err)
6346                 return 0;
6347
6348         /* other failures */
6349         if (err != -EIO)
6350                 return err;
6351
6352         /* MSI test failed, go back to INTx mode */
6353         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6354                "switching to INTx mode. Please report this failure to "
6355                "the PCI maintainer and include system chipset information.\n",
6356                        tp->dev->name);
6357
6358         free_irq(tp->pdev->irq, dev);
6359         pci_disable_msi(tp->pdev);
6360
6361         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6362
6363         {
6364                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6365                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6366                         fn = tg3_interrupt_tagged;
6367
6368                 err = request_irq(tp->pdev->irq, fn,
6369                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6370         }
6371         if (err)
6372                 return err;
6373
6374         /* Need to reset the chip because the MSI cycle may have terminated
6375          * with Master Abort.
6376          */
6377         tg3_full_lock(tp, 1);
6378
6379         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6380         err = tg3_init_hw(tp);
6381
6382         tg3_full_unlock(tp);
6383
6384         if (err)
6385                 free_irq(tp->pdev->irq, dev);
6386
6387         return err;
6388 }
6389
6390 static int tg3_open(struct net_device *dev)
6391 {
6392         struct tg3 *tp = netdev_priv(dev);
6393         int err;
6394
6395         tg3_full_lock(tp, 0);
6396
6397         tg3_disable_ints(tp);
6398         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6399
6400         tg3_full_unlock(tp);
6401
6402         /* The placement of this call is tied
6403          * to the setup and use of Host TX descriptors.
6404          */
6405         err = tg3_alloc_consistent(tp);
6406         if (err)
6407                 return err;
6408
6409         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6410             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6411             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
6412                 /* All MSI supporting chips should support tagged
6413                  * status.  Assert that this is the case.
6414                  */
6415                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6416                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6417                                "Not using MSI.\n", tp->dev->name);
6418                 } else if (pci_enable_msi(tp->pdev) == 0) {
6419                         u32 msi_mode;
6420
6421                         msi_mode = tr32(MSGINT_MODE);
6422                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6423                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6424                 }
6425         }
6426         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6427                 err = request_irq(tp->pdev->irq, tg3_msi,
6428                                   SA_SAMPLE_RANDOM, dev->name, dev);
6429         else {
6430                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6431                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6432                         fn = tg3_interrupt_tagged;
6433
6434                 err = request_irq(tp->pdev->irq, fn,
6435                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6436         }
6437
6438         if (err) {
6439                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6440                         pci_disable_msi(tp->pdev);
6441                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6442                 }
6443                 tg3_free_consistent(tp);
6444                 return err;
6445         }
6446
6447         tg3_full_lock(tp, 0);
6448
6449         err = tg3_init_hw(tp);
6450         if (err) {
6451                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6452                 tg3_free_rings(tp);
6453         } else {
6454                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6455                         tp->timer_offset = HZ;
6456                 else
6457                         tp->timer_offset = HZ / 10;
6458
6459                 BUG_ON(tp->timer_offset > HZ);
6460                 tp->timer_counter = tp->timer_multiplier =
6461                         (HZ / tp->timer_offset);
6462                 tp->asf_counter = tp->asf_multiplier =
6463                         ((HZ / tp->timer_offset) * 2);
6464
6465                 init_timer(&tp->timer);
6466                 tp->timer.expires = jiffies + tp->timer_offset;
6467                 tp->timer.data = (unsigned long) tp;
6468                 tp->timer.function = tg3_timer;
6469         }
6470
6471         tg3_full_unlock(tp);
6472
6473         if (err) {
6474                 free_irq(tp->pdev->irq, dev);
6475                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6476                         pci_disable_msi(tp->pdev);
6477                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6478                 }
6479                 tg3_free_consistent(tp);
6480                 return err;
6481         }
6482
6483         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6484                 err = tg3_test_msi(tp);
6485
6486                 if (err) {
6487                         tg3_full_lock(tp, 0);
6488
6489                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6490                                 pci_disable_msi(tp->pdev);
6491                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6492                         }
6493                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6494                         tg3_free_rings(tp);
6495                         tg3_free_consistent(tp);
6496
6497                         tg3_full_unlock(tp);
6498
6499                         return err;
6500                 }
6501         }
6502
6503         tg3_full_lock(tp, 0);
6504
6505         add_timer(&tp->timer);
6506         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6507         tg3_enable_ints(tp);
6508
6509         tg3_full_unlock(tp);
6510
6511         netif_start_queue(dev);
6512
6513         return 0;
6514 }
6515
6516 #if 0
6517 /*static*/ void tg3_dump_state(struct tg3 *tp)
6518 {
6519         u32 val32, val32_2, val32_3, val32_4, val32_5;
6520         u16 val16;
6521         int i;
6522
6523         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6524         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6525         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6526                val16, val32);
6527
6528         /* MAC block */
6529         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6530                tr32(MAC_MODE), tr32(MAC_STATUS));
6531         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6532                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6533         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6534                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6535         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6536                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6537
6538         /* Send data initiator control block */
6539         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6540                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6541         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6542                tr32(SNDDATAI_STATSCTRL));
6543
6544         /* Send data completion control block */
6545         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6546
6547         /* Send BD ring selector block */
6548         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6549                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6550
6551         /* Send BD initiator control block */
6552         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6553                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6554
6555         /* Send BD completion control block */
6556         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6557
6558         /* Receive list placement control block */
6559         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6560                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6561         printk("       RCVLPC_STATSCTRL[%08x]\n",
6562                tr32(RCVLPC_STATSCTRL));
6563
6564         /* Receive data and receive BD initiator control block */
6565         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6566                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6567
6568         /* Receive data completion control block */
6569         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6570                tr32(RCVDCC_MODE));
6571
6572         /* Receive BD initiator control block */
6573         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6574                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6575
6576         /* Receive BD completion control block */
6577         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6578                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6579
6580         /* Receive list selector control block */
6581         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6582                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6583
6584         /* Mbuf cluster free block */
6585         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6586                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6587
6588         /* Host coalescing control block */
6589         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6590                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6591         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6592                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6593                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6594         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6595                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6596                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6597         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6598                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6599         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6600                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6601
6602         /* Memory arbiter control block */
6603         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6604                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6605
6606         /* Buffer manager control block */
6607         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6608                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6609         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6610                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6611         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6612                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6613                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6614                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6615
6616         /* Read DMA control block */
6617         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6618                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6619
6620         /* Write DMA control block */
6621         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6622                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6623
6624         /* DMA completion block */
6625         printk("DEBUG: DMAC_MODE[%08x]\n",
6626                tr32(DMAC_MODE));
6627
6628         /* GRC block */
6629         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6630                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6631         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6632                tr32(GRC_LOCAL_CTRL));
6633
6634         /* TG3_BDINFOs */
6635         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6636                tr32(RCVDBDI_JUMBO_BD + 0x0),
6637                tr32(RCVDBDI_JUMBO_BD + 0x4),
6638                tr32(RCVDBDI_JUMBO_BD + 0x8),
6639                tr32(RCVDBDI_JUMBO_BD + 0xc));
6640         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6641                tr32(RCVDBDI_STD_BD + 0x0),
6642                tr32(RCVDBDI_STD_BD + 0x4),
6643                tr32(RCVDBDI_STD_BD + 0x8),
6644                tr32(RCVDBDI_STD_BD + 0xc));
6645         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6646                tr32(RCVDBDI_MINI_BD + 0x0),
6647                tr32(RCVDBDI_MINI_BD + 0x4),
6648                tr32(RCVDBDI_MINI_BD + 0x8),
6649                tr32(RCVDBDI_MINI_BD + 0xc));
6650
6651         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6652         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6653         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6654         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6655         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6656                val32, val32_2, val32_3, val32_4);
6657
6658         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6659         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6660         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6661         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6662         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6663                val32, val32_2, val32_3, val32_4);
6664
6665         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6666         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6667         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6668         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6669         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6670         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6671                val32, val32_2, val32_3, val32_4, val32_5);
6672
6673         /* SW status block */
6674         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6675                tp->hw_status->status,
6676                tp->hw_status->status_tag,
6677                tp->hw_status->rx_jumbo_consumer,
6678                tp->hw_status->rx_consumer,
6679                tp->hw_status->rx_mini_consumer,
6680                tp->hw_status->idx[0].rx_producer,
6681                tp->hw_status->idx[0].tx_consumer);
6682
6683         /* SW statistics block */
6684         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6685                ((u32 *)tp->hw_stats)[0],
6686                ((u32 *)tp->hw_stats)[1],
6687                ((u32 *)tp->hw_stats)[2],
6688                ((u32 *)tp->hw_stats)[3]);
6689
6690         /* Mailboxes */
6691         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6692                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6693                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6694                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6695                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6696
6697         /* NIC side send descriptors. */
6698         for (i = 0; i < 6; i++) {
6699                 unsigned long txd;
6700
6701                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6702                         + (i * sizeof(struct tg3_tx_buffer_desc));
6703                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6704                        i,
6705                        readl(txd + 0x0), readl(txd + 0x4),
6706                        readl(txd + 0x8), readl(txd + 0xc));
6707         }
6708
6709         /* NIC side RX descriptors. */
6710         for (i = 0; i < 6; i++) {
6711                 unsigned long rxd;
6712
6713                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6714                         + (i * sizeof(struct tg3_rx_buffer_desc));
6715                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6716                        i,
6717                        readl(rxd + 0x0), readl(rxd + 0x4),
6718                        readl(rxd + 0x8), readl(rxd + 0xc));
6719                 rxd += (4 * sizeof(u32));
6720                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6721                        i,
6722                        readl(rxd + 0x0), readl(rxd + 0x4),
6723                        readl(rxd + 0x8), readl(rxd + 0xc));
6724         }
6725
6726         for (i = 0; i < 6; i++) {
6727                 unsigned long rxd;
6728
6729                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6730                         + (i * sizeof(struct tg3_rx_buffer_desc));
6731                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6732                        i,
6733                        readl(rxd + 0x0), readl(rxd + 0x4),
6734                        readl(rxd + 0x8), readl(rxd + 0xc));
6735                 rxd += (4 * sizeof(u32));
6736                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6737                        i,
6738                        readl(rxd + 0x0), readl(rxd + 0x4),
6739                        readl(rxd + 0x8), readl(rxd + 0xc));
6740         }
6741 }
6742 #endif
6743
6744 static struct net_device_stats *tg3_get_stats(struct net_device *);
6745 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6746
6747 static int tg3_close(struct net_device *dev)
6748 {
6749         struct tg3 *tp = netdev_priv(dev);
6750
6751         netif_stop_queue(dev);
6752
6753         del_timer_sync(&tp->timer);
6754
6755         tg3_full_lock(tp, 1);
6756 #if 0
6757         tg3_dump_state(tp);
6758 #endif
6759
6760         tg3_disable_ints(tp);
6761
6762         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6763         tg3_free_rings(tp);
6764         tp->tg3_flags &=
6765                 ~(TG3_FLAG_INIT_COMPLETE |
6766                   TG3_FLAG_GOT_SERDES_FLOWCTL);
6767         netif_carrier_off(tp->dev);
6768
6769         tg3_full_unlock(tp);
6770
6771         free_irq(tp->pdev->irq, dev);
6772         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6773                 pci_disable_msi(tp->pdev);
6774                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6775         }
6776
6777         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6778                sizeof(tp->net_stats_prev));
6779         memcpy(&tp->estats_prev, tg3_get_estats(tp),
6780                sizeof(tp->estats_prev));
6781
6782         tg3_free_consistent(tp);
6783
6784         return 0;
6785 }
6786
6787 static inline unsigned long get_stat64(tg3_stat64_t *val)
6788 {
6789         unsigned long ret;
6790
6791 #if (BITS_PER_LONG == 32)
6792         ret = val->low;
6793 #else
6794         ret = ((u64)val->high << 32) | ((u64)val->low);
6795 #endif
6796         return ret;
6797 }
6798
6799 static unsigned long calc_crc_errors(struct tg3 *tp)
6800 {
6801         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6802
6803         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6804             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6805              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6806                 u32 val;
6807
6808                 spin_lock_bh(&tp->lock);
6809                 if (!tg3_readphy(tp, 0x1e, &val)) {
6810                         tg3_writephy(tp, 0x1e, val | 0x8000);
6811                         tg3_readphy(tp, 0x14, &val);
6812                 } else
6813                         val = 0;
6814                 spin_unlock_bh(&tp->lock);
6815
6816                 tp->phy_crc_errors += val;
6817
6818                 return tp->phy_crc_errors;
6819         }
6820
6821         return get_stat64(&hw_stats->rx_fcs_errors);
6822 }
6823
6824 #define ESTAT_ADD(member) \
6825         estats->member =        old_estats->member + \
6826                                 get_stat64(&hw_stats->member)
6827
6828 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6829 {
6830         struct tg3_ethtool_stats *estats = &tp->estats;
6831         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6832         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6833
6834         if (!hw_stats)
6835                 return old_estats;
6836
6837         ESTAT_ADD(rx_octets);
6838         ESTAT_ADD(rx_fragments);
6839         ESTAT_ADD(rx_ucast_packets);
6840         ESTAT_ADD(rx_mcast_packets);
6841         ESTAT_ADD(rx_bcast_packets);
6842         ESTAT_ADD(rx_fcs_errors);
6843         ESTAT_ADD(rx_align_errors);
6844         ESTAT_ADD(rx_xon_pause_rcvd);
6845         ESTAT_ADD(rx_xoff_pause_rcvd);
6846         ESTAT_ADD(rx_mac_ctrl_rcvd);
6847         ESTAT_ADD(rx_xoff_entered);
6848         ESTAT_ADD(rx_frame_too_long_errors);
6849         ESTAT_ADD(rx_jabbers);
6850         ESTAT_ADD(rx_undersize_packets);
6851         ESTAT_ADD(rx_in_length_errors);
6852         ESTAT_ADD(rx_out_length_errors);
6853         ESTAT_ADD(rx_64_or_less_octet_packets);
6854         ESTAT_ADD(rx_65_to_127_octet_packets);
6855         ESTAT_ADD(rx_128_to_255_octet_packets);
6856         ESTAT_ADD(rx_256_to_511_octet_packets);
6857         ESTAT_ADD(rx_512_to_1023_octet_packets);
6858         ESTAT_ADD(rx_1024_to_1522_octet_packets);
6859         ESTAT_ADD(rx_1523_to_2047_octet_packets);
6860         ESTAT_ADD(rx_2048_to_4095_octet_packets);
6861         ESTAT_ADD(rx_4096_to_8191_octet_packets);
6862         ESTAT_ADD(rx_8192_to_9022_octet_packets);
6863
6864         ESTAT_ADD(tx_octets);
6865         ESTAT_ADD(tx_collisions);
6866         ESTAT_ADD(tx_xon_sent);
6867         ESTAT_ADD(tx_xoff_sent);
6868         ESTAT_ADD(tx_flow_control);
6869         ESTAT_ADD(tx_mac_errors);
6870         ESTAT_ADD(tx_single_collisions);
6871         ESTAT_ADD(tx_mult_collisions);
6872         ESTAT_ADD(tx_deferred);
6873         ESTAT_ADD(tx_excessive_collisions);
6874         ESTAT_ADD(tx_late_collisions);
6875         ESTAT_ADD(tx_collide_2times);
6876         ESTAT_ADD(tx_collide_3times);
6877         ESTAT_ADD(tx_collide_4times);
6878         ESTAT_ADD(tx_collide_5times);
6879         ESTAT_ADD(tx_collide_6times);
6880         ESTAT_ADD(tx_collide_7times);
6881         ESTAT_ADD(tx_collide_8times);
6882         ESTAT_ADD(tx_collide_9times);
6883         ESTAT_ADD(tx_collide_10times);
6884         ESTAT_ADD(tx_collide_11times);
6885         ESTAT_ADD(tx_collide_12times);
6886         ESTAT_ADD(tx_collide_13times);
6887         ESTAT_ADD(tx_collide_14times);
6888         ESTAT_ADD(tx_collide_15times);
6889         ESTAT_ADD(tx_ucast_packets);
6890         ESTAT_ADD(tx_mcast_packets);
6891         ESTAT_ADD(tx_bcast_packets);
6892         ESTAT_ADD(tx_carrier_sense_errors);
6893         ESTAT_ADD(tx_discards);
6894         ESTAT_ADD(tx_errors);
6895
6896         ESTAT_ADD(dma_writeq_full);
6897         ESTAT_ADD(dma_write_prioq_full);
6898         ESTAT_ADD(rxbds_empty);
6899         ESTAT_ADD(rx_discards);
6900         ESTAT_ADD(rx_errors);
6901         ESTAT_ADD(rx_threshold_hit);
6902
6903         ESTAT_ADD(dma_readq_full);
6904         ESTAT_ADD(dma_read_prioq_full);
6905         ESTAT_ADD(tx_comp_queue_full);
6906
6907         ESTAT_ADD(ring_set_send_prod_index);
6908         ESTAT_ADD(ring_status_update);
6909         ESTAT_ADD(nic_irqs);
6910         ESTAT_ADD(nic_avoided_irqs);
6911         ESTAT_ADD(nic_tx_threshold_hit);
6912
6913         return estats;
6914 }
6915
6916 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6917 {
6918         struct tg3 *tp = netdev_priv(dev);
6919         struct net_device_stats *stats = &tp->net_stats;
6920         struct net_device_stats *old_stats = &tp->net_stats_prev;
6921         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6922
6923         if (!hw_stats)
6924                 return old_stats;
6925
6926         stats->rx_packets = old_stats->rx_packets +
6927                 get_stat64(&hw_stats->rx_ucast_packets) +
6928                 get_stat64(&hw_stats->rx_mcast_packets) +
6929                 get_stat64(&hw_stats->rx_bcast_packets);
6930
6931         stats->tx_packets = old_stats->tx_packets +
6932                 get_stat64(&hw_stats->tx_ucast_packets) +
6933                 get_stat64(&hw_stats->tx_mcast_packets) +
6934                 get_stat64(&hw_stats->tx_bcast_packets);
6935
6936         stats->rx_bytes = old_stats->rx_bytes +
6937                 get_stat64(&hw_stats->rx_octets);
6938         stats->tx_bytes = old_stats->tx_bytes +
6939                 get_stat64(&hw_stats->tx_octets);
6940
6941         stats->rx_errors = old_stats->rx_errors +
6942                 get_stat64(&hw_stats->rx_errors);
6943         stats->tx_errors = old_stats->tx_errors +
6944                 get_stat64(&hw_stats->tx_errors) +
6945                 get_stat64(&hw_stats->tx_mac_errors) +
6946                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6947                 get_stat64(&hw_stats->tx_discards);
6948
6949         stats->multicast = old_stats->multicast +
6950                 get_stat64(&hw_stats->rx_mcast_packets);
6951         stats->collisions = old_stats->collisions +
6952                 get_stat64(&hw_stats->tx_collisions);
6953
6954         stats->rx_length_errors = old_stats->rx_length_errors +
6955                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6956                 get_stat64(&hw_stats->rx_undersize_packets);
6957
6958         stats->rx_over_errors = old_stats->rx_over_errors +
6959                 get_stat64(&hw_stats->rxbds_empty);
6960         stats->rx_frame_errors = old_stats->rx_frame_errors +
6961                 get_stat64(&hw_stats->rx_align_errors);
6962         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6963                 get_stat64(&hw_stats->tx_discards);
6964         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6965                 get_stat64(&hw_stats->tx_carrier_sense_errors);
6966
6967         stats->rx_crc_errors = old_stats->rx_crc_errors +
6968                 calc_crc_errors(tp);
6969
6970         stats->rx_missed_errors = old_stats->rx_missed_errors +
6971                 get_stat64(&hw_stats->rx_discards);
6972
6973         return stats;
6974 }
6975
6976 static inline u32 calc_crc(unsigned char *buf, int len)
6977 {
6978         u32 reg;
6979         u32 tmp;
6980         int j, k;
6981
6982         reg = 0xffffffff;
6983
6984         for (j = 0; j < len; j++) {
6985                 reg ^= buf[j];
6986
6987                 for (k = 0; k < 8; k++) {
6988                         tmp = reg & 0x01;
6989
6990                         reg >>= 1;
6991
6992                         if (tmp) {
6993                                 reg ^= 0xedb88320;
6994                         }
6995                 }
6996         }
6997
6998         return ~reg;
6999 }
7000
7001 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7002 {
7003         /* accept or reject all multicast frames */
7004         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7005         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7006         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7007         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7008 }
7009
7010 static void __tg3_set_rx_mode(struct net_device *dev)
7011 {
7012         struct tg3 *tp = netdev_priv(dev);
7013         u32 rx_mode;
7014
7015         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7016                                   RX_MODE_KEEP_VLAN_TAG);
7017
7018         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7019          * flag clear.
7020          */
7021 #if TG3_VLAN_TAG_USED
7022         if (!tp->vlgrp &&
7023             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7024                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7025 #else
7026         /* By definition, VLAN is disabled always in this
7027          * case.
7028          */
7029         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7030                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7031 #endif
7032
7033         if (dev->flags & IFF_PROMISC) {
7034                 /* Promiscuous mode. */
7035                 rx_mode |= RX_MODE_PROMISC;
7036         } else if (dev->flags & IFF_ALLMULTI) {
7037                 /* Accept all multicast. */
7038                 tg3_set_multi (tp, 1);
7039         } else if (dev->mc_count < 1) {
7040                 /* Reject all multicast. */
7041                 tg3_set_multi (tp, 0);
7042         } else {
7043                 /* Accept one or more multicast(s). */
7044                 struct dev_mc_list *mclist;
7045                 unsigned int i;
7046                 u32 mc_filter[4] = { 0, };
7047                 u32 regidx;
7048                 u32 bit;
7049                 u32 crc;
7050
7051                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7052                      i++, mclist = mclist->next) {
7053
7054                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7055                         bit = ~crc & 0x7f;
7056                         regidx = (bit & 0x60) >> 5;
7057                         bit &= 0x1f;
7058                         mc_filter[regidx] |= (1 << bit);
7059                 }
7060
7061                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7062                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7063                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7064                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7065         }
7066
7067         if (rx_mode != tp->rx_mode) {
7068                 tp->rx_mode = rx_mode;
7069                 tw32_f(MAC_RX_MODE, rx_mode);
7070                 udelay(10);
7071         }
7072 }
7073
7074 static void tg3_set_rx_mode(struct net_device *dev)
7075 {
7076         struct tg3 *tp = netdev_priv(dev);
7077
7078         tg3_full_lock(tp, 0);
7079         __tg3_set_rx_mode(dev);
7080         tg3_full_unlock(tp);
7081 }
7082
7083 #define TG3_REGDUMP_LEN         (32 * 1024)
7084
7085 static int tg3_get_regs_len(struct net_device *dev)
7086 {
7087         return TG3_REGDUMP_LEN;
7088 }
7089
7090 static void tg3_get_regs(struct net_device *dev,
7091                 struct ethtool_regs *regs, void *_p)
7092 {
7093         u32 *p = _p;
7094         struct tg3 *tp = netdev_priv(dev);
7095         u8 *orig_p = _p;
7096         int i;
7097
7098         regs->version = 0;
7099
7100         memset(p, 0, TG3_REGDUMP_LEN);
7101
7102         tg3_full_lock(tp, 0);
7103
7104 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7105 #define GET_REG32_LOOP(base,len)                \
7106 do {    p = (u32 *)(orig_p + (base));           \
7107         for (i = 0; i < len; i += 4)            \
7108                 __GET_REG32((base) + i);        \
7109 } while (0)
7110 #define GET_REG32_1(reg)                        \
7111 do {    p = (u32 *)(orig_p + (reg));            \
7112         __GET_REG32((reg));                     \
7113 } while (0)
7114
7115         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7116         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7117         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7118         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7119         GET_REG32_1(SNDDATAC_MODE);
7120         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7121         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7122         GET_REG32_1(SNDBDC_MODE);
7123         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7124         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7125         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7126         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7127         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7128         GET_REG32_1(RCVDCC_MODE);
7129         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7130         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7131         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7132         GET_REG32_1(MBFREE_MODE);
7133         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7134         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7135         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7136         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7137         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7138         GET_REG32_LOOP(RX_CPU_BASE, 0x280);
7139         GET_REG32_LOOP(TX_CPU_BASE, 0x280);
7140         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7141         GET_REG32_LOOP(FTQ_RESET, 0x120);
7142         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7143         GET_REG32_1(DMAC_MODE);
7144         GET_REG32_LOOP(GRC_MODE, 0x4c);
7145         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7146                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7147
7148 #undef __GET_REG32
7149 #undef GET_REG32_LOOP
7150 #undef GET_REG32_1
7151
7152         tg3_full_unlock(tp);
7153 }
7154
7155 static int tg3_get_eeprom_len(struct net_device *dev)
7156 {
7157         struct tg3 *tp = netdev_priv(dev);
7158
7159         return tp->nvram_size;
7160 }
7161
7162 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7163
7164 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7165 {
7166         struct tg3 *tp = netdev_priv(dev);
7167         int ret;
7168         u8  *pd;
7169         u32 i, offset, len, val, b_offset, b_count;
7170
7171         offset = eeprom->offset;
7172         len = eeprom->len;
7173         eeprom->len = 0;
7174
7175         eeprom->magic = TG3_EEPROM_MAGIC;
7176
7177         if (offset & 3) {
7178                 /* adjustments to start on required 4 byte boundary */
7179                 b_offset = offset & 3;
7180                 b_count = 4 - b_offset;
7181                 if (b_count > len) {
7182                         /* i.e. offset=1 len=2 */
7183                         b_count = len;
7184                 }
7185                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7186                 if (ret)
7187                         return ret;
7188                 val = cpu_to_le32(val);
7189                 memcpy(data, ((char*)&val) + b_offset, b_count);
7190                 len -= b_count;
7191                 offset += b_count;
7192                 eeprom->len += b_count;
7193         }
7194
7195         /* read bytes upto the last 4 byte boundary */
7196         pd = &data[eeprom->len];
7197         for (i = 0; i < (len - (len & 3)); i += 4) {
7198                 ret = tg3_nvram_read(tp, offset + i, &val);
7199                 if (ret) {
7200                         eeprom->len += i;
7201                         return ret;
7202                 }
7203                 val = cpu_to_le32(val);
7204                 memcpy(pd + i, &val, 4);
7205         }
7206         eeprom->len += i;
7207
7208         if (len & 3) {
7209                 /* read last bytes not ending on 4 byte boundary */
7210                 pd = &data[eeprom->len];
7211                 b_count = len & 3;
7212                 b_offset = offset + len - b_count;
7213                 ret = tg3_nvram_read(tp, b_offset, &val);
7214                 if (ret)
7215                         return ret;
7216                 val = cpu_to_le32(val);
7217                 memcpy(pd, ((char*)&val), b_count);
7218                 eeprom->len += b_count;
7219         }
7220         return 0;
7221 }
7222
7223 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7224
7225 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7226 {
7227         struct tg3 *tp = netdev_priv(dev);
7228         int ret;
7229         u32 offset, len, b_offset, odd_len, start, end;
7230         u8 *buf;
7231
7232         if (eeprom->magic != TG3_EEPROM_MAGIC)
7233                 return -EINVAL;
7234
7235         offset = eeprom->offset;
7236         len = eeprom->len;
7237
7238         if ((b_offset = (offset & 3))) {
7239                 /* adjustments to start on required 4 byte boundary */
7240                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7241                 if (ret)
7242                         return ret;
7243                 start = cpu_to_le32(start);
7244                 len += b_offset;
7245                 offset &= ~3;
7246                 if (len < 4)
7247                         len = 4;
7248         }
7249
7250         odd_len = 0;
7251         if (len & 3) {
7252                 /* adjustments to end on required 4 byte boundary */
7253                 odd_len = 1;
7254                 len = (len + 3) & ~3;
7255                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7256                 if (ret)
7257                         return ret;
7258                 end = cpu_to_le32(end);
7259         }
7260
7261         buf = data;
7262         if (b_offset || odd_len) {
7263                 buf = kmalloc(len, GFP_KERNEL);
7264                 if (buf == 0)
7265                         return -ENOMEM;
7266                 if (b_offset)
7267                         memcpy(buf, &start, 4);
7268                 if (odd_len)
7269                         memcpy(buf+len-4, &end, 4);
7270                 memcpy(buf + b_offset, data, eeprom->len);
7271         }
7272
7273         ret = tg3_nvram_write_block(tp, offset, len, buf);
7274
7275         if (buf != data)
7276                 kfree(buf);
7277
7278         return ret;
7279 }
7280
7281 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7282 {
7283         struct tg3 *tp = netdev_priv(dev);
7284
7285         cmd->supported = (SUPPORTED_Autoneg);
7286
7287         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7288                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7289                                    SUPPORTED_1000baseT_Full);
7290
7291         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
7292                 cmd->supported |= (SUPPORTED_100baseT_Half |
7293                                   SUPPORTED_100baseT_Full |
7294                                   SUPPORTED_10baseT_Half |
7295                                   SUPPORTED_10baseT_Full |
7296                                   SUPPORTED_MII);
7297         else
7298                 cmd->supported |= SUPPORTED_FIBRE;
7299
7300         cmd->advertising = tp->link_config.advertising;
7301         if (netif_running(dev)) {
7302                 cmd->speed = tp->link_config.active_speed;
7303                 cmd->duplex = tp->link_config.active_duplex;
7304         }
7305         cmd->port = 0;
7306         cmd->phy_address = PHY_ADDR;
7307         cmd->transceiver = 0;
7308         cmd->autoneg = tp->link_config.autoneg;
7309         cmd->maxtxpkt = 0;
7310         cmd->maxrxpkt = 0;
7311         return 0;
7312 }
7313
7314 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7315 {
7316         struct tg3 *tp = netdev_priv(dev);
7317
7318         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7319                 /* These are the only valid advertisement bits allowed.  */
7320                 if (cmd->autoneg == AUTONEG_ENABLE &&
7321                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7322                                           ADVERTISED_1000baseT_Full |
7323                                           ADVERTISED_Autoneg |
7324                                           ADVERTISED_FIBRE)))
7325                         return -EINVAL;
7326                 /* Fiber can only do SPEED_1000.  */
7327                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7328                          (cmd->speed != SPEED_1000))
7329                         return -EINVAL;
7330         /* Copper cannot force SPEED_1000.  */
7331         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7332                    (cmd->speed == SPEED_1000))
7333                 return -EINVAL;
7334         else if ((cmd->speed == SPEED_1000) &&
7335                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7336                 return -EINVAL;
7337
7338         tg3_full_lock(tp, 0);
7339
7340         tp->link_config.autoneg = cmd->autoneg;
7341         if (cmd->autoneg == AUTONEG_ENABLE) {
7342                 tp->link_config.advertising = cmd->advertising;
7343                 tp->link_config.speed = SPEED_INVALID;
7344                 tp->link_config.duplex = DUPLEX_INVALID;
7345         } else {
7346                 tp->link_config.advertising = 0;
7347                 tp->link_config.speed = cmd->speed;
7348                 tp->link_config.duplex = cmd->duplex;
7349         }
7350
7351         if (netif_running(dev))
7352                 tg3_setup_phy(tp, 1);
7353
7354         tg3_full_unlock(tp);
7355
7356         return 0;
7357 }
7358
7359 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7360 {
7361         struct tg3 *tp = netdev_priv(dev);
7362
7363         strcpy(info->driver, DRV_MODULE_NAME);
7364         strcpy(info->version, DRV_MODULE_VERSION);
7365         strcpy(info->bus_info, pci_name(tp->pdev));
7366 }
7367
7368 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7369 {
7370         struct tg3 *tp = netdev_priv(dev);
7371
7372         wol->supported = WAKE_MAGIC;
7373         wol->wolopts = 0;
7374         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7375                 wol->wolopts = WAKE_MAGIC;
7376         memset(&wol->sopass, 0, sizeof(wol->sopass));
7377 }
7378
7379 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7380 {
7381         struct tg3 *tp = netdev_priv(dev);
7382
7383         if (wol->wolopts & ~WAKE_MAGIC)
7384                 return -EINVAL;
7385         if ((wol->wolopts & WAKE_MAGIC) &&
7386             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7387             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7388                 return -EINVAL;
7389
7390         spin_lock_bh(&tp->lock);
7391         if (wol->wolopts & WAKE_MAGIC)
7392                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7393         else
7394                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7395         spin_unlock_bh(&tp->lock);
7396
7397         return 0;
7398 }
7399
7400 static u32 tg3_get_msglevel(struct net_device *dev)
7401 {
7402         struct tg3 *tp = netdev_priv(dev);
7403         return tp->msg_enable;
7404 }
7405
7406 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7407 {
7408         struct tg3 *tp = netdev_priv(dev);
7409         tp->msg_enable = value;
7410 }
7411
7412 #if TG3_TSO_SUPPORT != 0
7413 static int tg3_set_tso(struct net_device *dev, u32 value)
7414 {
7415         struct tg3 *tp = netdev_priv(dev);
7416
7417         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7418                 if (value)
7419                         return -EINVAL;
7420                 return 0;
7421         }
7422         return ethtool_op_set_tso(dev, value);
7423 }
7424 #endif
7425
7426 static int tg3_nway_reset(struct net_device *dev)
7427 {
7428         struct tg3 *tp = netdev_priv(dev);
7429         u32 bmcr;
7430         int r;
7431
7432         if (!netif_running(dev))
7433                 return -EAGAIN;
7434
7435         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7436                 return -EINVAL;
7437
7438         spin_lock_bh(&tp->lock);
7439         r = -EINVAL;
7440         tg3_readphy(tp, MII_BMCR, &bmcr);
7441         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7442             ((bmcr & BMCR_ANENABLE) ||
7443              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7444                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7445                                            BMCR_ANENABLE);
7446                 r = 0;
7447         }
7448         spin_unlock_bh(&tp->lock);
7449
7450         return r;
7451 }
7452
7453 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7454 {
7455         struct tg3 *tp = netdev_priv(dev);
7456
7457         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7458         ering->rx_mini_max_pending = 0;
7459         ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7460
7461         ering->rx_pending = tp->rx_pending;
7462         ering->rx_mini_pending = 0;
7463         ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7464         ering->tx_pending = tp->tx_pending;
7465 }
7466
7467 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7468 {
7469         struct tg3 *tp = netdev_priv(dev);
7470         int irq_sync = 0;
7471
7472         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7473             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7474             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7475                 return -EINVAL;
7476
7477         if (netif_running(dev)) {
7478                 tg3_netif_stop(tp);
7479                 irq_sync = 1;
7480         }
7481
7482         tg3_full_lock(tp, irq_sync);
7483
7484         tp->rx_pending = ering->rx_pending;
7485
7486         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7487             tp->rx_pending > 63)
7488                 tp->rx_pending = 63;
7489         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7490         tp->tx_pending = ering->tx_pending;
7491
7492         if (netif_running(dev)) {
7493                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7494                 tg3_init_hw(tp);
7495                 tg3_netif_start(tp);
7496         }
7497
7498         tg3_full_unlock(tp);
7499
7500         return 0;
7501 }
7502
7503 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7504 {
7505         struct tg3 *tp = netdev_priv(dev);
7506
7507         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7508         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7509         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7510 }
7511
7512 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7513 {
7514         struct tg3 *tp = netdev_priv(dev);
7515         int irq_sync = 0;
7516
7517         if (netif_running(dev)) {
7518                 tg3_netif_stop(tp);
7519                 irq_sync = 1;
7520         }
7521
7522         tg3_full_lock(tp, irq_sync);
7523
7524         if (epause->autoneg)
7525                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7526         else
7527                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7528         if (epause->rx_pause)
7529                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7530         else
7531                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7532         if (epause->tx_pause)
7533                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7534         else
7535                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7536
7537         if (netif_running(dev)) {
7538                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7539                 tg3_init_hw(tp);
7540                 tg3_netif_start(tp);
7541         }
7542
7543         tg3_full_unlock(tp);
7544
7545         return 0;
7546 }
7547
7548 static u32 tg3_get_rx_csum(struct net_device *dev)
7549 {
7550         struct tg3 *tp = netdev_priv(dev);
7551         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7552 }
7553
7554 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7555 {
7556         struct tg3 *tp = netdev_priv(dev);
7557
7558         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7559                 if (data != 0)
7560                         return -EINVAL;
7561                 return 0;
7562         }
7563
7564         spin_lock_bh(&tp->lock);
7565         if (data)
7566                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7567         else
7568                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7569         spin_unlock_bh(&tp->lock);
7570
7571         return 0;
7572 }
7573
7574 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7575 {
7576         struct tg3 *tp = netdev_priv(dev);
7577
7578         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7579                 if (data != 0)
7580                         return -EINVAL;
7581                 return 0;
7582         }
7583
7584         if (data)
7585                 dev->features |= NETIF_F_IP_CSUM;
7586         else
7587                 dev->features &= ~NETIF_F_IP_CSUM;
7588
7589         return 0;
7590 }
7591
7592 static int tg3_get_stats_count (struct net_device *dev)
7593 {
7594         return TG3_NUM_STATS;
7595 }
7596
7597 static int tg3_get_test_count (struct net_device *dev)
7598 {
7599         return TG3_NUM_TEST;
7600 }
7601
7602 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7603 {
7604         switch (stringset) {
7605         case ETH_SS_STATS:
7606                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7607                 break;
7608         case ETH_SS_TEST:
7609                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7610                 break;
7611         default:
7612                 WARN_ON(1);     /* we need a WARN() */
7613                 break;
7614         }
7615 }
7616
7617 static int tg3_phys_id(struct net_device *dev, u32 data)
7618 {
7619         struct tg3 *tp = netdev_priv(dev);
7620         int i;
7621
7622         if (!netif_running(tp->dev))
7623                 return -EAGAIN;
7624
7625         if (data == 0)
7626                 data = 2;
7627
7628         for (i = 0; i < (data * 2); i++) {
7629                 if ((i % 2) == 0)
7630                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7631                                            LED_CTRL_1000MBPS_ON |
7632                                            LED_CTRL_100MBPS_ON |
7633                                            LED_CTRL_10MBPS_ON |
7634                                            LED_CTRL_TRAFFIC_OVERRIDE |
7635                                            LED_CTRL_TRAFFIC_BLINK |
7636                                            LED_CTRL_TRAFFIC_LED);
7637
7638                 else
7639                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7640                                            LED_CTRL_TRAFFIC_OVERRIDE);
7641
7642                 if (msleep_interruptible(500))
7643                         break;
7644         }
7645         tw32(MAC_LED_CTRL, tp->led_ctrl);
7646         return 0;
7647 }
7648
7649 static void tg3_get_ethtool_stats (struct net_device *dev,
7650                                    struct ethtool_stats *estats, u64 *tmp_stats)
7651 {
7652         struct tg3 *tp = netdev_priv(dev);
7653         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7654 }
7655
7656 #define NVRAM_TEST_SIZE 0x100
7657
7658 static int tg3_test_nvram(struct tg3 *tp)
7659 {
7660         u32 *buf, csum;
7661         int i, j, err = 0;
7662
7663         buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7664         if (buf == NULL)
7665                 return -ENOMEM;
7666
7667         for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7668                 u32 val;
7669
7670                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7671                         break;
7672                 buf[j] = cpu_to_le32(val);
7673         }
7674         if (i < NVRAM_TEST_SIZE)
7675                 goto out;
7676
7677         err = -EIO;
7678         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7679                 goto out;
7680
7681         /* Bootstrap checksum at offset 0x10 */
7682         csum = calc_crc((unsigned char *) buf, 0x10);
7683         if(csum != cpu_to_le32(buf[0x10/4]))
7684                 goto out;
7685
7686         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7687         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7688         if (csum != cpu_to_le32(buf[0xfc/4]))
7689                  goto out;
7690
7691         err = 0;
7692
7693 out:
7694         kfree(buf);
7695         return err;
7696 }
7697
7698 #define TG3_SERDES_TIMEOUT_SEC  2
7699 #define TG3_COPPER_TIMEOUT_SEC  6
7700
7701 static int tg3_test_link(struct tg3 *tp)
7702 {
7703         int i, max;
7704
7705         if (!netif_running(tp->dev))
7706                 return -ENODEV;
7707
7708         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
7709                 max = TG3_SERDES_TIMEOUT_SEC;
7710         else
7711                 max = TG3_COPPER_TIMEOUT_SEC;
7712
7713         for (i = 0; i < max; i++) {
7714                 if (netif_carrier_ok(tp->dev))
7715                         return 0;
7716
7717                 if (msleep_interruptible(1000))
7718                         break;
7719         }
7720
7721         return -EIO;
7722 }
7723
7724 /* Only test the commonly used registers */
7725 static int tg3_test_registers(struct tg3 *tp)
7726 {
7727         int i, is_5705;
7728         u32 offset, read_mask, write_mask, val, save_val, read_val;
7729         static struct {
7730                 u16 offset;
7731                 u16 flags;
7732 #define TG3_FL_5705     0x1
7733 #define TG3_FL_NOT_5705 0x2
7734 #define TG3_FL_NOT_5788 0x4
7735                 u32 read_mask;
7736                 u32 write_mask;
7737         } reg_tbl[] = {
7738                 /* MAC Control Registers */
7739                 { MAC_MODE, TG3_FL_NOT_5705,
7740                         0x00000000, 0x00ef6f8c },
7741                 { MAC_MODE, TG3_FL_5705,
7742                         0x00000000, 0x01ef6b8c },
7743                 { MAC_STATUS, TG3_FL_NOT_5705,
7744                         0x03800107, 0x00000000 },
7745                 { MAC_STATUS, TG3_FL_5705,
7746                         0x03800100, 0x00000000 },
7747                 { MAC_ADDR_0_HIGH, 0x0000,
7748                         0x00000000, 0x0000ffff },
7749                 { MAC_ADDR_0_LOW, 0x0000,
7750                         0x00000000, 0xffffffff },
7751                 { MAC_RX_MTU_SIZE, 0x0000,
7752                         0x00000000, 0x0000ffff },
7753                 { MAC_TX_MODE, 0x0000,
7754                         0x00000000, 0x00000070 },
7755                 { MAC_TX_LENGTHS, 0x0000,
7756                         0x00000000, 0x00003fff },
7757                 { MAC_RX_MODE, TG3_FL_NOT_5705,
7758                         0x00000000, 0x000007fc },
7759                 { MAC_RX_MODE, TG3_FL_5705,
7760                         0x00000000, 0x000007dc },
7761                 { MAC_HASH_REG_0, 0x0000,
7762                         0x00000000, 0xffffffff },
7763                 { MAC_HASH_REG_1, 0x0000,
7764                         0x00000000, 0xffffffff },
7765                 { MAC_HASH_REG_2, 0x0000,
7766                         0x00000000, 0xffffffff },
7767                 { MAC_HASH_REG_3, 0x0000,
7768                         0x00000000, 0xffffffff },
7769
7770                 /* Receive Data and Receive BD Initiator Control Registers. */
7771                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7772                         0x00000000, 0xffffffff },
7773                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7774                         0x00000000, 0xffffffff },
7775                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7776                         0x00000000, 0x00000003 },
7777                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7778                         0x00000000, 0xffffffff },
7779                 { RCVDBDI_STD_BD+0, 0x0000,
7780                         0x00000000, 0xffffffff },
7781                 { RCVDBDI_STD_BD+4, 0x0000,
7782                         0x00000000, 0xffffffff },
7783                 { RCVDBDI_STD_BD+8, 0x0000,
7784                         0x00000000, 0xffff0002 },
7785                 { RCVDBDI_STD_BD+0xc, 0x0000,
7786                         0x00000000, 0xffffffff },
7787
7788                 /* Receive BD Initiator Control Registers. */
7789                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7790                         0x00000000, 0xffffffff },
7791                 { RCVBDI_STD_THRESH, TG3_FL_5705,
7792                         0x00000000, 0x000003ff },
7793                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7794                         0x00000000, 0xffffffff },
7795
7796                 /* Host Coalescing Control Registers. */
7797                 { HOSTCC_MODE, TG3_FL_NOT_5705,
7798                         0x00000000, 0x00000004 },
7799                 { HOSTCC_MODE, TG3_FL_5705,
7800                         0x00000000, 0x000000f6 },
7801                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7802                         0x00000000, 0xffffffff },
7803                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7804                         0x00000000, 0x000003ff },
7805                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7806                         0x00000000, 0xffffffff },
7807                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7808                         0x00000000, 0x000003ff },
7809                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7810                         0x00000000, 0xffffffff },
7811                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7812                         0x00000000, 0x000000ff },
7813                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7814                         0x00000000, 0xffffffff },
7815                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7816                         0x00000000, 0x000000ff },
7817                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7818                         0x00000000, 0xffffffff },
7819                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7820                         0x00000000, 0xffffffff },
7821                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7822                         0x00000000, 0xffffffff },
7823                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7824                         0x00000000, 0x000000ff },
7825                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7826                         0x00000000, 0xffffffff },
7827                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7828                         0x00000000, 0x000000ff },
7829                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7830                         0x00000000, 0xffffffff },
7831                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7832                         0x00000000, 0xffffffff },
7833                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7834                         0x00000000, 0xffffffff },
7835                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7836                         0x00000000, 0xffffffff },
7837                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7838                         0x00000000, 0xffffffff },
7839                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7840                         0xffffffff, 0x00000000 },
7841                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7842                         0xffffffff, 0x00000000 },
7843
7844                 /* Buffer Manager Control Registers. */
7845                 { BUFMGR_MB_POOL_ADDR, 0x0000,
7846                         0x00000000, 0x007fff80 },
7847                 { BUFMGR_MB_POOL_SIZE, 0x0000,
7848                         0x00000000, 0x007fffff },
7849                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7850                         0x00000000, 0x0000003f },
7851                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7852                         0x00000000, 0x000001ff },
7853                 { BUFMGR_MB_HIGH_WATER, 0x0000,
7854                         0x00000000, 0x000001ff },
7855                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7856                         0xffffffff, 0x00000000 },
7857                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7858                         0xffffffff, 0x00000000 },
7859
7860                 /* Mailbox Registers */
7861                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7862                         0x00000000, 0x000001ff },
7863                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7864                         0x00000000, 0x000001ff },
7865                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7866                         0x00000000, 0x000007ff },
7867                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7868                         0x00000000, 0x000001ff },
7869
7870                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7871         };
7872
7873         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7874                 is_5705 = 1;
7875         else
7876                 is_5705 = 0;
7877
7878         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7879                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7880                         continue;
7881
7882                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7883                         continue;
7884
7885                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7886                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
7887                         continue;
7888
7889                 offset = (u32) reg_tbl[i].offset;
7890                 read_mask = reg_tbl[i].read_mask;
7891                 write_mask = reg_tbl[i].write_mask;
7892
7893                 /* Save the original register content */
7894                 save_val = tr32(offset);
7895
7896                 /* Determine the read-only value. */
7897                 read_val = save_val & read_mask;
7898
7899                 /* Write zero to the register, then make sure the read-only bits
7900                  * are not changed and the read/write bits are all zeros.
7901                  */
7902                 tw32(offset, 0);
7903
7904                 val = tr32(offset);
7905
7906                 /* Test the read-only and read/write bits. */
7907                 if (((val & read_mask) != read_val) || (val & write_mask))
7908                         goto out;
7909
7910                 /* Write ones to all the bits defined by RdMask and WrMask, then
7911                  * make sure the read-only bits are not changed and the
7912                  * read/write bits are all ones.
7913                  */
7914                 tw32(offset, read_mask | write_mask);
7915
7916                 val = tr32(offset);
7917
7918                 /* Test the read-only bits. */
7919                 if ((val & read_mask) != read_val)
7920                         goto out;
7921
7922                 /* Test the read/write bits. */
7923                 if ((val & write_mask) != write_mask)
7924                         goto out;
7925
7926                 tw32(offset, save_val);
7927         }
7928
7929         return 0;
7930
7931 out:
7932         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7933         tw32(offset, save_val);
7934         return -EIO;
7935 }
7936
7937 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7938 {
7939         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7940         int i;
7941         u32 j;
7942
7943         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7944                 for (j = 0; j < len; j += 4) {
7945                         u32 val;
7946
7947                         tg3_write_mem(tp, offset + j, test_pattern[i]);
7948                         tg3_read_mem(tp, offset + j, &val);
7949                         if (val != test_pattern[i])
7950                                 return -EIO;
7951                 }
7952         }
7953         return 0;
7954 }
7955
7956 static int tg3_test_memory(struct tg3 *tp)
7957 {
7958         static struct mem_entry {
7959                 u32 offset;
7960                 u32 len;
7961         } mem_tbl_570x[] = {
7962                 { 0x00000000, 0x01000},
7963                 { 0x00002000, 0x1c000},
7964                 { 0xffffffff, 0x00000}
7965         }, mem_tbl_5705[] = {
7966                 { 0x00000100, 0x0000c},
7967                 { 0x00000200, 0x00008},
7968                 { 0x00000b50, 0x00400},
7969                 { 0x00004000, 0x00800},
7970                 { 0x00006000, 0x01000},
7971                 { 0x00008000, 0x02000},
7972                 { 0x00010000, 0x0e000},
7973                 { 0xffffffff, 0x00000}
7974         };
7975         struct mem_entry *mem_tbl;
7976         int err = 0;
7977         int i;
7978
7979         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7980                 mem_tbl = mem_tbl_5705;
7981         else
7982                 mem_tbl = mem_tbl_570x;
7983
7984         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7985                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7986                     mem_tbl[i].len)) != 0)
7987                         break;
7988         }
7989
7990         return err;
7991 }
7992
7993 #define TG3_MAC_LOOPBACK        0
7994 #define TG3_PHY_LOOPBACK        1
7995
7996 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
7997 {
7998         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
7999         u32 desc_idx;
8000         struct sk_buff *skb, *rx_skb;
8001         u8 *tx_data;
8002         dma_addr_t map;
8003         int num_pkts, tx_len, rx_len, i, err;
8004         struct tg3_rx_buffer_desc *desc;
8005
8006         if (loopback_mode == TG3_MAC_LOOPBACK) {
8007                 /* HW errata - mac loopback fails in some cases on 5780.
8008                  * Normal traffic and PHY loopback are not affected by
8009                  * errata.
8010                  */
8011                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8012                         return 0;
8013
8014                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8015                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8016                            MAC_MODE_PORT_MODE_GMII;
8017                 tw32(MAC_MODE, mac_mode);
8018         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8019                 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8020                                            BMCR_SPEED1000);
8021                 udelay(40);
8022                 /* reset to prevent losing 1st rx packet intermittently */
8023                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8024                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8025                         udelay(10);
8026                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8027                 }
8028                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8029                            MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8030                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8031                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8032                 tw32(MAC_MODE, mac_mode);
8033         }
8034         else
8035                 return -EINVAL;
8036
8037         err = -EIO;
8038
8039         tx_len = 1514;
8040         skb = dev_alloc_skb(tx_len);
8041         tx_data = skb_put(skb, tx_len);
8042         memcpy(tx_data, tp->dev->dev_addr, 6);
8043         memset(tx_data + 6, 0x0, 8);
8044
8045         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8046
8047         for (i = 14; i < tx_len; i++)
8048                 tx_data[i] = (u8) (i & 0xff);
8049
8050         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8051
8052         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8053              HOSTCC_MODE_NOW);
8054
8055         udelay(10);
8056
8057         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8058
8059         num_pkts = 0;
8060
8061         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8062
8063         tp->tx_prod++;
8064         num_pkts++;
8065
8066         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8067                      tp->tx_prod);
8068         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8069
8070         udelay(10);
8071
8072         for (i = 0; i < 10; i++) {
8073                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8074                        HOSTCC_MODE_NOW);
8075
8076                 udelay(10);
8077
8078                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8079                 rx_idx = tp->hw_status->idx[0].rx_producer;
8080                 if ((tx_idx == tp->tx_prod) &&
8081                     (rx_idx == (rx_start_idx + num_pkts)))
8082                         break;
8083         }
8084
8085         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8086         dev_kfree_skb(skb);
8087
8088         if (tx_idx != tp->tx_prod)
8089                 goto out;
8090
8091         if (rx_idx != rx_start_idx + num_pkts)
8092                 goto out;
8093
8094         desc = &tp->rx_rcb[rx_start_idx];
8095         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8096         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8097         if (opaque_key != RXD_OPAQUE_RING_STD)
8098                 goto out;
8099
8100         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8101             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8102                 goto out;
8103
8104         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8105         if (rx_len != tx_len)
8106                 goto out;
8107
8108         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8109
8110         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8111         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8112
8113         for (i = 14; i < tx_len; i++) {
8114                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8115                         goto out;
8116         }
8117         err = 0;
8118
8119         /* tg3_free_rings will unmap and free the rx_skb */
8120 out:
8121         return err;
8122 }
8123
8124 #define TG3_MAC_LOOPBACK_FAILED         1
8125 #define TG3_PHY_LOOPBACK_FAILED         2
8126 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8127                                          TG3_PHY_LOOPBACK_FAILED)
8128
8129 static int tg3_test_loopback(struct tg3 *tp)
8130 {
8131         int err = 0;
8132
8133         if (!netif_running(tp->dev))
8134                 return TG3_LOOPBACK_FAILED;
8135
8136         tg3_reset_hw(tp);
8137
8138         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8139                 err |= TG3_MAC_LOOPBACK_FAILED;
8140         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8141                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8142                         err |= TG3_PHY_LOOPBACK_FAILED;
8143         }
8144
8145         return err;
8146 }
8147
8148 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8149                           u64 *data)
8150 {
8151         struct tg3 *tp = netdev_priv(dev);
8152
8153         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8154
8155         if (tg3_test_nvram(tp) != 0) {
8156                 etest->flags |= ETH_TEST_FL_FAILED;
8157                 data[0] = 1;
8158         }
8159         if (tg3_test_link(tp) != 0) {
8160                 etest->flags |= ETH_TEST_FL_FAILED;
8161                 data[1] = 1;
8162         }
8163         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8164                 int irq_sync = 0;
8165
8166                 if (netif_running(dev)) {
8167                         tg3_netif_stop(tp);
8168                         irq_sync = 1;
8169                 }
8170
8171                 tg3_full_lock(tp, irq_sync);
8172
8173                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8174                 tg3_nvram_lock(tp);
8175                 tg3_halt_cpu(tp, RX_CPU_BASE);
8176                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8177                         tg3_halt_cpu(tp, TX_CPU_BASE);
8178                 tg3_nvram_unlock(tp);
8179
8180                 if (tg3_test_registers(tp) != 0) {
8181                         etest->flags |= ETH_TEST_FL_FAILED;
8182                         data[2] = 1;
8183                 }
8184                 if (tg3_test_memory(tp) != 0) {
8185                         etest->flags |= ETH_TEST_FL_FAILED;
8186                         data[3] = 1;
8187                 }
8188                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8189                         etest->flags |= ETH_TEST_FL_FAILED;
8190
8191                 tg3_full_unlock(tp);
8192
8193                 if (tg3_test_interrupt(tp) != 0) {
8194                         etest->flags |= ETH_TEST_FL_FAILED;
8195                         data[5] = 1;
8196                 }
8197
8198                 tg3_full_lock(tp, 0);
8199
8200                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8201                 if (netif_running(dev)) {
8202                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8203                         tg3_init_hw(tp);
8204                         tg3_netif_start(tp);
8205                 }
8206
8207                 tg3_full_unlock(tp);
8208         }
8209 }
8210
8211 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8212 {
8213         struct mii_ioctl_data *data = if_mii(ifr);
8214         struct tg3 *tp = netdev_priv(dev);
8215         int err;
8216
8217         switch(cmd) {
8218         case SIOCGMIIPHY:
8219                 data->phy_id = PHY_ADDR;
8220
8221                 /* fallthru */
8222         case SIOCGMIIREG: {
8223                 u32 mii_regval;
8224
8225                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8226                         break;                  /* We have no PHY */
8227
8228                 spin_lock_bh(&tp->lock);
8229                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8230                 spin_unlock_bh(&tp->lock);
8231
8232                 data->val_out = mii_regval;
8233
8234                 return err;
8235         }
8236
8237         case SIOCSMIIREG:
8238                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8239                         break;                  /* We have no PHY */
8240
8241                 if (!capable(CAP_NET_ADMIN))
8242                         return -EPERM;
8243
8244                 spin_lock_bh(&tp->lock);
8245                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8246                 spin_unlock_bh(&tp->lock);
8247
8248                 return err;
8249
8250         default:
8251                 /* do nothing */
8252                 break;
8253         }
8254         return -EOPNOTSUPP;
8255 }
8256
8257 #if TG3_VLAN_TAG_USED
8258 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8259 {
8260         struct tg3 *tp = netdev_priv(dev);
8261
8262         tg3_full_lock(tp, 0);
8263
8264         tp->vlgrp = grp;
8265
8266         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8267         __tg3_set_rx_mode(dev);
8268
8269         tg3_full_unlock(tp);
8270 }
8271
8272 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8273 {
8274         struct tg3 *tp = netdev_priv(dev);
8275
8276         tg3_full_lock(tp, 0);
8277         if (tp->vlgrp)
8278                 tp->vlgrp->vlan_devices[vid] = NULL;
8279         tg3_full_unlock(tp);
8280 }
8281 #endif
8282
8283 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8284 {
8285         struct tg3 *tp = netdev_priv(dev);
8286
8287         memcpy(ec, &tp->coal, sizeof(*ec));
8288         return 0;
8289 }
8290
8291 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8292 {
8293         struct tg3 *tp = netdev_priv(dev);
8294         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8295         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8296
8297         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8298                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8299                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8300                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8301                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8302         }
8303
8304         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8305             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8306             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8307             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8308             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8309             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8310             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8311             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8312             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8313             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8314                 return -EINVAL;
8315
8316         /* No rx interrupts will be generated if both are zero */
8317         if ((ec->rx_coalesce_usecs == 0) &&
8318             (ec->rx_max_coalesced_frames == 0))
8319                 return -EINVAL;
8320
8321         /* No tx interrupts will be generated if both are zero */
8322         if ((ec->tx_coalesce_usecs == 0) &&
8323             (ec->tx_max_coalesced_frames == 0))
8324                 return -EINVAL;
8325
8326         /* Only copy relevant parameters, ignore all others. */
8327         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8328         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8329         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8330         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8331         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8332         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8333         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8334         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8335         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8336
8337         if (netif_running(dev)) {
8338                 tg3_full_lock(tp, 0);
8339                 __tg3_set_coalesce(tp, &tp->coal);
8340                 tg3_full_unlock(tp);
8341         }
8342         return 0;
8343 }
8344
8345 static struct ethtool_ops tg3_ethtool_ops = {
8346         .get_settings           = tg3_get_settings,
8347         .set_settings           = tg3_set_settings,
8348         .get_drvinfo            = tg3_get_drvinfo,
8349         .get_regs_len           = tg3_get_regs_len,
8350         .get_regs               = tg3_get_regs,
8351         .get_wol                = tg3_get_wol,
8352         .set_wol                = tg3_set_wol,
8353         .get_msglevel           = tg3_get_msglevel,
8354         .set_msglevel           = tg3_set_msglevel,
8355         .nway_reset             = tg3_nway_reset,
8356         .get_link               = ethtool_op_get_link,
8357         .get_eeprom_len         = tg3_get_eeprom_len,
8358         .get_eeprom             = tg3_get_eeprom,
8359         .set_eeprom             = tg3_set_eeprom,
8360         .get_ringparam          = tg3_get_ringparam,
8361         .set_ringparam          = tg3_set_ringparam,
8362         .get_pauseparam         = tg3_get_pauseparam,
8363         .set_pauseparam         = tg3_set_pauseparam,
8364         .get_rx_csum            = tg3_get_rx_csum,
8365         .set_rx_csum            = tg3_set_rx_csum,
8366         .get_tx_csum            = ethtool_op_get_tx_csum,
8367         .set_tx_csum            = tg3_set_tx_csum,
8368         .get_sg                 = ethtool_op_get_sg,
8369         .set_sg                 = ethtool_op_set_sg,
8370 #if TG3_TSO_SUPPORT != 0
8371         .get_tso                = ethtool_op_get_tso,
8372         .set_tso                = tg3_set_tso,
8373 #endif
8374         .self_test_count        = tg3_get_test_count,
8375         .self_test              = tg3_self_test,
8376         .get_strings            = tg3_get_strings,
8377         .phys_id                = tg3_phys_id,
8378         .get_stats_count        = tg3_get_stats_count,
8379         .get_ethtool_stats      = tg3_get_ethtool_stats,
8380         .get_coalesce           = tg3_get_coalesce,
8381         .set_coalesce           = tg3_set_coalesce,
8382         .get_perm_addr          = ethtool_op_get_perm_addr,
8383 };
8384
8385 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8386 {
8387         u32 cursize, val;
8388
8389         tp->nvram_size = EEPROM_CHIP_SIZE;
8390
8391         if (tg3_nvram_read(tp, 0, &val) != 0)
8392                 return;
8393
8394         if (swab32(val) != TG3_EEPROM_MAGIC)
8395                 return;
8396
8397         /*
8398          * Size the chip by reading offsets at increasing powers of two.
8399          * When we encounter our validation signature, we know the addressing
8400          * has wrapped around, and thus have our chip size.
8401          */
8402         cursize = 0x800;
8403
8404         while (cursize < tp->nvram_size) {
8405                 if (tg3_nvram_read(tp, cursize, &val) != 0)
8406                         return;
8407
8408                 if (swab32(val) == TG3_EEPROM_MAGIC)
8409                         break;
8410
8411                 cursize <<= 1;
8412         }
8413
8414         tp->nvram_size = cursize;
8415 }
8416
8417 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8418 {
8419         u32 val;
8420
8421         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8422                 if (val != 0) {
8423                         tp->nvram_size = (val >> 16) * 1024;
8424                         return;
8425                 }
8426         }
8427         tp->nvram_size = 0x20000;
8428 }
8429
8430 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8431 {
8432         u32 nvcfg1;
8433
8434         nvcfg1 = tr32(NVRAM_CFG1);
8435         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8436                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8437         }
8438         else {
8439                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8440                 tw32(NVRAM_CFG1, nvcfg1);
8441         }
8442
8443         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8444             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8445                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8446                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8447                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8448                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8449                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8450                                 break;
8451                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8452                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8453                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8454                                 break;
8455                         case FLASH_VENDOR_ATMEL_EEPROM:
8456                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8457                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8458                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8459                                 break;
8460                         case FLASH_VENDOR_ST:
8461                                 tp->nvram_jedecnum = JEDEC_ST;
8462                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8463                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8464                                 break;
8465                         case FLASH_VENDOR_SAIFUN:
8466                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
8467                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8468                                 break;
8469                         case FLASH_VENDOR_SST_SMALL:
8470                         case FLASH_VENDOR_SST_LARGE:
8471                                 tp->nvram_jedecnum = JEDEC_SST;
8472                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8473                                 break;
8474                 }
8475         }
8476         else {
8477                 tp->nvram_jedecnum = JEDEC_ATMEL;
8478                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8479                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8480         }
8481 }
8482
8483 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8484 {
8485         u32 nvcfg1;
8486
8487         nvcfg1 = tr32(NVRAM_CFG1);
8488
8489         /* NVRAM protection for TPM */
8490         if (nvcfg1 & (1 << 27))
8491                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8492
8493         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8494                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8495                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8496                         tp->nvram_jedecnum = JEDEC_ATMEL;
8497                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8498                         break;
8499                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8500                         tp->nvram_jedecnum = JEDEC_ATMEL;
8501                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8502                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8503                         break;
8504                 case FLASH_5752VENDOR_ST_M45PE10:
8505                 case FLASH_5752VENDOR_ST_M45PE20:
8506                 case FLASH_5752VENDOR_ST_M45PE40:
8507                         tp->nvram_jedecnum = JEDEC_ST;
8508                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8509                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8510                         break;
8511         }
8512
8513         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8514                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8515                         case FLASH_5752PAGE_SIZE_256:
8516                                 tp->nvram_pagesize = 256;
8517                                 break;
8518                         case FLASH_5752PAGE_SIZE_512:
8519                                 tp->nvram_pagesize = 512;
8520                                 break;
8521                         case FLASH_5752PAGE_SIZE_1K:
8522                                 tp->nvram_pagesize = 1024;
8523                                 break;
8524                         case FLASH_5752PAGE_SIZE_2K:
8525                                 tp->nvram_pagesize = 2048;
8526                                 break;
8527                         case FLASH_5752PAGE_SIZE_4K:
8528                                 tp->nvram_pagesize = 4096;
8529                                 break;
8530                         case FLASH_5752PAGE_SIZE_264:
8531                                 tp->nvram_pagesize = 264;
8532                                 break;
8533                 }
8534         }
8535         else {
8536                 /* For eeprom, set pagesize to maximum eeprom size */
8537                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8538
8539                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8540                 tw32(NVRAM_CFG1, nvcfg1);
8541         }
8542 }
8543
8544 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
8545 static void __devinit tg3_nvram_init(struct tg3 *tp)
8546 {
8547         int j;
8548
8549         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8550                 return;
8551
8552         tw32_f(GRC_EEPROM_ADDR,
8553              (EEPROM_ADDR_FSM_RESET |
8554               (EEPROM_DEFAULT_CLOCK_PERIOD <<
8555                EEPROM_ADDR_CLKPERD_SHIFT)));
8556
8557         /* XXX schedule_timeout() ... */
8558         for (j = 0; j < 100; j++)
8559                 udelay(10);
8560
8561         /* Enable seeprom accesses. */
8562         tw32_f(GRC_LOCAL_CTRL,
8563              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8564         udelay(100);
8565
8566         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8567             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8568                 tp->tg3_flags |= TG3_FLAG_NVRAM;
8569
8570                 tg3_nvram_lock(tp);
8571                 tg3_enable_nvram_access(tp);
8572
8573                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8574                         tg3_get_5752_nvram_info(tp);
8575                 else
8576                         tg3_get_nvram_info(tp);
8577
8578                 tg3_get_nvram_size(tp);
8579
8580                 tg3_disable_nvram_access(tp);
8581                 tg3_nvram_unlock(tp);
8582
8583         } else {
8584                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8585
8586                 tg3_get_eeprom_size(tp);
8587         }
8588 }
8589
8590 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8591                                         u32 offset, u32 *val)
8592 {
8593         u32 tmp;
8594         int i;
8595
8596         if (offset > EEPROM_ADDR_ADDR_MASK ||
8597             (offset % 4) != 0)
8598                 return -EINVAL;
8599
8600         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8601                                         EEPROM_ADDR_DEVID_MASK |
8602                                         EEPROM_ADDR_READ);
8603         tw32(GRC_EEPROM_ADDR,
8604              tmp |
8605              (0 << EEPROM_ADDR_DEVID_SHIFT) |
8606              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8607               EEPROM_ADDR_ADDR_MASK) |
8608              EEPROM_ADDR_READ | EEPROM_ADDR_START);
8609
8610         for (i = 0; i < 10000; i++) {
8611                 tmp = tr32(GRC_EEPROM_ADDR);
8612
8613                 if (tmp & EEPROM_ADDR_COMPLETE)
8614                         break;
8615                 udelay(100);
8616         }
8617         if (!(tmp & EEPROM_ADDR_COMPLETE))
8618                 return -EBUSY;
8619
8620         *val = tr32(GRC_EEPROM_DATA);
8621         return 0;
8622 }
8623
8624 #define NVRAM_CMD_TIMEOUT 10000
8625
8626 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8627 {
8628         int i;
8629
8630         tw32(NVRAM_CMD, nvram_cmd);
8631         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8632                 udelay(10);
8633                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8634                         udelay(10);
8635                         break;
8636                 }
8637         }
8638         if (i == NVRAM_CMD_TIMEOUT) {
8639                 return -EBUSY;
8640         }
8641         return 0;
8642 }
8643
8644 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8645 {
8646         int ret;
8647
8648         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8649                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8650                 return -EINVAL;
8651         }
8652
8653         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8654                 return tg3_nvram_read_using_eeprom(tp, offset, val);
8655
8656         if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8657                 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8658                 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8659
8660                 offset = ((offset / tp->nvram_pagesize) <<
8661                           ATMEL_AT45DB0X1B_PAGE_POS) +
8662                         (offset % tp->nvram_pagesize);
8663         }
8664
8665         if (offset > NVRAM_ADDR_MSK)
8666                 return -EINVAL;
8667
8668         tg3_nvram_lock(tp);
8669
8670         tg3_enable_nvram_access(tp);
8671
8672         tw32(NVRAM_ADDR, offset);
8673         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8674                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8675
8676         if (ret == 0)
8677                 *val = swab32(tr32(NVRAM_RDDATA));
8678
8679         tg3_disable_nvram_access(tp);
8680
8681         tg3_nvram_unlock(tp);
8682
8683         return ret;
8684 }
8685
8686 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8687                                     u32 offset, u32 len, u8 *buf)
8688 {
8689         int i, j, rc = 0;
8690         u32 val;
8691
8692         for (i = 0; i < len; i += 4) {
8693                 u32 addr, data;
8694
8695                 addr = offset + i;
8696
8697                 memcpy(&data, buf + i, 4);
8698
8699                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8700
8701                 val = tr32(GRC_EEPROM_ADDR);
8702                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8703
8704                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8705                         EEPROM_ADDR_READ);
8706                 tw32(GRC_EEPROM_ADDR, val |
8707                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
8708                         (addr & EEPROM_ADDR_ADDR_MASK) |
8709                         EEPROM_ADDR_START |
8710                         EEPROM_ADDR_WRITE);
8711
8712                 for (j = 0; j < 10000; j++) {
8713                         val = tr32(GRC_EEPROM_ADDR);
8714
8715                         if (val & EEPROM_ADDR_COMPLETE)
8716                                 break;
8717                         udelay(100);
8718                 }
8719                 if (!(val & EEPROM_ADDR_COMPLETE)) {
8720                         rc = -EBUSY;
8721                         break;
8722                 }
8723         }
8724
8725         return rc;
8726 }
8727
8728 /* offset and length are dword aligned */
8729 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8730                 u8 *buf)
8731 {
8732         int ret = 0;
8733         u32 pagesize = tp->nvram_pagesize;
8734         u32 pagemask = pagesize - 1;
8735         u32 nvram_cmd;
8736         u8 *tmp;
8737
8738         tmp = kmalloc(pagesize, GFP_KERNEL);
8739         if (tmp == NULL)
8740                 return -ENOMEM;
8741
8742         while (len) {
8743                 int j;
8744                 u32 phy_addr, page_off, size;
8745
8746                 phy_addr = offset & ~pagemask;
8747
8748                 for (j = 0; j < pagesize; j += 4) {
8749                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
8750                                                 (u32 *) (tmp + j))))
8751                                 break;
8752                 }
8753                 if (ret)
8754                         break;
8755
8756                 page_off = offset & pagemask;
8757                 size = pagesize;
8758                 if (len < size)
8759                         size = len;
8760
8761                 len -= size;
8762
8763                 memcpy(tmp + page_off, buf, size);
8764
8765                 offset = offset + (pagesize - page_off);
8766
8767                 /* Nvram lock released by tg3_nvram_read() above,
8768                  * so need to get it again.
8769                  */
8770                 tg3_nvram_lock(tp);
8771                 tg3_enable_nvram_access(tp);
8772
8773                 /*
8774                  * Before we can erase the flash page, we need
8775                  * to issue a special "write enable" command.
8776                  */
8777                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8778
8779                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8780                         break;
8781
8782                 /* Erase the target page */
8783                 tw32(NVRAM_ADDR, phy_addr);
8784
8785                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8786                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8787
8788                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8789                         break;
8790
8791                 /* Issue another write enable to start the write. */
8792                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8793
8794                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8795                         break;
8796
8797                 for (j = 0; j < pagesize; j += 4) {
8798                         u32 data;
8799
8800                         data = *((u32 *) (tmp + j));
8801                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
8802
8803                         tw32(NVRAM_ADDR, phy_addr + j);
8804
8805                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8806                                 NVRAM_CMD_WR;
8807
8808                         if (j == 0)
8809                                 nvram_cmd |= NVRAM_CMD_FIRST;
8810                         else if (j == (pagesize - 4))
8811                                 nvram_cmd |= NVRAM_CMD_LAST;
8812
8813                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8814                                 break;
8815                 }
8816                 if (ret)
8817                         break;
8818         }
8819
8820         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8821         tg3_nvram_exec_cmd(tp, nvram_cmd);
8822
8823         kfree(tmp);
8824
8825         return ret;
8826 }
8827
8828 /* offset and length are dword aligned */
8829 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8830                 u8 *buf)
8831 {
8832         int i, ret = 0;
8833
8834         for (i = 0; i < len; i += 4, offset += 4) {
8835                 u32 data, page_off, phy_addr, nvram_cmd;
8836
8837                 memcpy(&data, buf + i, 4);
8838                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8839
8840                 page_off = offset % tp->nvram_pagesize;
8841
8842                 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8843                         (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8844
8845                         phy_addr = ((offset / tp->nvram_pagesize) <<
8846                                     ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8847                 }
8848                 else {
8849                         phy_addr = offset;
8850                 }
8851
8852                 tw32(NVRAM_ADDR, phy_addr);
8853
8854                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8855
8856                 if ((page_off == 0) || (i == 0))
8857                         nvram_cmd |= NVRAM_CMD_FIRST;
8858                 else if (page_off == (tp->nvram_pagesize - 4))
8859                         nvram_cmd |= NVRAM_CMD_LAST;
8860
8861                 if (i == (len - 4))
8862                         nvram_cmd |= NVRAM_CMD_LAST;
8863
8864                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
8865                     (tp->nvram_jedecnum == JEDEC_ST) &&
8866                     (nvram_cmd & NVRAM_CMD_FIRST)) {
8867
8868                         if ((ret = tg3_nvram_exec_cmd(tp,
8869                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8870                                 NVRAM_CMD_DONE)))
8871
8872                                 break;
8873                 }
8874                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8875                         /* We always do complete word writes to eeprom. */
8876                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8877                 }
8878
8879                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8880                         break;
8881         }
8882         return ret;
8883 }
8884
8885 /* offset and length are dword aligned */
8886 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8887 {
8888         int ret;
8889
8890         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8891                 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8892                 return -EINVAL;
8893         }
8894
8895         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8896                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8897                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
8898                 udelay(40);
8899         }
8900
8901         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8902                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8903         }
8904         else {
8905                 u32 grc_mode;
8906
8907                 tg3_nvram_lock(tp);
8908
8909                 tg3_enable_nvram_access(tp);
8910                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8911                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
8912                         tw32(NVRAM_WRITE1, 0x406);
8913
8914                 grc_mode = tr32(GRC_MODE);
8915                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8916
8917                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8918                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8919
8920                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
8921                                 buf);
8922                 }
8923                 else {
8924                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8925                                 buf);
8926                 }
8927
8928                 grc_mode = tr32(GRC_MODE);
8929                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8930
8931                 tg3_disable_nvram_access(tp);
8932                 tg3_nvram_unlock(tp);
8933         }
8934
8935         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8936                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8937                 udelay(40);
8938         }
8939
8940         return ret;
8941 }
8942
8943 struct subsys_tbl_ent {
8944         u16 subsys_vendor, subsys_devid;
8945         u32 phy_id;
8946 };
8947
8948 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8949         /* Broadcom boards. */
8950         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8951         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8952         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8953         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
8954         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8955         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8956         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
8957         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8958         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8959         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8960         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8961
8962         /* 3com boards. */
8963         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8964         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8965         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
8966         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8967         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8968
8969         /* DELL boards. */
8970         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8971         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8972         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8973         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8974
8975         /* Compaq boards. */
8976         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8977         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8978         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
8979         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8980         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8981
8982         /* IBM boards. */
8983         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8984 };
8985
8986 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8987 {
8988         int i;
8989
8990         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8991                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8992                      tp->pdev->subsystem_vendor) &&
8993                     (subsys_id_to_phy_id[i].subsys_devid ==
8994                      tp->pdev->subsystem_device))
8995                         return &subsys_id_to_phy_id[i];
8996         }
8997         return NULL;
8998 }
8999
9000 /* Since this function may be called in D3-hot power state during
9001  * tg3_init_one(), only config cycles are allowed.
9002  */
9003 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9004 {
9005         u32 val;
9006
9007         /* Make sure register accesses (indirect or otherwise)
9008          * will function correctly.
9009          */
9010         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9011                                tp->misc_host_ctrl);
9012
9013         tp->phy_id = PHY_ID_INVALID;
9014         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9015
9016         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9017         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9018                 u32 nic_cfg, led_cfg;
9019                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9020                 int eeprom_phy_serdes = 0;
9021
9022                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9023                 tp->nic_sram_data_cfg = nic_cfg;
9024
9025                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9026                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9027                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9028                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9029                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9030                     (ver > 0) && (ver < 0x100))
9031                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9032
9033                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9034                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9035                         eeprom_phy_serdes = 1;
9036
9037                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9038                 if (nic_phy_id != 0) {
9039                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9040                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9041
9042                         eeprom_phy_id  = (id1 >> 16) << 10;
9043                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
9044                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
9045                 } else
9046                         eeprom_phy_id = 0;
9047
9048                 tp->phy_id = eeprom_phy_id;
9049                 if (eeprom_phy_serdes) {
9050                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
9051                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9052                         else
9053                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9054                 }
9055
9056                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9057                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9058                                     SHASTA_EXT_LED_MODE_MASK);
9059                 else
9060                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9061
9062                 switch (led_cfg) {
9063                 default:
9064                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9065                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9066                         break;
9067
9068                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9069                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9070                         break;
9071
9072                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9073                         tp->led_ctrl = LED_CTRL_MODE_MAC;
9074
9075                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9076                          * read on some older 5700/5701 bootcode.
9077                          */
9078                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9079                             ASIC_REV_5700 ||
9080                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
9081                             ASIC_REV_5701)
9082                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9083
9084                         break;
9085
9086                 case SHASTA_EXT_LED_SHARED:
9087                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
9088                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9089                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9090                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9091                                                  LED_CTRL_MODE_PHY_2);
9092                         break;
9093
9094                 case SHASTA_EXT_LED_MAC:
9095                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9096                         break;
9097
9098                 case SHASTA_EXT_LED_COMBO:
9099                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
9100                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9101                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9102                                                  LED_CTRL_MODE_PHY_2);
9103                         break;
9104
9105                 };
9106
9107                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9108                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9109                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9110                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9111
9112                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9113                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9114                     (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
9115                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9116
9117                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9118                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9119                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9120                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9121                 }
9122                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9123                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9124
9125                 if (cfg2 & (1 << 17))
9126                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9127
9128                 /* serdes signal pre-emphasis in register 0x590 set by */
9129                 /* bootcode if bit 18 is set */
9130                 if (cfg2 & (1 << 18))
9131                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9132         }
9133 }
9134
9135 static int __devinit tg3_phy_probe(struct tg3 *tp)
9136 {
9137         u32 hw_phy_id_1, hw_phy_id_2;
9138         u32 hw_phy_id, hw_phy_id_masked;
9139         int err;
9140
9141         /* Reading the PHY ID register can conflict with ASF
9142          * firwmare access to the PHY hardware.
9143          */
9144         err = 0;
9145         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9146                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9147         } else {
9148                 /* Now read the physical PHY_ID from the chip and verify
9149                  * that it is sane.  If it doesn't look good, we fall back
9150                  * to either the hard-coded table based PHY_ID and failing
9151                  * that the value found in the eeprom area.
9152                  */
9153                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9154                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9155
9156                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
9157                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9158                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
9159
9160                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9161         }
9162
9163         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9164                 tp->phy_id = hw_phy_id;
9165                 if (hw_phy_id_masked == PHY_ID_BCM8002)
9166                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9167                 else
9168                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9169         } else {
9170                 if (tp->phy_id != PHY_ID_INVALID) {
9171                         /* Do nothing, phy ID already set up in
9172                          * tg3_get_eeprom_hw_cfg().
9173                          */
9174                 } else {
9175                         struct subsys_tbl_ent *p;
9176
9177                         /* No eeprom signature?  Try the hardcoded
9178                          * subsys device table.
9179                          */
9180                         p = lookup_by_subsys(tp);
9181                         if (!p)
9182                                 return -ENODEV;
9183
9184                         tp->phy_id = p->phy_id;
9185                         if (!tp->phy_id ||
9186                             tp->phy_id == PHY_ID_BCM8002)
9187                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9188                 }
9189         }
9190
9191         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9192             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9193                 u32 bmsr, adv_reg, tg3_ctrl;
9194
9195                 tg3_readphy(tp, MII_BMSR, &bmsr);
9196                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9197                     (bmsr & BMSR_LSTATUS))
9198                         goto skip_phy_reset;
9199
9200                 err = tg3_phy_reset(tp);
9201                 if (err)
9202                         return err;
9203
9204                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9205                            ADVERTISE_100HALF | ADVERTISE_100FULL |
9206                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9207                 tg3_ctrl = 0;
9208                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9209                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9210                                     MII_TG3_CTRL_ADV_1000_FULL);
9211                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9212                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9213                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9214                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
9215                 }
9216
9217                 if (!tg3_copper_is_advertising_all(tp)) {
9218                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9219
9220                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9221                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9222
9223                         tg3_writephy(tp, MII_BMCR,
9224                                      BMCR_ANENABLE | BMCR_ANRESTART);
9225                 }
9226                 tg3_phy_set_wirespeed(tp);
9227
9228                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9229                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9230                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9231         }
9232
9233 skip_phy_reset:
9234         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9235                 err = tg3_init_5401phy_dsp(tp);
9236                 if (err)
9237                         return err;
9238         }
9239
9240         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9241                 err = tg3_init_5401phy_dsp(tp);
9242         }
9243
9244         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9245                 tp->link_config.advertising =
9246                         (ADVERTISED_1000baseT_Half |
9247                          ADVERTISED_1000baseT_Full |
9248                          ADVERTISED_Autoneg |
9249                          ADVERTISED_FIBRE);
9250         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9251                 tp->link_config.advertising &=
9252                         ~(ADVERTISED_1000baseT_Half |
9253                           ADVERTISED_1000baseT_Full);
9254
9255         return err;
9256 }
9257
9258 static void __devinit tg3_read_partno(struct tg3 *tp)
9259 {
9260         unsigned char vpd_data[256];
9261         int i;
9262
9263         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9264                 /* Sun decided not to put the necessary bits in the
9265                  * NVRAM of their onboard tg3 parts :(
9266                  */
9267                 strcpy(tp->board_part_number, "Sun 570X");
9268                 return;
9269         }
9270
9271         for (i = 0; i < 256; i += 4) {
9272                 u32 tmp;
9273
9274                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9275                         goto out_not_found;
9276
9277                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
9278                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
9279                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9280                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9281         }
9282
9283         /* Now parse and find the part number. */
9284         for (i = 0; i < 256; ) {
9285                 unsigned char val = vpd_data[i];
9286                 int block_end;
9287
9288                 if (val == 0x82 || val == 0x91) {
9289                         i = (i + 3 +
9290                              (vpd_data[i + 1] +
9291                               (vpd_data[i + 2] << 8)));
9292                         continue;
9293                 }
9294
9295                 if (val != 0x90)
9296                         goto out_not_found;
9297
9298                 block_end = (i + 3 +
9299                              (vpd_data[i + 1] +
9300                               (vpd_data[i + 2] << 8)));
9301                 i += 3;
9302                 while (i < block_end) {
9303                         if (vpd_data[i + 0] == 'P' &&
9304                             vpd_data[i + 1] == 'N') {
9305                                 int partno_len = vpd_data[i + 2];
9306
9307                                 if (partno_len > 24)
9308                                         goto out_not_found;
9309
9310                                 memcpy(tp->board_part_number,
9311                                        &vpd_data[i + 3],
9312                                        partno_len);
9313
9314                                 /* Success. */
9315                                 return;
9316                         }
9317                 }
9318
9319                 /* Part number not found. */
9320                 goto out_not_found;
9321         }
9322
9323 out_not_found:
9324         strcpy(tp->board_part_number, "none");
9325 }
9326
9327 #ifdef CONFIG_SPARC64
9328 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9329 {
9330         struct pci_dev *pdev = tp->pdev;
9331         struct pcidev_cookie *pcp = pdev->sysdata;
9332
9333         if (pcp != NULL) {
9334                 int node = pcp->prom_node;
9335                 u32 venid;
9336                 int err;
9337
9338                 err = prom_getproperty(node, "subsystem-vendor-id",
9339                                        (char *) &venid, sizeof(venid));
9340                 if (err == 0 || err == -1)
9341                         return 0;
9342                 if (venid == PCI_VENDOR_ID_SUN)
9343                         return 1;
9344         }
9345         return 0;
9346 }
9347 #endif
9348
9349 static int __devinit tg3_get_invariants(struct tg3 *tp)
9350 {
9351         static struct pci_device_id write_reorder_chipsets[] = {
9352                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9353                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9354                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
9355                              PCI_DEVICE_ID_VIA_8385_0) },
9356                 { },
9357         };
9358         u32 misc_ctrl_reg;
9359         u32 cacheline_sz_reg;
9360         u32 pci_state_reg, grc_misc_cfg;
9361         u32 val;
9362         u16 pci_cmd;
9363         int err;
9364
9365 #ifdef CONFIG_SPARC64
9366         if (tg3_is_sun_570X(tp))
9367                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9368 #endif
9369
9370         /* Force memory write invalidate off.  If we leave it on,
9371          * then on 5700_BX chips we have to enable a workaround.
9372          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
9373          * to match the cacheline size.  The Broadcom driver have this
9374          * workaround but turns MWI off all the times so never uses
9375          * it.  This seems to suggest that the workaround is insufficient.
9376          */
9377         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9378         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
9379         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9380
9381         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
9382          * has the register indirect write enable bit set before
9383          * we try to access any of the MMIO registers.  It is also
9384          * critical that the PCI-X hw workaround situation is decided
9385          * before that as well.
9386          */
9387         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9388                               &misc_ctrl_reg);
9389
9390         tp->pci_chip_rev_id = (misc_ctrl_reg >>
9391                                MISC_HOST_CTRL_CHIPREV_SHIFT);
9392
9393         /* Wrong chip ID in 5752 A0. This code can be removed later
9394          * as A0 is not in production.
9395          */
9396         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
9397                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
9398
9399         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
9400          * we need to disable memory and use config. cycles
9401          * only to access all registers. The 5702/03 chips
9402          * can mistakenly decode the special cycles from the
9403          * ICH chipsets as memory write cycles, causing corruption
9404          * of register and memory space. Only certain ICH bridges
9405          * will drive special cycles with non-zero data during the
9406          * address phase which can fall within the 5703's address
9407          * range. This is not an ICH bug as the PCI spec allows
9408          * non-zero address during special cycles. However, only
9409          * these ICH bridges are known to drive non-zero addresses
9410          * during special cycles.
9411          *
9412          * Since special cycles do not cross PCI bridges, we only
9413          * enable this workaround if the 5703 is on the secondary
9414          * bus of these ICH bridges.
9415          */
9416         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
9417             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
9418                 static struct tg3_dev_id {
9419                         u32     vendor;
9420                         u32     device;
9421                         u32     rev;
9422                 } ich_chipsets[] = {
9423                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
9424                           PCI_ANY_ID },
9425                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
9426                           PCI_ANY_ID },
9427                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
9428                           0xa },
9429                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
9430                           PCI_ANY_ID },
9431                         { },
9432                 };
9433                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
9434                 struct pci_dev *bridge = NULL;
9435
9436                 while (pci_id->vendor != 0) {
9437                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
9438                                                 bridge);
9439                         if (!bridge) {
9440                                 pci_id++;
9441                                 continue;
9442                         }
9443                         if (pci_id->rev != PCI_ANY_ID) {
9444                                 u8 rev;
9445
9446                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
9447                                                      &rev);
9448                                 if (rev > pci_id->rev)
9449                                         continue;
9450                         }
9451                         if (bridge->subordinate &&
9452                             (bridge->subordinate->number ==
9453                              tp->pdev->bus->number)) {
9454
9455                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
9456                                 pci_dev_put(bridge);
9457                                 break;
9458                         }
9459                 }
9460         }
9461
9462         /* Find msi capability. */
9463         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
9464             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9465                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
9466                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
9467         }
9468
9469         /* Initialize misc host control in PCI block. */
9470         tp->misc_host_ctrl |= (misc_ctrl_reg &
9471                                MISC_HOST_CTRL_CHIPREV);
9472         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9473                                tp->misc_host_ctrl);
9474
9475         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9476                               &cacheline_sz_reg);
9477
9478         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
9479         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
9480         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
9481         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
9482
9483         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
9484             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
9485             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
9486                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
9487
9488         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
9489             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
9490                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
9491
9492         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9493                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
9494
9495         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9496             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9497             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9498                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9499
9500         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9501                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9502
9503         /* If we have an AMD 762 or VIA K8T800 chipset, write
9504          * reordering to the mailbox registers done by the host
9505          * controller can cause major troubles.  We read back from
9506          * every mailbox register write to force the writes to be
9507          * posted to the chip in order.
9508          */
9509         if (pci_dev_present(write_reorder_chipsets) &&
9510             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9511                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9512
9513         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9514             tp->pci_lat_timer < 64) {
9515                 tp->pci_lat_timer = 64;
9516
9517                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
9518                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
9519                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
9520                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
9521
9522                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9523                                        cacheline_sz_reg);
9524         }
9525
9526         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9527                               &pci_state_reg);
9528
9529         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
9530                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
9531
9532                 /* If this is a 5700 BX chipset, and we are in PCI-X
9533                  * mode, enable register write workaround.
9534                  *
9535                  * The workaround is to use indirect register accesses
9536                  * for all chip writes not to mailbox registers.
9537                  */
9538                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
9539                         u32 pm_reg;
9540                         u16 pci_cmd;
9541
9542                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9543
9544                         /* The chip can have it's power management PCI config
9545                          * space registers clobbered due to this bug.
9546                          * So explicitly force the chip into D0 here.
9547                          */
9548                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9549                                               &pm_reg);
9550                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
9551                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9552                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9553                                                pm_reg);
9554
9555                         /* Also, force SERR#/PERR# in PCI command. */
9556                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9557                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
9558                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9559                 }
9560         }
9561
9562         /* 5700 BX chips need to have their TX producer index mailboxes
9563          * written twice to workaround a bug.
9564          */
9565         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9566                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9567
9568         /* Back to back register writes can cause problems on this chip,
9569          * the workaround is to read back all reg writes except those to
9570          * mailbox regs.  See tg3_write_indirect_reg32().
9571          *
9572          * PCI Express 5750_A0 rev chips need this workaround too.
9573          */
9574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9575             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
9576              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
9577                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
9578
9579         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
9580                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
9581         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
9582                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
9583
9584         /* Chip-specific fixup from Broadcom driver */
9585         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
9586             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
9587                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
9588                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
9589         }
9590
9591         /* Default fast path register access methods */
9592         tp->read32 = tg3_read32;
9593         tp->write32 = tg3_write32;
9594         tp->read32_mbox = tg3_read32;
9595         tp->write32_mbox = tg3_write32;
9596         tp->write32_tx_mbox = tg3_write32;
9597         tp->write32_rx_mbox = tg3_write32;
9598
9599         /* Various workaround register access methods */
9600         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
9601                 tp->write32 = tg3_write_indirect_reg32;
9602         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
9603                 tp->write32 = tg3_write_flush_reg32;
9604
9605         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
9606             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
9607                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9608                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
9609                         tp->write32_rx_mbox = tg3_write_flush_reg32;
9610         }
9611
9612         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
9613                 tp->read32 = tg3_read_indirect_reg32;
9614                 tp->write32 = tg3_write_indirect_reg32;
9615                 tp->read32_mbox = tg3_read_indirect_mbox;
9616                 tp->write32_mbox = tg3_write_indirect_mbox;
9617                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
9618                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
9619
9620                 iounmap(tp->regs);
9621                 tp->regs = NULL;
9622
9623                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9624                 pci_cmd &= ~PCI_COMMAND_MEMORY;
9625                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9626         }
9627
9628         /* Get eeprom hw config before calling tg3_set_power_state().
9629          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
9630          * determined before calling tg3_set_power_state() so that
9631          * we know whether or not to switch out of Vaux power.
9632          * When the flag is set, it means that GPIO1 is used for eeprom
9633          * write protect and also implies that it is a LOM where GPIOs
9634          * are not used to switch power.
9635          */
9636         tg3_get_eeprom_hw_cfg(tp);
9637
9638         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9639          * GPIO1 driven high will bring 5700's external PHY out of reset.
9640          * It is also used as eeprom write protect on LOMs.
9641          */
9642         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9643         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9644             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9645                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9646                                        GRC_LCLCTRL_GPIO_OUTPUT1);
9647         /* Unused GPIO3 must be driven as output on 5752 because there
9648          * are no pull-up resistors on unused GPIO pins.
9649          */
9650         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9651                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
9652
9653         /* Force the chip into D0. */
9654         err = tg3_set_power_state(tp, 0);
9655         if (err) {
9656                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9657                        pci_name(tp->pdev));
9658                 return err;
9659         }
9660
9661         /* 5700 B0 chips do not support checksumming correctly due
9662          * to hardware bugs.
9663          */
9664         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9665                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9666
9667         /* Pseudo-header checksum is done by hardware logic and not
9668          * the offload processers, so make the chip do the pseudo-
9669          * header checksums on receive.  For transmit it is more
9670          * convenient to do the pseudo-header checksum in software
9671          * as Linux does that on transmit for us in all cases.
9672          */
9673         tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9674         tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9675
9676         /* Derive initial jumbo mode from MTU assigned in
9677          * ether_setup() via the alloc_etherdev() call
9678          */
9679         if (tp->dev->mtu > ETH_DATA_LEN &&
9680             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
9681                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
9682
9683         /* Determine WakeOnLan speed to use. */
9684         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9685             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9686             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9687             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9688                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9689         } else {
9690                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9691         }
9692
9693         /* A few boards don't want Ethernet@WireSpeed phy feature */
9694         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9695             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9696              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9697              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
9698             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9699                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9700
9701         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9702             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9703                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9704         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9705                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9706
9707         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9708                 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9709
9710         tp->coalesce_mode = 0;
9711         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9712             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9713                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9714
9715         /* Initialize MAC MI mode, polling disabled. */
9716         tw32_f(MAC_MI_MODE, tp->mi_mode);
9717         udelay(80);
9718
9719         /* Initialize data/descriptor byte/word swapping. */
9720         val = tr32(GRC_MODE);
9721         val &= GRC_MODE_HOST_STACKUP;
9722         tw32(GRC_MODE, val | tp->grc_mode);
9723
9724         tg3_switch_clocks(tp);
9725
9726         /* Clear this out for sanity. */
9727         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9728
9729         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9730                               &pci_state_reg);
9731         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9732             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9733                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9734
9735                 if (chiprevid == CHIPREV_ID_5701_A0 ||
9736                     chiprevid == CHIPREV_ID_5701_B0 ||
9737                     chiprevid == CHIPREV_ID_5701_B2 ||
9738                     chiprevid == CHIPREV_ID_5701_B5) {
9739                         void __iomem *sram_base;
9740
9741                         /* Write some dummy words into the SRAM status block
9742                          * area, see if it reads back correctly.  If the return
9743                          * value is bad, force enable the PCIX workaround.
9744                          */
9745                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9746
9747                         writel(0x00000000, sram_base);
9748                         writel(0x00000000, sram_base + 4);
9749                         writel(0xffffffff, sram_base + 4);
9750                         if (readl(sram_base) != 0x00000000)
9751                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9752                 }
9753         }
9754
9755         udelay(50);
9756         tg3_nvram_init(tp);
9757
9758         grc_misc_cfg = tr32(GRC_MISC_CFG);
9759         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9760
9761         /* Broadcom's driver says that CIOBE multisplit has a bug */
9762 #if 0
9763         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9764             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9765                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9766                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9767         }
9768 #endif
9769         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9770             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9771              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9772                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9773
9774         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9775             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9776                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9777         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9778                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9779                                       HOSTCC_MODE_CLRTICK_TXBD);
9780
9781                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9782                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9783                                        tp->misc_host_ctrl);
9784         }
9785
9786         /* these are limited to 10/100 only */
9787         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9788              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9789             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9790              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9791              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9792               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9793               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9794             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9795              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9796               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9797                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9798
9799         err = tg3_phy_probe(tp);
9800         if (err) {
9801                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9802                        pci_name(tp->pdev), err);
9803                 /* ... but do not return immediately ... */
9804         }
9805
9806         tg3_read_partno(tp);
9807
9808         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9809                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9810         } else {
9811                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9812                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9813                 else
9814                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9815         }
9816
9817         /* 5700 {AX,BX} chips have a broken status block link
9818          * change bit implementation, so we must use the
9819          * status register in those cases.
9820          */
9821         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9822                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9823         else
9824                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9825
9826         /* The led_ctrl is set during tg3_phy_probe, here we might
9827          * have to force the link status polling mechanism based
9828          * upon subsystem IDs.
9829          */
9830         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9831             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9832                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9833                                   TG3_FLAG_USE_LINKCHG_REG);
9834         }
9835
9836         /* For all SERDES we poll the MAC status register. */
9837         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9838                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9839         else
9840                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9841
9842         /* It seems all chips can get confused if TX buffers
9843          * straddle the 4GB address boundary in some cases.
9844          */
9845         tp->dev->hard_start_xmit = tg3_start_xmit;
9846
9847         tp->rx_offset = 2;
9848         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9849             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9850                 tp->rx_offset = 0;
9851
9852         /* By default, disable wake-on-lan.  User can change this
9853          * using ETHTOOL_SWOL.
9854          */
9855         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9856
9857         return err;
9858 }
9859
9860 #ifdef CONFIG_SPARC64
9861 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9862 {
9863         struct net_device *dev = tp->dev;
9864         struct pci_dev *pdev = tp->pdev;
9865         struct pcidev_cookie *pcp = pdev->sysdata;
9866
9867         if (pcp != NULL) {
9868                 int node = pcp->prom_node;
9869
9870                 if (prom_getproplen(node, "local-mac-address") == 6) {
9871                         prom_getproperty(node, "local-mac-address",
9872                                          dev->dev_addr, 6);
9873                         memcpy(dev->perm_addr, dev->dev_addr, 6);
9874                         return 0;
9875                 }
9876         }
9877         return -ENODEV;
9878 }
9879
9880 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9881 {
9882         struct net_device *dev = tp->dev;
9883
9884         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9885         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
9886         return 0;
9887 }
9888 #endif
9889
9890 static int __devinit tg3_get_device_address(struct tg3 *tp)
9891 {
9892         struct net_device *dev = tp->dev;
9893         u32 hi, lo, mac_offset;
9894
9895 #ifdef CONFIG_SPARC64
9896         if (!tg3_get_macaddr_sparc(tp))
9897                 return 0;
9898 #endif
9899
9900         mac_offset = 0x7c;
9901         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9902              !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
9903             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9904                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9905                         mac_offset = 0xcc;
9906                 if (tg3_nvram_lock(tp))
9907                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9908                 else
9909                         tg3_nvram_unlock(tp);
9910         }
9911
9912         /* First try to get it from MAC address mailbox. */
9913         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9914         if ((hi >> 16) == 0x484b) {
9915                 dev->dev_addr[0] = (hi >>  8) & 0xff;
9916                 dev->dev_addr[1] = (hi >>  0) & 0xff;
9917
9918                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9919                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9920                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9921                 dev->dev_addr[4] = (lo >>  8) & 0xff;
9922                 dev->dev_addr[5] = (lo >>  0) & 0xff;
9923         }
9924         /* Next, try NVRAM. */
9925         else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9926                  !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9927                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9928                 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9929                 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9930                 dev->dev_addr[2] = ((lo >>  0) & 0xff);
9931                 dev->dev_addr[3] = ((lo >>  8) & 0xff);
9932                 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9933                 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9934         }
9935         /* Finally just fetch it out of the MAC control regs. */
9936         else {
9937                 hi = tr32(MAC_ADDR_0_HIGH);
9938                 lo = tr32(MAC_ADDR_0_LOW);
9939
9940                 dev->dev_addr[5] = lo & 0xff;
9941                 dev->dev_addr[4] = (lo >> 8) & 0xff;
9942                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9943                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9944                 dev->dev_addr[1] = hi & 0xff;
9945                 dev->dev_addr[0] = (hi >> 8) & 0xff;
9946         }
9947
9948         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9949 #ifdef CONFIG_SPARC64
9950                 if (!tg3_get_default_macaddr_sparc(tp))
9951                         return 0;
9952 #endif
9953                 return -EINVAL;
9954         }
9955         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
9956         return 0;
9957 }
9958
9959 #define BOUNDARY_SINGLE_CACHELINE       1
9960 #define BOUNDARY_MULTI_CACHELINE        2
9961
9962 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9963 {
9964         int cacheline_size;
9965         u8 byte;
9966         int goal;
9967
9968         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9969         if (byte == 0)
9970                 cacheline_size = 1024;
9971         else
9972                 cacheline_size = (int) byte * 4;
9973
9974         /* On 5703 and later chips, the boundary bits have no
9975          * effect.
9976          */
9977         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9978             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9979             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9980                 goto out;
9981
9982 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9983         goal = BOUNDARY_MULTI_CACHELINE;
9984 #else
9985 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9986         goal = BOUNDARY_SINGLE_CACHELINE;
9987 #else
9988         goal = 0;
9989 #endif
9990 #endif
9991
9992         if (!goal)
9993                 goto out;
9994
9995         /* PCI controllers on most RISC systems tend to disconnect
9996          * when a device tries to burst across a cache-line boundary.
9997          * Therefore, letting tg3 do so just wastes PCI bandwidth.
9998          *
9999          * Unfortunately, for PCI-E there are only limited
10000          * write-side controls for this, and thus for reads
10001          * we will still get the disconnects.  We'll also waste
10002          * these PCI cycles for both read and write for chips
10003          * other than 5700 and 5701 which do not implement the
10004          * boundary bits.
10005          */
10006         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10007             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10008                 switch (cacheline_size) {
10009                 case 16:
10010                 case 32:
10011                 case 64:
10012                 case 128:
10013                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10014                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10015                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10016                         } else {
10017                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10018                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10019                         }
10020                         break;
10021
10022                 case 256:
10023                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10024                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10025                         break;
10026
10027                 default:
10028                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10029                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10030                         break;
10031                 };
10032         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10033                 switch (cacheline_size) {
10034                 case 16:
10035                 case 32:
10036                 case 64:
10037                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10038                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10039                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10040                                 break;
10041                         }
10042                         /* fallthrough */
10043                 case 128:
10044                 default:
10045                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10046                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10047                         break;
10048                 };
10049         } else {
10050                 switch (cacheline_size) {
10051                 case 16:
10052                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10053                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10054                                         DMA_RWCTRL_WRITE_BNDRY_16);
10055                                 break;
10056                         }
10057                         /* fallthrough */
10058                 case 32:
10059                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10060                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10061                                         DMA_RWCTRL_WRITE_BNDRY_32);
10062                                 break;
10063                         }
10064                         /* fallthrough */
10065                 case 64:
10066                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10067                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10068                                         DMA_RWCTRL_WRITE_BNDRY_64);
10069                                 break;
10070                         }
10071                         /* fallthrough */
10072                 case 128:
10073                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10074                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10075                                         DMA_RWCTRL_WRITE_BNDRY_128);
10076                                 break;
10077                         }
10078                         /* fallthrough */
10079                 case 256:
10080                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
10081                                 DMA_RWCTRL_WRITE_BNDRY_256);
10082                         break;
10083                 case 512:
10084                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
10085                                 DMA_RWCTRL_WRITE_BNDRY_512);
10086                         break;
10087                 case 1024:
10088                 default:
10089                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10090                                 DMA_RWCTRL_WRITE_BNDRY_1024);
10091                         break;
10092                 };
10093         }
10094
10095 out:
10096         return val;
10097 }
10098
10099 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10100 {
10101         struct tg3_internal_buffer_desc test_desc;
10102         u32 sram_dma_descs;
10103         int i, ret;
10104
10105         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10106
10107         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10108         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10109         tw32(RDMAC_STATUS, 0);
10110         tw32(WDMAC_STATUS, 0);
10111
10112         tw32(BUFMGR_MODE, 0);
10113         tw32(FTQ_RESET, 0);
10114
10115         test_desc.addr_hi = ((u64) buf_dma) >> 32;
10116         test_desc.addr_lo = buf_dma & 0xffffffff;
10117         test_desc.nic_mbuf = 0x00002100;
10118         test_desc.len = size;
10119
10120         /*
10121          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10122          * the *second* time the tg3 driver was getting loaded after an
10123          * initial scan.
10124          *
10125          * Broadcom tells me:
10126          *   ...the DMA engine is connected to the GRC block and a DMA
10127          *   reset may affect the GRC block in some unpredictable way...
10128          *   The behavior of resets to individual blocks has not been tested.
10129          *
10130          * Broadcom noted the GRC reset will also reset all sub-components.
10131          */
10132         if (to_device) {
10133                 test_desc.cqid_sqid = (13 << 8) | 2;
10134
10135                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10136                 udelay(40);
10137         } else {
10138                 test_desc.cqid_sqid = (16 << 8) | 7;
10139
10140                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10141                 udelay(40);
10142         }
10143         test_desc.flags = 0x00000005;
10144
10145         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10146                 u32 val;
10147
10148                 val = *(((u32 *)&test_desc) + i);
10149                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10150                                        sram_dma_descs + (i * sizeof(u32)));
10151                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10152         }
10153         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10154
10155         if (to_device) {
10156                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10157         } else {
10158                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10159         }
10160
10161         ret = -ENODEV;
10162         for (i = 0; i < 40; i++) {
10163                 u32 val;
10164
10165                 if (to_device)
10166                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10167                 else
10168                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10169                 if ((val & 0xffff) == sram_dma_descs) {
10170                         ret = 0;
10171                         break;
10172                 }
10173
10174                 udelay(100);
10175         }
10176
10177         return ret;
10178 }
10179
10180 #define TEST_BUFFER_SIZE        0x2000
10181
10182 static int __devinit tg3_test_dma(struct tg3 *tp)
10183 {
10184         dma_addr_t buf_dma;
10185         u32 *buf, saved_dma_rwctrl;
10186         int ret;
10187
10188         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10189         if (!buf) {
10190                 ret = -ENOMEM;
10191                 goto out_nofree;
10192         }
10193
10194         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10195                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10196
10197         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10198
10199         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10200                 /* DMA read watermark not used on PCIE */
10201                 tp->dma_rwctrl |= 0x00180000;
10202         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10204                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10205                         tp->dma_rwctrl |= 0x003f0000;
10206                 else
10207                         tp->dma_rwctrl |= 0x003f000f;
10208         } else {
10209                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10210                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10211                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10212
10213                         if (ccval == 0x6 || ccval == 0x7)
10214                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10215
10216                         /* Set bit 23 to enable PCIX hw bug fix */
10217                         tp->dma_rwctrl |= 0x009f0000;
10218                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10219                         /* 5780 always in PCIX mode */
10220                         tp->dma_rwctrl |= 0x00144000;
10221                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10222                         /* 5714 always in PCIX mode */
10223                         tp->dma_rwctrl |= 0x00148000;
10224                 } else {
10225                         tp->dma_rwctrl |= 0x001b000f;
10226                 }
10227         }
10228
10229         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10230             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10231                 tp->dma_rwctrl &= 0xfffffff0;
10232
10233         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10234             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10235                 /* Remove this if it causes problems for some boards. */
10236                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10237
10238                 /* On 5700/5701 chips, we need to set this bit.
10239                  * Otherwise the chip will issue cacheline transactions
10240                  * to streamable DMA memory with not all the byte
10241                  * enables turned on.  This is an error on several
10242                  * RISC PCI controllers, in particular sparc64.
10243                  *
10244                  * On 5703/5704 chips, this bit has been reassigned
10245                  * a different meaning.  In particular, it is used
10246                  * on those chips to enable a PCI-X workaround.
10247                  */
10248                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10249         }
10250
10251         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10252
10253 #if 0
10254         /* Unneeded, already done by tg3_get_invariants.  */
10255         tg3_switch_clocks(tp);
10256 #endif
10257
10258         ret = 0;
10259         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10260             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10261                 goto out;
10262
10263         /* It is best to perform DMA test with maximum write burst size
10264          * to expose the 5700/5701 write DMA bug.
10265          */
10266         saved_dma_rwctrl = tp->dma_rwctrl;
10267         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10268         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10269
10270         while (1) {
10271                 u32 *p = buf, i;
10272
10273                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10274                         p[i] = i;
10275
10276                 /* Send the buffer to the chip. */
10277                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10278                 if (ret) {
10279                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10280                         break;
10281                 }
10282
10283 #if 0
10284                 /* validate data reached card RAM correctly. */
10285                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10286                         u32 val;
10287                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
10288                         if (le32_to_cpu(val) != p[i]) {
10289                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
10290                                 /* ret = -ENODEV here? */
10291                         }
10292                         p[i] = 0;
10293                 }
10294 #endif
10295                 /* Now read it back. */
10296                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10297                 if (ret) {
10298                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10299
10300                         break;
10301                 }
10302
10303                 /* Verify it. */
10304                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10305                         if (p[i] == i)
10306                                 continue;
10307
10308                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10309                             DMA_RWCTRL_WRITE_BNDRY_16) {
10310                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10311                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10312                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10313                                 break;
10314                         } else {
10315                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
10316                                 ret = -ENODEV;
10317                                 goto out;
10318                         }
10319                 }
10320
10321                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
10322                         /* Success. */
10323                         ret = 0;
10324                         break;
10325                 }
10326         }
10327         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10328             DMA_RWCTRL_WRITE_BNDRY_16) {
10329                 static struct pci_device_id dma_wait_state_chipsets[] = {
10330                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
10331                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
10332                         { },
10333                 };
10334
10335                 /* DMA test passed without adjusting DMA boundary,
10336                  * now look for chipsets that are known to expose the
10337                  * DMA bug without failing the test.
10338                  */
10339                 if (pci_dev_present(dma_wait_state_chipsets)) {
10340                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10341                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10342                 }
10343                 else
10344                         /* Safe to use the calculated DMA boundary. */
10345                         tp->dma_rwctrl = saved_dma_rwctrl;
10346
10347                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10348         }
10349
10350 out:
10351         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
10352 out_nofree:
10353         return ret;
10354 }
10355
10356 static void __devinit tg3_init_link_config(struct tg3 *tp)
10357 {
10358         tp->link_config.advertising =
10359                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10360                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10361                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
10362                  ADVERTISED_Autoneg | ADVERTISED_MII);
10363         tp->link_config.speed = SPEED_INVALID;
10364         tp->link_config.duplex = DUPLEX_INVALID;
10365         tp->link_config.autoneg = AUTONEG_ENABLE;
10366         netif_carrier_off(tp->dev);
10367         tp->link_config.active_speed = SPEED_INVALID;
10368         tp->link_config.active_duplex = DUPLEX_INVALID;
10369         tp->link_config.phy_is_low_power = 0;
10370         tp->link_config.orig_speed = SPEED_INVALID;
10371         tp->link_config.orig_duplex = DUPLEX_INVALID;
10372         tp->link_config.orig_autoneg = AUTONEG_INVALID;
10373 }
10374
10375 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
10376 {
10377         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10378                 tp->bufmgr_config.mbuf_read_dma_low_water =
10379                         DEFAULT_MB_RDMA_LOW_WATER_5705;
10380                 tp->bufmgr_config.mbuf_mac_rx_low_water =
10381                         DEFAULT_MB_MACRX_LOW_WATER_5705;
10382                 tp->bufmgr_config.mbuf_high_water =
10383                         DEFAULT_MB_HIGH_WATER_5705;
10384
10385                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10386                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
10387                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10388                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
10389                 tp->bufmgr_config.mbuf_high_water_jumbo =
10390                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
10391         } else {
10392                 tp->bufmgr_config.mbuf_read_dma_low_water =
10393                         DEFAULT_MB_RDMA_LOW_WATER;
10394                 tp->bufmgr_config.mbuf_mac_rx_low_water =
10395                         DEFAULT_MB_MACRX_LOW_WATER;
10396                 tp->bufmgr_config.mbuf_high_water =
10397                         DEFAULT_MB_HIGH_WATER;
10398
10399                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10400                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
10401                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10402                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
10403                 tp->bufmgr_config.mbuf_high_water_jumbo =
10404                         DEFAULT_MB_HIGH_WATER_JUMBO;
10405         }
10406
10407         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
10408         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
10409 }
10410
10411 static char * __devinit tg3_phy_string(struct tg3 *tp)
10412 {
10413         switch (tp->phy_id & PHY_ID_MASK) {
10414         case PHY_ID_BCM5400:    return "5400";
10415         case PHY_ID_BCM5401:    return "5401";
10416         case PHY_ID_BCM5411:    return "5411";
10417         case PHY_ID_BCM5701:    return "5701";
10418         case PHY_ID_BCM5703:    return "5703";
10419         case PHY_ID_BCM5704:    return "5704";
10420         case PHY_ID_BCM5705:    return "5705";
10421         case PHY_ID_BCM5750:    return "5750";
10422         case PHY_ID_BCM5752:    return "5752";
10423         case PHY_ID_BCM5714:    return "5714";
10424         case PHY_ID_BCM5780:    return "5780";
10425         case PHY_ID_BCM8002:    return "8002/serdes";
10426         case 0:                 return "serdes";
10427         default:                return "unknown";
10428         };
10429 }
10430
10431 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10432 {
10433         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10434                 strcpy(str, "PCI Express");
10435                 return str;
10436         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
10437                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
10438
10439                 strcpy(str, "PCIX:");
10440
10441                 if ((clock_ctrl == 7) ||
10442                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
10443                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
10444                         strcat(str, "133MHz");
10445                 else if (clock_ctrl == 0)
10446                         strcat(str, "33MHz");
10447                 else if (clock_ctrl == 2)
10448                         strcat(str, "50MHz");
10449                 else if (clock_ctrl == 4)
10450                         strcat(str, "66MHz");
10451                 else if (clock_ctrl == 6)
10452                         strcat(str, "100MHz");
10453                 else if (clock_ctrl == 7)
10454                         strcat(str, "133MHz");
10455         } else {
10456                 strcpy(str, "PCI:");
10457                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
10458                         strcat(str, "66MHz");
10459                 else
10460                         strcat(str, "33MHz");
10461         }
10462         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
10463                 strcat(str, ":32-bit");
10464         else
10465                 strcat(str, ":64-bit");
10466         return str;
10467 }
10468
10469 static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
10470 {
10471         struct pci_dev *peer;
10472         unsigned int func, devnr = tp->pdev->devfn & ~7;
10473
10474         for (func = 0; func < 8; func++) {
10475                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
10476                 if (peer && peer != tp->pdev)
10477                         break;
10478                 pci_dev_put(peer);
10479         }
10480         /* 5704 can be configured in single-port mode, set peer to
10481          * tp->pdev in that case.
10482          */
10483         if (!peer) {
10484                 peer = tp->pdev;
10485                 return peer;
10486         }
10487
10488         /*
10489          * We don't need to keep the refcount elevated; there's no way
10490          * to remove one half of this device without removing the other
10491          */
10492         pci_dev_put(peer);
10493
10494         return peer;
10495 }
10496
10497 static void __devinit tg3_init_coal(struct tg3 *tp)
10498 {
10499         struct ethtool_coalesce *ec = &tp->coal;
10500
10501         memset(ec, 0, sizeof(*ec));
10502         ec->cmd = ETHTOOL_GCOALESCE;
10503         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
10504         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
10505         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
10506         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
10507         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
10508         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
10509         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
10510         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
10511         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
10512
10513         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
10514                                  HOSTCC_MODE_CLRTICK_TXBD)) {
10515                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
10516                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
10517                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
10518                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
10519         }
10520
10521         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10522                 ec->rx_coalesce_usecs_irq = 0;
10523                 ec->tx_coalesce_usecs_irq = 0;
10524                 ec->stats_block_coalesce_usecs = 0;
10525         }
10526 }
10527
10528 static int __devinit tg3_init_one(struct pci_dev *pdev,
10529                                   const struct pci_device_id *ent)
10530 {
10531         static int tg3_version_printed = 0;
10532         unsigned long tg3reg_base, tg3reg_len;
10533         struct net_device *dev;
10534         struct tg3 *tp;
10535         int i, err, pci_using_dac, pm_cap;
10536         char str[40];
10537
10538         if (tg3_version_printed++ == 0)
10539                 printk(KERN_INFO "%s", version);
10540
10541         err = pci_enable_device(pdev);
10542         if (err) {
10543                 printk(KERN_ERR PFX "Cannot enable PCI device, "
10544                        "aborting.\n");
10545                 return err;
10546         }
10547
10548         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10549                 printk(KERN_ERR PFX "Cannot find proper PCI device "
10550                        "base address, aborting.\n");
10551                 err = -ENODEV;
10552                 goto err_out_disable_pdev;
10553         }
10554
10555         err = pci_request_regions(pdev, DRV_MODULE_NAME);
10556         if (err) {
10557                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
10558                        "aborting.\n");
10559                 goto err_out_disable_pdev;
10560         }
10561
10562         pci_set_master(pdev);
10563
10564         /* Find power-management capability. */
10565         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10566         if (pm_cap == 0) {
10567                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
10568                        "aborting.\n");
10569                 err = -EIO;
10570                 goto err_out_free_res;
10571         }
10572
10573         /* Configure DMA attributes. */
10574         err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
10575         if (!err) {
10576                 pci_using_dac = 1;
10577                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
10578                 if (err < 0) {
10579                         printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
10580                                "for consistent allocations\n");
10581                         goto err_out_free_res;
10582                 }
10583         } else {
10584                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
10585                 if (err) {
10586                         printk(KERN_ERR PFX "No usable DMA configuration, "
10587                                "aborting.\n");
10588                         goto err_out_free_res;
10589                 }
10590                 pci_using_dac = 0;
10591         }
10592
10593         tg3reg_base = pci_resource_start(pdev, 0);
10594         tg3reg_len = pci_resource_len(pdev, 0);
10595
10596         dev = alloc_etherdev(sizeof(*tp));
10597         if (!dev) {
10598                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
10599                 err = -ENOMEM;
10600                 goto err_out_free_res;
10601         }
10602
10603         SET_MODULE_OWNER(dev);
10604         SET_NETDEV_DEV(dev, &pdev->dev);
10605
10606         if (pci_using_dac)
10607                 dev->features |= NETIF_F_HIGHDMA;
10608         dev->features |= NETIF_F_LLTX;
10609 #if TG3_VLAN_TAG_USED
10610         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
10611         dev->vlan_rx_register = tg3_vlan_rx_register;
10612         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
10613 #endif
10614
10615         tp = netdev_priv(dev);
10616         tp->pdev = pdev;
10617         tp->dev = dev;
10618         tp->pm_cap = pm_cap;
10619         tp->mac_mode = TG3_DEF_MAC_MODE;
10620         tp->rx_mode = TG3_DEF_RX_MODE;
10621         tp->tx_mode = TG3_DEF_TX_MODE;
10622         tp->mi_mode = MAC_MI_MODE_BASE;
10623         if (tg3_debug > 0)
10624                 tp->msg_enable = tg3_debug;
10625         else
10626                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
10627
10628         /* The word/byte swap controls here control register access byte
10629          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
10630          * setting below.
10631          */
10632         tp->misc_host_ctrl =
10633                 MISC_HOST_CTRL_MASK_PCI_INT |
10634                 MISC_HOST_CTRL_WORD_SWAP |
10635                 MISC_HOST_CTRL_INDIR_ACCESS |
10636                 MISC_HOST_CTRL_PCISTATE_RW;
10637
10638         /* The NONFRM (non-frame) byte/word swap controls take effect
10639          * on descriptor entries, anything which isn't packet data.
10640          *
10641          * The StrongARM chips on the board (one for tx, one for rx)
10642          * are running in big-endian mode.
10643          */
10644         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
10645                         GRC_MODE_WSWAP_NONFRM_DATA);
10646 #ifdef __BIG_ENDIAN
10647         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
10648 #endif
10649         spin_lock_init(&tp->lock);
10650         spin_lock_init(&tp->tx_lock);
10651         spin_lock_init(&tp->indirect_lock);
10652         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
10653
10654         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
10655         if (tp->regs == 0UL) {
10656                 printk(KERN_ERR PFX "Cannot map device registers, "
10657                        "aborting.\n");
10658                 err = -ENOMEM;
10659                 goto err_out_free_dev;
10660         }
10661
10662         tg3_init_link_config(tp);
10663
10664         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10665         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10666         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
10667
10668         dev->open = tg3_open;
10669         dev->stop = tg3_close;
10670         dev->get_stats = tg3_get_stats;
10671         dev->set_multicast_list = tg3_set_rx_mode;
10672         dev->set_mac_address = tg3_set_mac_addr;
10673         dev->do_ioctl = tg3_ioctl;
10674         dev->tx_timeout = tg3_tx_timeout;
10675         dev->poll = tg3_poll;
10676         dev->ethtool_ops = &tg3_ethtool_ops;
10677         dev->weight = 64;
10678         dev->watchdog_timeo = TG3_TX_TIMEOUT;
10679         dev->change_mtu = tg3_change_mtu;
10680         dev->irq = pdev->irq;
10681 #ifdef CONFIG_NET_POLL_CONTROLLER
10682         dev->poll_controller = tg3_poll_controller;
10683 #endif
10684
10685         err = tg3_get_invariants(tp);
10686         if (err) {
10687                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
10688                        "aborting.\n");
10689                 goto err_out_iounmap;
10690         }
10691
10692         tg3_init_bufmgr_config(tp);
10693
10694 #if TG3_TSO_SUPPORT != 0
10695         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10696                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10697         }
10698         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10699             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10700             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
10701             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
10702                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
10703         } else {
10704                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10705         }
10706
10707         /* TSO is off by default, user can enable using ethtool.  */
10708 #if 0
10709         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
10710                 dev->features |= NETIF_F_TSO;
10711 #endif
10712
10713 #endif
10714
10715         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10716             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10717             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10718                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10719                 tp->rx_pending = 63;
10720         }
10721
10722         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10723                 tp->pdev_peer = tg3_find_5704_peer(tp);
10724
10725         err = tg3_get_device_address(tp);
10726         if (err) {
10727                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10728                        "aborting.\n");
10729                 goto err_out_iounmap;
10730         }
10731
10732         /*
10733          * Reset chip in case UNDI or EFI driver did not shutdown
10734          * DMA self test will enable WDMAC and we'll see (spurious)
10735          * pending DMA on the PCI bus at that point.
10736          */
10737         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10738             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10739                 pci_save_state(tp->pdev);
10740                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
10741                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10742         }
10743
10744         err = tg3_test_dma(tp);
10745         if (err) {
10746                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10747                 goto err_out_iounmap;
10748         }
10749
10750         /* Tigon3 can do ipv4 only... and some chips have buggy
10751          * checksumming.
10752          */
10753         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10754                 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10755                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10756         } else
10757                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10758
10759         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10760                 dev->features &= ~NETIF_F_HIGHDMA;
10761
10762         /* flow control autonegotiation is default behavior */
10763         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10764
10765         tg3_init_coal(tp);
10766
10767         /* Now that we have fully setup the chip, save away a snapshot
10768          * of the PCI config space.  We need to restore this after
10769          * GRC_MISC_CFG core clock resets and some resume events.
10770          */
10771         pci_save_state(tp->pdev);
10772
10773         err = register_netdev(dev);
10774         if (err) {
10775                 printk(KERN_ERR PFX "Cannot register net device, "
10776                        "aborting.\n");
10777                 goto err_out_iounmap;
10778         }
10779
10780         pci_set_drvdata(pdev, dev);
10781
10782         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
10783                dev->name,
10784                tp->board_part_number,
10785                tp->pci_chip_rev_id,
10786                tg3_phy_string(tp),
10787                tg3_bus_string(tp, str),
10788                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10789
10790         for (i = 0; i < 6; i++)
10791                 printk("%2.2x%c", dev->dev_addr[i],
10792                        i == 5 ? '\n' : ':');
10793
10794         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10795                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10796                "TSOcap[%d] \n",
10797                dev->name,
10798                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10799                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10800                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10801                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10802                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10803                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10804                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10805         printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10806                dev->name, tp->dma_rwctrl);
10807
10808         return 0;
10809
10810 err_out_iounmap:
10811         if (tp->regs) {
10812                 iounmap(tp->regs);
10813                 tp->regs = NULL;
10814         }
10815
10816 err_out_free_dev:
10817         free_netdev(dev);
10818
10819 err_out_free_res:
10820         pci_release_regions(pdev);
10821
10822 err_out_disable_pdev:
10823         pci_disable_device(pdev);
10824         pci_set_drvdata(pdev, NULL);
10825         return err;
10826 }
10827
10828 static void __devexit tg3_remove_one(struct pci_dev *pdev)
10829 {
10830         struct net_device *dev = pci_get_drvdata(pdev);
10831
10832         if (dev) {
10833                 struct tg3 *tp = netdev_priv(dev);
10834
10835                 unregister_netdev(dev);
10836                 if (tp->regs) {
10837                         iounmap(tp->regs);
10838                         tp->regs = NULL;
10839                 }
10840                 free_netdev(dev);
10841                 pci_release_regions(pdev);
10842                 pci_disable_device(pdev);
10843                 pci_set_drvdata(pdev, NULL);
10844         }
10845 }
10846
10847 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10848 {
10849         struct net_device *dev = pci_get_drvdata(pdev);
10850         struct tg3 *tp = netdev_priv(dev);
10851         int err;
10852
10853         if (!netif_running(dev))
10854                 return 0;
10855
10856         tg3_netif_stop(tp);
10857
10858         del_timer_sync(&tp->timer);
10859
10860         tg3_full_lock(tp, 1);
10861         tg3_disable_ints(tp);
10862         tg3_full_unlock(tp);
10863
10864         netif_device_detach(dev);
10865
10866         tg3_full_lock(tp, 0);
10867         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10868         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
10869         tg3_full_unlock(tp);
10870
10871         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10872         if (err) {
10873                 tg3_full_lock(tp, 0);
10874
10875                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10876                 tg3_init_hw(tp);
10877
10878                 tp->timer.expires = jiffies + tp->timer_offset;
10879                 add_timer(&tp->timer);
10880
10881                 netif_device_attach(dev);
10882                 tg3_netif_start(tp);
10883
10884                 tg3_full_unlock(tp);
10885         }
10886
10887         return err;
10888 }
10889
10890 static int tg3_resume(struct pci_dev *pdev)
10891 {
10892         struct net_device *dev = pci_get_drvdata(pdev);
10893         struct tg3 *tp = netdev_priv(dev);
10894         int err;
10895
10896         if (!netif_running(dev))
10897                 return 0;
10898
10899         pci_restore_state(tp->pdev);
10900
10901         err = tg3_set_power_state(tp, 0);
10902         if (err)
10903                 return err;
10904
10905         netif_device_attach(dev);
10906
10907         tg3_full_lock(tp, 0);
10908
10909         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10910         tg3_init_hw(tp);
10911
10912         tp->timer.expires = jiffies + tp->timer_offset;
10913         add_timer(&tp->timer);
10914
10915         tg3_netif_start(tp);
10916
10917         tg3_full_unlock(tp);
10918
10919         return 0;
10920 }
10921
10922 static struct pci_driver tg3_driver = {
10923         .name           = DRV_MODULE_NAME,
10924         .id_table       = tg3_pci_tbl,
10925         .probe          = tg3_init_one,
10926         .remove         = __devexit_p(tg3_remove_one),
10927         .suspend        = tg3_suspend,
10928         .resume         = tg3_resume
10929 };
10930
10931 static int __init tg3_init(void)
10932 {
10933         return pci_module_init(&tg3_driver);
10934 }
10935
10936 static void __exit tg3_cleanup(void)
10937 {
10938         pci_unregister_driver(&tg3_driver);
10939 }
10940
10941 module_init(tg3_init);
10942 module_exit(tg3_cleanup);