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   1 /*
   2  * arch/arm/mach-at91/at91sam9260.c
   3  *
   4  *  Copyright (C) 2006 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/pm.h>
  15
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/map.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/at91sam9260.h>
  20 #include <asm/arch/at91_pmc.h>
  21 #include <asm/arch/at91_rstc.h>
  22 #include <asm/arch/at91_shdwc.h>
  23
  24 #include "generic.h"
  25 #include "clock.h"
  26
  27 static struct map_desc at91sam9260_io_desc[] __initdata = {
  28         {
  29                 .virtual        = AT91_VA_BASE_SYS,
  30                 .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  31                 .length         = SZ_16K,
  32                 .type           = MT_DEVICE,
  33         }
  34 };
  35
  36 static struct map_desc at91sam9260_sram_desc[] __initdata = {
  37         {
  38                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
  39                 .pfn            = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
  40                 .length         = AT91SAM9260_SRAM0_SIZE,
  41                 .type           = MT_DEVICE,
  42         }, {
  43                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
  44                 .pfn            = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
  45                 .length         = AT91SAM9260_SRAM1_SIZE,
  46                 .type           = MT_DEVICE,
  47         }
  48 };
  49
  50 static struct map_desc at91sam9xe_sram_desc[] __initdata = {
  51         {
  52                 .pfn            = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
  53                 .type           = MT_DEVICE,
  54         }
  55 };
  56
  57 /* --------------------------------------------------------------------
  58  *  Clocks
  59  * -------------------------------------------------------------------- */
  60
  61 /*
  62  * The peripheral clocks.
  63  */
  64 static struct clk pioA_clk = {
  65         .name           = "pioA_clk",
  66         .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
  67         .type           = CLK_TYPE_PERIPHERAL,
  68 };
  69 static struct clk pioB_clk = {
  70         .name           = "pioB_clk",
  71         .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
  72         .type           = CLK_TYPE_PERIPHERAL,
  73 };
  74 static struct clk pioC_clk = {
  75         .name           = "pioC_clk",
  76         .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
  77         .type           = CLK_TYPE_PERIPHERAL,
  78 };
  79 static struct clk adc_clk = {
  80         .name           = "adc_clk",
  81         .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
  82         .type           = CLK_TYPE_PERIPHERAL,
  83 };
  84 static struct clk usart0_clk = {
  85         .name           = "usart0_clk",
  86         .pmc_mask       = 1 << AT91SAM9260_ID_US0,
  87         .type           = CLK_TYPE_PERIPHERAL,
  88 };
  89 static struct clk usart1_clk = {
  90         .name           = "usart1_clk",
  91         .pmc_mask       = 1 << AT91SAM9260_ID_US1,
  92         .type           = CLK_TYPE_PERIPHERAL,
  93 };
  94 static struct clk usart2_clk = {
  95         .name           = "usart2_clk",
  96         .pmc_mask       = 1 << AT91SAM9260_ID_US2,
  97         .type           = CLK_TYPE_PERIPHERAL,
  98 };
  99 static struct clk mmc_clk = {
 100         .name           = "mci_clk",
 101         .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
 102         .type           = CLK_TYPE_PERIPHERAL,
 103 };
 104 static struct clk udc_clk = {
 105         .name           = "udc_clk",
 106         .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
 107         .type           = CLK_TYPE_PERIPHERAL,
 108 };
 109 static struct clk twi_clk = {
 110         .name           = "twi_clk",
 111         .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
 112         .type           = CLK_TYPE_PERIPHERAL,
 113 };
 114 static struct clk spi0_clk = {
 115         .name           = "spi0_clk",
 116         .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
 117         .type           = CLK_TYPE_PERIPHERAL,
 118 };
 119 static struct clk spi1_clk = {
 120         .name           = "spi1_clk",
 121         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
 122         .type           = CLK_TYPE_PERIPHERAL,
 123 };
 124 static struct clk ssc_clk = {
 125         .name           = "ssc_clk",
 126         .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 127         .type           = CLK_TYPE_PERIPHERAL,
 128 };
 129 static struct clk tc0_clk = {
 130         .name           = "tc0_clk",
 131         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 132         .type           = CLK_TYPE_PERIPHERAL,
 133 };
 134 static struct clk tc1_clk = {
 135         .name           = "tc1_clk",
 136         .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
 137         .type           = CLK_TYPE_PERIPHERAL,
 138 };
 139 static struct clk tc2_clk = {
 140         .name           = "tc2_clk",
 141         .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
 142         .type           = CLK_TYPE_PERIPHERAL,
 143 };
 144 static struct clk ohci_clk = {
 145         .name           = "ohci_clk",
 146         .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
 147         .type           = CLK_TYPE_PERIPHERAL,
 148 };
 149 static struct clk macb_clk = {
 150         .name           = "macb_clk",
 151         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
 152         .type           = CLK_TYPE_PERIPHERAL,
 153 };
 154 static struct clk isi_clk = {
 155         .name           = "isi_clk",
 156         .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
 157         .type           = CLK_TYPE_PERIPHERAL,
 158 };
 159 static struct clk usart3_clk = {
 160         .name           = "usart3_clk",
 161         .pmc_mask       = 1 << AT91SAM9260_ID_US3,
 162         .type           = CLK_TYPE_PERIPHERAL,
 163 };
 164 static struct clk usart4_clk = {
 165         .name           = "usart4_clk",
 166         .pmc_mask       = 1 << AT91SAM9260_ID_US4,
 167         .type           = CLK_TYPE_PERIPHERAL,
 168 };
 169 static struct clk usart5_clk = {
 170         .name           = "usart5_clk",
 171         .pmc_mask       = 1 << AT91SAM9260_ID_US5,
 172         .type           = CLK_TYPE_PERIPHERAL,
 173 };
 174 static struct clk tc3_clk = {
 175         .name           = "tc3_clk",
 176         .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
 177         .type           = CLK_TYPE_PERIPHERAL,
 178 };
 179 static struct clk tc4_clk = {
 180         .name           = "tc4_clk",
 181         .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
 182         .type           = CLK_TYPE_PERIPHERAL,
 183 };
 184 static struct clk tc5_clk = {
 185         .name           = "tc5_clk",
 186         .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
 187         .type           = CLK_TYPE_PERIPHERAL,
 188 };
 189
 190 static struct clk *periph_clocks[] __initdata = {
 191         &pioA_clk,
 192         &pioB_clk,
 193         &pioC_clk,
 194         &adc_clk,
 195         &usart0_clk,
 196         &usart1_clk,
 197         &usart2_clk,
 198         &mmc_clk,
 199         &udc_clk,
 200         &twi_clk,
 201         &spi0_clk,
 202         &spi1_clk,
 203         &ssc_clk,
 204         &tc0_clk,
 205         &tc1_clk,
 206         &tc2_clk,
 207         &ohci_clk,
 208         &macb_clk,
 209         &isi_clk,
 210         &usart3_clk,
 211         &usart4_clk,
 212         &usart5_clk,
 213         &tc3_clk,
 214         &tc4_clk,
 215         &tc5_clk,
 216         // irq0 .. irq2
 217 };
 218
 219 /*
 220  * The two programmable clocks.
 221  * You must configure pin multiplexing to bring these signals out.
 222  */
 223 static struct clk pck0 = {
 224         .name           = "pck0",
 225         .pmc_mask       = AT91_PMC_PCK0,
 226         .type           = CLK_TYPE_PROGRAMMABLE,
 227         .id             = 0,
 228 };
 229 static struct clk pck1 = {
 230         .name           = "pck1",
 231         .pmc_mask       = AT91_PMC_PCK1,
 232         .type           = CLK_TYPE_PROGRAMMABLE,
 233         .id             = 1,
 234 };
 235
 236 static void __init at91sam9260_register_clocks(void)
 237 {
 238         int i;
 239
 240         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 241                 clk_register(periph_clocks[i]);
 242
 243         clk_register(&pck0);
 244         clk_register(&pck1);
 245 }
 246
 247 /* --------------------------------------------------------------------
 248  *  GPIO
 249  * -------------------------------------------------------------------- */
 250
 251 static struct at91_gpio_bank at91sam9260_gpio[] = {
 252         {
 253                 .id             = AT91SAM9260_ID_PIOA,
 254                 .offset         = AT91_PIOA,
 255                 .clock          = &pioA_clk,
 256         }, {
 257                 .id             = AT91SAM9260_ID_PIOB,
 258                 .offset         = AT91_PIOB,
 259                 .clock          = &pioB_clk,
 260         }, {
 261                 .id             = AT91SAM9260_ID_PIOC,
 262                 .offset         = AT91_PIOC,
 263                 .clock          = &pioC_clk,
 264         }
 265 };
 266
 267 static void at91sam9260_reset(void)
 268 {
 269         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 270 }
 271
 272 static void at91sam9260_poweroff(void)
 273 {
 274         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 275 }
 276
 277
 278 /* --------------------------------------------------------------------
 279  *  AT91SAM9260 processor initialization
 280  * -------------------------------------------------------------------- */
 281
 282 static void __init at91sam9xe_initialize(void)
 283 {
 284         unsigned long cidr, sram_size;
 285
 286         cidr = at91_sys_read(AT91_DBGU_CIDR);
 287
 288         switch (cidr & AT91_CIDR_SRAMSIZ) {
 289                 case AT91_CIDR_SRAMSIZ_32K:
 290                         sram_size = 2 * SZ_16K;
 291                         break;
 292                 case AT91_CIDR_SRAMSIZ_16K:
 293                 default:
 294                         sram_size = SZ_16K;
 295         }
 296
 297         at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
 298         at91sam9xe_sram_desc->length = sram_size;
 299
 300         iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
 301 }
 302
 303 void __init at91sam9260_initialize(unsigned long main_clock)
 304 {
 305         /* Map peripherals */
 306         iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
 307
 308         if (cpu_is_at91sam9xe())
 309                 at91sam9xe_initialize();
 310         else
 311                 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 312
 313         at91_arch_reset = at91sam9260_reset;
 314         pm_power_off = at91sam9260_poweroff;
 315         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
 316                         | (1 << AT91SAM9260_ID_IRQ2);
 317
 318         /* Init clock subsystem */
 319         at91_clock_init(main_clock);
 320
 321         /* Register the processor-specific clocks */
 322         at91sam9260_register_clocks();
 323
 324         /* Register GPIO subsystem */
 325         at91_gpio_init(at91sam9260_gpio, 3);
 326 }
 327
 328 /* --------------------------------------------------------------------
 329  *  Interrupt initialization
 330  * -------------------------------------------------------------------- */
 331
 332 /*
 333  * The default interrupt priority levels (0 = lowest, 7 = highest).
 334  */
 335 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 336         7,      /* Advanced Interrupt Controller */
 337         7,      /* System Peripherals */
 338         1,      /* Parallel IO Controller A */
 339         1,      /* Parallel IO Controller B */
 340         1,      /* Parallel IO Controller C */
 341         0,      /* Analog-to-Digital Converter */
 342         5,      /* USART 0 */
 343         5,      /* USART 1 */
 344         5,      /* USART 2 */
 345         0,      /* Multimedia Card Interface */
 346         2,      /* USB Device Port */
 347         6,      /* Two-Wire Interface */
 348         5,      /* Serial Peripheral Interface 0 */
 349         5,      /* Serial Peripheral Interface 1 */
 350         5,      /* Serial Synchronous Controller */
 351         0,
 352         0,
 353         0,      /* Timer Counter 0 */
 354         0,      /* Timer Counter 1 */
 355         0,      /* Timer Counter 2 */
 356         2,      /* USB Host port */
 357         3,      /* Ethernet */
 358         0,      /* Image Sensor Interface */
 359         5,      /* USART 3 */
 360         5,      /* USART 4 */
 361         5,      /* USART 5 */
 362         0,      /* Timer Counter 3 */
 363         0,      /* Timer Counter 4 */
 364         0,      /* Timer Counter 5 */
 365         0,      /* Advanced Interrupt Controller */
 366         0,      /* Advanced Interrupt Controller */
 367         0,      /* Advanced Interrupt Controller */
 368 };
 369
 370 void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 371 {
 372         if (!priority)
 373                 priority = at91sam9260_default_irq_priority;
 374
 375         /* Initialize the AIC interrupt controller */
 376         at91_aic_init(priority);
 377
 378         /* Enable GPIO interrupts */
 379         at91_gpio_irq_setup();
 380 }