git.oblomov.eu Git - linux-2.6/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 106  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 107  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 108  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 109  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 110  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 111  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 112  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 113  *
 114  * Known bugs:
 115  * We suspect that on some hardware no TX done interrupts are generated.
 116  * This means recovery from netif_stop_queue only happens if the hw timer
 117  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 118  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 119  * If your hardware reliably generates tx done interrupts, then you can remove
 120  * DEV_NEED_TIMERIRQ from the driver_data flags.
 121  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 122  * superfluous timer interrupts from the nic.
 123  */
 124 #ifdef CONFIG_FORCEDETH_NAPI
 125 #define DRIVERNAPI "-NAPI"
 126 #else
 127 #define DRIVERNAPI
 128 #endif
 129 #define FORCEDETH_VERSION               "0.57"
 130 #define DRV_NAME                        "forcedeth"
 131
 132 #include <linux/module.h>
 133 #include <linux/types.h>
 134 #include <linux/pci.h>
 135 #include <linux/interrupt.h>
 136 #include <linux/netdevice.h>
 137 #include <linux/etherdevice.h>
 138 #include <linux/delay.h>
 139 #include <linux/spinlock.h>
 140 #include <linux/ethtool.h>
 141 #include <linux/timer.h>
 142 #include <linux/skbuff.h>
 143 #include <linux/mii.h>
 144 #include <linux/random.h>
 145 #include <linux/init.h>
 146 #include <linux/if_vlan.h>
 147 #include <linux/dma-mapping.h>
 148
 149 #include <asm/irq.h>
 150 #include <asm/io.h>
 151 #include <asm/uaccess.h>
 152 #include <asm/system.h>
 153
 154 #if 0
 155 #define dprintk                 printk
 156 #else
 157 #define dprintk(x...)           do { } while (0)
 158 #endif
 159
 160
 161 /*
 162  * Hardware access:
 163  */
 164
 165 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 166 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 167 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 168 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 169 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 170 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 171 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 172 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 173 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 174 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 175 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 176 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 177
 178 enum {
 179         NvRegIrqStatus = 0x000,
 180 #define NVREG_IRQSTAT_MIIEVENT  0x040
 181 #define NVREG_IRQSTAT_MASK              0x1ff
 182         NvRegIrqMask = 0x004,
 183 #define NVREG_IRQ_RX_ERROR              0x0001
 184 #define NVREG_IRQ_RX                    0x0002
 185 #define NVREG_IRQ_RX_NOBUF              0x0004
 186 #define NVREG_IRQ_TX_ERR                0x0008
 187 #define NVREG_IRQ_TX_OK                 0x0010
 188 #define NVREG_IRQ_TIMER                 0x0020
 189 #define NVREG_IRQ_LINK                  0x0040
 190 #define NVREG_IRQ_RX_FORCED             0x0080
 191 #define NVREG_IRQ_TX_FORCED             0x0100
 192 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 193 #define NVREG_IRQMASK_CPU               0x0040
 194 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 195 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 196 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
 197
 198 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 199                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 200                                         NVREG_IRQ_TX_FORCED))
 201
 202         NvRegUnknownSetupReg6 = 0x008,
 203 #define NVREG_UNKSETUP6_VAL             3
 204
 205 /*
 206  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 207  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 208  */
 209         NvRegPollingInterval = 0x00c,
 210 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 211 #define NVREG_POLL_DEFAULT_CPU  13
 212         NvRegMSIMap0 = 0x020,
 213         NvRegMSIMap1 = 0x024,
 214         NvRegMSIIrqMask = 0x030,
 215 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 216         NvRegMisc1 = 0x080,
 217 #define NVREG_MISC1_PAUSE_TX    0x01
 218 #define NVREG_MISC1_HD          0x02
 219 #define NVREG_MISC1_FORCE       0x3b0f3c
 220
 221         NvRegMacReset = 0x3c,
 222 #define NVREG_MAC_RESET_ASSERT  0x0F3
 223         NvRegTransmitterControl = 0x084,
 224 #define NVREG_XMITCTL_START     0x01
 225         NvRegTransmitterStatus = 0x088,
 226 #define NVREG_XMITSTAT_BUSY     0x01
 227
 228         NvRegPacketFilterFlags = 0x8c,
 229 #define NVREG_PFF_PAUSE_RX      0x08
 230 #define NVREG_PFF_ALWAYS        0x7F0000
 231 #define NVREG_PFF_PROMISC       0x80
 232 #define NVREG_PFF_MYADDR        0x20
 233 #define NVREG_PFF_LOOPBACK      0x10
 234
 235         NvRegOffloadConfig = 0x90,
 236 #define NVREG_OFFLOAD_HOMEPHY   0x601
 237 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 238         NvRegReceiverControl = 0x094,
 239 #define NVREG_RCVCTL_START      0x01
 240         NvRegReceiverStatus = 0x98,
 241 #define NVREG_RCVSTAT_BUSY      0x01
 242
 243         NvRegRandomSeed = 0x9c,
 244 #define NVREG_RNDSEED_MASK      0x00ff
 245 #define NVREG_RNDSEED_FORCE     0x7f00
 246 #define NVREG_RNDSEED_FORCE2    0x2d00
 247 #define NVREG_RNDSEED_FORCE3    0x7400
 248
 249         NvRegTxDeferral = 0xA0,
 250 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 251 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 252 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 253         NvRegRxDeferral = 0xA4,
 254 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 255         NvRegMacAddrA = 0xA8,
 256         NvRegMacAddrB = 0xAC,
 257         NvRegMulticastAddrA = 0xB0,
 258 #define NVREG_MCASTADDRA_FORCE  0x01
 259         NvRegMulticastAddrB = 0xB4,
 260         NvRegMulticastMaskA = 0xB8,
 261         NvRegMulticastMaskB = 0xBC,
 262
 263         NvRegPhyInterface = 0xC0,
 264 #define PHY_RGMII               0x10000000
 265
 266         NvRegTxRingPhysAddr = 0x100,
 267         NvRegRxRingPhysAddr = 0x104,
 268         NvRegRingSizes = 0x108,
 269 #define NVREG_RINGSZ_TXSHIFT 0
 270 #define NVREG_RINGSZ_RXSHIFT 16
 271         NvRegTransmitPoll = 0x10c,
 272 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 273         NvRegLinkSpeed = 0x110,
 274 #define NVREG_LINKSPEED_FORCE 0x10000
 275 #define NVREG_LINKSPEED_10      1000
 276 #define NVREG_LINKSPEED_100     100
 277 #define NVREG_LINKSPEED_1000    50
 278 #define NVREG_LINKSPEED_MASK    (0xFFF)
 279         NvRegUnknownSetupReg5 = 0x130,
 280 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 281         NvRegTxWatermark = 0x13c,
 282 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 283 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 284 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 285         NvRegTxRxControl = 0x144,
 286 #define NVREG_TXRXCTL_KICK      0x0001
 287 #define NVREG_TXRXCTL_BIT1      0x0002
 288 #define NVREG_TXRXCTL_BIT2      0x0004
 289 #define NVREG_TXRXCTL_IDLE      0x0008
 290 #define NVREG_TXRXCTL_RESET     0x0010
 291 #define NVREG_TXRXCTL_RXCHECK   0x0400
 292 #define NVREG_TXRXCTL_DESC_1    0
 293 #define NVREG_TXRXCTL_DESC_2    0x02100
 294 #define NVREG_TXRXCTL_DESC_3    0x02200
 295 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 296 #define NVREG_TXRXCTL_VLANINS   0x00080
 297         NvRegTxRingPhysAddrHigh = 0x148,
 298         NvRegRxRingPhysAddrHigh = 0x14C,
 299         NvRegTxPauseFrame = 0x170,
 300 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 301 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 302         NvRegMIIStatus = 0x180,
 303 #define NVREG_MIISTAT_ERROR             0x0001
 304 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 305 #define NVREG_MIISTAT_MASK              0x000f
 306 #define NVREG_MIISTAT_MASK2             0x000f
 307         NvRegUnknownSetupReg4 = 0x184,
 308 #define NVREG_UNKSETUP4_VAL     8
 309
 310         NvRegAdapterControl = 0x188,
 311 #define NVREG_ADAPTCTL_START    0x02
 312 #define NVREG_ADAPTCTL_LINKUP   0x04
 313 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 314 #define NVREG_ADAPTCTL_RUNNING  0x100000
 315 #define NVREG_ADAPTCTL_PHYSHIFT 24
 316         NvRegMIISpeed = 0x18c,
 317 #define NVREG_MIISPEED_BIT8     (1<<8)
 318 #define NVREG_MIIDELAY  5
 319         NvRegMIIControl = 0x190,
 320 #define NVREG_MIICTL_INUSE      0x08000
 321 #define NVREG_MIICTL_WRITE      0x00400
 322 #define NVREG_MIICTL_ADDRSHIFT  5
 323         NvRegMIIData = 0x194,
 324         NvRegWakeUpFlags = 0x200,
 325 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 326 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 327 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 328 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 329 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 330 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 331 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 332 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 333 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 334 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 335 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 336
 337         NvRegPatternCRC = 0x204,
 338         NvRegPatternMask = 0x208,
 339         NvRegPowerCap = 0x268,
 340 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 341 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 342 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 343         NvRegPowerState = 0x26c,
 344 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 345 #define NVREG_POWERSTATE_VALID          0x0100
 346 #define NVREG_POWERSTATE_MASK           0x0003
 347 #define NVREG_POWERSTATE_D0             0x0000
 348 #define NVREG_POWERSTATE_D1             0x0001
 349 #define NVREG_POWERSTATE_D2             0x0002
 350 #define NVREG_POWERSTATE_D3             0x0003
 351         NvRegTxCnt = 0x280,
 352         NvRegTxZeroReXmt = 0x284,
 353         NvRegTxOneReXmt = 0x288,
 354         NvRegTxManyReXmt = 0x28c,
 355         NvRegTxLateCol = 0x290,
 356         NvRegTxUnderflow = 0x294,
 357         NvRegTxLossCarrier = 0x298,
 358         NvRegTxExcessDef = 0x29c,
 359         NvRegTxRetryErr = 0x2a0,
 360         NvRegRxFrameErr = 0x2a4,
 361         NvRegRxExtraByte = 0x2a8,
 362         NvRegRxLateCol = 0x2ac,
 363         NvRegRxRunt = 0x2b0,
 364         NvRegRxFrameTooLong = 0x2b4,
 365         NvRegRxOverflow = 0x2b8,
 366         NvRegRxFCSErr = 0x2bc,
 367         NvRegRxFrameAlignErr = 0x2c0,
 368         NvRegRxLenErr = 0x2c4,
 369         NvRegRxUnicast = 0x2c8,
 370         NvRegRxMulticast = 0x2cc,
 371         NvRegRxBroadcast = 0x2d0,
 372         NvRegTxDef = 0x2d4,
 373         NvRegTxFrame = 0x2d8,
 374         NvRegRxCnt = 0x2dc,
 375         NvRegTxPause = 0x2e0,
 376         NvRegRxPause = 0x2e4,
 377         NvRegRxDropFrame = 0x2e8,
 378         NvRegVlanControl = 0x300,
 379 #define NVREG_VLANCONTROL_ENABLE        0x2000
 380         NvRegMSIXMap0 = 0x3e0,
 381         NvRegMSIXMap1 = 0x3e4,
 382         NvRegMSIXIrqStatus = 0x3f0,
 383
 384         NvRegPowerState2 = 0x600,
 385 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 386 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 387 };
 388
 389 /* Big endian: should work, but is untested */
 390 struct ring_desc {
 391         __le32 buf;
 392         __le32 flaglen;
 393 };
 394
 395 struct ring_desc_ex {
 396         __le32 bufhigh;
 397         __le32 buflow;
 398         __le32 txvlan;
 399         __le32 flaglen;
 400 };
 401
 402 union ring_type {
 403         struct ring_desc* orig;
 404         struct ring_desc_ex* ex;
 405 };
 406
 407 #define FLAG_MASK_V1 0xffff0000
 408 #define FLAG_MASK_V2 0xffffc000
 409 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 410 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 411
 412 #define NV_TX_LASTPACKET        (1<<16)
 413 #define NV_TX_RETRYERROR        (1<<19)
 414 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 415 #define NV_TX_DEFERRED          (1<<26)
 416 #define NV_TX_CARRIERLOST       (1<<27)
 417 #define NV_TX_LATECOLLISION     (1<<28)
 418 #define NV_TX_UNDERFLOW         (1<<29)
 419 #define NV_TX_ERROR             (1<<30)
 420 #define NV_TX_VALID             (1<<31)
 421
 422 #define NV_TX2_LASTPACKET       (1<<29)
 423 #define NV_TX2_RETRYERROR       (1<<18)
 424 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 425 #define NV_TX2_DEFERRED         (1<<25)
 426 #define NV_TX2_CARRIERLOST      (1<<26)
 427 #define NV_TX2_LATECOLLISION    (1<<27)
 428 #define NV_TX2_UNDERFLOW        (1<<28)
 429 /* error and valid are the same for both */
 430 #define NV_TX2_ERROR            (1<<30)
 431 #define NV_TX2_VALID            (1<<31)
 432 #define NV_TX2_TSO              (1<<28)
 433 #define NV_TX2_TSO_SHIFT        14
 434 #define NV_TX2_TSO_MAX_SHIFT    14
 435 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 436 #define NV_TX2_CHECKSUM_L3      (1<<27)
 437 #define NV_TX2_CHECKSUM_L4      (1<<26)
 438
 439 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 440
 441 #define NV_RX_DESCRIPTORVALID   (1<<16)
 442 #define NV_RX_MISSEDFRAME       (1<<17)
 443 #define NV_RX_SUBSTRACT1        (1<<18)
 444 #define NV_RX_ERROR1            (1<<23)
 445 #define NV_RX_ERROR2            (1<<24)
 446 #define NV_RX_ERROR3            (1<<25)
 447 #define NV_RX_ERROR4            (1<<26)
 448 #define NV_RX_CRCERR            (1<<27)
 449 #define NV_RX_OVERFLOW          (1<<28)
 450 #define NV_RX_FRAMINGERR        (1<<29)
 451 #define NV_RX_ERROR             (1<<30)
 452 #define NV_RX_AVAIL             (1<<31)
 453
 454 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 455 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 456 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 457 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 458 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 459 #define NV_RX2_SUBSTRACT1       (1<<25)
 460 #define NV_RX2_ERROR1           (1<<18)
 461 #define NV_RX2_ERROR2           (1<<19)
 462 #define NV_RX2_ERROR3           (1<<20)
 463 #define NV_RX2_ERROR4           (1<<21)
 464 #define NV_RX2_CRCERR           (1<<22)
 465 #define NV_RX2_OVERFLOW         (1<<23)
 466 #define NV_RX2_FRAMINGERR       (1<<24)
 467 /* error and avail are the same for both */
 468 #define NV_RX2_ERROR            (1<<30)
 469 #define NV_RX2_AVAIL            (1<<31)
 470
 471 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 472 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 473
 474 /* Miscelaneous hardware related defines: */
 475 #define NV_PCI_REGSZ_VER1       0x270
 476 #define NV_PCI_REGSZ_VER2       0x604
 477
 478 /* various timeout delays: all in usec */
 479 #define NV_TXRX_RESET_DELAY     4
 480 #define NV_TXSTOP_DELAY1        10
 481 #define NV_TXSTOP_DELAY1MAX     500000
 482 #define NV_TXSTOP_DELAY2        100
 483 #define NV_RXSTOP_DELAY1        10
 484 #define NV_RXSTOP_DELAY1MAX     500000
 485 #define NV_RXSTOP_DELAY2        100
 486 #define NV_SETUP5_DELAY         5
 487 #define NV_SETUP5_DELAYMAX      50000
 488 #define NV_POWERUP_DELAY        5
 489 #define NV_POWERUP_DELAYMAX     5000
 490 #define NV_MIIBUSY_DELAY        50
 491 #define NV_MIIPHY_DELAY 10
 492 #define NV_MIIPHY_DELAYMAX      10000
 493 #define NV_MAC_RESET_DELAY      64
 494
 495 #define NV_WAKEUPPATTERNS       5
 496 #define NV_WAKEUPMASKENTRIES    4
 497
 498 /* General driver defaults */
 499 #define NV_WATCHDOG_TIMEO       (5*HZ)
 500
 501 #define RX_RING_DEFAULT         128
 502 #define TX_RING_DEFAULT         256
 503 #define RX_RING_MIN             128
 504 #define TX_RING_MIN             64
 505 #define RING_MAX_DESC_VER_1     1024
 506 #define RING_MAX_DESC_VER_2_3   16384
 507 /*
 508  * Difference between the get and put pointers for the tx ring.
 509  * This is used to throttle the amount of data outstanding in the
 510  * tx ring.
 511  */
 512 #define TX_LIMIT_DIFFERENCE     1
 513
 514 /* rx/tx mac addr + type + vlan + align + slack*/
 515 #define NV_RX_HEADERS           (64)
 516 /* even more slack. */
 517 #define NV_RX_ALLOC_PAD         (64)
 518
 519 /* maximum mtu size */
 520 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 521 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 522
 523 #define OOM_REFILL      (1+HZ/20)
 524 #define POLL_WAIT       (1+HZ/100)
 525 #define LINK_TIMEOUT    (3*HZ)
 526 #define STATS_INTERVAL  (10*HZ)
 527
 528 /*
 529  * desc_ver values:
 530  * The nic supports three different descriptor types:
 531  * - DESC_VER_1: Original
 532  * - DESC_VER_2: support for jumbo frames.
 533  * - DESC_VER_3: 64-bit format.
 534  */
 535 #define DESC_VER_1      1
 536 #define DESC_VER_2      2
 537 #define DESC_VER_3      3
 538
 539 /* PHY defines */
 540 #define PHY_OUI_MARVELL 0x5043
 541 #define PHY_OUI_CICADA  0x03f1
 542 #define PHYID1_OUI_MASK 0x03ff
 543 #define PHYID1_OUI_SHFT 6
 544 #define PHYID2_OUI_MASK 0xfc00
 545 #define PHYID2_OUI_SHFT 10
 546 #define PHYID2_MODEL_MASK               0x03f0
 547 #define PHY_MODEL_MARVELL_E3016         0x220
 548 #define PHY_MARVELL_E3016_INITMASK      0x0300
 549 #define PHY_INIT1       0x0f000
 550 #define PHY_INIT2       0x0e00
 551 #define PHY_INIT3       0x01000
 552 #define PHY_INIT4       0x0200
 553 #define PHY_INIT5       0x0004
 554 #define PHY_INIT6       0x02000
 555 #define PHY_GIGABIT     0x0100
 556
 557 #define PHY_TIMEOUT     0x1
 558 #define PHY_ERROR       0x2
 559
 560 #define PHY_100 0x1
 561 #define PHY_1000        0x2
 562 #define PHY_HALF        0x100
 563
 564 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 565 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 566 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 567 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 568 #define NV_PAUSEFRAME_RX_REQ     0x0010
 569 #define NV_PAUSEFRAME_TX_REQ     0x0020
 570 #define NV_PAUSEFRAME_AUTONEG    0x0040
 571
 572 /* MSI/MSI-X defines */
 573 #define NV_MSI_X_MAX_VECTORS  8
 574 #define NV_MSI_X_VECTORS_MASK 0x000f
 575 #define NV_MSI_CAPABLE        0x0010
 576 #define NV_MSI_X_CAPABLE      0x0020
 577 #define NV_MSI_ENABLED        0x0040
 578 #define NV_MSI_X_ENABLED      0x0080
 579
 580 #define NV_MSI_X_VECTOR_ALL   0x0
 581 #define NV_MSI_X_VECTOR_RX    0x0
 582 #define NV_MSI_X_VECTOR_TX    0x1
 583 #define NV_MSI_X_VECTOR_OTHER 0x2
 584
 585 /* statistics */
 586 struct nv_ethtool_str {
 587         char name[ETH_GSTRING_LEN];
 588 };
 589
 590 static const struct nv_ethtool_str nv_estats_str[] = {
 591         { "tx_bytes" },
 592         { "tx_zero_rexmt" },
 593         { "tx_one_rexmt" },
 594         { "tx_many_rexmt" },
 595         { "tx_late_collision" },
 596         { "tx_fifo_errors" },
 597         { "tx_carrier_errors" },
 598         { "tx_excess_deferral" },
 599         { "tx_retry_error" },
 600         { "tx_deferral" },
 601         { "tx_packets" },
 602         { "tx_pause" },
 603         { "rx_frame_error" },
 604         { "rx_extra_byte" },
 605         { "rx_late_collision" },
 606         { "rx_runt" },
 607         { "rx_frame_too_long" },
 608         { "rx_over_errors" },
 609         { "rx_crc_errors" },
 610         { "rx_frame_align_error" },
 611         { "rx_length_error" },
 612         { "rx_unicast" },
 613         { "rx_multicast" },
 614         { "rx_broadcast" },
 615         { "rx_bytes" },
 616         { "rx_pause" },
 617         { "rx_drop_frame" },
 618         { "rx_packets" },
 619         { "rx_errors_total" }
 620 };
 621
 622 struct nv_ethtool_stats {
 623         u64 tx_bytes;
 624         u64 tx_zero_rexmt;
 625         u64 tx_one_rexmt;
 626         u64 tx_many_rexmt;
 627         u64 tx_late_collision;
 628         u64 tx_fifo_errors;
 629         u64 tx_carrier_errors;
 630         u64 tx_excess_deferral;
 631         u64 tx_retry_error;
 632         u64 tx_deferral;
 633         u64 tx_packets;
 634         u64 tx_pause;
 635         u64 rx_frame_error;
 636         u64 rx_extra_byte;
 637         u64 rx_late_collision;
 638         u64 rx_runt;
 639         u64 rx_frame_too_long;
 640         u64 rx_over_errors;
 641         u64 rx_crc_errors;
 642         u64 rx_frame_align_error;
 643         u64 rx_length_error;
 644         u64 rx_unicast;
 645         u64 rx_multicast;
 646         u64 rx_broadcast;
 647         u64 rx_bytes;
 648         u64 rx_pause;
 649         u64 rx_drop_frame;
 650         u64 rx_packets;
 651         u64 rx_errors_total;
 652 };
 653
 654 /* diagnostics */
 655 #define NV_TEST_COUNT_BASE 3
 656 #define NV_TEST_COUNT_EXTENDED 4
 657
 658 static const struct nv_ethtool_str nv_etests_str[] = {
 659         { "link      (online/offline)" },
 660         { "register  (offline)       " },
 661         { "interrupt (offline)       " },
 662         { "loopback  (offline)       " }
 663 };
 664
 665 struct register_test {
 666         __le32 reg;
 667         __le32 mask;
 668 };
 669
 670 static const struct register_test nv_registers_test[] = {
 671         { NvRegUnknownSetupReg6, 0x01 },
 672         { NvRegMisc1, 0x03c },
 673         { NvRegOffloadConfig, 0x03ff },
 674         { NvRegMulticastAddrA, 0xffffffff },
 675         { NvRegTxWatermark, 0x0ff },
 676         { NvRegWakeUpFlags, 0x07777 },
 677         { 0,0 }
 678 };
 679
 680 /*
 681  * SMP locking:
 682  * All hardware access under dev->priv->lock, except the performance
 683  * critical parts:
 684  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 685  *      by the arch code for interrupts.
 686  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 687  *      needs dev->priv->lock :-(
 688  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 689  */
 690
 691 /* in dev: base, irq */
 692 struct fe_priv {
 693         spinlock_t lock;
 694
 695         /* General data:
 696          * Locking: spin_lock(&np->lock); */
 697         struct net_device_stats stats;
 698         struct nv_ethtool_stats estats;
 699         int in_shutdown;
 700         u32 linkspeed;
 701         int duplex;
 702         int autoneg;
 703         int fixed_mode;
 704         int phyaddr;
 705         int wolenabled;
 706         unsigned int phy_oui;
 707         unsigned int phy_model;
 708         u16 gigabit;
 709         int intr_test;
 710
 711         /* General data: RO fields */
 712         dma_addr_t ring_addr;
 713         struct pci_dev *pci_dev;
 714         u32 orig_mac[2];
 715         u32 irqmask;
 716         u32 desc_ver;
 717         u32 txrxctl_bits;
 718         u32 vlanctl_bits;
 719         u32 driver_data;
 720         u32 register_size;
 721         int rx_csum;
 722
 723         void __iomem *base;
 724
 725         /* rx specific fields.
 726          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 727          */
 728         union ring_type rx_ring;
 729         unsigned int cur_rx, refill_rx;
 730         struct sk_buff **rx_skbuff;
 731         dma_addr_t *rx_dma;
 732         unsigned int rx_buf_sz;
 733         unsigned int pkt_limit;
 734         struct timer_list oom_kick;
 735         struct timer_list nic_poll;
 736         struct timer_list stats_poll;
 737         u32 nic_poll_irq;
 738         int rx_ring_size;
 739
 740         /* media detection workaround.
 741          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 742          */
 743         int need_linktimer;
 744         unsigned long link_timeout;
 745         /*
 746          * tx specific fields.
 747          */
 748         union ring_type tx_ring;
 749         unsigned int next_tx, nic_tx;
 750         struct sk_buff **tx_skbuff;
 751         dma_addr_t *tx_dma;
 752         unsigned int *tx_dma_len;
 753         u32 tx_flags;
 754         int tx_ring_size;
 755         int tx_limit_start;
 756         int tx_limit_stop;
 757
 758         /* vlan fields */
 759         struct vlan_group *vlangrp;
 760
 761         /* msi/msi-x fields */
 762         u32 msi_flags;
 763         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 764
 765         /* flow control */
 766         u32 pause_flags;
 767 };
 768
 769 /*
 770  * Maximum number of loops until we assume that a bit in the irq mask
 771  * is stuck. Overridable with module param.
 772  */
 773 static int max_interrupt_work = 5;
 774
 775 /*
 776  * Optimization can be either throuput mode or cpu mode
 777  *
 778  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 779  * CPU Mode: Interrupts are controlled by a timer.
 780  */
 781 enum {
 782         NV_OPTIMIZATION_MODE_THROUGHPUT,
 783         NV_OPTIMIZATION_MODE_CPU
 784 };
 785 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 786
 787 /*
 788  * Poll interval for timer irq
 789  *
 790  * This interval determines how frequent an interrupt is generated.
 791  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 792  * Min = 0, and Max = 65535
 793  */
 794 static int poll_interval = -1;
 795
 796 /*
 797  * MSI interrupts
 798  */
 799 enum {
 800         NV_MSI_INT_DISABLED,
 801         NV_MSI_INT_ENABLED
 802 };
 803 static int msi = NV_MSI_INT_ENABLED;
 804
 805 /*
 806  * MSIX interrupts
 807  */
 808 enum {
 809         NV_MSIX_INT_DISABLED,
 810         NV_MSIX_INT_ENABLED
 811 };
 812 static int msix = NV_MSIX_INT_ENABLED;
 813
 814 /*
 815  * DMA 64bit
 816  */
 817 enum {
 818         NV_DMA_64BIT_DISABLED,
 819         NV_DMA_64BIT_ENABLED
 820 };
 821 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 822
 823 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 824 {
 825         return netdev_priv(dev);
 826 }
 827
 828 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 829 {
 830         return ((struct fe_priv *)netdev_priv(dev))->base;
 831 }
 832
 833 static inline void pci_push(u8 __iomem *base)
 834 {
 835         /* force out pending posted writes */
 836         readl(base);
 837 }
 838
 839 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 840 {
 841         return le32_to_cpu(prd->flaglen)
 842                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 843 }
 844
 845 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 846 {
 847         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 848 }
 849
 850 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 851                                 int delay, int delaymax, const char *msg)
 852 {
 853         u8 __iomem *base = get_hwbase(dev);
 854
 855         pci_push(base);
 856         do {
 857                 udelay(delay);
 858                 delaymax -= delay;
 859                 if (delaymax < 0) {
 860                         if (msg)
 861                                 printk(msg);
 862                         return 1;
 863                 }
 864         } while ((readl(base + offset) & mask) != target);
 865         return 0;
 866 }
 867
 868 #define NV_SETUP_RX_RING 0x01
 869 #define NV_SETUP_TX_RING 0x02
 870
 871 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 872 {
 873         struct fe_priv *np = get_nvpriv(dev);
 874         u8 __iomem *base = get_hwbase(dev);
 875
 876         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 877                 if (rxtx_flags & NV_SETUP_RX_RING) {
 878                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 879                 }
 880                 if (rxtx_flags & NV_SETUP_TX_RING) {
 881                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 882                 }
 883         } else {
 884                 if (rxtx_flags & NV_SETUP_RX_RING) {
 885                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 886                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 887                 }
 888                 if (rxtx_flags & NV_SETUP_TX_RING) {
 889                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 890                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 891                 }
 892         }
 893 }
 894
 895 static void free_rings(struct net_device *dev)
 896 {
 897         struct fe_priv *np = get_nvpriv(dev);
 898
 899         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 900                 if (np->rx_ring.orig)
 901                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 902                                             np->rx_ring.orig, np->ring_addr);
 903         } else {
 904                 if (np->rx_ring.ex)
 905                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 906                                             np->rx_ring.ex, np->ring_addr);
 907         }
 908         if (np->rx_skbuff)
 909                 kfree(np->rx_skbuff);
 910         if (np->rx_dma)
 911                 kfree(np->rx_dma);
 912         if (np->tx_skbuff)
 913                 kfree(np->tx_skbuff);
 914         if (np->tx_dma)
 915                 kfree(np->tx_dma);
 916         if (np->tx_dma_len)
 917                 kfree(np->tx_dma_len);
 918 }
 919
 920 static int using_multi_irqs(struct net_device *dev)
 921 {
 922         struct fe_priv *np = get_nvpriv(dev);
 923
 924         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 925             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 926              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 927                 return 0;
 928         else
 929                 return 1;
 930 }
 931
 932 static void nv_enable_irq(struct net_device *dev)
 933 {
 934         struct fe_priv *np = get_nvpriv(dev);
 935
 936         if (!using_multi_irqs(dev)) {
 937                 if (np->msi_flags & NV_MSI_X_ENABLED)
 938                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 939                 else
 940                         enable_irq(dev->irq);
 941         } else {
 942                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 943                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 944                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 945         }
 946 }
 947
 948 static void nv_disable_irq(struct net_device *dev)
 949 {
 950         struct fe_priv *np = get_nvpriv(dev);
 951
 952         if (!using_multi_irqs(dev)) {
 953                 if (np->msi_flags & NV_MSI_X_ENABLED)
 954                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 955                 else
 956                         disable_irq(dev->irq);
 957         } else {
 958                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 959                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 960                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 961         }
 962 }
 963
 964 /* In MSIX mode, a write to irqmask behaves as XOR */
 965 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 966 {
 967         u8 __iomem *base = get_hwbase(dev);
 968
 969         writel(mask, base + NvRegIrqMask);
 970 }
 971
 972 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 973 {
 974         struct fe_priv *np = get_nvpriv(dev);
 975         u8 __iomem *base = get_hwbase(dev);
 976
 977         if (np->msi_flags & NV_MSI_X_ENABLED) {
 978                 writel(mask, base + NvRegIrqMask);
 979         } else {
 980                 if (np->msi_flags & NV_MSI_ENABLED)
 981                         writel(0, base + NvRegMSIIrqMask);
 982                 writel(0, base + NvRegIrqMask);
 983         }
 984 }
 985
 986 #define MII_READ        (-1)
 987 /* mii_rw: read/write a register on the PHY.
 988  *
 989  * Caller must guarantee serialization
 990  */
 991 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 992 {
 993         u8 __iomem *base = get_hwbase(dev);
 994         u32 reg;
 995         int retval;
 996
 997         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 998
 999         reg = readl(base + NvRegMIIControl);
1000         if (reg & NVREG_MIICTL_INUSE) {
1001                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1002                 udelay(NV_MIIBUSY_DELAY);
1003         }
1004
1005         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1006         if (value != MII_READ) {
1007                 writel(value, base + NvRegMIIData);
1008                 reg |= NVREG_MIICTL_WRITE;
1009         }
1010         writel(reg, base + NvRegMIIControl);
1011
1012         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1013                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1014                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1015                                 dev->name, miireg, addr);
1016                 retval = -1;
1017         } else if (value != MII_READ) {
1018                 /* it was a write operation - fewer failures are detectable */
1019                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1020                                 dev->name, value, miireg, addr);
1021                 retval = 0;
1022         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1023                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1024                                 dev->name, miireg, addr);
1025                 retval = -1;
1026         } else {
1027                 retval = readl(base + NvRegMIIData);
1028                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1029                                 dev->name, miireg, addr, retval);
1030         }
1031
1032         return retval;
1033 }
1034
1035 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1036 {
1037         struct fe_priv *np = netdev_priv(dev);
1038         u32 miicontrol;
1039         unsigned int tries = 0;
1040
1041         miicontrol = BMCR_RESET | bmcr_setup;
1042         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1043                 return -1;
1044         }
1045
1046         /* wait for 500ms */
1047         msleep(500);
1048
1049         /* must wait till reset is deasserted */
1050         while (miicontrol & BMCR_RESET) {
1051                 msleep(10);
1052                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1053                 /* FIXME: 100 tries seem excessive */
1054                 if (tries++ > 100)
1055                         return -1;
1056         }
1057         return 0;
1058 }
1059
1060 static int phy_init(struct net_device *dev)
1061 {
1062         struct fe_priv *np = get_nvpriv(dev);
1063         u8 __iomem *base = get_hwbase(dev);
1064         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1065
1066         /* phy errata for E3016 phy */
1067         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1068                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1069                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1070                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1071                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1072                         return PHY_ERROR;
1073                 }
1074         }
1075
1076         /* set advertise register */
1077         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1078         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1079         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1080                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1081                 return PHY_ERROR;
1082         }
1083
1084         /* get phy interface type */
1085         phyinterface = readl(base + NvRegPhyInterface);
1086
1087         /* see if gigabit phy */
1088         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1089         if (mii_status & PHY_GIGABIT) {
1090                 np->gigabit = PHY_GIGABIT;
1091                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1092                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1093                 if (phyinterface & PHY_RGMII)
1094                         mii_control_1000 |= ADVERTISE_1000FULL;
1095                 else
1096                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1097
1098                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1099                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1100                         return PHY_ERROR;
1101                 }
1102         }
1103         else
1104                 np->gigabit = 0;
1105
1106         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1107         mii_control |= BMCR_ANENABLE;
1108
1109         /* reset the phy
1110          * (certain phys need bmcr to be setup with reset)
1111          */
1112         if (phy_reset(dev, mii_control)) {
1113                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1114                 return PHY_ERROR;
1115         }
1116
1117         /* phy vendor specific configuration */
1118         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1119                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1120                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1121                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1122                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1123                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1124                         return PHY_ERROR;
1125                 }
1126                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1127                 phy_reserved |= PHY_INIT5;
1128                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1129                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1130                         return PHY_ERROR;
1131                 }
1132         }
1133         if (np->phy_oui == PHY_OUI_CICADA) {
1134                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1135                 phy_reserved |= PHY_INIT6;
1136                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1137                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1138                         return PHY_ERROR;
1139                 }
1140         }
1141         /* some phys clear out pause advertisment on reset, set it back */
1142         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1143
1144         /* restart auto negotiation */
1145         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1146         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1147         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1148                 return PHY_ERROR;
1149         }
1150
1151         return 0;
1152 }
1153
1154 static void nv_start_rx(struct net_device *dev)
1155 {
1156         struct fe_priv *np = netdev_priv(dev);
1157         u8 __iomem *base = get_hwbase(dev);
1158
1159         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1160         /* Already running? Stop it. */
1161         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1162                 writel(0, base + NvRegReceiverControl);
1163                 pci_push(base);
1164         }
1165         writel(np->linkspeed, base + NvRegLinkSpeed);
1166         pci_push(base);
1167         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1168         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1169                                 dev->name, np->duplex, np->linkspeed);
1170         pci_push(base);
1171 }
1172
1173 static void nv_stop_rx(struct net_device *dev)
1174 {
1175         u8 __iomem *base = get_hwbase(dev);
1176
1177         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1178         writel(0, base + NvRegReceiverControl);
1179         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1180                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1181                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1182
1183         udelay(NV_RXSTOP_DELAY2);
1184         writel(0, base + NvRegLinkSpeed);
1185 }
1186
1187 static void nv_start_tx(struct net_device *dev)
1188 {
1189         u8 __iomem *base = get_hwbase(dev);
1190
1191         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1192         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1193         pci_push(base);
1194 }
1195
1196 static void nv_stop_tx(struct net_device *dev)
1197 {
1198         u8 __iomem *base = get_hwbase(dev);
1199
1200         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1201         writel(0, base + NvRegTransmitterControl);
1202         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1203                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1204                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1205
1206         udelay(NV_TXSTOP_DELAY2);
1207         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
1208 }
1209
1210 static void nv_txrx_reset(struct net_device *dev)
1211 {
1212         struct fe_priv *np = netdev_priv(dev);
1213         u8 __iomem *base = get_hwbase(dev);
1214
1215         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1216         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1217         pci_push(base);
1218         udelay(NV_TXRX_RESET_DELAY);
1219         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1220         pci_push(base);
1221 }
1222
1223 static void nv_mac_reset(struct net_device *dev)
1224 {
1225         struct fe_priv *np = netdev_priv(dev);
1226         u8 __iomem *base = get_hwbase(dev);
1227
1228         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1229         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1230         pci_push(base);
1231         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1232         pci_push(base);
1233         udelay(NV_MAC_RESET_DELAY);
1234         writel(0, base + NvRegMacReset);
1235         pci_push(base);
1236         udelay(NV_MAC_RESET_DELAY);
1237         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1238         pci_push(base);
1239 }
1240
1241 /*
1242  * nv_get_stats: dev->get_stats function
1243  * Get latest stats value from the nic.
1244  * Called with read_lock(&dev_base_lock) held for read -
1245  * only synchronized against unregister_netdevice.
1246  */
1247 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1248 {
1249         struct fe_priv *np = netdev_priv(dev);
1250
1251         /* It seems that the nic always generates interrupts and doesn't
1252          * accumulate errors internally. Thus the current values in np->stats
1253          * are already up to date.
1254          */
1255         return &np->stats;
1256 }
1257
1258 /*
1259  * nv_alloc_rx: fill rx ring entries.
1260  * Return 1 if the allocations for the skbs failed and the
1261  * rx engine is without Available descriptors
1262  */
1263 static int nv_alloc_rx(struct net_device *dev)
1264 {
1265         struct fe_priv *np = netdev_priv(dev);
1266         unsigned int refill_rx = np->refill_rx;
1267         int nr;
1268
1269         while (np->cur_rx != refill_rx) {
1270                 struct sk_buff *skb;
1271
1272                 nr = refill_rx % np->rx_ring_size;
1273                 if (np->rx_skbuff[nr] == NULL) {
1274
1275                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1276                         if (!skb)
1277                                 break;
1278
1279                         skb->dev = dev;
1280                         np->rx_skbuff[nr] = skb;
1281                 } else {
1282                         skb = np->rx_skbuff[nr];
1283                 }
1284                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1285                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1286                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1287                         np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
1288                         wmb();
1289                         np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1290                 } else {
1291                         np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1292                         np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1293                         wmb();
1294                         np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1295                 }
1296                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1297                                         dev->name, refill_rx);
1298                 refill_rx++;
1299         }
1300         np->refill_rx = refill_rx;
1301         if (np->cur_rx - refill_rx == np->rx_ring_size)
1302                 return 1;
1303         return 0;
1304 }
1305
1306 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1307 #ifdef CONFIG_FORCEDETH_NAPI
1308 static void nv_do_rx_refill(unsigned long data)
1309 {
1310         struct net_device *dev = (struct net_device *) data;
1311
1312         /* Just reschedule NAPI rx processing */
1313         netif_rx_schedule(dev);
1314 }
1315 #else
1316 static void nv_do_rx_refill(unsigned long data)
1317 {
1318         struct net_device *dev = (struct net_device *) data;
1319         struct fe_priv *np = netdev_priv(dev);
1320
1321         if (!using_multi_irqs(dev)) {
1322                 if (np->msi_flags & NV_MSI_X_ENABLED)
1323                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1324                 else
1325                         disable_irq(dev->irq);
1326         } else {
1327                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1328         }
1329         if (nv_alloc_rx(dev)) {
1330                 spin_lock_irq(&np->lock);
1331                 if (!np->in_shutdown)
1332                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1333                 spin_unlock_irq(&np->lock);
1334         }
1335         if (!using_multi_irqs(dev)) {
1336                 if (np->msi_flags & NV_MSI_X_ENABLED)
1337                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1338                 else
1339                         enable_irq(dev->irq);
1340         } else {
1341                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1342         }
1343 }
1344 #endif
1345
1346 static void nv_init_rx(struct net_device *dev)
1347 {
1348         struct fe_priv *np = netdev_priv(dev);
1349         int i;
1350
1351         np->cur_rx = np->rx_ring_size;
1352         np->refill_rx = 0;
1353         for (i = 0; i < np->rx_ring_size; i++)
1354                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1355                         np->rx_ring.orig[i].flaglen = 0;
1356                 else
1357                         np->rx_ring.ex[i].flaglen = 0;
1358 }
1359
1360 static void nv_init_tx(struct net_device *dev)
1361 {
1362         struct fe_priv *np = netdev_priv(dev);
1363         int i;
1364
1365         np->next_tx = np->nic_tx = 0;
1366         for (i = 0; i < np->tx_ring_size; i++) {
1367                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1368                         np->tx_ring.orig[i].flaglen = 0;
1369                 else
1370                         np->tx_ring.ex[i].flaglen = 0;
1371                 np->tx_skbuff[i] = NULL;
1372                 np->tx_dma[i] = 0;
1373         }
1374 }
1375
1376 static int nv_init_ring(struct net_device *dev)
1377 {
1378         nv_init_tx(dev);
1379         nv_init_rx(dev);
1380         return nv_alloc_rx(dev);
1381 }
1382
1383 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1384 {
1385         struct fe_priv *np = netdev_priv(dev);
1386
1387         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1388                 dev->name, skbnr);
1389
1390         if (np->tx_dma[skbnr]) {
1391                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1392                                np->tx_dma_len[skbnr],
1393                                PCI_DMA_TODEVICE);
1394                 np->tx_dma[skbnr] = 0;
1395         }
1396
1397         if (np->tx_skbuff[skbnr]) {
1398                 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1399                 np->tx_skbuff[skbnr] = NULL;
1400                 return 1;
1401         } else {
1402                 return 0;
1403         }
1404 }
1405
1406 static void nv_drain_tx(struct net_device *dev)
1407 {
1408         struct fe_priv *np = netdev_priv(dev);
1409         unsigned int i;
1410
1411         for (i = 0; i < np->tx_ring_size; i++) {
1412                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1413                         np->tx_ring.orig[i].flaglen = 0;
1414                 else
1415                         np->tx_ring.ex[i].flaglen = 0;
1416                 if (nv_release_txskb(dev, i))
1417                         np->stats.tx_dropped++;
1418         }
1419 }
1420
1421 static void nv_drain_rx(struct net_device *dev)
1422 {
1423         struct fe_priv *np = netdev_priv(dev);
1424         int i;
1425         for (i = 0; i < np->rx_ring_size; i++) {
1426                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1427                         np->rx_ring.orig[i].flaglen = 0;
1428                 else
1429                         np->rx_ring.ex[i].flaglen = 0;
1430                 wmb();
1431                 if (np->rx_skbuff[i]) {
1432                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1433                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1434                                                 PCI_DMA_FROMDEVICE);
1435                         dev_kfree_skb(np->rx_skbuff[i]);
1436                         np->rx_skbuff[i] = NULL;
1437                 }
1438         }
1439 }
1440
1441 static void drain_ring(struct net_device *dev)
1442 {
1443         nv_drain_tx(dev);
1444         nv_drain_rx(dev);
1445 }
1446
1447 /*
1448  * nv_start_xmit: dev->hard_start_xmit function
1449  * Called with netif_tx_lock held.
1450  */
1451 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1452 {
1453         struct fe_priv *np = netdev_priv(dev);
1454         u32 tx_flags = 0;
1455         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1456         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1457         unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1458         unsigned int start_nr = np->next_tx % np->tx_ring_size;
1459         unsigned int i;
1460         u32 offset = 0;
1461         u32 bcnt;
1462         u32 size = skb->len-skb->data_len;
1463         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1464         u32 tx_flags_vlan = 0;
1465
1466         /* add fragments to entries count */
1467         for (i = 0; i < fragments; i++) {
1468                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1469                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1470         }
1471
1472         spin_lock_irq(&np->lock);
1473
1474         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1475                 spin_unlock_irq(&np->lock);
1476                 netif_stop_queue(dev);
1477                 return NETDEV_TX_BUSY;
1478         }
1479
1480         /* setup the header buffer */
1481         do {
1482                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1483                 nr = (nr + 1) % np->tx_ring_size;
1484
1485                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1486                                                 PCI_DMA_TODEVICE);
1487                 np->tx_dma_len[nr] = bcnt;
1488
1489                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1490                         np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1491                         np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1492                 } else {
1493                         np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1494                         np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1495                         np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1496                 }
1497                 tx_flags = np->tx_flags;
1498                 offset += bcnt;
1499                 size -= bcnt;
1500         } while (size);
1501
1502         /* setup the fragments */
1503         for (i = 0; i < fragments; i++) {
1504                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1505                 u32 size = frag->size;
1506                 offset = 0;
1507
1508                 do {
1509                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1510                         nr = (nr + 1) % np->tx_ring_size;
1511
1512                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1513                                                       PCI_DMA_TODEVICE);
1514                         np->tx_dma_len[nr] = bcnt;
1515
1516                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1517                                 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1518                                 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1519                         } else {
1520                                 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1521                                 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1522                                 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1523                         }
1524                         offset += bcnt;
1525                         size -= bcnt;
1526                 } while (size);
1527         }
1528
1529         /* set last fragment flag  */
1530         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1531                 np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1532         } else {
1533                 np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1534         }
1535
1536         np->tx_skbuff[nr] = skb;
1537
1538 #ifdef NETIF_F_TSO
1539         if (skb_is_gso(skb))
1540                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1541         else
1542 #endif
1543         tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1544
1545         /* vlan tag */
1546         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1547                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1548         }
1549
1550         /* set tx flags */
1551         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1552                 np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1553         } else {
1554                 np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
1555                 np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1556         }
1557
1558         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1559                 dev->name, np->next_tx, entries, tx_flags_extra);
1560         {
1561                 int j;
1562                 for (j=0; j<64; j++) {
1563                         if ((j%16) == 0)
1564                                 dprintk("\n%03x:", j);
1565                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1566                 }
1567                 dprintk("\n");
1568         }
1569
1570         np->next_tx += entries;
1571
1572         dev->trans_start = jiffies;
1573         spin_unlock_irq(&np->lock);
1574         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1575         pci_push(get_hwbase(dev));
1576         return NETDEV_TX_OK;
1577 }
1578
1579 /*
1580  * nv_tx_done: check for completed packets, release the skbs.
1581  *
1582  * Caller must own np->lock.
1583  */
1584 static void nv_tx_done(struct net_device *dev)
1585 {
1586         struct fe_priv *np = netdev_priv(dev);
1587         u32 flags;
1588         unsigned int i;
1589         struct sk_buff *skb;
1590
1591         while (np->nic_tx != np->next_tx) {
1592                 i = np->nic_tx % np->tx_ring_size;
1593
1594                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1595                         flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
1596                 else
1597                         flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
1598
1599                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1600                                         dev->name, np->nic_tx, flags);
1601                 if (flags & NV_TX_VALID)
1602                         break;
1603                 if (np->desc_ver == DESC_VER_1) {
1604                         if (flags & NV_TX_LASTPACKET) {
1605                                 skb = np->tx_skbuff[i];
1606                                 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1607                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1608                                         if (flags & NV_TX_UNDERFLOW)
1609                                                 np->stats.tx_fifo_errors++;
1610                                         if (flags & NV_TX_CARRIERLOST)
1611                                                 np->stats.tx_carrier_errors++;
1612                                         np->stats.tx_errors++;
1613                                 } else {
1614                                         np->stats.tx_packets++;
1615                                         np->stats.tx_bytes += skb->len;
1616                                 }
1617                         }
1618                 } else {
1619                         if (flags & NV_TX2_LASTPACKET) {
1620                                 skb = np->tx_skbuff[i];
1621                                 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1622                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1623                                         if (flags & NV_TX2_UNDERFLOW)
1624                                                 np->stats.tx_fifo_errors++;
1625                                         if (flags & NV_TX2_CARRIERLOST)
1626                                                 np->stats.tx_carrier_errors++;
1627                                         np->stats.tx_errors++;
1628                                 } else {
1629                                         np->stats.tx_packets++;
1630                                         np->stats.tx_bytes += skb->len;
1631                                 }
1632                         }
1633                 }
1634                 nv_release_txskb(dev, i);
1635                 np->nic_tx++;
1636         }
1637         if (np->next_tx - np->nic_tx < np->tx_limit_start)
1638                 netif_wake_queue(dev);
1639 }
1640
1641 /*
1642  * nv_tx_timeout: dev->tx_timeout function
1643  * Called with netif_tx_lock held.
1644  */
1645 static void nv_tx_timeout(struct net_device *dev)
1646 {
1647         struct fe_priv *np = netdev_priv(dev);
1648         u8 __iomem *base = get_hwbase(dev);
1649         u32 status;
1650
1651         if (np->msi_flags & NV_MSI_X_ENABLED)
1652                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1653         else
1654                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1655
1656         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1657
1658         {
1659                 int i;
1660
1661                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1662                                 dev->name, (unsigned long)np->ring_addr,
1663                                 np->next_tx, np->nic_tx);
1664                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1665                 for (i=0;i<=np->register_size;i+= 32) {
1666                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1667                                         i,
1668                                         readl(base + i + 0), readl(base + i + 4),
1669                                         readl(base + i + 8), readl(base + i + 12),
1670                                         readl(base + i + 16), readl(base + i + 20),
1671                                         readl(base + i + 24), readl(base + i + 28));
1672                 }
1673                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1674                 for (i=0;i<np->tx_ring_size;i+= 4) {
1675                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1676                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1677                                        i,
1678                                        le32_to_cpu(np->tx_ring.orig[i].buf),
1679                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
1680                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
1681                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1682                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
1683                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1684                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
1685                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1686                         } else {
1687                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1688                                        i,
1689                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1690                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
1691                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
1692                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1693                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1694                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1695                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1696                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1697                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1698                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1699                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1700                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1701                         }
1702                 }
1703         }
1704
1705         spin_lock_irq(&np->lock);
1706
1707         /* 1) stop tx engine */
1708         nv_stop_tx(dev);
1709
1710         /* 2) check that the packets were not sent already: */
1711         nv_tx_done(dev);
1712
1713         /* 3) if there are dead entries: clear everything */
1714         if (np->next_tx != np->nic_tx) {
1715                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1716                 nv_drain_tx(dev);
1717                 np->next_tx = np->nic_tx = 0;
1718                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1719                 netif_wake_queue(dev);
1720         }
1721
1722         /* 4) restart tx engine */
1723         nv_start_tx(dev);
1724         spin_unlock_irq(&np->lock);
1725 }
1726
1727 /*
1728  * Called when the nic notices a mismatch between the actual data len on the
1729  * wire and the len indicated in the 802 header
1730  */
1731 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1732 {
1733         int hdrlen;     /* length of the 802 header */
1734         int protolen;   /* length as stored in the proto field */
1735
1736         /* 1) calculate len according to header */
1737         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1738                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1739                 hdrlen = VLAN_HLEN;
1740         } else {
1741                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1742                 hdrlen = ETH_HLEN;
1743         }
1744         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1745                                 dev->name, datalen, protolen, hdrlen);
1746         if (protolen > ETH_DATA_LEN)
1747                 return datalen; /* Value in proto field not a len, no checks possible */
1748
1749         protolen += hdrlen;
1750         /* consistency checks: */
1751         if (datalen > ETH_ZLEN) {
1752                 if (datalen >= protolen) {
1753                         /* more data on wire than in 802 header, trim of
1754                          * additional data.
1755                          */
1756                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1757                                         dev->name, protolen);
1758                         return protolen;
1759                 } else {
1760                         /* less data on wire than mentioned in header.
1761                          * Discard the packet.
1762                          */
1763                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1764                                         dev->name);
1765                         return -1;
1766                 }
1767         } else {
1768                 /* short packet. Accept only if 802 values are also short */
1769                 if (protolen > ETH_ZLEN) {
1770                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1771                                         dev->name);
1772                         return -1;
1773                 }
1774                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1775                                 dev->name, datalen);
1776                 return datalen;
1777         }
1778 }
1779
1780 static int nv_rx_process(struct net_device *dev, int limit)
1781 {
1782         struct fe_priv *np = netdev_priv(dev);
1783         u32 flags;
1784         u32 vlanflags = 0;
1785         int count;
1786
1787         for (count = 0; count < limit; ++count) {
1788                 struct sk_buff *skb;
1789                 int len;
1790                 int i;
1791                 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1792                         break;  /* we scanned the whole ring - do not continue */
1793
1794                 i = np->cur_rx % np->rx_ring_size;
1795                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1796                         flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
1797                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1798                 } else {
1799                         flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
1800                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1801                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
1802                 }
1803
1804                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1805                                         dev->name, np->cur_rx, flags);
1806
1807                 if (flags & NV_RX_AVAIL)
1808                         break;  /* still owned by hardware, */
1809
1810                 /*
1811                  * the packet is for us - immediately tear down the pci mapping.
1812                  * TODO: check if a prefetch of the first cacheline improves
1813                  * the performance.
1814                  */
1815                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1816                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1817                                 PCI_DMA_FROMDEVICE);
1818
1819                 {
1820                         int j;
1821                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1822                         for (j=0; j<64; j++) {
1823                                 if ((j%16) == 0)
1824                                         dprintk("\n%03x:", j);
1825                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1826                         }
1827                         dprintk("\n");
1828                 }
1829                 /* look at what we actually got: */
1830                 if (np->desc_ver == DESC_VER_1) {
1831                         if (!(flags & NV_RX_DESCRIPTORVALID))
1832                                 goto next_pkt;
1833
1834                         if (flags & NV_RX_ERROR) {
1835                                 if (flags & NV_RX_MISSEDFRAME) {
1836                                         np->stats.rx_missed_errors++;
1837                                         np->stats.rx_errors++;
1838                                         goto next_pkt;
1839                                 }
1840                                 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1841                                         np->stats.rx_errors++;
1842                                         goto next_pkt;
1843                                 }
1844                                 if (flags & NV_RX_CRCERR) {
1845                                         np->stats.rx_crc_errors++;
1846                                         np->stats.rx_errors++;
1847                                         goto next_pkt;
1848                                 }
1849                                 if (flags & NV_RX_OVERFLOW) {
1850                                         np->stats.rx_over_errors++;
1851                                         np->stats.rx_errors++;
1852                                         goto next_pkt;
1853                                 }
1854                                 if (flags & NV_RX_ERROR4) {
1855                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1856                                         if (len < 0) {
1857                                                 np->stats.rx_errors++;
1858                                                 goto next_pkt;
1859                                         }
1860                                 }
1861                                 /* framing errors are soft errors. */
1862                                 if (flags & NV_RX_FRAMINGERR) {
1863                                         if (flags & NV_RX_SUBSTRACT1) {
1864                                                 len--;
1865                                         }
1866                                 }
1867                         }
1868                 } else {
1869                         if (!(flags & NV_RX2_DESCRIPTORVALID))
1870                                 goto next_pkt;
1871
1872                         if (flags & NV_RX2_ERROR) {
1873                                 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1874                                         np->stats.rx_errors++;
1875                                         goto next_pkt;
1876                                 }
1877                                 if (flags & NV_RX2_CRCERR) {
1878                                         np->stats.rx_crc_errors++;
1879                                         np->stats.rx_errors++;
1880                                         goto next_pkt;
1881                                 }
1882                                 if (flags & NV_RX2_OVERFLOW) {
1883                                         np->stats.rx_over_errors++;
1884                                         np->stats.rx_errors++;
1885                                         goto next_pkt;
1886                                 }
1887                                 if (flags & NV_RX2_ERROR4) {
1888                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1889                                         if (len < 0) {
1890                                                 np->stats.rx_errors++;
1891                                                 goto next_pkt;
1892                                         }
1893                                 }
1894                                 /* framing errors are soft errors */
1895                                 if (flags & NV_RX2_FRAMINGERR) {
1896                                         if (flags & NV_RX2_SUBSTRACT1) {
1897                                                 len--;
1898                                         }
1899                                 }
1900                         }
1901                         if (np->rx_csum) {
1902                                 flags &= NV_RX2_CHECKSUMMASK;
1903                                 if (flags == NV_RX2_CHECKSUMOK1 ||
1904                                     flags == NV_RX2_CHECKSUMOK2 ||
1905                                     flags == NV_RX2_CHECKSUMOK3) {
1906                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1907                                         np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1908                                 } else {
1909                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1910                                 }
1911                         }
1912                 }
1913                 /* got a valid packet - forward it to the network core */
1914                 skb = np->rx_skbuff[i];
1915                 np->rx_skbuff[i] = NULL;
1916
1917                 skb_put(skb, len);
1918                 skb->protocol = eth_type_trans(skb, dev);
1919                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1920                                         dev->name, np->cur_rx, len, skb->protocol);
1921 #ifdef CONFIG_FORCEDETH_NAPI
1922                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1923                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
1924                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
1925                 else
1926                         netif_receive_skb(skb);
1927 #else
1928                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
1929                         vlan_hwaccel_rx(skb, np->vlangrp,
1930                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
1931                 else
1932                         netif_rx(skb);
1933 #endif
1934                 dev->last_rx = jiffies;
1935                 np->stats.rx_packets++;
1936                 np->stats.rx_bytes += len;
1937 next_pkt:
1938                 np->cur_rx++;
1939         }
1940
1941         return count;
1942 }
1943
1944 static void set_bufsize(struct net_device *dev)
1945 {
1946         struct fe_priv *np = netdev_priv(dev);
1947
1948         if (dev->mtu <= ETH_DATA_LEN)
1949                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1950         else
1951                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1952 }
1953
1954 /*
1955  * nv_change_mtu: dev->change_mtu function
1956  * Called with dev_base_lock held for read.
1957  */
1958 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1959 {
1960         struct fe_priv *np = netdev_priv(dev);
1961         int old_mtu;
1962
1963         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1964                 return -EINVAL;
1965
1966         old_mtu = dev->mtu;
1967         dev->mtu = new_mtu;
1968
1969         /* return early if the buffer sizes will not change */
1970         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1971                 return 0;
1972         if (old_mtu == new_mtu)
1973                 return 0;
1974
1975         /* synchronized against open : rtnl_lock() held by caller */
1976         if (netif_running(dev)) {
1977                 u8 __iomem *base = get_hwbase(dev);
1978                 /*
1979                  * It seems that the nic preloads valid ring entries into an
1980                  * internal buffer. The procedure for flushing everything is
1981                  * guessed, there is probably a simpler approach.
1982                  * Changing the MTU is a rare event, it shouldn't matter.
1983                  */
1984                 nv_disable_irq(dev);
1985                 netif_tx_lock_bh(dev);
1986                 spin_lock(&np->lock);
1987                 /* stop engines */
1988                 nv_stop_rx(dev);
1989                 nv_stop_tx(dev);
1990                 nv_txrx_reset(dev);
1991                 /* drain rx queue */
1992                 nv_drain_rx(dev);
1993                 nv_drain_tx(dev);
1994                 /* reinit driver view of the rx queue */
1995                 set_bufsize(dev);
1996                 if (nv_init_ring(dev)) {
1997                         if (!np->in_shutdown)
1998                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1999                 }
2000                 /* reinit nic view of the rx queue */
2001                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2002                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2003                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2004                         base + NvRegRingSizes);
2005                 pci_push(base);
2006                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2007                 pci_push(base);
2008
2009                 /* restart rx engine */
2010                 nv_start_rx(dev);
2011                 nv_start_tx(dev);
2012                 spin_unlock(&np->lock);
2013                 netif_tx_unlock_bh(dev);
2014                 nv_enable_irq(dev);
2015         }
2016         return 0;
2017 }
2018
2019 static void nv_copy_mac_to_hw(struct net_device *dev)
2020 {
2021         u8 __iomem *base = get_hwbase(dev);
2022         u32 mac[2];
2023
2024         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2025                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2026         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2027
2028         writel(mac[0], base + NvRegMacAddrA);
2029         writel(mac[1], base + NvRegMacAddrB);
2030 }
2031
2032 /*
2033  * nv_set_mac_address: dev->set_mac_address function
2034  * Called with rtnl_lock() held.
2035  */
2036 static int nv_set_mac_address(struct net_device *dev, void *addr)
2037 {
2038         struct fe_priv *np = netdev_priv(dev);
2039         struct sockaddr *macaddr = (struct sockaddr*)addr;
2040
2041         if (!is_valid_ether_addr(macaddr->sa_data))
2042                 return -EADDRNOTAVAIL;
2043
2044         /* synchronized against open : rtnl_lock() held by caller */
2045         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2046
2047         if (netif_running(dev)) {
2048                 netif_tx_lock_bh(dev);
2049                 spin_lock_irq(&np->lock);
2050
2051                 /* stop rx engine */
2052                 nv_stop_rx(dev);
2053
2054                 /* set mac address */
2055                 nv_copy_mac_to_hw(dev);
2056
2057                 /* restart rx engine */
2058                 nv_start_rx(dev);
2059                 spin_unlock_irq(&np->lock);
2060                 netif_tx_unlock_bh(dev);
2061         } else {
2062                 nv_copy_mac_to_hw(dev);
2063         }
2064         return 0;
2065 }
2066
2067 /*
2068  * nv_set_multicast: dev->set_multicast function
2069  * Called with netif_tx_lock held.
2070  */
2071 static void nv_set_multicast(struct net_device *dev)
2072 {
2073         struct fe_priv *np = netdev_priv(dev);
2074         u8 __iomem *base = get_hwbase(dev);
2075         u32 addr[2];
2076         u32 mask[2];
2077         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2078
2079         memset(addr, 0, sizeof(addr));
2080         memset(mask, 0, sizeof(mask));
2081
2082         if (dev->flags & IFF_PROMISC) {
2083                 pff |= NVREG_PFF_PROMISC;
2084         } else {
2085                 pff |= NVREG_PFF_MYADDR;
2086
2087                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2088                         u32 alwaysOff[2];
2089                         u32 alwaysOn[2];
2090
2091                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2092                         if (dev->flags & IFF_ALLMULTI) {
2093                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2094                         } else {
2095                                 struct dev_mc_list *walk;
2096
2097                                 walk = dev->mc_list;
2098                                 while (walk != NULL) {
2099                                         u32 a, b;
2100                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2101                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2102                                         alwaysOn[0] &= a;
2103                                         alwaysOff[0] &= ~a;
2104                                         alwaysOn[1] &= b;
2105                                         alwaysOff[1] &= ~b;
2106                                         walk = walk->next;
2107                                 }
2108                         }
2109                         addr[0] = alwaysOn[0];
2110                         addr[1] = alwaysOn[1];
2111                         mask[0] = alwaysOn[0] | alwaysOff[0];
2112                         mask[1] = alwaysOn[1] | alwaysOff[1];
2113                 }
2114         }
2115         addr[0] |= NVREG_MCASTADDRA_FORCE;
2116         pff |= NVREG_PFF_ALWAYS;
2117         spin_lock_irq(&np->lock);
2118         nv_stop_rx(dev);
2119         writel(addr[0], base + NvRegMulticastAddrA);
2120         writel(addr[1], base + NvRegMulticastAddrB);
2121         writel(mask[0], base + NvRegMulticastMaskA);
2122         writel(mask[1], base + NvRegMulticastMaskB);
2123         writel(pff, base + NvRegPacketFilterFlags);
2124         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2125                 dev->name);
2126         nv_start_rx(dev);
2127         spin_unlock_irq(&np->lock);
2128 }
2129
2130 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2131 {
2132         struct fe_priv *np = netdev_priv(dev);
2133         u8 __iomem *base = get_hwbase(dev);
2134
2135         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2136
2137         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2138                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2139                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2140                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2141                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2142                 } else {
2143                         writel(pff, base + NvRegPacketFilterFlags);
2144                 }
2145         }
2146         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2147                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2148                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2149                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2150                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2151                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2152                 } else {
2153                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2154                         writel(regmisc, base + NvRegMisc1);
2155                 }
2156         }
2157 }
2158
2159 /**
2160  * nv_update_linkspeed: Setup the MAC according to the link partner
2161  * @dev: Network device to be configured
2162  *
2163  * The function queries the PHY and checks if there is a link partner.
2164  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2165  * set to 10 MBit HD.
2166  *
2167  * The function returns 0 if there is no link partner and 1 if there is
2168  * a good link partner.
2169  */
2170 static int nv_update_linkspeed(struct net_device *dev)
2171 {
2172         struct fe_priv *np = netdev_priv(dev);
2173         u8 __iomem *base = get_hwbase(dev);
2174         int adv = 0;
2175         int lpa = 0;
2176         int adv_lpa, adv_pause, lpa_pause;
2177         int newls = np->linkspeed;
2178         int newdup = np->duplex;
2179         int mii_status;
2180         int retval = 0;
2181         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2182
2183         /* BMSR_LSTATUS is latched, read it twice:
2184          * we want the current value.
2185          */
2186         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2187         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2188
2189         if (!(mii_status & BMSR_LSTATUS)) {
2190                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2191                                 dev->name);
2192                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2193                 newdup = 0;
2194                 retval = 0;
2195                 goto set_speed;
2196         }
2197
2198         if (np->autoneg == 0) {
2199                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2200                                 dev->name, np->fixed_mode);
2201                 if (np->fixed_mode & LPA_100FULL) {
2202                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2203                         newdup = 1;
2204                 } else if (np->fixed_mode & LPA_100HALF) {
2205                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2206                         newdup = 0;
2207                 } else if (np->fixed_mode & LPA_10FULL) {
2208                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2209                         newdup = 1;
2210                 } else {
2211                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2212                         newdup = 0;
2213                 }
2214                 retval = 1;
2215                 goto set_speed;
2216         }
2217         /* check auto negotiation is complete */
2218         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2219                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2220                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2221                 newdup = 0;
2222                 retval = 0;
2223                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2224                 goto set_speed;
2225         }
2226
2227         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2228         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2229         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2230                                 dev->name, adv, lpa);
2231
2232         retval = 1;
2233         if (np->gigabit == PHY_GIGABIT) {
2234                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2235                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2236
2237                 if ((control_1000 & ADVERTISE_1000FULL) &&
2238                         (status_1000 & LPA_1000FULL)) {
2239                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2240                                 dev->name);
2241                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2242                         newdup = 1;
2243                         goto set_speed;
2244                 }
2245         }
2246
2247         /* FIXME: handle parallel detection properly */
2248         adv_lpa = lpa & adv;
2249         if (adv_lpa & LPA_100FULL) {
2250                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2251                 newdup = 1;
2252         } else if (adv_lpa & LPA_100HALF) {
2253                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2254                 newdup = 0;
2255         } else if (adv_lpa & LPA_10FULL) {
2256                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2257                 newdup = 1;
2258         } else if (adv_lpa & LPA_10HALF) {
2259                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2260                 newdup = 0;
2261         } else {
2262                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2263                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2264                 newdup = 0;
2265         }
2266
2267 set_speed:
2268         if (np->duplex == newdup && np->linkspeed == newls)
2269                 return retval;
2270
2271         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2272                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2273
2274         np->duplex = newdup;
2275         np->linkspeed = newls;
2276
2277         if (np->gigabit == PHY_GIGABIT) {
2278                 phyreg = readl(base + NvRegRandomSeed);
2279                 phyreg &= ~(0x3FF00);
2280                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2281                         phyreg |= NVREG_RNDSEED_FORCE3;
2282                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2283                         phyreg |= NVREG_RNDSEED_FORCE2;
2284                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2285                         phyreg |= NVREG_RNDSEED_FORCE;
2286                 writel(phyreg, base + NvRegRandomSeed);
2287         }
2288
2289         phyreg = readl(base + NvRegPhyInterface);
2290         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2291         if (np->duplex == 0)
2292                 phyreg |= PHY_HALF;
2293         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2294                 phyreg |= PHY_100;
2295         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2296                 phyreg |= PHY_1000;
2297         writel(phyreg, base + NvRegPhyInterface);
2298
2299         if (phyreg & PHY_RGMII) {
2300                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2301                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2302                 else
2303                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2304         } else {
2305                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2306         }
2307         writel(txreg, base + NvRegTxDeferral);
2308
2309         if (np->desc_ver == DESC_VER_1) {
2310                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2311         } else {
2312                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2313                         txreg = NVREG_TX_WM_DESC2_3_1000;
2314                 else
2315                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2316         }
2317         writel(txreg, base + NvRegTxWatermark);
2318
2319         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2320                 base + NvRegMisc1);
2321         pci_push(base);
2322         writel(np->linkspeed, base + NvRegLinkSpeed);
2323         pci_push(base);
2324
2325         pause_flags = 0;
2326         /* setup pause frame */
2327         if (np->duplex != 0) {
2328                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2329                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2330                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2331
2332                         switch (adv_pause) {
2333                         case ADVERTISE_PAUSE_CAP:
2334                                 if (lpa_pause & LPA_PAUSE_CAP) {
2335                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2336                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2337                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2338                                 }
2339                                 break;
2340                         case ADVERTISE_PAUSE_ASYM:
2341                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2342                                 {
2343                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2344                                 }
2345                                 break;
2346                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2347                                 if (lpa_pause & LPA_PAUSE_CAP)
2348                                 {
2349                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2350                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2351                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2352                                 }
2353                                 if (lpa_pause == LPA_PAUSE_ASYM)
2354                                 {
2355                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2356                                 }
2357                                 break;
2358                         }
2359                 } else {
2360                         pause_flags = np->pause_flags;
2361                 }
2362         }
2363         nv_update_pause(dev, pause_flags);
2364
2365         return retval;
2366 }
2367
2368 static void nv_linkchange(struct net_device *dev)
2369 {
2370         if (nv_update_linkspeed(dev)) {
2371                 if (!netif_carrier_ok(dev)) {
2372                         netif_carrier_on(dev);
2373                         printk(KERN_INFO "%s: link up.\n", dev->name);
2374                         nv_start_rx(dev);
2375                 }
2376         } else {
2377                 if (netif_carrier_ok(dev)) {
2378                         netif_carrier_off(dev);
2379                         printk(KERN_INFO "%s: link down.\n", dev->name);
2380                         nv_stop_rx(dev);
2381                 }
2382         }
2383 }
2384
2385 static void nv_link_irq(struct net_device *dev)
2386 {
2387         u8 __iomem *base = get_hwbase(dev);
2388         u32 miistat;
2389
2390         miistat = readl(base + NvRegMIIStatus);
2391         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2392         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2393
2394         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2395                 nv_linkchange(dev);
2396         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2397 }
2398
2399 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2400 {
2401         struct net_device *dev = (struct net_device *) data;
2402         struct fe_priv *np = netdev_priv(dev);
2403         u8 __iomem *base = get_hwbase(dev);
2404         u32 events;
2405         int i;
2406
2407         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2408
2409         for (i=0; ; i++) {
2410                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2411                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2412                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2413                 } else {
2414                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2415                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2416                 }
2417                 pci_push(base);
2418                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2419                 if (!(events & np->irqmask))
2420                         break;
2421
2422                 spin_lock(&np->lock);
2423                 nv_tx_done(dev);
2424                 spin_unlock(&np->lock);
2425
2426                 if (events & NVREG_IRQ_LINK) {
2427                         spin_lock(&np->lock);
2428                         nv_link_irq(dev);
2429                         spin_unlock(&np->lock);
2430                 }
2431                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2432                         spin_lock(&np->lock);
2433                         nv_linkchange(dev);
2434                         spin_unlock(&np->lock);
2435                         np->link_timeout = jiffies + LINK_TIMEOUT;
2436                 }
2437                 if (events & (NVREG_IRQ_TX_ERR)) {
2438                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2439                                                 dev->name, events);
2440                 }
2441                 if (events & (NVREG_IRQ_UNKNOWN)) {
2442                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2443                                                 dev->name, events);
2444                 }
2445 #ifdef CONFIG_FORCEDETH_NAPI
2446                 if (events & NVREG_IRQ_RX_ALL) {
2447                         netif_rx_schedule(dev);
2448
2449                         /* Disable furthur receive irq's */
2450                         spin_lock(&np->lock);
2451                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2452
2453                         if (np->msi_flags & NV_MSI_X_ENABLED)
2454                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2455                         else
2456                                 writel(np->irqmask, base + NvRegIrqMask);
2457                         spin_unlock(&np->lock);
2458                 }
2459 #else
2460                 nv_rx_process(dev, dev->weight);
2461                 if (nv_alloc_rx(dev)) {
2462                         spin_lock(&np->lock);
2463                         if (!np->in_shutdown)
2464                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2465                         spin_unlock(&np->lock);
2466                 }
2467 #endif
2468                 if (i > max_interrupt_work) {
2469                         spin_lock(&np->lock);
2470                         /* disable interrupts on the nic */
2471                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2472                                 writel(0, base + NvRegIrqMask);
2473                         else
2474                                 writel(np->irqmask, base + NvRegIrqMask);
2475                         pci_push(base);
2476
2477                         if (!np->in_shutdown) {
2478                                 np->nic_poll_irq = np->irqmask;
2479                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2480                         }
2481                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2482                         spin_unlock(&np->lock);
2483                         break;
2484                 }
2485
2486         }
2487         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2488
2489         return IRQ_RETVAL(i);
2490 }
2491
2492 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2493 {
2494         struct net_device *dev = (struct net_device *) data;
2495         struct fe_priv *np = netdev_priv(dev);
2496         u8 __iomem *base = get_hwbase(dev);
2497         u32 events;
2498         int i;
2499
2500         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2501
2502         for (i=0; ; i++) {
2503                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2504                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2505                 pci_push(base);
2506                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2507                 if (!(events & np->irqmask))
2508                         break;
2509
2510                 spin_lock_irq(&np->lock);
2511                 nv_tx_done(dev);
2512                 spin_unlock_irq(&np->lock);
2513
2514                 if (events & (NVREG_IRQ_TX_ERR)) {
2515                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2516                                                 dev->name, events);
2517                 }
2518                 if (i > max_interrupt_work) {
2519                         spin_lock_irq(&np->lock);
2520                         /* disable interrupts on the nic */
2521                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2522                         pci_push(base);
2523
2524                         if (!np->in_shutdown) {
2525                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2526                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2527                         }
2528                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2529                         spin_unlock_irq(&np->lock);
2530                         break;
2531                 }
2532
2533         }
2534         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2535
2536         return IRQ_RETVAL(i);
2537 }
2538
2539 #ifdef CONFIG_FORCEDETH_NAPI
2540 static int nv_napi_poll(struct net_device *dev, int *budget)
2541 {
2542         int pkts, limit = min(*budget, dev->quota);
2543         struct fe_priv *np = netdev_priv(dev);
2544         u8 __iomem *base = get_hwbase(dev);
2545
2546         pkts = nv_rx_process(dev, limit);
2547
2548         if (nv_alloc_rx(dev)) {
2549                 spin_lock_irq(&np->lock);
2550                 if (!np->in_shutdown)
2551                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2552                 spin_unlock_irq(&np->lock);
2553         }
2554
2555         if (pkts < limit) {
2556                 /* all done, no more packets present */
2557                 netif_rx_complete(dev);
2558
2559                 /* re-enable receive interrupts */
2560                 spin_lock_irq(&np->lock);
2561                 np->irqmask |= NVREG_IRQ_RX_ALL;
2562                 if (np->msi_flags & NV_MSI_X_ENABLED)
2563                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2564                 else
2565                         writel(np->irqmask, base + NvRegIrqMask);
2566                 spin_unlock_irq(&np->lock);
2567                 return 0;
2568         } else {
2569                 /* used up our quantum, so reschedule */
2570                 dev->quota -= pkts;
2571                 *budget -= pkts;
2572                 return 1;
2573         }
2574 }
2575 #endif
2576
2577 #ifdef CONFIG_FORCEDETH_NAPI
2578 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2579 {
2580         struct net_device *dev = (struct net_device *) data;
2581         u8 __iomem *base = get_hwbase(dev);
2582         u32 events;
2583
2584         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2585         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2586
2587         if (events) {
2588                 netif_rx_schedule(dev);
2589                 /* disable receive interrupts on the nic */
2590                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2591                 pci_push(base);
2592         }
2593         return IRQ_HANDLED;
2594 }
2595 #else
2596 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2597 {
2598         struct net_device *dev = (struct net_device *) data;
2599         struct fe_priv *np = netdev_priv(dev);
2600         u8 __iomem *base = get_hwbase(dev);
2601         u32 events;
2602         int i;
2603
2604         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2605
2606         for (i=0; ; i++) {
2607                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2608                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2609                 pci_push(base);
2610                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2611                 if (!(events & np->irqmask))
2612                         break;
2613
2614                 nv_rx_process(dev, dev->weight);
2615                 if (nv_alloc_rx(dev)) {
2616                         spin_lock_irq(&np->lock);
2617                         if (!np->in_shutdown)
2618                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2619                         spin_unlock_irq(&np->lock);
2620                 }
2621
2622                 if (i > max_interrupt_work) {
2623                         spin_lock_irq(&np->lock);
2624                         /* disable interrupts on the nic */
2625                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2626                         pci_push(base);
2627
2628                         if (!np->in_shutdown) {
2629                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2630                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2631                         }
2632                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2633                         spin_unlock_irq(&np->lock);
2634                         break;
2635                 }
2636         }
2637         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2638
2639         return IRQ_RETVAL(i);
2640 }
2641 #endif
2642
2643 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2644 {
2645         struct net_device *dev = (struct net_device *) data;
2646         struct fe_priv *np = netdev_priv(dev);
2647         u8 __iomem *base = get_hwbase(dev);
2648         u32 events;
2649         int i;
2650
2651         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2652
2653         for (i=0; ; i++) {
2654                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2655                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2656                 pci_push(base);
2657                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2658                 if (!(events & np->irqmask))
2659                         break;
2660
2661                 if (events & NVREG_IRQ_LINK) {
2662                         spin_lock_irq(&np->lock);
2663                         nv_link_irq(dev);
2664                         spin_unlock_irq(&np->lock);
2665                 }
2666                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2667                         spin_lock_irq(&np->lock);
2668                         nv_linkchange(dev);
2669                         spin_unlock_irq(&np->lock);
2670                         np->link_timeout = jiffies + LINK_TIMEOUT;
2671                 }
2672                 if (events & (NVREG_IRQ_UNKNOWN)) {
2673                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2674                                                 dev->name, events);
2675                 }
2676                 if (i > max_interrupt_work) {
2677                         spin_lock_irq(&np->lock);
2678                         /* disable interrupts on the nic */
2679                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2680                         pci_push(base);
2681
2682                         if (!np->in_shutdown) {
2683                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2684                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2685                         }
2686                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2687                         spin_unlock_irq(&np->lock);
2688                         break;
2689                 }
2690
2691         }
2692         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2693
2694         return IRQ_RETVAL(i);
2695 }
2696
2697 static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs)
2698 {
2699         struct net_device *dev = (struct net_device *) data;
2700         struct fe_priv *np = netdev_priv(dev);
2701         u8 __iomem *base = get_hwbase(dev);
2702         u32 events;
2703
2704         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2705
2706         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2707                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2708                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2709         } else {
2710                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2711                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2712         }
2713         pci_push(base);
2714         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2715         if (!(events & NVREG_IRQ_TIMER))
2716                 return IRQ_RETVAL(0);
2717
2718         spin_lock(&np->lock);
2719         np->intr_test = 1;
2720         spin_unlock(&np->lock);
2721
2722         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2723
2724         return IRQ_RETVAL(1);
2725 }
2726
2727 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2728 {
2729         u8 __iomem *base = get_hwbase(dev);
2730         int i;
2731         u32 msixmap = 0;
2732
2733         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2734          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2735          * the remaining 8 interrupts.
2736          */
2737         for (i = 0; i < 8; i++) {
2738                 if ((irqmask >> i) & 0x1) {
2739                         msixmap |= vector << (i << 2);
2740                 }
2741         }
2742         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2743
2744         msixmap = 0;
2745         for (i = 0; i < 8; i++) {
2746                 if ((irqmask >> (i + 8)) & 0x1) {
2747                         msixmap |= vector << (i << 2);
2748                 }
2749         }
2750         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2751 }
2752
2753 static int nv_request_irq(struct net_device *dev, int intr_test)
2754 {
2755         struct fe_priv *np = get_nvpriv(dev);
2756         u8 __iomem *base = get_hwbase(dev);
2757         int ret = 1;
2758         int i;
2759
2760         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2761                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2762                         np->msi_x_entry[i].entry = i;
2763                 }
2764                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2765                         np->msi_flags |= NV_MSI_X_ENABLED;
2766                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2767                                 /* Request irq for rx handling */
2768                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2769                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2770                                         pci_disable_msix(np->pci_dev);
2771                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2772                                         goto out_err;
2773                                 }
2774                                 /* Request irq for tx handling */
2775                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2776                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2777                                         pci_disable_msix(np->pci_dev);
2778                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2779                                         goto out_free_rx;
2780                                 }
2781                                 /* Request irq for link and timer handling */
2782                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2783                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2784                                         pci_disable_msix(np->pci_dev);
2785                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2786                                         goto out_free_tx;
2787                                 }
2788                                 /* map interrupts to their respective vector */
2789                                 writel(0, base + NvRegMSIXMap0);
2790                                 writel(0, base + NvRegMSIXMap1);
2791                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2792                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2793                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2794                         } else {
2795                                 /* Request irq for all interrupts */
2796                                 if ((!intr_test &&
2797                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2798                                     (intr_test &&
2799                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2800                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2801                                         pci_disable_msix(np->pci_dev);
2802                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2803                                         goto out_err;
2804                                 }
2805
2806                                 /* map interrupts to vector 0 */
2807                                 writel(0, base + NvRegMSIXMap0);
2808                                 writel(0, base + NvRegMSIXMap1);
2809                         }
2810                 }
2811         }
2812         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2813                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2814                         np->msi_flags |= NV_MSI_ENABLED;
2815                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2816                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2817                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2818                                 pci_disable_msi(np->pci_dev);
2819                                 np->msi_flags &= ~NV_MSI_ENABLED;
2820                                 goto out_err;
2821                         }
2822
2823                         /* map interrupts to vector 0 */
2824                         writel(0, base + NvRegMSIMap0);
2825                         writel(0, base + NvRegMSIMap1);
2826                         /* enable msi vector 0 */
2827                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2828                 }
2829         }
2830         if (ret != 0) {
2831                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2832                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2833                         goto out_err;
2834
2835         }
2836
2837         return 0;
2838 out_free_tx:
2839         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2840 out_free_rx:
2841         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2842 out_err:
2843         return 1;
2844 }
2845
2846 static void nv_free_irq(struct net_device *dev)
2847 {
2848         struct fe_priv *np = get_nvpriv(dev);
2849         int i;
2850
2851         if (np->msi_flags & NV_MSI_X_ENABLED) {
2852                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2853                         free_irq(np->msi_x_entry[i].vector, dev);
2854                 }
2855                 pci_disable_msix(np->pci_dev);
2856                 np->msi_flags &= ~NV_MSI_X_ENABLED;
2857         } else {
2858                 free_irq(np->pci_dev->irq, dev);
2859                 if (np->msi_flags & NV_MSI_ENABLED) {
2860                         pci_disable_msi(np->pci_dev);
2861                         np->msi_flags &= ~NV_MSI_ENABLED;
2862                 }
2863         }
2864 }
2865
2866 static void nv_do_nic_poll(unsigned long data)
2867 {
2868         struct net_device *dev = (struct net_device *) data;
2869         struct fe_priv *np = netdev_priv(dev);
2870         u8 __iomem *base = get_hwbase(dev);
2871         u32 mask = 0;
2872
2873         /*
2874          * First disable irq(s) and then
2875          * reenable interrupts on the nic, we have to do this before calling
2876          * nv_nic_irq because that may decide to do otherwise
2877          */
2878
2879         if (!using_multi_irqs(dev)) {
2880                 if (np->msi_flags & NV_MSI_X_ENABLED)
2881                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2882                 else
2883                         disable_irq_lockdep(dev->irq);
2884                 mask = np->irqmask;
2885         } else {
2886                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2887                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2888                         mask |= NVREG_IRQ_RX_ALL;
2889                 }
2890                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2891                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2892                         mask |= NVREG_IRQ_TX_ALL;
2893                 }
2894                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2895                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2896                         mask |= NVREG_IRQ_OTHER;
2897                 }
2898         }
2899         np->nic_poll_irq = 0;
2900
2901         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2902
2903         writel(mask, base + NvRegIrqMask);
2904         pci_push(base);
2905
2906         if (!using_multi_irqs(dev)) {
2907                 nv_nic_irq(0, dev, NULL);
2908                 if (np->msi_flags & NV_MSI_X_ENABLED)
2909                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2910                 else
2911                         enable_irq_lockdep(dev->irq);
2912         } else {
2913                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2914                         nv_nic_irq_rx(0, dev, NULL);
2915                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2916                 }
2917                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2918                         nv_nic_irq_tx(0, dev, NULL);
2919                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2920                 }
2921                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2922                         nv_nic_irq_other(0, dev, NULL);
2923                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2924                 }
2925         }
2926 }
2927
2928 #ifdef CONFIG_NET_POLL_CONTROLLER
2929 static void nv_poll_controller(struct net_device *dev)
2930 {
2931         nv_do_nic_poll((unsigned long) dev);
2932 }
2933 #endif
2934
2935 static void nv_do_stats_poll(unsigned long data)
2936 {
2937         struct net_device *dev = (struct net_device *) data;
2938         struct fe_priv *np = netdev_priv(dev);
2939         u8 __iomem *base = get_hwbase(dev);
2940
2941         np->estats.tx_bytes += readl(base + NvRegTxCnt);
2942         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2943         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2944         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2945         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2946         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2947         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2948         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2949         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2950         np->estats.tx_deferral += readl(base + NvRegTxDef);
2951         np->estats.tx_packets += readl(base + NvRegTxFrame);
2952         np->estats.tx_pause += readl(base + NvRegTxPause);
2953         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2954         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2955         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2956         np->estats.rx_runt += readl(base + NvRegRxRunt);
2957         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2958         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2959         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2960         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2961         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2962         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2963         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2964         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2965         np->estats.rx_bytes += readl(base + NvRegRxCnt);
2966         np->estats.rx_pause += readl(base + NvRegRxPause);
2967         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2968         np->estats.rx_packets =
2969                 np->estats.rx_unicast +
2970                 np->estats.rx_multicast +
2971                 np->estats.rx_broadcast;
2972         np->estats.rx_errors_total =
2973                 np->estats.rx_crc_errors +
2974                 np->estats.rx_over_errors +
2975                 np->estats.rx_frame_error +
2976                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2977                 np->estats.rx_late_collision +
2978                 np->estats.rx_runt +
2979                 np->estats.rx_frame_too_long;
2980
2981         if (!np->in_shutdown)
2982                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2983 }
2984
2985 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2986 {
2987         struct fe_priv *np = netdev_priv(dev);
2988         strcpy(info->driver, "forcedeth");
2989         strcpy(info->version, FORCEDETH_VERSION);
2990         strcpy(info->bus_info, pci_name(np->pci_dev));
2991 }
2992
2993 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2994 {
2995         struct fe_priv *np = netdev_priv(dev);
2996         wolinfo->supported = WAKE_MAGIC;
2997
2998         spin_lock_irq(&np->lock);
2999         if (np->wolenabled)
3000                 wolinfo->wolopts = WAKE_MAGIC;
3001         spin_unlock_irq(&np->lock);
3002 }
3003
3004 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3005 {
3006         struct fe_priv *np = netdev_priv(dev);
3007         u8 __iomem *base = get_hwbase(dev);
3008         u32 flags = 0;
3009
3010         if (wolinfo->wolopts == 0) {
3011                 np->wolenabled = 0;
3012         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3013                 np->wolenabled = 1;
3014                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3015         }
3016         if (netif_running(dev)) {
3017                 spin_lock_irq(&np->lock);
3018                 writel(flags, base + NvRegWakeUpFlags);
3019                 spin_unlock_irq(&np->lock);
3020         }
3021         return 0;
3022 }
3023
3024 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3025 {
3026         struct fe_priv *np = netdev_priv(dev);
3027         int adv;
3028
3029         spin_lock_irq(&np->lock);
3030         ecmd->port = PORT_MII;
3031         if (!netif_running(dev)) {
3032                 /* We do not track link speed / duplex setting if the
3033                  * interface is disabled. Force a link check */
3034                 if (nv_update_linkspeed(dev)) {
3035                         if (!netif_carrier_ok(dev))
3036                                 netif_carrier_on(dev);
3037                 } else {
3038                         if (netif_carrier_ok(dev))
3039                                 netif_carrier_off(dev);
3040                 }
3041         }
3042
3043         if (netif_carrier_ok(dev)) {
3044                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3045                 case NVREG_LINKSPEED_10:
3046                         ecmd->speed = SPEED_10;
3047                         break;
3048                 case NVREG_LINKSPEED_100:
3049                         ecmd->speed = SPEED_100;
3050                         break;
3051                 case NVREG_LINKSPEED_1000:
3052                         ecmd->speed = SPEED_1000;
3053                         break;
3054                 }
3055                 ecmd->duplex = DUPLEX_HALF;
3056                 if (np->duplex)
3057                         ecmd->duplex = DUPLEX_FULL;
3058         } else {
3059                 ecmd->speed = -1;
3060                 ecmd->duplex = -1;
3061         }
3062
3063         ecmd->autoneg = np->autoneg;
3064
3065         ecmd->advertising = ADVERTISED_MII;
3066         if (np->autoneg) {
3067                 ecmd->advertising |= ADVERTISED_Autoneg;
3068                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3069                 if (adv & ADVERTISE_10HALF)
3070                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3071                 if (adv & ADVERTISE_10FULL)
3072                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3073                 if (adv & ADVERTISE_100HALF)
3074                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3075                 if (adv & ADVERTISE_100FULL)
3076                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3077                 if (np->gigabit == PHY_GIGABIT) {
3078                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3079                         if (adv & ADVERTISE_1000FULL)
3080                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3081                 }
3082         }
3083         ecmd->supported = (SUPPORTED_Autoneg |
3084                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3085                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3086                 SUPPORTED_MII);
3087         if (np->gigabit == PHY_GIGABIT)
3088                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3089
3090         ecmd->phy_address = np->phyaddr;
3091         ecmd->transceiver = XCVR_EXTERNAL;
3092
3093         /* ignore maxtxpkt, maxrxpkt for now */
3094         spin_unlock_irq(&np->lock);
3095         return 0;
3096 }
3097
3098 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3099 {
3100         struct fe_priv *np = netdev_priv(dev);
3101
3102         if (ecmd->port != PORT_MII)
3103                 return -EINVAL;
3104         if (ecmd->transceiver != XCVR_EXTERNAL)
3105                 return -EINVAL;
3106         if (ecmd->phy_address != np->phyaddr) {
3107                 /* TODO: support switching between multiple phys. Should be
3108                  * trivial, but not enabled due to lack of test hardware. */
3109                 return -EINVAL;
3110         }
3111         if (ecmd->autoneg == AUTONEG_ENABLE) {
3112                 u32 mask;
3113
3114                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3115                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3116                 if (np->gigabit == PHY_GIGABIT)
3117                         mask |= ADVERTISED_1000baseT_Full;
3118
3119                 if ((ecmd->advertising & mask) == 0)
3120                         return -EINVAL;
3121
3122         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3123                 /* Note: autonegotiation disable, speed 1000 intentionally
3124                  * forbidden - noone should need that. */
3125
3126                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3127                         return -EINVAL;
3128                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3129                         return -EINVAL;
3130         } else {
3131                 return -EINVAL;
3132         }
3133
3134         netif_carrier_off(dev);
3135         if (netif_running(dev)) {
3136                 nv_disable_irq(dev);
3137                 netif_tx_lock_bh(dev);
3138                 spin_lock(&np->lock);
3139                 /* stop engines */
3140                 nv_stop_rx(dev);
3141                 nv_stop_tx(dev);
3142                 spin_unlock(&np->lock);
3143                 netif_tx_unlock_bh(dev);
3144         }
3145
3146         if (ecmd->autoneg == AUTONEG_ENABLE) {
3147                 int adv, bmcr;
3148
3149                 np->autoneg = 1;
3150
3151                 /* advertise only what has been requested */
3152                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3153                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3154                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3155                         adv |= ADVERTISE_10HALF;
3156                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3157                         adv |= ADVERTISE_10FULL;
3158                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3159                         adv |= ADVERTISE_100HALF;
3160                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3161                         adv |= ADVERTISE_100FULL;
3162                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3163                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3164                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3165                         adv |=  ADVERTISE_PAUSE_ASYM;
3166                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3167
3168                 if (np->gigabit == PHY_GIGABIT) {
3169                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3170                         adv &= ~ADVERTISE_1000FULL;
3171                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3172                                 adv |= ADVERTISE_1000FULL;
3173                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3174                 }
3175
3176                 if (netif_running(dev))
3177                         printk(KERN_INFO "%s: link down.\n", dev->name);
3178                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3179                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3180                         bmcr |= BMCR_ANENABLE;
3181                         /* reset the phy in order for settings to stick,
3182                          * and cause autoneg to start */
3183                         if (phy_reset(dev, bmcr)) {
3184                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3185                                 return -EINVAL;
3186                         }
3187                 } else {
3188                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3189                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3190                 }
3191         } else {
3192                 int adv, bmcr;
3193
3194                 np->autoneg = 0;
3195
3196                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3197                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3198                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3199                         adv |= ADVERTISE_10HALF;
3200                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3201                         adv |= ADVERTISE_10FULL;
3202                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3203                         adv |= ADVERTISE_100HALF;
3204                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3205                         adv |= ADVERTISE_100FULL;
3206                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3207                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3208                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3209                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3210                 }
3211                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3212                         adv |=  ADVERTISE_PAUSE_ASYM;
3213                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3214                 }
3215                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3216                 np->fixed_mode = adv;
3217
3218                 if (np->gigabit == PHY_GIGABIT) {
3219                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3220                         adv &= ~ADVERTISE_1000FULL;
3221                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3222                 }
3223
3224                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3225                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3226                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3227                         bmcr |= BMCR_FULLDPLX;
3228                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3229                         bmcr |= BMCR_SPEED100;
3230                 if (np->phy_oui == PHY_OUI_MARVELL) {
3231                         /* reset the phy in order for forced mode settings to stick */
3232                         if (phy_reset(dev, bmcr)) {
3233                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3234                                 return -EINVAL;
3235                         }
3236                 } else {
3237                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3238                         if (netif_running(dev)) {
3239                                 /* Wait a bit and then reconfigure the nic. */
3240                                 udelay(10);
3241                                 nv_linkchange(dev);
3242                         }
3243                 }
3244         }
3245
3246         if (netif_running(dev)) {
3247                 nv_start_rx(dev);
3248                 nv_start_tx(dev);
3249                 nv_enable_irq(dev);
3250         }
3251
3252         return 0;
3253 }
3254
3255 #define FORCEDETH_REGS_VER      1
3256
3257 static int nv_get_regs_len(struct net_device *dev)
3258 {
3259         struct fe_priv *np = netdev_priv(dev);
3260         return np->register_size;
3261 }
3262
3263 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3264 {
3265         struct fe_priv *np = netdev_priv(dev);
3266         u8 __iomem *base = get_hwbase(dev);
3267         u32 *rbuf = buf;
3268         int i;
3269
3270         regs->version = FORCEDETH_REGS_VER;
3271         spin_lock_irq(&np->lock);
3272         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3273                 rbuf[i] = readl(base + i*sizeof(u32));
3274         spin_unlock_irq(&np->lock);
3275 }
3276
3277 static int nv_nway_reset(struct net_device *dev)
3278 {
3279         struct fe_priv *np = netdev_priv(dev);
3280         int ret;
3281
3282         if (np->autoneg) {
3283                 int bmcr;
3284
3285                 netif_carrier_off(dev);
3286                 if (netif_running(dev)) {
3287                         nv_disable_irq(dev);
3288                         netif_tx_lock_bh(dev);
3289                         spin_lock(&np->lock);
3290                         /* stop engines */
3291                         nv_stop_rx(dev);
3292                         nv_stop_tx(dev);
3293                         spin_unlock(&np->lock);
3294                         netif_tx_unlock_bh(dev);
3295                         printk(KERN_INFO "%s: link down.\n", dev->name);
3296                 }
3297
3298                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3299                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3300                         bmcr |= BMCR_ANENABLE;
3301                         /* reset the phy in order for settings to stick*/
3302                         if (phy_reset(dev, bmcr)) {
3303                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3304                                 return -EINVAL;
3305                         }
3306                 } else {
3307                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3308                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3309                 }
3310
3311                 if (netif_running(dev)) {
3312                         nv_start_rx(dev);
3313                         nv_start_tx(dev);
3314                         nv_enable_irq(dev);
3315                 }
3316                 ret = 0;
3317         } else {
3318                 ret = -EINVAL;
3319         }
3320
3321         return ret;
3322 }
3323
3324 static int nv_set_tso(struct net_device *dev, u32 value)
3325 {
3326         struct fe_priv *np = netdev_priv(dev);
3327
3328         if ((np->driver_data & DEV_HAS_CHECKSUM))
3329                 return ethtool_op_set_tso(dev, value);
3330         else
3331                 return -EOPNOTSUPP;
3332 }
3333
3334 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3335 {
3336         struct fe_priv *np = netdev_priv(dev);
3337
3338         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3339         ring->rx_mini_max_pending = 0;
3340         ring->rx_jumbo_max_pending = 0;
3341         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3342
3343         ring->rx_pending = np->rx_ring_size;
3344         ring->rx_mini_pending = 0;
3345         ring->rx_jumbo_pending = 0;
3346         ring->tx_pending = np->tx_ring_size;
3347 }
3348
3349 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3350 {
3351         struct fe_priv *np = netdev_priv(dev);
3352         u8 __iomem *base = get_hwbase(dev);
3353         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3354         dma_addr_t ring_addr;
3355
3356         if (ring->rx_pending < RX_RING_MIN ||
3357             ring->tx_pending < TX_RING_MIN ||
3358             ring->rx_mini_pending != 0 ||
3359             ring->rx_jumbo_pending != 0 ||
3360             (np->desc_ver == DESC_VER_1 &&
3361              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3362               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3363             (np->desc_ver != DESC_VER_1 &&
3364              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3365               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3366                 return -EINVAL;
3367         }
3368
3369         /* allocate new rings */
3370         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3371                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3372                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3373                                             &ring_addr);
3374         } else {
3375                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3376                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3377                                             &ring_addr);
3378         }
3379         rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3380         rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3381         tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3382         tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3383         tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3384         if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3385                 /* fall back to old rings */
3386                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3387                         if (rxtx_ring)
3388                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3389                                                     rxtx_ring, ring_addr);
3390                 } else {
3391                         if (rxtx_ring)
3392                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3393                                                     rxtx_ring, ring_addr);
3394                 }
3395                 if (rx_skbuff)
3396                         kfree(rx_skbuff);
3397                 if (rx_dma)
3398                         kfree(rx_dma);
3399                 if (tx_skbuff)
3400                         kfree(tx_skbuff);
3401                 if (tx_dma)
3402                         kfree(tx_dma);
3403                 if (tx_dma_len)
3404                         kfree(tx_dma_len);
3405                 goto exit;
3406         }
3407
3408         if (netif_running(dev)) {
3409                 nv_disable_irq(dev);
3410                 netif_tx_lock_bh(dev);
3411                 spin_lock(&np->lock);
3412                 /* stop engines */
3413                 nv_stop_rx(dev);
3414                 nv_stop_tx(dev);
3415                 nv_txrx_reset(dev);
3416                 /* drain queues */
3417                 nv_drain_rx(dev);
3418                 nv_drain_tx(dev);
3419                 /* delete queues */
3420                 free_rings(dev);
3421         }
3422
3423         /* set new values */
3424         np->rx_ring_size = ring->rx_pending;
3425         np->tx_ring_size = ring->tx_pending;
3426         np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3427         np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3428         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3429                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3430                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3431         } else {
3432                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3433                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3434         }
3435         np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3436         np->rx_dma = (dma_addr_t*)rx_dma;
3437         np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3438         np->tx_dma = (dma_addr_t*)tx_dma;
3439         np->tx_dma_len = (unsigned int*)tx_dma_len;
3440         np->ring_addr = ring_addr;
3441
3442         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3443         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3444         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3445         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3446         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3447
3448         if (netif_running(dev)) {
3449                 /* reinit driver view of the queues */
3450                 set_bufsize(dev);
3451                 if (nv_init_ring(dev)) {
3452                         if (!np->in_shutdown)
3453                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3454                 }
3455
3456                 /* reinit nic view of the queues */
3457                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3458                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3459                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3460                         base + NvRegRingSizes);
3461                 pci_push(base);
3462                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3463                 pci_push(base);
3464
3465                 /* restart engines */
3466                 nv_start_rx(dev);
3467                 nv_start_tx(dev);
3468                 spin_unlock(&np->lock);
3469                 netif_tx_unlock_bh(dev);
3470                 nv_enable_irq(dev);
3471         }
3472         return 0;
3473 exit:
3474         return -ENOMEM;
3475 }
3476
3477 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3478 {
3479         struct fe_priv *np = netdev_priv(dev);
3480
3481         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3482         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3483         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3484 }
3485
3486 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3487 {
3488         struct fe_priv *np = netdev_priv(dev);
3489         int adv, bmcr;
3490
3491         if ((!np->autoneg && np->duplex == 0) ||
3492             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3493                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3494                        dev->name);
3495                 return -EINVAL;
3496         }
3497         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3498                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3499                 return -EINVAL;
3500         }
3501
3502         netif_carrier_off(dev);
3503         if (netif_running(dev)) {
3504                 nv_disable_irq(dev);
3505                 netif_tx_lock_bh(dev);
3506                 spin_lock(&np->lock);
3507                 /* stop engines */
3508                 nv_stop_rx(dev);
3509                 nv_stop_tx(dev);
3510                 spin_unlock(&np->lock);
3511                 netif_tx_unlock_bh(dev);
3512         }
3513
3514         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3515         if (pause->rx_pause)
3516                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3517         if (pause->tx_pause)
3518                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3519
3520         if (np->autoneg && pause->autoneg) {
3521                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3522
3523                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3524                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3525                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3526                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3527                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3528                         adv |=  ADVERTISE_PAUSE_ASYM;
3529                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3530
3531                 if (netif_running(dev))
3532                         printk(KERN_INFO "%s: link down.\n", dev->name);
3533                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3534                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3535                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3536         } else {
3537                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3538                 if (pause->rx_pause)
3539                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3540                 if (pause->tx_pause)
3541                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3542
3543                 if (!netif_running(dev))
3544                         nv_update_linkspeed(dev);
3545                 else
3546                         nv_update_pause(dev, np->pause_flags);
3547         }
3548
3549         if (netif_running(dev)) {
3550                 nv_start_rx(dev);
3551                 nv_start_tx(dev);
3552                 nv_enable_irq(dev);
3553         }
3554         return 0;
3555 }
3556
3557 static u32 nv_get_rx_csum(struct net_device *dev)
3558 {
3559         struct fe_priv *np = netdev_priv(dev);
3560         return (np->rx_csum) != 0;
3561 }
3562
3563 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3564 {
3565         struct fe_priv *np = netdev_priv(dev);
3566         u8 __iomem *base = get_hwbase(dev);
3567         int retcode = 0;
3568
3569         if (np->driver_data & DEV_HAS_CHECKSUM) {
3570                 if (data) {
3571                         np->rx_csum = 1;
3572                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3573                 } else {
3574                         np->rx_csum = 0;
3575                         /* vlan is dependent on rx checksum offload */
3576                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
3577                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3578                 }
3579                 if (netif_running(dev)) {
3580                         spin_lock_irq(&np->lock);
3581                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3582                         spin_unlock_irq(&np->lock);
3583                 }
3584         } else {
3585                 return -EINVAL;
3586         }
3587
3588         return retcode;
3589 }
3590
3591 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3592 {
3593         struct fe_priv *np = netdev_priv(dev);
3594
3595         if (np->driver_data & DEV_HAS_CHECKSUM)
3596                 return ethtool_op_set_tx_hw_csum(dev, data);
3597         else
3598                 return -EOPNOTSUPP;
3599 }
3600
3601 static int nv_set_sg(struct net_device *dev, u32 data)
3602 {
3603         struct fe_priv *np = netdev_priv(dev);
3604
3605         if (np->driver_data & DEV_HAS_CHECKSUM)
3606                 return ethtool_op_set_sg(dev, data);
3607         else
3608                 return -EOPNOTSUPP;
3609 }
3610
3611 static int nv_get_stats_count(struct net_device *dev)
3612 {
3613         struct fe_priv *np = netdev_priv(dev);
3614
3615         if (np->driver_data & DEV_HAS_STATISTICS)
3616                 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3617         else
3618                 return 0;
3619 }
3620
3621 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3622 {
3623         struct fe_priv *np = netdev_priv(dev);
3624
3625         /* update stats */
3626         nv_do_stats_poll((unsigned long)dev);
3627
3628         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3629 }
3630
3631 static int nv_self_test_count(struct net_device *dev)
3632 {
3633         struct fe_priv *np = netdev_priv(dev);
3634
3635         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3636                 return NV_TEST_COUNT_EXTENDED;
3637         else
3638                 return NV_TEST_COUNT_BASE;
3639 }
3640
3641 static int nv_link_test(struct net_device *dev)
3642 {
3643         struct fe_priv *np = netdev_priv(dev);
3644         int mii_status;
3645
3646         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3647         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3648
3649         /* check phy link status */
3650         if (!(mii_status & BMSR_LSTATUS))
3651                 return 0;
3652         else
3653                 return 1;
3654 }
3655
3656 static int nv_register_test(struct net_device *dev)
3657 {
3658         u8 __iomem *base = get_hwbase(dev);
3659         int i = 0;
3660         u32 orig_read, new_read;
3661
3662         do {
3663                 orig_read = readl(base + nv_registers_test[i].reg);
3664
3665                 /* xor with mask to toggle bits */
3666                 orig_read ^= nv_registers_test[i].mask;
3667
3668                 writel(orig_read, base + nv_registers_test[i].reg);
3669
3670                 new_read = readl(base + nv_registers_test[i].reg);
3671
3672                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3673                         return 0;
3674
3675                 /* restore original value */
3676                 orig_read ^= nv_registers_test[i].mask;
3677                 writel(orig_read, base + nv_registers_test[i].reg);
3678
3679         } while (nv_registers_test[++i].reg != 0);
3680
3681         return 1;
3682 }
3683
3684 static int nv_interrupt_test(struct net_device *dev)
3685 {
3686         struct fe_priv *np = netdev_priv(dev);
3687         u8 __iomem *base = get_hwbase(dev);
3688         int ret = 1;
3689         int testcnt;
3690         u32 save_msi_flags, save_poll_interval = 0;
3691
3692         if (netif_running(dev)) {
3693                 /* free current irq */
3694                 nv_free_irq(dev);
3695                 save_poll_interval = readl(base+NvRegPollingInterval);
3696         }
3697
3698         /* flag to test interrupt handler */
3699         np->intr_test = 0;
3700
3701         /* setup test irq */
3702         save_msi_flags = np->msi_flags;
3703         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3704         np->msi_flags |= 0x001; /* setup 1 vector */
3705         if (nv_request_irq(dev, 1))
3706                 return 0;
3707
3708         /* setup timer interrupt */
3709         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3710         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3711
3712         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3713
3714         /* wait for at least one interrupt */
3715         msleep(100);
3716
3717         spin_lock_irq(&np->lock);
3718
3719         /* flag should be set within ISR */
3720         testcnt = np->intr_test;
3721         if (!testcnt)
3722                 ret = 2;
3723
3724         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3725         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3726                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3727         else
3728                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3729
3730         spin_unlock_irq(&np->lock);
3731
3732         nv_free_irq(dev);
3733
3734         np->msi_flags = save_msi_flags;
3735
3736         if (netif_running(dev)) {
3737                 writel(save_poll_interval, base + NvRegPollingInterval);
3738                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3739                 /* restore original irq */
3740                 if (nv_request_irq(dev, 0))
3741                         return 0;
3742         }
3743
3744         return ret;
3745 }
3746
3747 static int nv_loopback_test(struct net_device *dev)
3748 {
3749         struct fe_priv *np = netdev_priv(dev);
3750         u8 __iomem *base = get_hwbase(dev);
3751         struct sk_buff *tx_skb, *rx_skb;
3752         dma_addr_t test_dma_addr;
3753         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3754         u32 flags;
3755         int len, i, pkt_len;
3756         u8 *pkt_data;
3757         u32 filter_flags = 0;
3758         u32 misc1_flags = 0;
3759         int ret = 1;
3760
3761         if (netif_running(dev)) {
3762                 nv_disable_irq(dev);
3763                 filter_flags = readl(base + NvRegPacketFilterFlags);
3764                 misc1_flags = readl(base + NvRegMisc1);
3765         } else {
3766                 nv_txrx_reset(dev);
3767         }
3768
3769         /* reinit driver view of the rx queue */
3770         set_bufsize(dev);
3771         nv_init_ring(dev);
3772
3773         /* setup hardware for loopback */
3774         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3775         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3776
3777         /* reinit nic view of the rx queue */
3778         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3779         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3780         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3781                 base + NvRegRingSizes);
3782         pci_push(base);
3783
3784         /* restart rx engine */
3785         nv_start_rx(dev);
3786         nv_start_tx(dev);
3787
3788         /* setup packet for tx */
3789         pkt_len = ETH_DATA_LEN;
3790         tx_skb = dev_alloc_skb(pkt_len);
3791         pkt_data = skb_put(tx_skb, pkt_len);
3792         for (i = 0; i < pkt_len; i++)
3793                 pkt_data[i] = (u8)(i & 0xff);
3794         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3795                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3796
3797         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3798                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
3799                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3800         } else {
3801                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
3802                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3803                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3804         }
3805         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3806         pci_push(get_hwbase(dev));
3807
3808         msleep(500);
3809
3810         /* check for rx of the packet */
3811         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3812                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
3813                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3814
3815         } else {
3816                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
3817                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3818         }
3819
3820         if (flags & NV_RX_AVAIL) {
3821                 ret = 0;
3822         } else if (np->desc_ver == DESC_VER_1) {
3823                 if (flags & NV_RX_ERROR)
3824                         ret = 0;
3825         } else {
3826                 if (flags & NV_RX2_ERROR) {
3827                         ret = 0;
3828                 }
3829         }
3830
3831         if (ret) {
3832                 if (len != pkt_len) {
3833                         ret = 0;
3834                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3835                                 dev->name, len, pkt_len);
3836                 } else {
3837                         rx_skb = np->rx_skbuff[0];
3838                         for (i = 0; i < pkt_len; i++) {
3839                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3840                                         ret = 0;
3841                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3842                                                 dev->name, i);
3843                                         break;
3844                                 }
3845                         }
3846                 }
3847         } else {
3848                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3849         }
3850
3851         pci_unmap_page(np->pci_dev, test_dma_addr,
3852                        tx_skb->end-tx_skb->data,
3853                        PCI_DMA_TODEVICE);
3854         dev_kfree_skb_any(tx_skb);
3855
3856         /* stop engines */
3857         nv_stop_rx(dev);
3858         nv_stop_tx(dev);
3859         nv_txrx_reset(dev);
3860         /* drain rx queue */
3861         nv_drain_rx(dev);
3862         nv_drain_tx(dev);
3863
3864         if (netif_running(dev)) {
3865                 writel(misc1_flags, base + NvRegMisc1);
3866                 writel(filter_flags, base + NvRegPacketFilterFlags);
3867                 nv_enable_irq(dev);
3868         }
3869
3870         return ret;
3871 }
3872
3873 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3874 {
3875         struct fe_priv *np = netdev_priv(dev);
3876         u8 __iomem *base = get_hwbase(dev);
3877         int result;
3878         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3879
3880         if (!nv_link_test(dev)) {
3881                 test->flags |= ETH_TEST_FL_FAILED;
3882                 buffer[0] = 1;
3883         }
3884
3885         if (test->flags & ETH_TEST_FL_OFFLINE) {
3886                 if (netif_running(dev)) {
3887                         netif_stop_queue(dev);
3888                         netif_poll_disable(dev);
3889                         netif_tx_lock_bh(dev);
3890                         spin_lock_irq(&np->lock);
3891                         nv_disable_hw_interrupts(dev, np->irqmask);
3892                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3893                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3894                         } else {
3895                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3896                         }
3897                         /* stop engines */
3898                         nv_stop_rx(dev);
3899                         nv_stop_tx(dev);
3900                         nv_txrx_reset(dev);
3901                         /* drain rx queue */
3902                         nv_drain_rx(dev);
3903                         nv_drain_tx(dev);
3904                         spin_unlock_irq(&np->lock);
3905                         netif_tx_unlock_bh(dev);
3906                 }
3907
3908                 if (!nv_register_test(dev)) {
3909                         test->flags |= ETH_TEST_FL_FAILED;
3910                         buffer[1] = 1;
3911                 }
3912
3913                 result = nv_interrupt_test(dev);
3914                 if (result != 1) {
3915                         test->flags |= ETH_TEST_FL_FAILED;
3916                         buffer[2] = 1;
3917                 }
3918                 if (result == 0) {
3919                         /* bail out */
3920                         return;
3921                 }
3922
3923                 if (!nv_loopback_test(dev)) {
3924                         test->flags |= ETH_TEST_FL_FAILED;
3925                         buffer[3] = 1;
3926                 }
3927
3928                 if (netif_running(dev)) {
3929                         /* reinit driver view of the rx queue */
3930                         set_bufsize(dev);
3931                         if (nv_init_ring(dev)) {
3932                                 if (!np->in_shutdown)
3933                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3934                         }
3935                         /* reinit nic view of the rx queue */
3936                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3937                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3938                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3939                                 base + NvRegRingSizes);
3940                         pci_push(base);
3941                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3942                         pci_push(base);
3943                         /* restart rx engine */
3944                         nv_start_rx(dev);
3945                         nv_start_tx(dev);
3946                         netif_start_queue(dev);
3947                         netif_poll_enable(dev);
3948                         nv_enable_hw_interrupts(dev, np->irqmask);
3949                 }
3950         }
3951 }
3952
3953 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3954 {
3955         switch (stringset) {
3956         case ETH_SS_STATS:
3957                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3958                 break;
3959         case ETH_SS_TEST:
3960                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
3961                 break;
3962         }
3963 }
3964
3965 static struct ethtool_ops ops = {
3966         .get_drvinfo = nv_get_drvinfo,
3967         .get_link = ethtool_op_get_link,
3968         .get_wol = nv_get_wol,
3969         .set_wol = nv_set_wol,
3970         .get_settings = nv_get_settings,
3971         .set_settings = nv_set_settings,
3972         .get_regs_len = nv_get_regs_len,
3973         .get_regs = nv_get_regs,
3974         .nway_reset = nv_nway_reset,
3975         .get_perm_addr = ethtool_op_get_perm_addr,
3976         .get_tso = ethtool_op_get_tso,
3977         .set_tso = nv_set_tso,
3978         .get_ringparam = nv_get_ringparam,
3979         .set_ringparam = nv_set_ringparam,
3980         .get_pauseparam = nv_get_pauseparam,
3981         .set_pauseparam = nv_set_pauseparam,
3982         .get_rx_csum = nv_get_rx_csum,
3983         .set_rx_csum = nv_set_rx_csum,
3984         .get_tx_csum = ethtool_op_get_tx_csum,
3985         .set_tx_csum = nv_set_tx_csum,
3986         .get_sg = ethtool_op_get_sg,
3987         .set_sg = nv_set_sg,
3988         .get_strings = nv_get_strings,
3989         .get_stats_count = nv_get_stats_count,
3990         .get_ethtool_stats = nv_get_ethtool_stats,
3991         .self_test_count = nv_self_test_count,
3992         .self_test = nv_self_test,
3993 };
3994
3995 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
3996 {
3997         struct fe_priv *np = get_nvpriv(dev);
3998
3999         spin_lock_irq(&np->lock);
4000
4001         /* save vlan group */
4002         np->vlangrp = grp;
4003
4004         if (grp) {
4005                 /* enable vlan on MAC */
4006                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4007         } else {
4008                 /* disable vlan on MAC */
4009                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4010                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4011         }
4012
4013         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4014
4015         spin_unlock_irq(&np->lock);
4016 };
4017
4018 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4019 {
4020         /* nothing to do */
4021 };
4022
4023 static int nv_open(struct net_device *dev)
4024 {
4025         struct fe_priv *np = netdev_priv(dev);
4026         u8 __iomem *base = get_hwbase(dev);
4027         int ret = 1;
4028         int oom, i;
4029
4030         dprintk(KERN_DEBUG "nv_open: begin\n");
4031
4032         /* erase previous misconfiguration */
4033         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4034                 nv_mac_reset(dev);
4035         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4036         writel(0, base + NvRegMulticastAddrB);
4037         writel(0, base + NvRegMulticastMaskA);
4038         writel(0, base + NvRegMulticastMaskB);
4039         writel(0, base + NvRegPacketFilterFlags);
4040
4041         writel(0, base + NvRegTransmitterControl);
4042         writel(0, base + NvRegReceiverControl);
4043
4044         writel(0, base + NvRegAdapterControl);
4045
4046         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4047                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4048
4049         /* initialize descriptor rings */
4050         set_bufsize(dev);
4051         oom = nv_init_ring(dev);
4052
4053         writel(0, base + NvRegLinkSpeed);
4054         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4055         nv_txrx_reset(dev);
4056         writel(0, base + NvRegUnknownSetupReg6);
4057
4058         np->in_shutdown = 0;
4059
4060         /* give hw rings */
4061         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4062         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4063                 base + NvRegRingSizes);
4064
4065         writel(np->linkspeed, base + NvRegLinkSpeed);
4066         if (np->desc_ver == DESC_VER_1)
4067                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4068         else
4069                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4070         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4071         writel(np->vlanctl_bits, base + NvRegVlanControl);
4072         pci_push(base);
4073         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4074         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4075                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4076                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4077
4078         writel(0, base + NvRegUnknownSetupReg4);
4079         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4080         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4081
4082         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4083         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4084         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4085         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4086
4087         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4088         get_random_bytes(&i, sizeof(i));
4089         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4090         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4091         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4092         if (poll_interval == -1) {
4093                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4094                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4095                 else
4096                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4097         }
4098         else
4099                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4100         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4101         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4102                         base + NvRegAdapterControl);
4103         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4104         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
4105         if (np->wolenabled)
4106                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4107
4108         i = readl(base + NvRegPowerState);
4109         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4110                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4111
4112         pci_push(base);
4113         udelay(10);
4114         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4115
4116         nv_disable_hw_interrupts(dev, np->irqmask);
4117         pci_push(base);
4118         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4119         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4120         pci_push(base);
4121
4122         if (nv_request_irq(dev, 0)) {
4123                 goto out_drain;
4124         }
4125
4126         /* ask for interrupts */
4127         nv_enable_hw_interrupts(dev, np->irqmask);
4128
4129         spin_lock_irq(&np->lock);
4130         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4131         writel(0, base + NvRegMulticastAddrB);
4132         writel(0, base + NvRegMulticastMaskA);
4133         writel(0, base + NvRegMulticastMaskB);
4134         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4135         /* One manual link speed update: Interrupts are enabled, future link
4136          * speed changes cause interrupts and are handled by nv_link_irq().
4137          */
4138         {
4139                 u32 miistat;
4140                 miistat = readl(base + NvRegMIIStatus);
4141                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4142                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4143         }
4144         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4145          * to init hw */
4146         np->linkspeed = 0;
4147         ret = nv_update_linkspeed(dev);
4148         nv_start_rx(dev);
4149         nv_start_tx(dev);
4150         netif_start_queue(dev);
4151         netif_poll_enable(dev);
4152
4153         if (ret) {
4154                 netif_carrier_on(dev);
4155         } else {
4156                 printk("%s: no link during initialization.\n", dev->name);
4157                 netif_carrier_off(dev);
4158         }
4159         if (oom)
4160                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4161
4162         /* start statistics timer */
4163         if (np->driver_data & DEV_HAS_STATISTICS)
4164                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4165
4166         spin_unlock_irq(&np->lock);
4167
4168         return 0;
4169 out_drain:
4170         drain_ring(dev);
4171         return ret;
4172 }
4173
4174 static int nv_close(struct net_device *dev)
4175 {
4176         struct fe_priv *np = netdev_priv(dev);
4177         u8 __iomem *base;
4178
4179         spin_lock_irq(&np->lock);
4180         np->in_shutdown = 1;
4181         spin_unlock_irq(&np->lock);
4182         netif_poll_disable(dev);
4183         synchronize_irq(dev->irq);
4184
4185         del_timer_sync(&np->oom_kick);
4186         del_timer_sync(&np->nic_poll);
4187         del_timer_sync(&np->stats_poll);
4188
4189         netif_stop_queue(dev);
4190         spin_lock_irq(&np->lock);
4191         nv_stop_tx(dev);
4192         nv_stop_rx(dev);
4193         nv_txrx_reset(dev);
4194
4195         /* disable interrupts on the nic or we will lock up */
4196         base = get_hwbase(dev);
4197         nv_disable_hw_interrupts(dev, np->irqmask);
4198         pci_push(base);
4199         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4200
4201         spin_unlock_irq(&np->lock);
4202
4203         nv_free_irq(dev);
4204
4205         drain_ring(dev);
4206
4207         if (np->wolenabled)
4208                 nv_start_rx(dev);
4209
4210         /* FIXME: power down nic */
4211
4212         return 0;
4213 }
4214
4215 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4216 {
4217         struct net_device *dev;
4218         struct fe_priv *np;
4219         unsigned long addr;
4220         u8 __iomem *base;
4221         int err, i;
4222         u32 powerstate, txreg;
4223
4224         dev = alloc_etherdev(sizeof(struct fe_priv));
4225         err = -ENOMEM;
4226         if (!dev)
4227                 goto out;
4228
4229         np = netdev_priv(dev);
4230         np->pci_dev = pci_dev;
4231         spin_lock_init(&np->lock);
4232         SET_MODULE_OWNER(dev);
4233         SET_NETDEV_DEV(dev, &pci_dev->dev);
4234
4235         init_timer(&np->oom_kick);
4236         np->oom_kick.data = (unsigned long) dev;
4237         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4238         init_timer(&np->nic_poll);
4239         np->nic_poll.data = (unsigned long) dev;
4240         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4241         init_timer(&np->stats_poll);
4242         np->stats_poll.data = (unsigned long) dev;
4243         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4244
4245         err = pci_enable_device(pci_dev);
4246         if (err) {
4247                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4248                                 err, pci_name(pci_dev));
4249                 goto out_free;
4250         }
4251
4252         pci_set_master(pci_dev);
4253
4254         err = pci_request_regions(pci_dev, DRV_NAME);
4255         if (err < 0)
4256                 goto out_disable;
4257
4258         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4259                 np->register_size = NV_PCI_REGSZ_VER2;
4260         else
4261                 np->register_size = NV_PCI_REGSZ_VER1;
4262
4263         err = -EINVAL;
4264         addr = 0;
4265         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4266                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4267                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4268                                 pci_resource_len(pci_dev, i),
4269                                 pci_resource_flags(pci_dev, i));
4270                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4271                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4272                         addr = pci_resource_start(pci_dev, i);
4273                         break;
4274                 }
4275         }
4276         if (i == DEVICE_COUNT_RESOURCE) {
4277                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4278                                         pci_name(pci_dev));
4279                 goto out_relreg;
4280         }
4281
4282         /* copy of driver data */
4283         np->driver_data = id->driver_data;
4284
4285         /* handle different descriptor versions */
4286         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4287                 /* packet format 3: supports 40-bit addressing */
4288                 np->desc_ver = DESC_VER_3;
4289                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4290                 if (dma_64bit) {
4291                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4292                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4293                                        pci_name(pci_dev));
4294                         } else {
4295                                 dev->features |= NETIF_F_HIGHDMA;
4296                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4297                         }
4298                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4299                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4300                                        pci_name(pci_dev));
4301                         }
4302                 }
4303         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4304                 /* packet format 2: supports jumbo frames */
4305                 np->desc_ver = DESC_VER_2;
4306                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4307         } else {
4308                 /* original packet format */
4309                 np->desc_ver = DESC_VER_1;
4310                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4311         }
4312
4313         np->pkt_limit = NV_PKTLIMIT_1;
4314         if (id->driver_data & DEV_HAS_LARGEDESC)
4315                 np->pkt_limit = NV_PKTLIMIT_2;
4316
4317         if (id->driver_data & DEV_HAS_CHECKSUM) {
4318                 np->rx_csum = 1;
4319                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4320                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4321 #ifdef NETIF_F_TSO
4322                 dev->features |= NETIF_F_TSO;
4323 #endif
4324         }
4325
4326         np->vlanctl_bits = 0;
4327         if (id->driver_data & DEV_HAS_VLAN) {
4328                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4329                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4330                 dev->vlan_rx_register = nv_vlan_rx_register;
4331                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4332         }
4333
4334         np->msi_flags = 0;
4335         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4336                 np->msi_flags |= NV_MSI_CAPABLE;
4337         }
4338         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4339                 np->msi_flags |= NV_MSI_X_CAPABLE;
4340         }
4341
4342         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4343         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4344                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4345         }
4346
4347
4348         err = -ENOMEM;
4349         np->base = ioremap(addr, np->register_size);
4350         if (!np->base)
4351                 goto out_relreg;
4352         dev->base_addr = (unsigned long)np->base;
4353
4354         dev->irq = pci_dev->irq;
4355
4356         np->rx_ring_size = RX_RING_DEFAULT;
4357         np->tx_ring_size = TX_RING_DEFAULT;
4358         np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4359         np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4360
4361         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4362                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4363                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4364                                         &np->ring_addr);
4365                 if (!np->rx_ring.orig)
4366                         goto out_unmap;
4367                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4368         } else {
4369                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4370                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4371                                         &np->ring_addr);
4372                 if (!np->rx_ring.ex)
4373                         goto out_unmap;
4374                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4375         }
4376         np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4377         np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4378         np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4379         np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4380         np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4381         if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4382                 goto out_freering;
4383         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4384         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4385         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4386         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4387         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4388
4389         dev->open = nv_open;
4390         dev->stop = nv_close;
4391         dev->hard_start_xmit = nv_start_xmit;
4392         dev->get_stats = nv_get_stats;
4393         dev->change_mtu = nv_change_mtu;
4394         dev->set_mac_address = nv_set_mac_address;
4395         dev->set_multicast_list = nv_set_multicast;
4396 #ifdef CONFIG_NET_POLL_CONTROLLER
4397         dev->poll_controller = nv_poll_controller;
4398 #endif
4399         dev->weight = 64;
4400 #ifdef CONFIG_FORCEDETH_NAPI
4401         dev->poll = nv_napi_poll;
4402 #endif
4403         SET_ETHTOOL_OPS(dev, &ops);
4404         dev->tx_timeout = nv_tx_timeout;
4405         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4406
4407         pci_set_drvdata(pci_dev, dev);
4408
4409         /* read the mac address */
4410         base = get_hwbase(dev);
4411         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4412         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4413
4414         /* check the workaround bit for correct mac address order */
4415         txreg = readl(base + NvRegTransmitPoll);
4416         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4417                 /* mac address is already in correct order */
4418                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
4419                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
4420                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4421                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4422                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
4423                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
4424         } else {
4425                 /* need to reverse mac address to correct order */
4426                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4427                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4428                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4429                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4430                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4431                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4432                 /* set permanent address to be correct aswell */
4433                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4434                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4435                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4436                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4437         }
4438         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4439
4440         if (!is_valid_ether_addr(dev->perm_addr)) {
4441                 /*
4442                  * Bad mac address. At least one bios sets the mac address
4443                  * to 01:23:45:67:89:ab
4444                  */
4445                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4446                         pci_name(pci_dev),
4447                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4448                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4449                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4450                 dev->dev_addr[0] = 0x00;
4451                 dev->dev_addr[1] = 0x00;
4452                 dev->dev_addr[2] = 0x6c;
4453                 get_random_bytes(&dev->dev_addr[3], 3);
4454         }
4455
4456         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4457                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4458                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4459
4460         /* set mac address */
4461         nv_copy_mac_to_hw(dev);
4462
4463         /* disable WOL */
4464         writel(0, base + NvRegWakeUpFlags);
4465         np->wolenabled = 0;
4466
4467         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4468                 u8 revision_id;
4469                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4470
4471                 /* take phy and nic out of low power mode */
4472                 powerstate = readl(base + NvRegPowerState2);
4473                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4474                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4475                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4476                     revision_id >= 0xA3)
4477                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4478                 writel(powerstate, base + NvRegPowerState2);
4479         }
4480
4481         if (np->desc_ver == DESC_VER_1) {
4482                 np->tx_flags = NV_TX_VALID;
4483         } else {
4484                 np->tx_flags = NV_TX2_VALID;
4485         }
4486         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4487                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4488                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4489                         np->msi_flags |= 0x0003;
4490         } else {
4491                 np->irqmask = NVREG_IRQMASK_CPU;
4492                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4493                         np->msi_flags |= 0x0001;
4494         }
4495
4496         if (id->driver_data & DEV_NEED_TIMERIRQ)
4497                 np->irqmask |= NVREG_IRQ_TIMER;
4498         if (id->driver_data & DEV_NEED_LINKTIMER) {
4499                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4500                 np->need_linktimer = 1;
4501                 np->link_timeout = jiffies + LINK_TIMEOUT;
4502         } else {
4503                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4504                 np->need_linktimer = 0;
4505         }
4506
4507         /* find a suitable phy */
4508         for (i = 1; i <= 32; i++) {
4509                 int id1, id2;
4510                 int phyaddr = i & 0x1F;
4511
4512                 spin_lock_irq(&np->lock);
4513                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4514                 spin_unlock_irq(&np->lock);
4515                 if (id1 < 0 || id1 == 0xffff)
4516                         continue;
4517                 spin_lock_irq(&np->lock);
4518                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4519                 spin_unlock_irq(&np->lock);
4520                 if (id2 < 0 || id2 == 0xffff)
4521                         continue;
4522
4523                 np->phy_model = id2 & PHYID2_MODEL_MASK;
4524                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4525                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4526                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4527                         pci_name(pci_dev), id1, id2, phyaddr);
4528                 np->phyaddr = phyaddr;
4529                 np->phy_oui = id1 | id2;
4530                 break;
4531         }
4532         if (i == 33) {
4533                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4534                        pci_name(pci_dev));
4535                 goto out_error;
4536         }
4537
4538         /* reset it */
4539         phy_init(dev);
4540
4541         /* set default link speed settings */
4542         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4543         np->duplex = 0;
4544         np->autoneg = 1;
4545
4546         err = register_netdev(dev);
4547         if (err) {
4548                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4549                 goto out_error;
4550         }
4551         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4552                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4553                         pci_name(pci_dev));
4554
4555         return 0;
4556
4557 out_error:
4558         pci_set_drvdata(pci_dev, NULL);
4559 out_freering:
4560         free_rings(dev);
4561 out_unmap:
4562         iounmap(get_hwbase(dev));
4563 out_relreg:
4564         pci_release_regions(pci_dev);
4565 out_disable:
4566         pci_disable_device(pci_dev);
4567 out_free:
4568         free_netdev(dev);
4569 out:
4570         return err;
4571 }
4572
4573 static void __devexit nv_remove(struct pci_dev *pci_dev)
4574 {
4575         struct net_device *dev = pci_get_drvdata(pci_dev);
4576         struct fe_priv *np = netdev_priv(dev);
4577         u8 __iomem *base = get_hwbase(dev);
4578
4579         unregister_netdev(dev);
4580
4581         /* special op: write back the misordered MAC address - otherwise
4582          * the next nv_probe would see a wrong address.
4583          */
4584         writel(np->orig_mac[0], base + NvRegMacAddrA);
4585         writel(np->orig_mac[1], base + NvRegMacAddrB);
4586
4587         /* free all structures */
4588         free_rings(dev);
4589         iounmap(get_hwbase(dev));
4590         pci_release_regions(pci_dev);
4591         pci_disable_device(pci_dev);
4592         free_netdev(dev);
4593         pci_set_drvdata(pci_dev, NULL);
4594 }
4595
4596 static struct pci_device_id pci_tbl[] = {
4597         {       /* nForce Ethernet Controller */
4598                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4599                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4600         },
4601         {       /* nForce2 Ethernet Controller */
4602                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4603                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4604         },
4605         {       /* nForce3 Ethernet Controller */
4606                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4607                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4608         },
4609         {       /* nForce3 Ethernet Controller */
4610                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4611                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4612         },
4613         {       /* nForce3 Ethernet Controller */
4614                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4615                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4616         },
4617         {       /* nForce3 Ethernet Controller */
4618                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4619                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4620         },
4621         {       /* nForce3 Ethernet Controller */
4622                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4623                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4624         },
4625         {       /* CK804 Ethernet Controller */
4626                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4627                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4628         },
4629         {       /* CK804 Ethernet Controller */
4630                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4631                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4632         },
4633         {       /* MCP04 Ethernet Controller */
4634                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4635                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4636         },
4637         {       /* MCP04 Ethernet Controller */
4638                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4639                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4640         },
4641         {       /* MCP51 Ethernet Controller */
4642                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4643                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4644         },
4645         {       /* MCP51 Ethernet Controller */
4646                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4647                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4648         },
4649         {       /* MCP55 Ethernet Controller */
4650                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4651                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4652         },
4653         {       /* MCP55 Ethernet Controller */
4654                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4655                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4656         },
4657         {       /* MCP61 Ethernet Controller */
4658                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4659                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4660         },
4661         {       /* MCP61 Ethernet Controller */
4662                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4663                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4664         },
4665         {       /* MCP61 Ethernet Controller */
4666                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4667                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4668         },
4669         {       /* MCP61 Ethernet Controller */
4670                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4671                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4672         },
4673         {       /* MCP65 Ethernet Controller */
4674                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4675                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4676         },
4677         {       /* MCP65 Ethernet Controller */
4678                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4679                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4680         },
4681         {       /* MCP65 Ethernet Controller */
4682                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4683                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4684         },
4685         {       /* MCP65 Ethernet Controller */
4686                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4687                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4688         },
4689         {0,},
4690 };
4691
4692 static struct pci_driver driver = {
4693         .name = "forcedeth",
4694         .id_table = pci_tbl,
4695         .probe = nv_probe,
4696         .remove = __devexit_p(nv_remove),
4697 };
4698
4699
4700 static int __init init_nic(void)
4701 {
4702         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4703         return pci_register_driver(&driver);
4704 }
4705
4706 static void __exit exit_nic(void)
4707 {
4708         pci_unregister_driver(&driver);
4709 }
4710
4711 module_param(max_interrupt_work, int, 0);
4712 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4713 module_param(optimization_mode, int, 0);
4714 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4715 module_param(poll_interval, int, 0);
4716 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4717 module_param(msi, int, 0);
4718 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4719 module_param(msix, int, 0);
4720 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4721 module_param(dma_64bit, int, 0);
4722 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4723
4724 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4725 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4726 MODULE_LICENSE("GPL");
4727
4728 MODULE_DEVICE_TABLE(pci, pci_tbl);
4729
4730 module_init(init_nic);
4731 module_exit(exit_nic);