git.oblomov.eu Git - linux-2.6/blob - drivers/video/nvidia/nvidia.c

   1 /*
   2  * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
   3  *
   4  * Copyright 2004 Antonino Daplas <adaplas@pol.net>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file COPYING in the main directory of this archive
   8  * for more details.
   9  *
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/errno.h>
  15 #include <linux/string.h>
  16 #include <linux/mm.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/fb.h>
  20 #include <linux/init.h>
  21 #include <linux/pci.h>
  22 #include <linux/console.h>
  23 #include <linux/backlight.h>
  24 #ifdef CONFIG_MTRR
  25 #include <asm/mtrr.h>
  26 #endif
  27 #ifdef CONFIG_PPC_OF
  28 #include <asm/prom.h>
  29 #include <asm/pci-bridge.h>
  30 #endif
  31 #ifdef CONFIG_BOOTX_TEXT
  32 #include <asm/btext.h>
  33 #endif
  34
  35 #include "nv_local.h"
  36 #include "nv_type.h"
  37 #include "nv_proto.h"
  38 #include "nv_dma.h"
  39
  40 #ifdef CONFIG_FB_NVIDIA_DEBUG
  41 #define NVTRACE          printk
  42 #else
  43 #define NVTRACE          if (0) printk
  44 #endif
  45
  46 #define NVTRACE_ENTER(...)  NVTRACE("%s START\n", __FUNCTION__)
  47 #define NVTRACE_LEAVE(...)  NVTRACE("%s END\n", __FUNCTION__)
  48
  49 #ifdef CONFIG_FB_NVIDIA_DEBUG
  50 #define assert(expr) \
  51         if (!(expr)) { \
  52         printk( "Assertion failed! %s,%s,%s,line=%d\n",\
  53         #expr,__FILE__,__FUNCTION__,__LINE__); \
  54         BUG(); \
  55         }
  56 #else
  57 #define assert(expr)
  58 #endif
  59
  60 #define PFX "nvidiafb: "
  61
  62 /* HW cursor parameters */
  63 #define MAX_CURS                32
  64
  65 static struct pci_device_id nvidiafb_pci_tbl[] = {
  66         {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  67          PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
  68         { 0, }
  69 };
  70 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
  71
  72 /* command line data, set in nvidiafb_setup() */
  73 static int flatpanel __devinitdata = -1;        /* Autodetect later */
  74 static int fpdither __devinitdata = -1;
  75 static int forceCRTC __devinitdata = -1;
  76 static int hwcur __devinitdata = 0;
  77 static int noaccel __devinitdata = 0;
  78 static int noscale __devinitdata = 0;
  79 static int paneltweak __devinitdata = 0;
  80 static int vram __devinitdata = 0;
  81 static int bpp __devinitdata = 8;
  82 #ifdef CONFIG_MTRR
  83 static int nomtrr __devinitdata = 0;
  84 #endif
  85 #ifdef CONFIG_PMAC_BACKLIGHT
  86 static int backlight __devinitdata = 1;
  87 #else
  88 static int backlight __devinitdata = 0;
  89 #endif
  90
  91 static char *mode_option __devinitdata = NULL;
  92
  93 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
  94         .type = FB_TYPE_PACKED_PIXELS,
  95         .xpanstep = 8,
  96         .ypanstep = 1,
  97 };
  98
  99 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
 100         .xres = 640,
 101         .yres = 480,
 102         .xres_virtual = 640,
 103         .yres_virtual = 480,
 104         .bits_per_pixel = 8,
 105         .red = {0, 8, 0},
 106         .green = {0, 8, 0},
 107         .blue = {0, 8, 0},
 108         .transp = {0, 0, 0},
 109         .activate = FB_ACTIVATE_NOW,
 110         .height = -1,
 111         .width = -1,
 112         .pixclock = 39721,
 113         .left_margin = 40,
 114         .right_margin = 24,
 115         .upper_margin = 32,
 116         .lower_margin = 11,
 117         .hsync_len = 96,
 118         .vsync_len = 2,
 119         .vmode = FB_VMODE_NONINTERLACED
 120 };
 121
 122 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
 123                                        u16 bg, u16 fg, u32 w, u32 h)
 124 {
 125         u32 *data = (u32 *) data8;
 126         int i, j, k = 0;
 127         u32 b, tmp;
 128
 129         w = (w + 1) & ~1;
 130
 131         for (i = 0; i < h; i++) {
 132                 b = *data++;
 133                 reverse_order(&b);
 134
 135                 for (j = 0; j < w / 2; j++) {
 136                         tmp = 0;
 137 #if defined (__BIG_ENDIAN)
 138                         tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
 139                         b <<= 1;
 140                         tmp |= (b & (1 << 31)) ? fg : bg;
 141                         b <<= 1;
 142 #else
 143                         tmp = (b & 1) ? fg : bg;
 144                         b >>= 1;
 145                         tmp |= (b & 1) ? fg << 16 : bg << 16;
 146                         b >>= 1;
 147 #endif
 148                         NV_WR32(&par->CURSOR[k++], 0, tmp);
 149                 }
 150                 k += (MAX_CURS - w) / 2;
 151         }
 152 }
 153
 154 static void nvidia_write_clut(struct nvidia_par *par,
 155                               u8 regnum, u8 red, u8 green, u8 blue)
 156 {
 157         NVWriteDacMask(par, 0xff);
 158         NVWriteDacWriteAddr(par, regnum);
 159         NVWriteDacData(par, red);
 160         NVWriteDacData(par, green);
 161         NVWriteDacData(par, blue);
 162 }
 163
 164 static void nvidia_read_clut(struct nvidia_par *par,
 165                              u8 regnum, u8 * red, u8 * green, u8 * blue)
 166 {
 167         NVWriteDacMask(par, 0xff);
 168         NVWriteDacReadAddr(par, regnum);
 169         *red = NVReadDacData(par);
 170         *green = NVReadDacData(par);
 171         *blue = NVReadDacData(par);
 172 }
 173
 174 static int nvidia_panel_tweak(struct nvidia_par *par,
 175                               struct _riva_hw_state *state)
 176 {
 177         int tweak = 0;
 178
 179    if (par->paneltweak) {
 180            tweak = par->paneltweak;
 181    } else {
 182            /* begin flat panel hacks */
 183            /* This is unfortunate, but some chips need this register
 184               tweaked or else you get artifacts where adjacent pixels are
 185               swapped.  There are no hard rules for what to set here so all
 186               we can do is experiment and apply hacks. */
 187
 188            if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
 189                    /* At least one NV34 laptop needs this workaround. */
 190                    tweak = -1;
 191            }
 192
 193            if((par->Chipset & 0xfff0) == 0x0310) {
 194                    tweak = 1;
 195            }
 196            /* end flat panel hacks */
 197    }
 198
 199    return tweak;
 200 }
 201
 202 static void nvidia_screen_off(struct nvidia_par *par, int on)
 203 {
 204         unsigned char tmp;
 205
 206         if (on) {
 207                 /*
 208                  * Turn off screen and disable sequencer.
 209                  */
 210                 tmp = NVReadSeq(par, 0x01);
 211
 212                 NVWriteSeq(par, 0x00, 0x01);            /* Synchronous Reset */
 213                 NVWriteSeq(par, 0x01, tmp | 0x20);      /* disable the display */
 214         } else {
 215                 /*
 216                  * Reenable sequencer, then turn on screen.
 217                  */
 218
 219                 tmp = NVReadSeq(par, 0x01);
 220
 221                 NVWriteSeq(par, 0x01, tmp & ~0x20);     /* reenable display */
 222                 NVWriteSeq(par, 0x00, 0x03);            /* End Reset */
 223         }
 224 }
 225
 226 static void nvidia_save_vga(struct nvidia_par *par,
 227                             struct _riva_hw_state *state)
 228 {
 229         int i;
 230
 231         NVTRACE_ENTER();
 232         NVLockUnlock(par, 0);
 233
 234         NVUnloadStateExt(par, state);
 235
 236         state->misc_output = NVReadMiscOut(par);
 237
 238         for (i = 0; i < NUM_CRT_REGS; i++)
 239                 state->crtc[i] = NVReadCrtc(par, i);
 240
 241         for (i = 0; i < NUM_ATC_REGS; i++)
 242                 state->attr[i] = NVReadAttr(par, i);
 243
 244         for (i = 0; i < NUM_GRC_REGS; i++)
 245                 state->gra[i] = NVReadGr(par, i);
 246
 247         for (i = 0; i < NUM_SEQ_REGS; i++)
 248                 state->seq[i] = NVReadSeq(par, i);
 249         NVTRACE_LEAVE();
 250 }
 251
 252 #undef DUMP_REG
 253
 254 static void nvidia_write_regs(struct nvidia_par *par,
 255                               struct _riva_hw_state *state)
 256 {
 257         int i;
 258
 259         NVTRACE_ENTER();
 260
 261         NVLoadStateExt(par, state);
 262
 263         NVWriteMiscOut(par, state->misc_output);
 264
 265         for (i = 1; i < NUM_SEQ_REGS; i++) {
 266 #ifdef DUMP_REG
 267                 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
 268 #endif
 269                 NVWriteSeq(par, i, state->seq[i]);
 270         }
 271
 272         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
 273         NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
 274
 275         for (i = 0; i < NUM_CRT_REGS; i++) {
 276                 switch (i) {
 277                 case 0x19:
 278                 case 0x20 ... 0x40:
 279                         break;
 280                 default:
 281 #ifdef DUMP_REG
 282                         printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
 283 #endif
 284                         NVWriteCrtc(par, i, state->crtc[i]);
 285                 }
 286         }
 287
 288         for (i = 0; i < NUM_GRC_REGS; i++) {
 289 #ifdef DUMP_REG
 290                 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
 291 #endif
 292                 NVWriteGr(par, i, state->gra[i]);
 293         }
 294
 295         for (i = 0; i < NUM_ATC_REGS; i++) {
 296 #ifdef DUMP_REG
 297                 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
 298 #endif
 299                 NVWriteAttr(par, i, state->attr[i]);
 300         }
 301
 302         NVTRACE_LEAVE();
 303 }
 304
 305 static int nvidia_calc_regs(struct fb_info *info)
 306 {
 307         struct nvidia_par *par = info->par;
 308         struct _riva_hw_state *state = &par->ModeReg;
 309         int i, depth = fb_get_color_depth(&info->var, &info->fix);
 310         int h_display = info->var.xres / 8 - 1;
 311         int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
 312         int h_end = (info->var.xres + info->var.right_margin +
 313                      info->var.hsync_len) / 8 - 1;
 314         int h_total = (info->var.xres + info->var.right_margin +
 315                        info->var.hsync_len + info->var.left_margin) / 8 - 5;
 316         int h_blank_s = h_display;
 317         int h_blank_e = h_total + 4;
 318         int v_display = info->var.yres - 1;
 319         int v_start = info->var.yres + info->var.lower_margin - 1;
 320         int v_end = (info->var.yres + info->var.lower_margin +
 321                      info->var.vsync_len) - 1;
 322         int v_total = (info->var.yres + info->var.lower_margin +
 323                        info->var.vsync_len + info->var.upper_margin) - 2;
 324         int v_blank_s = v_display;
 325         int v_blank_e = v_total + 1;
 326
 327         /*
 328          * Set all CRTC values.
 329          */
 330
 331         if (info->var.vmode & FB_VMODE_INTERLACED)
 332                 v_total |= 1;
 333
 334         if (par->FlatPanel == 1) {
 335                 v_start = v_total - 3;
 336                 v_end = v_total - 2;
 337                 v_blank_s = v_start;
 338                 h_start = h_total - 5;
 339                 h_end = h_total - 2;
 340                 h_blank_e = h_total + 4;
 341         }
 342
 343         state->crtc[0x0] = Set8Bits(h_total);
 344         state->crtc[0x1] = Set8Bits(h_display);
 345         state->crtc[0x2] = Set8Bits(h_blank_s);
 346         state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
 347                 | SetBit(7);
 348         state->crtc[0x4] = Set8Bits(h_start);
 349         state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
 350                 | SetBitField(h_end, 4: 0, 4:0);
 351         state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
 352         state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
 353                 | SetBitField(v_display, 8: 8, 1:1)
 354                 | SetBitField(v_start, 8: 8, 2:2)
 355                 | SetBitField(v_blank_s, 8: 8, 3:3)
 356                 | SetBit(4)
 357                 | SetBitField(v_total, 9: 9, 5:5)
 358                 | SetBitField(v_display, 9: 9, 6:6)
 359                 | SetBitField(v_start, 9: 9, 7:7);
 360         state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
 361                 | SetBit(6)
 362                 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
 363         state->crtc[0x10] = Set8Bits(v_start);
 364         state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
 365         state->crtc[0x12] = Set8Bits(v_display);
 366         state->crtc[0x13] = ((info->var.xres_virtual / 8) *
 367                              (info->var.bits_per_pixel / 8));
 368         state->crtc[0x15] = Set8Bits(v_blank_s);
 369         state->crtc[0x16] = Set8Bits(v_blank_e);
 370
 371         state->attr[0x10] = 0x01;
 372
 373         if (par->Television)
 374                 state->attr[0x11] = 0x00;
 375
 376         state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
 377                 | SetBitField(v_blank_s, 10: 10, 3:3)
 378                 | SetBitField(v_start, 10: 10, 2:2)
 379                 | SetBitField(v_display, 10: 10, 1:1)
 380                 | SetBitField(v_total, 10: 10, 0:0);
 381
 382         state->horiz = SetBitField(h_total, 8: 8, 0:0)
 383                 | SetBitField(h_display, 8: 8, 1:1)
 384                 | SetBitField(h_blank_s, 8: 8, 2:2)
 385                 | SetBitField(h_start, 8: 8, 3:3);
 386
 387         state->extra = SetBitField(v_total, 11: 11, 0:0)
 388                 | SetBitField(v_display, 11: 11, 2:2)
 389                 | SetBitField(v_start, 11: 11, 4:4)
 390                 | SetBitField(v_blank_s, 11: 11, 6:6);
 391
 392         if (info->var.vmode & FB_VMODE_INTERLACED) {
 393                 h_total = (h_total >> 1) & ~1;
 394                 state->interlace = Set8Bits(h_total);
 395                 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
 396         } else {
 397                 state->interlace = 0xff;        /* interlace off */
 398         }
 399
 400         /*
 401          * Calculate the extended registers.
 402          */
 403
 404         if (depth < 24)
 405                 i = depth;
 406         else
 407                 i = 32;
 408
 409         if (par->Architecture >= NV_ARCH_10)
 410                 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
 411                                                        par->CursorStart);
 412
 413         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 414                 state->misc_output &= ~0x40;
 415         else
 416                 state->misc_output |= 0x40;
 417         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 418                 state->misc_output &= ~0x80;
 419         else
 420                 state->misc_output |= 0x80;
 421
 422         NVCalcStateExt(par, state, i, info->var.xres_virtual,
 423                        info->var.xres, info->var.yres_virtual,
 424                        1000000000 / info->var.pixclock, info->var.vmode);
 425
 426         state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
 427         if (par->FlatPanel == 1) {
 428                 state->pixel |= (1 << 7);
 429
 430                 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
 431                     || (par->fpHeight <= info->var.yres)) {
 432                         state->scale |= (1 << 8);
 433                 }
 434
 435                 if (!par->crtcSync_read) {
 436                         state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
 437                         par->crtcSync_read = 1;
 438                 }
 439
 440                 par->PanelTweak = nvidia_panel_tweak(par, state);
 441         }
 442
 443         state->vpll = state->pll;
 444         state->vpll2 = state->pll;
 445         state->vpllB = state->pllB;
 446         state->vpll2B = state->pllB;
 447
 448         VGA_WR08(par->PCIO, 0x03D4, 0x1C);
 449         state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
 450
 451         if (par->CRTCnumber) {
 452                 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
 453                 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
 454                 state->crtcOwner = 3;
 455                 state->pllsel |= 0x20000800;
 456                 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
 457                 if (par->twoStagePLL)
 458                         state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
 459         } else if (par->twoHeads) {
 460                 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
 461                 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
 462                 state->crtcOwner = 0;
 463                 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
 464                 if (par->twoStagePLL)
 465                         state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
 466         }
 467
 468         state->cursorConfig = 0x00000100;
 469
 470         if (info->var.vmode & FB_VMODE_DOUBLE)
 471                 state->cursorConfig |= (1 << 4);
 472
 473         if (par->alphaCursor) {
 474                 if ((par->Chipset & 0x0ff0) != 0x0110)
 475                         state->cursorConfig |= 0x04011000;
 476                 else
 477                         state->cursorConfig |= 0x14011000;
 478                 state->general |= (1 << 29);
 479         } else
 480                 state->cursorConfig |= 0x02000000;
 481
 482         if (par->twoHeads) {
 483                 if ((par->Chipset & 0x0ff0) == 0x0110) {
 484                         state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
 485                             ~0x00010000;
 486                         if (par->FPDither)
 487                                 state->dither |= 0x00010000;
 488                 } else {
 489                         state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
 490                         if (par->FPDither)
 491                                 state->dither |= 1;
 492                 }
 493         }
 494
 495         state->timingH = 0;
 496         state->timingV = 0;
 497         state->displayV = info->var.xres;
 498
 499         return 0;
 500 }
 501
 502 static void nvidia_init_vga(struct fb_info *info)
 503 {
 504         struct nvidia_par *par = info->par;
 505         struct _riva_hw_state *state = &par->ModeReg;
 506         int i;
 507
 508         for (i = 0; i < 0x10; i++)
 509                 state->attr[i] = i;
 510         state->attr[0x10] = 0x41;
 511         state->attr[0x11] = 0xff;
 512         state->attr[0x12] = 0x0f;
 513         state->attr[0x13] = 0x00;
 514         state->attr[0x14] = 0x00;
 515
 516         memset(state->crtc, 0x00, NUM_CRT_REGS);
 517         state->crtc[0x0a] = 0x20;
 518         state->crtc[0x17] = 0xe3;
 519         state->crtc[0x18] = 0xff;
 520         state->crtc[0x28] = 0x40;
 521
 522         memset(state->gra, 0x00, NUM_GRC_REGS);
 523         state->gra[0x05] = 0x40;
 524         state->gra[0x06] = 0x05;
 525         state->gra[0x07] = 0x0f;
 526         state->gra[0x08] = 0xff;
 527
 528         state->seq[0x00] = 0x03;
 529         state->seq[0x01] = 0x01;
 530         state->seq[0x02] = 0x0f;
 531         state->seq[0x03] = 0x00;
 532         state->seq[0x04] = 0x0e;
 533
 534         state->misc_output = 0xeb;
 535 }
 536
 537 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 538 {
 539         struct nvidia_par *par = info->par;
 540         u8 data[MAX_CURS * MAX_CURS / 8];
 541         int i, set = cursor->set;
 542         u16 fg, bg;
 543
 544         if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
 545                 return -ENXIO;
 546
 547         NVShowHideCursor(par, 0);
 548
 549         if (par->cursor_reset) {
 550                 set = FB_CUR_SETALL;
 551                 par->cursor_reset = 0;
 552         }
 553
 554         if (set & FB_CUR_SETSIZE)
 555                 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
 556
 557         if (set & FB_CUR_SETPOS) {
 558                 u32 xx, yy, temp;
 559
 560                 yy = cursor->image.dy - info->var.yoffset;
 561                 xx = cursor->image.dx - info->var.xoffset;
 562                 temp = xx & 0xFFFF;
 563                 temp |= yy << 16;
 564
 565                 NV_WR32(par->PRAMDAC, 0x0000300, temp);
 566         }
 567
 568         if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
 569                 u32 bg_idx = cursor->image.bg_color;
 570                 u32 fg_idx = cursor->image.fg_color;
 571                 u32 s_pitch = (cursor->image.width + 7) >> 3;
 572                 u32 d_pitch = MAX_CURS / 8;
 573                 u8 *dat = (u8 *) cursor->image.data;
 574                 u8 *msk = (u8 *) cursor->mask;
 575                 u8 *src;
 576
 577                 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
 578
 579                 if (src) {
 580                         switch (cursor->rop) {
 581                         case ROP_XOR:
 582                                 for (i = 0; i < s_pitch * cursor->image.height; i++)
 583                                         src[i] = dat[i] ^ msk[i];
 584                                 break;
 585                         case ROP_COPY:
 586                         default:
 587                                 for (i = 0; i < s_pitch * cursor->image.height; i++)
 588                                         src[i] = dat[i] & msk[i];
 589                                 break;
 590                         }
 591
 592                         fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
 593                                                 cursor->image.height);
 594
 595                         bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
 596                             ((info->cmap.green[bg_idx] & 0xf8) << 2) |
 597                             ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
 598
 599                         fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
 600                             ((info->cmap.green[fg_idx] & 0xf8) << 2) |
 601                             ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
 602
 603                         NVLockUnlock(par, 0);
 604
 605                         nvidiafb_load_cursor_image(par, data, bg, fg,
 606                                                    cursor->image.width,
 607                                                    cursor->image.height);
 608                         kfree(src);
 609                 }
 610         }
 611
 612         if (cursor->enable)
 613                 NVShowHideCursor(par, 1);
 614
 615         return 0;
 616 }
 617
 618 static int nvidiafb_set_par(struct fb_info *info)
 619 {
 620         struct nvidia_par *par = info->par;
 621
 622         NVTRACE_ENTER();
 623
 624         NVLockUnlock(par, 1);
 625         if (!par->FlatPanel || !par->twoHeads)
 626                 par->FPDither = 0;
 627
 628         if (par->FPDither < 0) {
 629                 if ((par->Chipset & 0x0ff0) == 0x0110)
 630                         par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
 631                                            & 0x00010000);
 632                 else
 633                         par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
 634                 printk(KERN_INFO PFX "Flat panel dithering %s\n",
 635                        par->FPDither ? "enabled" : "disabled");
 636         }
 637
 638         info->fix.visual = (info->var.bits_per_pixel == 8) ?
 639             FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
 640
 641         nvidia_init_vga(info);
 642         nvidia_calc_regs(info);
 643
 644         NVLockUnlock(par, 0);
 645         if (par->twoHeads) {
 646                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
 647                 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
 648                 NVLockUnlock(par, 0);
 649         }
 650
 651         nvidia_screen_off(par, 1);
 652
 653         nvidia_write_regs(par, &par->ModeReg);
 654         NVSetStartAddress(par, 0);
 655
 656 #if defined (__BIG_ENDIAN)
 657         /* turn on LFB swapping */
 658         {
 659                 unsigned char tmp;
 660
 661                 VGA_WR08(par->PCIO, 0x3d4, 0x46);
 662                 tmp = VGA_RD08(par->PCIO, 0x3d5);
 663                 tmp |= (1 << 7);
 664                 VGA_WR08(par->PCIO, 0x3d5, tmp);
 665     }
 666 #endif
 667
 668         info->fix.line_length = (info->var.xres_virtual *
 669                                  info->var.bits_per_pixel) >> 3;
 670         if (info->var.accel_flags) {
 671                 info->fbops->fb_imageblit = nvidiafb_imageblit;
 672                 info->fbops->fb_fillrect = nvidiafb_fillrect;
 673                 info->fbops->fb_copyarea = nvidiafb_copyarea;
 674                 info->fbops->fb_sync = nvidiafb_sync;
 675                 info->pixmap.scan_align = 4;
 676                 info->flags &= ~FBINFO_HWACCEL_DISABLED;
 677                 NVResetGraphics(info);
 678         } else {
 679                 info->fbops->fb_imageblit = cfb_imageblit;
 680                 info->fbops->fb_fillrect = cfb_fillrect;
 681                 info->fbops->fb_copyarea = cfb_copyarea;
 682                 info->fbops->fb_sync = NULL;
 683                 info->pixmap.scan_align = 1;
 684                 info->flags |= FBINFO_HWACCEL_DISABLED;
 685         }
 686
 687         par->cursor_reset = 1;
 688
 689         nvidia_screen_off(par, 0);
 690
 691 #ifdef CONFIG_BOOTX_TEXT
 692         /* Update debug text engine */
 693         btext_update_display(info->fix.smem_start,
 694                              info->var.xres, info->var.yres,
 695                              info->var.bits_per_pixel, info->fix.line_length);
 696 #endif
 697
 698         NVLockUnlock(par, 0);
 699         NVTRACE_LEAVE();
 700         return 0;
 701 }
 702
 703 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
 704                               unsigned blue, unsigned transp,
 705                               struct fb_info *info)
 706 {
 707         struct nvidia_par *par = info->par;
 708         int i;
 709
 710         NVTRACE_ENTER();
 711         if (regno >= (1 << info->var.green.length))
 712                 return -EINVAL;
 713
 714         if (info->var.grayscale) {
 715                 /* gray = 0.30*R + 0.59*G + 0.11*B */
 716                 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
 717         }
 718
 719         if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
 720                 ((u32 *) info->pseudo_palette)[regno] =
 721                     (regno << info->var.red.offset) |
 722                     (regno << info->var.green.offset) |
 723                     (regno << info->var.blue.offset);
 724         }
 725
 726         switch (info->var.bits_per_pixel) {
 727         case 8:
 728                 /* "transparent" stuff is completely ignored. */
 729                 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
 730                 break;
 731         case 16:
 732                 if (info->var.green.length == 5) {
 733                         for (i = 0; i < 8; i++) {
 734                                 nvidia_write_clut(par, regno * 8 + i, red >> 8,
 735                                                   green >> 8, blue >> 8);
 736                         }
 737                 } else {
 738                         u8 r, g, b;
 739
 740                         if (regno < 32) {
 741                                 for (i = 0; i < 8; i++) {
 742                                         nvidia_write_clut(par, regno * 8 + i,
 743                                                           red >> 8, green >> 8,
 744                                                           blue >> 8);
 745                                 }
 746                         }
 747
 748                         nvidia_read_clut(par, regno * 4, &r, &g, &b);
 749
 750                         for (i = 0; i < 4; i++)
 751                                 nvidia_write_clut(par, regno * 4 + i, r,
 752                                                   green >> 8, b);
 753                 }
 754                 break;
 755         case 32:
 756                 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
 757                 break;
 758         default:
 759                 /* do nothing */
 760                 break;
 761         }
 762
 763         NVTRACE_LEAVE();
 764         return 0;
 765 }
 766
 767 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
 768                               struct fb_info *info)
 769 {
 770         struct nvidia_par *par = info->par;
 771         int memlen, vramlen, mode_valid = 0;
 772         int pitch, err = 0;
 773
 774         NVTRACE_ENTER();
 775
 776         var->transp.offset = 0;
 777         var->transp.length = 0;
 778
 779         var->xres &= ~7;
 780
 781         if (var->bits_per_pixel <= 8)
 782                 var->bits_per_pixel = 8;
 783         else if (var->bits_per_pixel <= 16)
 784                 var->bits_per_pixel = 16;
 785         else
 786                 var->bits_per_pixel = 32;
 787
 788         switch (var->bits_per_pixel) {
 789         case 8:
 790                 var->red.offset = 0;
 791                 var->red.length = 8;
 792                 var->green.offset = 0;
 793                 var->green.length = 8;
 794                 var->blue.offset = 0;
 795                 var->blue.length = 8;
 796                 var->transp.offset = 0;
 797                 var->transp.length = 0;
 798                 break;
 799         case 16:
 800                 var->green.length = (var->green.length < 6) ? 5 : 6;
 801                 var->red.length = 5;
 802                 var->blue.length = 5;
 803                 var->transp.length = 6 - var->green.length;
 804                 var->blue.offset = 0;
 805                 var->green.offset = 5;
 806                 var->red.offset = 5 + var->green.length;
 807                 var->transp.offset = (5 + var->red.offset) & 15;
 808                 break;
 809         case 32:                /* RGBA 8888 */
 810                 var->red.offset = 16;
 811                 var->red.length = 8;
 812                 var->green.offset = 8;
 813                 var->green.length = 8;
 814                 var->blue.offset = 0;
 815                 var->blue.length = 8;
 816                 var->transp.length = 8;
 817                 var->transp.offset = 24;
 818                 break;
 819         }
 820
 821         var->red.msb_right = 0;
 822         var->green.msb_right = 0;
 823         var->blue.msb_right = 0;
 824         var->transp.msb_right = 0;
 825
 826         if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
 827             !info->monspecs.dclkmax || !fb_validate_mode(var, info))
 828                 mode_valid = 1;
 829
 830         /* calculate modeline if supported by monitor */
 831         if (!mode_valid && info->monspecs.gtf) {
 832                 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
 833                         mode_valid = 1;
 834         }
 835
 836         if (!mode_valid) {
 837                 const struct fb_videomode *mode;
 838
 839                 mode = fb_find_best_mode(var, &info->modelist);
 840                 if (mode) {
 841                         fb_videomode_to_var(var, mode);
 842                         mode_valid = 1;
 843                 }
 844         }
 845
 846         if (!mode_valid && info->monspecs.modedb_len)
 847                 return -EINVAL;
 848
 849         if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
 850                                               par->fpHeight < var->yres))
 851                 return -EINVAL;
 852
 853         if (var->yres_virtual < var->yres)
 854                 var->yres_virtual = var->yres;
 855
 856         if (var->xres_virtual < var->xres)
 857                 var->xres_virtual = var->xres;
 858
 859         var->xres_virtual = (var->xres_virtual + 63) & ~63;
 860
 861         vramlen = info->screen_size;
 862         pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
 863         memlen = pitch * var->yres_virtual;
 864
 865         if (memlen > vramlen) {
 866                 var->yres_virtual = vramlen / pitch;
 867
 868                 if (var->yres_virtual < var->yres) {
 869                         var->yres_virtual = var->yres;
 870                         var->xres_virtual = vramlen / var->yres_virtual;
 871                         var->xres_virtual /= var->bits_per_pixel / 8;
 872                         var->xres_virtual &= ~63;
 873                         pitch = (var->xres_virtual *
 874                                  var->bits_per_pixel + 7) / 8;
 875                         memlen = pitch * var->yres;
 876
 877                         if (var->xres_virtual < var->xres) {
 878                                 printk("nvidiafb: required video memory, "
 879                                        "%d bytes, for %dx%d-%d (virtual) "
 880                                        "is out of range\n",
 881                                        memlen, var->xres_virtual,
 882                                        var->yres_virtual, var->bits_per_pixel);
 883                                 err = -ENOMEM;
 884                         }
 885                 }
 886         }
 887
 888         if (var->accel_flags) {
 889                 if (var->yres_virtual > 0x7fff)
 890                         var->yres_virtual = 0x7fff;
 891                 if (var->xres_virtual > 0x7fff)
 892                         var->xres_virtual = 0x7fff;
 893         }
 894
 895         var->xres_virtual &= ~63;
 896
 897         NVTRACE_LEAVE();
 898
 899         return err;
 900 }
 901
 902 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
 903                                 struct fb_info *info)
 904 {
 905         struct nvidia_par *par = info->par;
 906         u32 total;
 907
 908         total = var->yoffset * info->fix.line_length + var->xoffset;
 909
 910         NVSetStartAddress(par, total);
 911
 912         return 0;
 913 }
 914
 915 static int nvidiafb_blank(int blank, struct fb_info *info)
 916 {
 917         struct nvidia_par *par = info->par;
 918         unsigned char tmp, vesa;
 919
 920         tmp = NVReadSeq(par, 0x01) & ~0x20;     /* screen on/off */
 921         vesa = NVReadCrtc(par, 0x1a) & ~0xc0;   /* sync on/off */
 922
 923         NVTRACE_ENTER();
 924
 925         if (blank)
 926                 tmp |= 0x20;
 927
 928         switch (blank) {
 929         case FB_BLANK_UNBLANK:
 930         case FB_BLANK_NORMAL:
 931                 break;
 932         case FB_BLANK_VSYNC_SUSPEND:
 933                 vesa |= 0x80;
 934                 break;
 935         case FB_BLANK_HSYNC_SUSPEND:
 936                 vesa |= 0x40;
 937                 break;
 938         case FB_BLANK_POWERDOWN:
 939                 vesa |= 0xc0;
 940                 break;
 941         }
 942
 943         NVWriteSeq(par, 0x01, tmp);
 944         NVWriteCrtc(par, 0x1a, vesa);
 945
 946         NVTRACE_LEAVE();
 947
 948         return 0;
 949 }
 950
 951 /*
 952  * Because the VGA registers are not mapped linearly in its MMIO space,
 953  * restrict VGA register saving and restore to x86 only, where legacy VGA IO
 954  * access is legal. Consequently, we must also check if the device is the
 955  * primary display.
 956  */
 957 #ifdef CONFIG_X86
 958 static void save_vga_x86(struct nvidia_par *par)
 959 {
 960         struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
 961
 962         if (res && res->flags & IORESOURCE_ROM_SHADOW) {
 963                 memset(&par->vgastate, 0, sizeof(par->vgastate));
 964                 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS |
 965                         VGA_SAVE_CMAP;
 966                 save_vga(&par->vgastate);
 967         }
 968 }
 969
 970 static void restore_vga_x86(struct nvidia_par *par)
 971 {
 972         struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
 973
 974         if (res && res->flags & IORESOURCE_ROM_SHADOW)
 975                 restore_vga(&par->vgastate);
 976 }
 977 #else
 978 #define save_vga_x86(x) do {} while (0)
 979 #define restore_vga_x86(x) do {} while (0)
 980 #endif /* X86 */
 981
 982 static int nvidiafb_open(struct fb_info *info, int user)
 983 {
 984         struct nvidia_par *par = info->par;
 985
 986         mutex_lock(&par->open_lock);
 987
 988         if (!par->open_count) {
 989                 save_vga_x86(par);
 990                 nvidia_save_vga(par, &par->initial_state);
 991         }
 992
 993         par->open_count++;
 994         mutex_unlock(&par->open_lock);
 995         return 0;
 996 }
 997
 998 static int nvidiafb_release(struct fb_info *info, int user)
 999 {
1000         struct nvidia_par *par = info->par;
1001         int err = 0;
1002
1003         mutex_lock(&par->open_lock);
1004
1005         if (!par->open_count) {
1006                 err = -EINVAL;
1007                 goto done;
1008         }
1009
1010         if (par->open_count == 1) {
1011                 nvidia_write_regs(par, &par->initial_state);
1012                 restore_vga_x86(par);
1013         }
1014
1015         par->open_count--;
1016 done:
1017         mutex_unlock(&par->open_lock);
1018         return err;
1019 }
1020
1021 static struct fb_ops nvidia_fb_ops = {
1022         .owner          = THIS_MODULE,
1023         .fb_open        = nvidiafb_open,
1024         .fb_release     = nvidiafb_release,
1025         .fb_check_var   = nvidiafb_check_var,
1026         .fb_set_par     = nvidiafb_set_par,
1027         .fb_setcolreg   = nvidiafb_setcolreg,
1028         .fb_pan_display = nvidiafb_pan_display,
1029         .fb_blank       = nvidiafb_blank,
1030         .fb_fillrect    = nvidiafb_fillrect,
1031         .fb_copyarea    = nvidiafb_copyarea,
1032         .fb_imageblit   = nvidiafb_imageblit,
1033         .fb_cursor      = nvidiafb_cursor,
1034         .fb_sync        = nvidiafb_sync,
1035 };
1036
1037 #ifdef CONFIG_PM
1038 static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t mesg)
1039 {
1040         struct fb_info *info = pci_get_drvdata(dev);
1041         struct nvidia_par *par = info->par;
1042
1043         if (mesg.event == PM_EVENT_PRETHAW)
1044                 mesg.event = PM_EVENT_FREEZE;
1045         acquire_console_sem();
1046         par->pm_state = mesg.event;
1047
1048         if (mesg.event == PM_EVENT_SUSPEND) {
1049                 fb_set_suspend(info, 1);
1050                 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
1051                 nvidia_write_regs(par, &par->SavedReg);
1052                 pci_save_state(dev);
1053                 pci_disable_device(dev);
1054                 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1055         }
1056         dev->dev.power.power_state = mesg;
1057
1058         release_console_sem();
1059         return 0;
1060 }
1061
1062 static int nvidiafb_resume(struct pci_dev *dev)
1063 {
1064         struct fb_info *info = pci_get_drvdata(dev);
1065         struct nvidia_par *par = info->par;
1066
1067         acquire_console_sem();
1068         pci_set_power_state(dev, PCI_D0);
1069
1070         if (par->pm_state != PM_EVENT_FREEZE) {
1071                 pci_restore_state(dev);
1072
1073                 if (pci_enable_device(dev))
1074                         goto fail;
1075
1076                 pci_set_master(dev);
1077         }
1078
1079         par->pm_state = PM_EVENT_ON;
1080         nvidiafb_set_par(info);
1081         fb_set_suspend (info, 0);
1082         nvidiafb_blank(FB_BLANK_UNBLANK, info);
1083
1084 fail:
1085         release_console_sem();
1086         return 0;
1087 }
1088 #else
1089 #define nvidiafb_suspend NULL
1090 #define nvidiafb_resume NULL
1091 #endif
1092
1093 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1094 {
1095         struct fb_monspecs *specs = &info->monspecs;
1096         struct fb_videomode modedb;
1097         struct nvidia_par *par = info->par;
1098         int lpitch;
1099
1100         NVTRACE_ENTER();
1101         info->flags = FBINFO_DEFAULT
1102             | FBINFO_HWACCEL_IMAGEBLIT
1103             | FBINFO_HWACCEL_FILLRECT
1104             | FBINFO_HWACCEL_COPYAREA
1105             | FBINFO_HWACCEL_YPAN;
1106
1107         fb_videomode_to_modelist(info->monspecs.modedb,
1108                                  info->monspecs.modedb_len, &info->modelist);
1109         fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1110
1111         switch (bpp) {
1112         case 0 ... 8:
1113                 bpp = 8;
1114                 break;
1115         case 9 ... 16:
1116                 bpp = 16;
1117                 break;
1118         default:
1119                 bpp = 32;
1120                 break;
1121         }
1122
1123         if (specs->modedb != NULL) {
1124                 const struct fb_videomode *mode;
1125
1126                 mode = fb_find_best_display(specs, &info->modelist);
1127                 fb_videomode_to_var(&nvidiafb_default_var, mode);
1128                 nvidiafb_default_var.bits_per_pixel = bpp;
1129         } else if (par->fpWidth && par->fpHeight) {
1130                 char buf[16];
1131
1132                 memset(buf, 0, 16);
1133                 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1134                 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1135                              specs->modedb_len, &modedb, bpp);
1136         }
1137
1138         if (mode_option)
1139                 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1140                              specs->modedb, specs->modedb_len, &modedb, bpp);
1141
1142         info->var = nvidiafb_default_var;
1143         info->fix.visual = (info->var.bits_per_pixel == 8) ?
1144                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1145         info->pseudo_palette = par->pseudo_palette;
1146         fb_alloc_cmap(&info->cmap, 256, 0);
1147         fb_destroy_modedb(info->monspecs.modedb);
1148         info->monspecs.modedb = NULL;
1149
1150         /* maximize virtual vertical length */
1151         lpitch = info->var.xres_virtual *
1152                 ((info->var.bits_per_pixel + 7) >> 3);
1153         info->var.yres_virtual = info->screen_size / lpitch;
1154
1155         info->pixmap.scan_align = 4;
1156         info->pixmap.buf_align = 4;
1157         info->pixmap.access_align = 32;
1158         info->pixmap.size = 8 * 1024;
1159         info->pixmap.flags = FB_PIXMAP_SYSTEM;
1160
1161         if (!hwcur)
1162             info->fbops->fb_cursor = NULL;
1163
1164         info->var.accel_flags = (!noaccel);
1165
1166         switch (par->Architecture) {
1167         case NV_ARCH_04:
1168                 info->fix.accel = FB_ACCEL_NV4;
1169                 break;
1170         case NV_ARCH_10:
1171                 info->fix.accel = FB_ACCEL_NV_10;
1172                 break;
1173         case NV_ARCH_20:
1174                 info->fix.accel = FB_ACCEL_NV_20;
1175                 break;
1176         case NV_ARCH_30:
1177                 info->fix.accel = FB_ACCEL_NV_30;
1178                 break;
1179         case NV_ARCH_40:
1180                 info->fix.accel = FB_ACCEL_NV_40;
1181                 break;
1182         }
1183
1184         NVTRACE_LEAVE();
1185
1186         return nvidiafb_check_var(&info->var, info);
1187 }
1188
1189 static u32 __devinit nvidia_get_chipset(struct fb_info *info)
1190 {
1191         struct nvidia_par *par = info->par;
1192         u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1193
1194         printk(KERN_INFO PFX "Device ID: %x \n", id);
1195
1196         if ((id & 0xfff0) == 0x00f0) {
1197                 /* pci-e */
1198                 id = NV_RD32(par->REGS, 0x1800);
1199
1200                 if ((id & 0x0000ffff) == 0x000010DE)
1201                         id = 0x10DE0000 | (id >> 16);
1202                 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1203                         id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1204                             ((id >> 8) & 0x000000ff);
1205                 printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1206         }
1207
1208         return id;
1209 }
1210
1211 static u32 __devinit nvidia_get_arch(struct fb_info *info)
1212 {
1213         struct nvidia_par *par = info->par;
1214         u32 arch = 0;
1215
1216         switch (par->Chipset & 0x0ff0) {
1217         case 0x0100:            /* GeForce 256 */
1218         case 0x0110:            /* GeForce2 MX */
1219         case 0x0150:            /* GeForce2 */
1220         case 0x0170:            /* GeForce4 MX */
1221         case 0x0180:            /* GeForce4 MX (8x AGP) */
1222         case 0x01A0:            /* nForce */
1223         case 0x01F0:            /* nForce2 */
1224                 arch = NV_ARCH_10;
1225                 break;
1226         case 0x0200:            /* GeForce3 */
1227         case 0x0250:            /* GeForce4 Ti */
1228         case 0x0280:            /* GeForce4 Ti (8x AGP) */
1229                 arch = NV_ARCH_20;
1230                 break;
1231         case 0x0300:            /* GeForceFX 5800 */
1232         case 0x0310:            /* GeForceFX 5600 */
1233         case 0x0320:            /* GeForceFX 5200 */
1234         case 0x0330:            /* GeForceFX 5900 */
1235         case 0x0340:            /* GeForceFX 5700 */
1236                 arch = NV_ARCH_30;
1237                 break;
1238         case 0x0040:            /* GeForce 6800 */
1239         case 0x00C0:            /* GeForce 6800 */
1240         case 0x0120:            /* GeForce 6800 */
1241         case 0x0130:
1242         case 0x0140:            /* GeForce 6600 */
1243         case 0x0160:            /* GeForce 6200 */
1244         case 0x01D0:            /* GeForce 7200, 7300, 7400 */
1245         case 0x02E0:            /* GeForce 7300 GT */
1246         case 0x0090:            /* GeForce 7800 */
1247         case 0x0210:            /* GeForce 6800 */
1248         case 0x0220:            /* GeForce 6200 */
1249         case 0x0230:
1250         case 0x0240:            /* GeForce 6100 */
1251         case 0x0290:            /* GeForce 7900 */
1252         case 0x0390:            /* GeForce 7600 */
1253                 arch = NV_ARCH_40;
1254                 break;
1255         case 0x0020:            /* TNT, TNT2 */
1256                 arch = NV_ARCH_04;
1257                 break;
1258         default:                /* unknown architecture */
1259                 break;
1260         }
1261
1262         return arch;
1263 }
1264
1265 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1266                                     const struct pci_device_id *ent)
1267 {
1268         struct nvidia_par *par;
1269         struct fb_info *info;
1270         unsigned short cmd;
1271
1272
1273         NVTRACE_ENTER();
1274         assert(pd != NULL);
1275
1276         info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1277
1278         if (!info)
1279                 goto err_out;
1280
1281         par = info->par;
1282         par->pci_dev = pd;
1283         mutex_init(&par->open_lock);
1284         info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1285
1286         if (info->pixmap.addr == NULL)
1287                 goto err_out_kfree;
1288
1289         if (pci_enable_device(pd)) {
1290                 printk(KERN_ERR PFX "cannot enable PCI device\n");
1291                 goto err_out_enable;
1292         }
1293
1294         if (pci_request_regions(pd, "nvidiafb")) {
1295                 printk(KERN_ERR PFX "cannot request PCI regions\n");
1296                 goto err_out_enable;
1297         }
1298
1299         par->FlatPanel = flatpanel;
1300         if (flatpanel == 1)
1301                 printk(KERN_INFO PFX "flatpanel support enabled\n");
1302         par->FPDither = fpdither;
1303
1304         par->CRTCnumber = forceCRTC;
1305         par->FpScale = (!noscale);
1306         par->paneltweak = paneltweak;
1307
1308         /* enable IO and mem if not already done */
1309         pci_read_config_word(pd, PCI_COMMAND, &cmd);
1310         cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1311         pci_write_config_word(pd, PCI_COMMAND, cmd);
1312
1313         nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1314         nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1315         nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1316
1317         par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1318
1319         if (!par->REGS) {
1320                 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1321                 goto err_out_free_base0;
1322         }
1323
1324         par->Chipset = nvidia_get_chipset(info);
1325         par->Architecture = nvidia_get_arch(info);
1326
1327         if (par->Architecture == 0) {
1328                 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1329                 goto err_out_arch;
1330         }
1331
1332         sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1333
1334         if (NVCommonSetup(info))
1335                 goto err_out_arch;
1336
1337         par->FbAddress = nvidiafb_fix.smem_start;
1338         par->FbMapSize = par->RamAmountKBytes * 1024;
1339         if (vram && vram * 1024 * 1024 < par->FbMapSize)
1340                 par->FbMapSize = vram * 1024 * 1024;
1341
1342         /* Limit amount of vram to 64 MB */
1343         if (par->FbMapSize > 64 * 1024 * 1024)
1344                 par->FbMapSize = 64 * 1024 * 1024;
1345
1346         if(par->Architecture >= NV_ARCH_40)
1347                 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1348         else
1349                 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1350         par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1351             16 * 1024;
1352         par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1353         par->CursorStart = par->FbUsableSize + (32 * 1024);
1354
1355         info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1356         info->screen_size = par->FbUsableSize;
1357         nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1358
1359         if (!info->screen_base) {
1360                 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1361                 goto err_out_free_base1;
1362         }
1363
1364         par->FbStart = info->screen_base;
1365
1366 #ifdef CONFIG_MTRR
1367         if (!nomtrr) {
1368                 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1369                                           par->RamAmountKBytes * 1024,
1370                                           MTRR_TYPE_WRCOMB, 1);
1371                 if (par->mtrr.vram < 0) {
1372                         printk(KERN_ERR PFX "unable to setup MTRR\n");
1373                 } else {
1374                         par->mtrr.vram_valid = 1;
1375                         /* let there be speed */
1376                         printk(KERN_INFO PFX "MTRR set to ON\n");
1377                 }
1378         }
1379 #endif                          /* CONFIG_MTRR */
1380
1381         info->fbops = &nvidia_fb_ops;
1382         info->fix = nvidiafb_fix;
1383
1384         if (nvidia_set_fbinfo(info) < 0) {
1385                 printk(KERN_ERR PFX "error setting initial video mode\n");
1386                 goto err_out_iounmap_fb;
1387         }
1388
1389         nvidia_save_vga(par, &par->SavedReg);
1390
1391         pci_set_drvdata(pd, info);
1392
1393         if (backlight)
1394                 nvidia_bl_init(par);
1395
1396         if (register_framebuffer(info) < 0) {
1397                 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1398                 goto err_out_iounmap_fb;
1399         }
1400
1401
1402         printk(KERN_INFO PFX
1403                "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1404                info->fix.id,
1405                par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1406
1407         NVTRACE_LEAVE();
1408         return 0;
1409
1410 err_out_iounmap_fb:
1411         iounmap(info->screen_base);
1412 err_out_free_base1:
1413         fb_destroy_modedb(info->monspecs.modedb);
1414         nvidia_delete_i2c_busses(par);
1415 err_out_arch:
1416         iounmap(par->REGS);
1417  err_out_free_base0:
1418         pci_release_regions(pd);
1419 err_out_enable:
1420         kfree(info->pixmap.addr);
1421 err_out_kfree:
1422         framebuffer_release(info);
1423 err_out:
1424         return -ENODEV;
1425 }
1426
1427 static void __devexit nvidiafb_remove(struct pci_dev *pd)
1428 {
1429         struct fb_info *info = pci_get_drvdata(pd);
1430         struct nvidia_par *par = info->par;
1431
1432         NVTRACE_ENTER();
1433
1434         unregister_framebuffer(info);
1435
1436         nvidia_bl_exit(par);
1437
1438 #ifdef CONFIG_MTRR
1439         if (par->mtrr.vram_valid)
1440                 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1441                          info->fix.smem_len);
1442 #endif                          /* CONFIG_MTRR */
1443
1444         iounmap(info->screen_base);
1445         fb_destroy_modedb(info->monspecs.modedb);
1446         nvidia_delete_i2c_busses(par);
1447         iounmap(par->REGS);
1448         pci_release_regions(pd);
1449         kfree(info->pixmap.addr);
1450         framebuffer_release(info);
1451         pci_set_drvdata(pd, NULL);
1452         NVTRACE_LEAVE();
1453 }
1454
1455 /* ------------------------------------------------------------------------- *
1456  *
1457  * initialization
1458  *
1459  * ------------------------------------------------------------------------- */
1460
1461 #ifndef MODULE
1462 static int __devinit nvidiafb_setup(char *options)
1463 {
1464         char *this_opt;
1465
1466         NVTRACE_ENTER();
1467         if (!options || !*options)
1468                 return 0;
1469
1470         while ((this_opt = strsep(&options, ",")) != NULL) {
1471                 if (!strncmp(this_opt, "forceCRTC", 9)) {
1472                         char *p;
1473
1474                         p = this_opt + 9;
1475                         if (!*p || !*(++p))
1476                                 continue;
1477                         forceCRTC = *p - '0';
1478                         if (forceCRTC < 0 || forceCRTC > 1)
1479                                 forceCRTC = -1;
1480                 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1481                         flatpanel = 1;
1482                 } else if (!strncmp(this_opt, "hwcur", 5)) {
1483                         hwcur = 1;
1484                 } else if (!strncmp(this_opt, "noaccel", 6)) {
1485                         noaccel = 1;
1486                 } else if (!strncmp(this_opt, "noscale", 7)) {
1487                         noscale = 1;
1488                 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1489                         paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1490                 } else if (!strncmp(this_opt, "vram:", 5)) {
1491                         vram = simple_strtoul(this_opt+5, NULL, 0);
1492                 } else if (!strncmp(this_opt, "backlight:", 10)) {
1493                         backlight = simple_strtoul(this_opt+10, NULL, 0);
1494 #ifdef CONFIG_MTRR
1495                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1496                         nomtrr = 1;
1497 #endif
1498                 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1499                         fpdither = simple_strtol(this_opt+9, NULL, 0);
1500                 } else if (!strncmp(this_opt, "bpp:", 4)) {
1501                         bpp = simple_strtoul(this_opt+4, NULL, 0);
1502                 } else
1503                         mode_option = this_opt;
1504         }
1505         NVTRACE_LEAVE();
1506         return 0;
1507 }
1508 #endif                          /* !MODULE */
1509
1510 static struct pci_driver nvidiafb_driver = {
1511         .name = "nvidiafb",
1512         .id_table = nvidiafb_pci_tbl,
1513         .probe    = nvidiafb_probe,
1514         .suspend  = nvidiafb_suspend,
1515         .resume   = nvidiafb_resume,
1516         .remove   = __devexit_p(nvidiafb_remove),
1517 };
1518
1519 /* ------------------------------------------------------------------------- *
1520  *
1521  * modularization
1522  *
1523  * ------------------------------------------------------------------------- */
1524
1525 static int __devinit nvidiafb_init(void)
1526 {
1527 #ifndef MODULE
1528         char *option = NULL;
1529
1530         if (fb_get_options("nvidiafb", &option))
1531                 return -ENODEV;
1532         nvidiafb_setup(option);
1533 #endif
1534         return pci_register_driver(&nvidiafb_driver);
1535 }
1536
1537 module_init(nvidiafb_init);
1538
1539 #ifdef MODULE
1540 static void __exit nvidiafb_exit(void)
1541 {
1542         pci_unregister_driver(&nvidiafb_driver);
1543 }
1544
1545 module_exit(nvidiafb_exit);
1546
1547 module_param(flatpanel, int, 0);
1548 MODULE_PARM_DESC(flatpanel,
1549                  "Enables experimental flat panel support for some chipsets. "
1550                  "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1551 module_param(fpdither, int, 0);
1552 MODULE_PARM_DESC(fpdither,
1553                  "Enables dithering of flat panel for 6 bits panels. "
1554                  "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1555 module_param(hwcur, int, 0);
1556 MODULE_PARM_DESC(hwcur,
1557                  "Enables hardware cursor implementation. (0 or 1=enabled) "
1558                  "(default=0)");
1559 module_param(noaccel, int, 0);
1560 MODULE_PARM_DESC(noaccel,
1561                  "Disables hardware acceleration. (0 or 1=disable) "
1562                  "(default=0)");
1563 module_param(noscale, int, 0);
1564 MODULE_PARM_DESC(noscale,
1565                  "Disables screen scaleing. (0 or 1=disable) "
1566                  "(default=0, do scaling)");
1567 module_param(paneltweak, int, 0);
1568 MODULE_PARM_DESC(paneltweak,
1569                  "Tweak display settings for flatpanels. "
1570                  "(default=0, no tweaks)");
1571 module_param(forceCRTC, int, 0);
1572 MODULE_PARM_DESC(forceCRTC,
1573                  "Forces usage of a particular CRTC in case autodetection "
1574                  "fails. (0 or 1) (default=autodetect)");
1575 module_param(vram, int, 0);
1576 MODULE_PARM_DESC(vram,
1577                  "amount of framebuffer memory to remap in MiB"
1578                  "(default=0 - remap entire memory)");
1579 module_param(mode_option, charp, 0);
1580 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1581 module_param(bpp, int, 0);
1582 MODULE_PARM_DESC(bpp, "pixel width in bits"
1583                  "(default=8)");
1584 #ifdef CONFIG_MTRR
1585 module_param(nomtrr, bool, 0);
1586 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1587                  "(default=0)");
1588 #endif
1589
1590 MODULE_AUTHOR("Antonino Daplas");
1591 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1592 MODULE_LICENSE("GPL");
1593 #endif                          /* MODULE */
1594