1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/init.h>
32 * Default implementation of macro that returns current
33 * instruction pointer ("program counter").
35 static inline void *current_text_addr(void)
39 asm volatile("mov $1f, %0; 1:":"=r" (pc));
44 #ifdef CONFIG_X86_VSMP
45 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
46 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
48 # define ARCH_MIN_TASKALIGN 16
49 # define ARCH_MIN_MMSTRUCT_ALIGN 0
53 * CPU type and hardware bug flags. Kept separately for each CPU.
54 * Members of this structure are referenced in head.S, so think twice
55 * before touching them. [mj]
59 __u8 x86; /* CPU family */
60 __u8 x86_vendor; /* CPU vendor */
64 char wp_works_ok; /* It doesn't on 386's */
66 /* Problems on some 486Dx4's and old 386's: */
75 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
80 /* CPUID returned core id bits: */
82 /* Max extended CPUID function supported: */
83 __u32 extended_cpuid_level;
84 /* Maximum supported CPUID level, -1=no CPUID: */
86 __u32 x86_capability[NCAPINTS];
87 char x86_vendor_id[16];
88 char x86_model_id[64];
89 /* in KB - valid for CPUS which support this call: */
91 int x86_cache_alignment; /* In bytes */
93 unsigned long loops_per_jiffy;
95 /* cpus sharing the last level cache: */
96 cpumask_t llc_shared_map;
98 /* cpuid returned max cores value: */
102 u16 x86_clflush_size;
104 /* number of cores as seen by the OS: */
106 /* Physical processor id: */
110 /* Index into per_cpu list: */
113 unsigned int x86_hyper_vendor;
114 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
116 #define X86_VENDOR_INTEL 0
117 #define X86_VENDOR_CYRIX 1
118 #define X86_VENDOR_AMD 2
119 #define X86_VENDOR_UMC 3
120 #define X86_VENDOR_CENTAUR 5
121 #define X86_VENDOR_TRANSMETA 7
122 #define X86_VENDOR_NSC 8
123 #define X86_VENDOR_NUM 9
125 #define X86_VENDOR_UNKNOWN 0xff
127 #define X86_HYPER_VENDOR_NONE 0
128 #define X86_HYPER_VENDOR_VMWARE 1
131 * capabilities of CPUs
133 extern struct cpuinfo_x86 boot_cpu_data;
134 extern struct cpuinfo_x86 new_cpu_data;
136 extern struct tss_struct doublefault_tss;
137 extern __u32 cleared_cpu_caps[NCAPINTS];
140 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
141 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
142 #define current_cpu_data __get_cpu_var(cpu_info)
144 #define cpu_data(cpu) boot_cpu_data
145 #define current_cpu_data boot_cpu_data
148 extern const struct seq_operations cpuinfo_op;
150 static inline int hlt_works(int cpu)
153 return cpu_data(cpu).hlt_works_ok;
159 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
161 extern void cpu_detect(struct cpuinfo_x86 *c);
163 extern struct pt_regs *idle_regs(struct pt_regs *);
165 extern void early_cpu_init(void);
166 extern void identify_boot_cpu(void);
167 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
168 extern void print_cpu_info(struct cpuinfo_x86 *);
169 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
170 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
171 extern unsigned short num_cache_leaves;
173 extern void detect_extended_topology(struct cpuinfo_x86 *c);
174 extern void detect_ht(struct cpuinfo_x86 *c);
176 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
177 unsigned int *ecx, unsigned int *edx)
179 /* ecx is often an input as well as an output. */
185 : "0" (*eax), "2" (*ecx));
188 static inline void load_cr3(pgd_t *pgdir)
190 write_cr3(__pa(pgdir));
194 /* This is the TSS defined by the hardware. */
196 unsigned short back_link, __blh;
198 unsigned short ss0, __ss0h;
200 /* ss1 caches MSR_IA32_SYSENTER_CS: */
201 unsigned short ss1, __ss1h;
203 unsigned short ss2, __ss2h;
215 unsigned short es, __esh;
216 unsigned short cs, __csh;
217 unsigned short ss, __ssh;
218 unsigned short ds, __dsh;
219 unsigned short fs, __fsh;
220 unsigned short gs, __gsh;
221 unsigned short ldt, __ldth;
222 unsigned short trace;
223 unsigned short io_bitmap_base;
225 } __attribute__((packed));
239 } __attribute__((packed)) ____cacheline_aligned;
245 #define IO_BITMAP_BITS 65536
246 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
247 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
248 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
249 #define INVALID_IO_BITMAP_OFFSET 0x8000
250 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
254 * The hardware state:
256 struct x86_hw_tss x86_tss;
259 * The extra 1 is there because the CPU will access an
260 * additional byte beyond the end of the IO permission
261 * bitmap. The extra byte must be all 1 bits, and must
262 * be within the limit.
264 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
266 * Cache the current maximum and the last task that used the bitmap:
268 unsigned long io_bitmap_max;
269 struct thread_struct *io_bitmap_owner;
272 * .. and then another 0x100 bytes for the emergency kernel stack:
274 unsigned long stack[64];
276 } ____cacheline_aligned;
278 DECLARE_PER_CPU(struct tss_struct, init_tss);
281 * Save the original ist values for checking stack pointers during debugging
284 unsigned long ist[7];
287 #define MXCSR_DEFAULT 0x1f80
289 struct i387_fsave_struct {
290 u32 cwd; /* FPU Control Word */
291 u32 swd; /* FPU Status Word */
292 u32 twd; /* FPU Tag Word */
293 u32 fip; /* FPU IP Offset */
294 u32 fcs; /* FPU IP Selector */
295 u32 foo; /* FPU Operand Pointer Offset */
296 u32 fos; /* FPU Operand Pointer Selector */
298 /* 8*10 bytes for each FP-reg = 80 bytes: */
301 /* Software status information [not touched by FSAVE ]: */
305 struct i387_fxsave_struct {
306 u16 cwd; /* Control Word */
307 u16 swd; /* Status Word */
308 u16 twd; /* Tag Word */
309 u16 fop; /* Last Instruction Opcode */
312 u64 rip; /* Instruction Pointer */
313 u64 rdp; /* Data Pointer */
316 u32 fip; /* FPU IP Offset */
317 u32 fcs; /* FPU IP Selector */
318 u32 foo; /* FPU Operand Offset */
319 u32 fos; /* FPU Operand Selector */
322 u32 mxcsr; /* MXCSR Register State */
323 u32 mxcsr_mask; /* MXCSR Mask */
325 /* 8*16 bytes for each FP-reg = 128 bytes: */
328 /* 16*16 bytes for each XMM-reg = 256 bytes: */
338 } __attribute__((aligned(16)));
340 struct i387_soft_struct {
348 /* 8*10 bytes for each FP-reg = 80 bytes: */
360 struct xsave_hdr_struct {
364 } __attribute__((packed));
366 struct xsave_struct {
367 struct i387_fxsave_struct i387;
368 struct xsave_hdr_struct xsave_hdr;
369 /* new processor state extensions will go here */
370 } __attribute__ ((packed, aligned (64)));
372 union thread_xstate {
373 struct i387_fsave_struct fsave;
374 struct i387_fxsave_struct fxsave;
375 struct i387_soft_struct soft;
376 struct xsave_struct xsave;
380 DECLARE_PER_CPU(struct orig_ist, orig_ist);
382 union irq_stack_union {
383 char irq_stack[IRQ_STACK_SIZE];
385 * GCC hardcodes the stack canary as %gs:40. Since the
386 * irq_stack is the object at %gs:0, we reserve the bottom
387 * 48 bytes of the irq stack for the canary.
391 unsigned long stack_canary;
395 DECLARE_PER_CPU(union irq_stack_union, irq_stack_union);
396 DECLARE_INIT_PER_CPU(irq_stack_union);
398 DECLARE_PER_CPU(char *, irq_stack_ptr);
401 extern void print_cpu_info(struct cpuinfo_x86 *);
402 extern unsigned int xstate_size;
403 extern void free_thread_xstate(struct task_struct *);
404 extern struct kmem_cache *task_xstate_cachep;
405 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
406 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
407 extern unsigned short num_cache_leaves;
409 struct thread_struct {
410 /* Cached TLS descriptors: */
411 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
415 unsigned long sysenter_cs;
417 unsigned long usersp; /* Copy from PDA */
420 unsigned short fsindex;
421 unsigned short gsindex;
426 /* Hardware debugging registers: */
427 unsigned long debugreg0;
428 unsigned long debugreg1;
429 unsigned long debugreg2;
430 unsigned long debugreg3;
431 unsigned long debugreg6;
432 unsigned long debugreg7;
435 unsigned long trap_no;
436 unsigned long error_code;
437 /* floating point and extended processor state */
438 union thread_xstate *xstate;
440 /* Virtual 86 mode info */
441 struct vm86_struct __user *vm86_info;
442 unsigned long screen_bitmap;
443 unsigned long v86flags;
444 unsigned long v86mask;
445 unsigned long saved_sp0;
446 unsigned int saved_fs;
447 unsigned int saved_gs;
449 /* IO permissions: */
450 unsigned long *io_bitmap_ptr;
452 /* Max allowed port in the bitmap, in bytes: */
453 unsigned io_bitmap_max;
454 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
455 unsigned long debugctlmsr;
457 /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
458 struct ds_context *ds_ctx;
459 #endif /* CONFIG_X86_DS */
460 #ifdef CONFIG_X86_PTRACE_BTS
461 /* the signal to send on a bts buffer overflow */
462 unsigned int bts_ovfl_signal;
463 #endif /* CONFIG_X86_PTRACE_BTS */
466 static inline unsigned long native_get_debugreg(int regno)
468 unsigned long val = 0; /* Damn you, gcc! */
472 asm("mov %%db0, %0" :"=r" (val));
475 asm("mov %%db1, %0" :"=r" (val));
478 asm("mov %%db2, %0" :"=r" (val));
481 asm("mov %%db3, %0" :"=r" (val));
484 asm("mov %%db6, %0" :"=r" (val));
487 asm("mov %%db7, %0" :"=r" (val));
495 static inline void native_set_debugreg(int regno, unsigned long value)
499 asm("mov %0, %%db0" ::"r" (value));
502 asm("mov %0, %%db1" ::"r" (value));
505 asm("mov %0, %%db2" ::"r" (value));
508 asm("mov %0, %%db3" ::"r" (value));
511 asm("mov %0, %%db6" ::"r" (value));
514 asm("mov %0, %%db7" ::"r" (value));
522 * Set IOPL bits in EFLAGS from given mask
524 static inline void native_set_iopl_mask(unsigned mask)
529 asm volatile ("pushfl;"
536 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
541 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
543 tss->x86_tss.sp0 = thread->sp0;
545 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
546 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
547 tss->x86_tss.ss1 = thread->sysenter_cs;
548 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
553 static inline void native_swapgs(void)
556 asm volatile("swapgs" ::: "memory");
560 #ifdef CONFIG_PARAVIRT
561 #include <asm/paravirt.h>
563 #define __cpuid native_cpuid
564 #define paravirt_enabled() 0
567 * These special macros can be used to get or set a debugging register
569 #define get_debugreg(var, register) \
570 (var) = native_get_debugreg(register)
571 #define set_debugreg(value, register) \
572 native_set_debugreg(register, value)
574 static inline void load_sp0(struct tss_struct *tss,
575 struct thread_struct *thread)
577 native_load_sp0(tss, thread);
580 #define set_iopl_mask native_set_iopl_mask
581 #endif /* CONFIG_PARAVIRT */
584 * Save the cr4 feature set we're using (ie
585 * Pentium 4MB enable and PPro Global page
586 * enable), so that any CPU's that boot up
587 * after us can get the correct flags.
589 extern unsigned long mmu_cr4_features;
591 static inline void set_in_cr4(unsigned long mask)
595 mmu_cr4_features |= mask;
601 static inline void clear_in_cr4(unsigned long mask)
605 mmu_cr4_features &= ~mask;
617 * create a kernel thread without removing it from tasklists
619 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
621 /* Free all resources held by a thread. */
622 extern void release_thread(struct task_struct *);
624 /* Prepare to copy thread state - unlazy all lazy state */
625 extern void prepare_to_copy(struct task_struct *tsk);
627 unsigned long get_wchan(struct task_struct *p);
630 * Generic CPUID function
631 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
632 * resulting in stale register contents being returned.
634 static inline void cpuid(unsigned int op,
635 unsigned int *eax, unsigned int *ebx,
636 unsigned int *ecx, unsigned int *edx)
640 __cpuid(eax, ebx, ecx, edx);
643 /* Some CPUID calls want 'count' to be placed in ecx */
644 static inline void cpuid_count(unsigned int op, int count,
645 unsigned int *eax, unsigned int *ebx,
646 unsigned int *ecx, unsigned int *edx)
650 __cpuid(eax, ebx, ecx, edx);
654 * CPUID functions returning a single datum
656 static inline unsigned int cpuid_eax(unsigned int op)
658 unsigned int eax, ebx, ecx, edx;
660 cpuid(op, &eax, &ebx, &ecx, &edx);
665 static inline unsigned int cpuid_ebx(unsigned int op)
667 unsigned int eax, ebx, ecx, edx;
669 cpuid(op, &eax, &ebx, &ecx, &edx);
674 static inline unsigned int cpuid_ecx(unsigned int op)
676 unsigned int eax, ebx, ecx, edx;
678 cpuid(op, &eax, &ebx, &ecx, &edx);
683 static inline unsigned int cpuid_edx(unsigned int op)
685 unsigned int eax, ebx, ecx, edx;
687 cpuid(op, &eax, &ebx, &ecx, &edx);
692 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
693 static inline void rep_nop(void)
695 asm volatile("rep; nop" ::: "memory");
698 static inline void cpu_relax(void)
703 /* Stop speculative execution: */
704 static inline void sync_core(void)
708 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
709 : "ebx", "ecx", "edx", "memory");
712 static inline void __monitor(const void *eax, unsigned long ecx,
715 /* "monitor %eax, %ecx, %edx;" */
716 asm volatile(".byte 0x0f, 0x01, 0xc8;"
717 :: "a" (eax), "c" (ecx), "d"(edx));
720 static inline void __mwait(unsigned long eax, unsigned long ecx)
722 /* "mwait %eax, %ecx;" */
723 asm volatile(".byte 0x0f, 0x01, 0xc9;"
724 :: "a" (eax), "c" (ecx));
727 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
730 /* "mwait %eax, %ecx;" */
731 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
732 :: "a" (eax), "c" (ecx));
735 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
737 extern void select_idle_routine(const struct cpuinfo_x86 *c);
739 extern unsigned long boot_option_idle_override;
740 extern unsigned long idle_halt;
741 extern unsigned long idle_nomwait;
744 * on systems with caches, caches must be flashed as the absolute
745 * last instruction before going into a suspended halt. Otherwise,
746 * dirty data can linger in the cache and become stale on resume,
747 * leading to strange errors.
749 * perform a variety of operations to guarantee that the compiler
750 * will not reorder instructions. wbinvd itself is serializing
751 * so the processor will not reorder.
753 * Systems without cache can just go into halt.
755 static inline void wbinvd_halt(void)
758 /* check for clflush to determine if wbinvd is legal */
760 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
766 extern void enable_sep_cpu(void);
767 extern int sysenter_setup(void);
769 /* Defined in head.S */
770 extern struct desc_ptr early_gdt_descr;
772 extern void cpu_set_gdt(int);
773 extern void switch_to_new_gdt(int);
774 extern void load_percpu_segment(int);
775 extern void cpu_init(void);
777 static inline unsigned long get_debugctlmsr(void)
779 unsigned long debugctlmsr = 0;
781 #ifndef CONFIG_X86_DEBUGCTLMSR
782 if (boot_cpu_data.x86 < 6)
785 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
790 static inline void update_debugctlmsr(unsigned long debugctlmsr)
792 #ifndef CONFIG_X86_DEBUGCTLMSR
793 if (boot_cpu_data.x86 < 6)
796 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
800 * from system description table in BIOS. Mostly for MCA use, but
801 * others may find it useful:
803 extern unsigned int machine_id;
804 extern unsigned int machine_submodel_id;
805 extern unsigned int BIOS_revision;
807 /* Boot loader type from the setup header: */
808 extern int bootloader_type;
810 extern char ignore_fpu_irq;
812 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
813 #define ARCH_HAS_PREFETCHW
814 #define ARCH_HAS_SPINLOCK_PREFETCH
817 # define BASE_PREFETCH ASM_NOP4
818 # define ARCH_HAS_PREFETCH
820 # define BASE_PREFETCH "prefetcht0 (%1)"
824 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
826 * It's not worth to care about 3dnow prefetches for the K6
827 * because they are microcoded there and very slow.
829 static inline void prefetch(const void *x)
831 alternative_input(BASE_PREFETCH,
838 * 3dnow prefetch to get an exclusive cache line.
839 * Useful for spinlocks to avoid one state transition in the
840 * cache coherency protocol:
842 static inline void prefetchw(const void *x)
844 alternative_input(BASE_PREFETCH,
850 static inline void spin_lock_prefetch(const void *x)
857 * User space process size: 3GB (default).
859 #define TASK_SIZE PAGE_OFFSET
860 #define STACK_TOP TASK_SIZE
861 #define STACK_TOP_MAX STACK_TOP
863 #define INIT_THREAD { \
864 .sp0 = sizeof(init_stack) + (long)&init_stack, \
866 .sysenter_cs = __KERNEL_CS, \
867 .io_bitmap_ptr = NULL, \
868 .fs = __KERNEL_PERCPU, \
872 * Note that the .io_bitmap member must be extra-big. This is because
873 * the CPU will access an additional byte beyond the end of the IO
874 * permission bitmap. The extra byte must be all 1 bits, and must
875 * be within the limit.
879 .sp0 = sizeof(init_stack) + (long)&init_stack, \
880 .ss0 = __KERNEL_DS, \
881 .ss1 = __KERNEL_CS, \
882 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
884 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
887 extern unsigned long thread_saved_pc(struct task_struct *tsk);
889 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
890 #define KSTK_TOP(info) \
892 unsigned long *__ptr = (unsigned long *)(info); \
893 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
897 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
898 * This is necessary to guarantee that the entire "struct pt_regs"
899 * is accessable even if the CPU haven't stored the SS/ESP registers
900 * on the stack (interrupt gate does not save these registers
901 * when switching to the same priv ring).
902 * Therefore beware: accessing the ss/esp fields of the
903 * "struct pt_regs" is possible, but they may contain the
904 * completely wrong values.
906 #define task_pt_regs(task) \
908 struct pt_regs *__regs__; \
909 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
913 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
917 * User space process size. 47bits minus one guard page.
919 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
921 /* This decides where the kernel will search for a free chunk of vm
922 * space during mmap's.
924 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
925 0xc0000000 : 0xFFFFe000)
927 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
928 IA32_PAGE_OFFSET : TASK_SIZE64)
929 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
930 IA32_PAGE_OFFSET : TASK_SIZE64)
932 #define STACK_TOP TASK_SIZE
933 #define STACK_TOP_MAX TASK_SIZE64
935 #define INIT_THREAD { \
936 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
940 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
944 * Return saved PC of a blocked thread.
945 * What is this good for? it will be always the scheduler or ret_from_fork.
947 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
949 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
950 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
951 #endif /* CONFIG_X86_64 */
953 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
954 unsigned long new_sp);
957 * This decides where the kernel will search for a free chunk of vm
958 * space during mmap's.
960 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
962 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
964 /* Get/set a process' ability to use the timestamp counter instruction */
965 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
966 #define SET_TSC_CTL(val) set_tsc_mode((val))
968 extern int get_tsc_mode(unsigned long adr);
969 extern int set_tsc_mode(unsigned int val);
971 #endif /* _ASM_X86_PROCESSOR_H */