git.oblomov.eu Git - linux-2.6/blob - drivers/ide/pci/sgiioc4.c

   1 /*
   2  * Copyright (c) 2003 Silicon Graphics, Inc.  All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it would be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  11  *
  12  * You should have received a copy of the GNU General Public
  13  * License along with this program; if not, write the Free Software
  14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  15  *
  16  * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy,
  17  * Mountain View, CA  94043, or:
  18  *
  19  * http://www.sgi.com
  20  *
  21  * For further information regarding this notice, see:
  22  *
  23  * http://oss.sgi.com/projects/GenInfo/NoticeExplan
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/types.h>
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/hdreg.h>
  31 #include <linux/init.h>
  32 #include <linux/kernel.h>
  33 #include <linux/timer.h>
  34 #include <linux/mm.h>
  35 #include <linux/ioport.h>
  36 #include <linux/blkdev.h>
  37 #include <linux/ioc4_common.h>
  38 #include <asm/io.h>
  39
  40 #include <linux/ide.h>
  41
  42 /* IOC4 Specific Definitions */
  43 #define IOC4_CMD_OFFSET         0x100
  44 #define IOC4_CTRL_OFFSET        0x120
  45 #define IOC4_DMA_OFFSET         0x140
  46 #define IOC4_INTR_OFFSET        0x0
  47
  48 #define IOC4_TIMING             0x00
  49 #define IOC4_DMA_PTR_L          0x01
  50 #define IOC4_DMA_PTR_H          0x02
  51 #define IOC4_DMA_ADDR_L         0x03
  52 #define IOC4_DMA_ADDR_H         0x04
  53 #define IOC4_BC_DEV             0x05
  54 #define IOC4_BC_MEM             0x06
  55 #define IOC4_DMA_CTRL           0x07
  56 #define IOC4_DMA_END_ADDR       0x08
  57
  58 /* Bits in the IOC4 Control/Status Register */
  59 #define IOC4_S_DMA_START        0x01
  60 #define IOC4_S_DMA_STOP         0x02
  61 #define IOC4_S_DMA_DIR          0x04
  62 #define IOC4_S_DMA_ACTIVE       0x08
  63 #define IOC4_S_DMA_ERROR        0x10
  64 #define IOC4_ATA_MEMERR         0x02
  65
  66 /* Read/Write Directions */
  67 #define IOC4_DMA_WRITE          0x04
  68 #define IOC4_DMA_READ           0x00
  69
  70 /* Interrupt Register Offsets */
  71 #define IOC4_INTR_REG           0x03
  72 #define IOC4_INTR_SET           0x05
  73 #define IOC4_INTR_CLEAR         0x07
  74
  75 #define IOC4_IDE_CACHELINE_SIZE 128
  76 #define IOC4_CMD_CTL_BLK_SIZE   0x20
  77 #define IOC4_SUPPORTED_FIRMWARE_REV 46
  78
  79 typedef struct {
  80         u32 timing_reg0;
  81         u32 timing_reg1;
  82         u32 low_mem_ptr;
  83         u32 high_mem_ptr;
  84         u32 low_mem_addr;
  85         u32 high_mem_addr;
  86         u32 dev_byte_count;
  87         u32 mem_byte_count;
  88         u32 status;
  89 } ioc4_dma_regs_t;
  90
  91 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
  92 /* IOC4 has only 1 IDE channel */
  93 #define IOC4_PRD_BYTES       16
  94 #define IOC4_PRD_ENTRIES     (PAGE_SIZE /(4*IOC4_PRD_BYTES))
  95
  96
  97 static void
  98 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
  99                         unsigned long ctrl_port, unsigned long irq_port)
 100 {
 101         unsigned long reg = data_port;
 102         int i;
 103
 104         /* Registers are word (32 bit) aligned */
 105         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
 106                 hw->io_ports[i] = reg + i * 4;
 107
 108         if (ctrl_port)
 109                 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 110
 111         if (irq_port)
 112                 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
 113 }
 114
 115 static void
 116 sgiioc4_maskproc(ide_drive_t * drive, int mask)
 117 {
 118         ide_hwif_t *hwif = HWIF(drive);
 119         hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
 120                    IDE_CONTROL_REG);
 121 }
 122
 123
 124 static int
 125 sgiioc4_checkirq(ide_hwif_t * hwif)
 126 {
 127         u8 intr_reg =
 128             hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4);
 129
 130         if (intr_reg & 0x03)
 131                 return 1;
 132
 133         return 0;
 134 }
 135
 136
 137 static int
 138 sgiioc4_clearirq(ide_drive_t * drive)
 139 {
 140         u32 intr_reg;
 141         ide_hwif_t *hwif = HWIF(drive);
 142         unsigned long other_ir =
 143             hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
 144
 145         /* Code to check for PCI error conditions */
 146         intr_reg = hwif->INL(other_ir);
 147         if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
 148                 /*
 149                  * Using hwif->INB to read the IDE_STATUS_REG has a side effect
 150                  * of clearing the interrupt.  The first read should clear it
 151                  * if it is set.  The second read should return a "clear" status
 152                  * if it got cleared.  If not, then spin for a bit trying to
 153                  * clear it.
 154                  */
 155                 u8 stat = hwif->INB(IDE_STATUS_REG);
 156                 int count = 0;
 157                 stat = hwif->INB(IDE_STATUS_REG);
 158                 while ((stat & 0x80) && (count++ < 100)) {
 159                         udelay(1);
 160                         stat = hwif->INB(IDE_STATUS_REG);
 161                 }
 162
 163                 if (intr_reg & 0x02) {
 164                         /* Error when transferring DMA data on PCI bus */
 165                         u32 pci_err_addr_low, pci_err_addr_high,
 166                             pci_stat_cmd_reg;
 167
 168                         pci_err_addr_low =
 169                                 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET]);
 170                         pci_err_addr_high =
 171                                 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + 4);
 172                         pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
 173                                               &pci_stat_cmd_reg);
 174                         printk(KERN_ERR
 175                                "%s(%s) : PCI Bus Error when doing DMA:"
 176                                    " status-cmd reg is 0x%x\n",
 177                                __FUNCTION__, drive->name, pci_stat_cmd_reg);
 178                         printk(KERN_ERR
 179                                "%s(%s) : PCI Error Address is 0x%x%x\n",
 180                                __FUNCTION__, drive->name,
 181                                pci_err_addr_high, pci_err_addr_low);
 182                         /* Clear the PCI Error indicator */
 183                         pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
 184                                                0x00000146);
 185                 }
 186
 187                 /* Clear the Interrupt, Error bits on the IOC4 */
 188                 hwif->OUTL(0x03, other_ir);
 189
 190                 intr_reg = hwif->INL(other_ir);
 191         }
 192
 193         return intr_reg & 3;
 194 }
 195
 196 static void sgiioc4_ide_dma_start(ide_drive_t * drive)
 197 {
 198         ide_hwif_t *hwif = HWIF(drive);
 199         unsigned int reg = hwif->INL(hwif->dma_base + IOC4_DMA_CTRL * 4);
 200         unsigned int temp_reg = reg | IOC4_S_DMA_START;
 201
 202         hwif->OUTL(temp_reg, hwif->dma_base + IOC4_DMA_CTRL * 4);
 203 }
 204
 205 static u32
 206 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
 207 {
 208         u32     ioc4_dma;
 209         int     count;
 210
 211         count = 0;
 212         ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
 213         while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
 214                 udelay(1);
 215                 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
 216         }
 217         return ioc4_dma;
 218 }
 219
 220 /* Stops the IOC4 DMA Engine */
 221 static int
 222 sgiioc4_ide_dma_end(ide_drive_t * drive)
 223 {
 224         u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
 225         ide_hwif_t *hwif = HWIF(drive);
 226         u64 dma_base = hwif->dma_base;
 227         int dma_stat = 0;
 228         unsigned long *ending_dma = (unsigned long *) hwif->dma_base2;
 229
 230         hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
 231
 232         ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 233
 234         if (ioc4_dma & IOC4_S_DMA_STOP) {
 235                 printk(KERN_ERR
 236                        "%s(%s): IOC4 DMA STOP bit is still 1 :"
 237                        "ioc4_dma_reg 0x%x\n",
 238                        __FUNCTION__, drive->name, ioc4_dma);
 239                 dma_stat = 1;
 240         }
 241
 242         /*
 243          * The IOC4 will DMA 1's to the ending dma area to indicate that
 244          * previous data DMA is complete.  This is necessary because of relaxed
 245          * ordering between register reads and DMA writes on the Altix.
 246          */
 247         while ((cnt++ < 200) && (!valid)) {
 248                 for (num = 0; num < 16; num++) {
 249                         if (ending_dma[num]) {
 250                                 valid = 1;
 251                                 break;
 252                         }
 253                 }
 254                 udelay(1);
 255         }
 256         if (!valid) {
 257                 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
 258                        drive->name);
 259                 dma_stat = 1;
 260         }
 261
 262         bc_dev = hwif->INL(dma_base + IOC4_BC_DEV * 4);
 263         bc_mem = hwif->INL(dma_base + IOC4_BC_MEM * 4);
 264
 265         if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
 266                 if (bc_dev > bc_mem + 8) {
 267                         printk(KERN_ERR
 268                                "%s(%s): WARNING!! byte_count_dev %d "
 269                                "!= byte_count_mem %d\n",
 270                                __FUNCTION__, drive->name, bc_dev, bc_mem);
 271                 }
 272         }
 273
 274         drive->waiting_for_dma = 0;
 275         ide_destroy_dmatable(drive);
 276
 277         return dma_stat;
 278 }
 279
 280 static int
 281 sgiioc4_ide_dma_check(ide_drive_t * drive)
 282 {
 283         if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0) {
 284                 printk(KERN_INFO
 285                        "Couldnot set %s in Multimode-2 DMA mode | "
 286                            "Drive %s using PIO instead\n",
 287                        drive->name, drive->name);
 288                 drive->using_dma = 0;
 289         } else
 290                 drive->using_dma = 1;
 291
 292         return 0;
 293 }
 294
 295 static int
 296 sgiioc4_ide_dma_on(ide_drive_t * drive)
 297 {
 298         drive->using_dma = 1;
 299
 300         return HWIF(drive)->ide_dma_host_on(drive);
 301 }
 302
 303 static int
 304 sgiioc4_ide_dma_off_quietly(ide_drive_t * drive)
 305 {
 306         drive->using_dma = 0;
 307
 308         return HWIF(drive)->ide_dma_host_off(drive);
 309 }
 310
 311 /* returns 1 if dma irq issued, 0 otherwise */
 312 static int
 313 sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
 314 {
 315         return sgiioc4_checkirq(HWIF(drive));
 316 }
 317
 318 static int
 319 sgiioc4_ide_dma_host_on(ide_drive_t * drive)
 320 {
 321         if (drive->using_dma)
 322                 return 0;
 323
 324         return 1;
 325 }
 326
 327 static int
 328 sgiioc4_ide_dma_host_off(ide_drive_t * drive)
 329 {
 330         sgiioc4_clearirq(drive);
 331
 332         return 0;
 333 }
 334
 335 static int
 336 sgiioc4_ide_dma_lostirq(ide_drive_t * drive)
 337 {
 338         HWIF(drive)->resetproc(drive);
 339
 340         return __ide_dma_lostirq(drive);
 341 }
 342
 343 static void
 344 sgiioc4_resetproc(ide_drive_t * drive)
 345 {
 346         sgiioc4_ide_dma_end(drive);
 347         sgiioc4_clearirq(drive);
 348 }
 349
 350 static u8
 351 sgiioc4_INB(unsigned long port)
 352 {
 353         u8 reg = (u8) inb(port);
 354
 355         if ((port & 0xFFF) == 0x11C) {  /* Status register of IOC4 */
 356                 if (reg & 0x51) {       /* Not busy...check for interrupt */
 357                         unsigned long other_ir = port - 0x110;
 358                         unsigned int intr_reg = (u32) inl(other_ir);
 359
 360                         /* Clear the Interrupt, Error bits on the IOC4 */
 361                         if (intr_reg & 0x03) {
 362                                 outl(0x03, other_ir);
 363                                 intr_reg = (u32) inl(other_ir);
 364                         }
 365                 }
 366         }
 367
 368         return reg;
 369 }
 370
 371 /* Creates a dma map for the scatter-gather list entries */
 372 static void __devinit
 373 ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
 374 {
 375         int num_ports = sizeof (ioc4_dma_regs_t);
 376
 377         printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
 378                dma_base, dma_base + num_ports - 1);
 379
 380         if (!request_region(dma_base, num_ports, hwif->name)) {
 381                 printk(KERN_ERR
 382                        "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
 383                        "ALREADY in use\n",
 384                        __FUNCTION__, hwif->name, (void *) dma_base,
 385                        (void *) dma_base + num_ports - 1);
 386                 goto dma_alloc_failure;
 387         }
 388
 389         hwif->dma_base = dma_base;
 390         hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
 391                                           IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
 392                                           &hwif->dmatable_dma);
 393
 394         if (!hwif->dmatable_cpu)
 395                 goto dma_alloc_failure;
 396
 397         hwif->sg_max_nents = IOC4_PRD_ENTRIES;
 398
 399         hwif->dma_base2 = (unsigned long)
 400                 pci_alloc_consistent(hwif->pci_dev,
 401                                      IOC4_IDE_CACHELINE_SIZE,
 402                                      (dma_addr_t *) &(hwif->dma_status));
 403
 404         if (!hwif->dma_base2)
 405                 goto dma_base2alloc_failure;
 406
 407         return;
 408
 409 dma_base2alloc_failure:
 410         pci_free_consistent(hwif->pci_dev,
 411                             IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
 412                             hwif->dmatable_cpu, hwif->dmatable_dma);
 413         printk(KERN_INFO
 414                "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
 415                __FUNCTION__, hwif->name);
 416         printk(KERN_INFO
 417                "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
 418
 419 dma_alloc_failure:
 420         /* Disable DMA because we couldnot allocate any DMA maps */
 421         hwif->autodma = 0;
 422         hwif->atapi_dma = 0;
 423 }
 424
 425 /* Initializes the IOC4 DMA Engine */
 426 static void
 427 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
 428 {
 429         u32 ioc4_dma;
 430         ide_hwif_t *hwif = HWIF(drive);
 431         u64 dma_base = hwif->dma_base;
 432         u32 dma_addr, ending_dma_addr;
 433
 434         ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
 435
 436         if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
 437                 printk(KERN_WARNING
 438                         "%s(%s):Warning!! DMA from previous transfer was still active\n",
 439                        __FUNCTION__, drive->name);
 440                 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
 441                 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 442
 443                 if (ioc4_dma & IOC4_S_DMA_STOP)
 444                         printk(KERN_ERR
 445                                "%s(%s) : IOC4 Dma STOP bit is still 1\n",
 446                                __FUNCTION__, drive->name);
 447         }
 448
 449         ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
 450         if (ioc4_dma & IOC4_S_DMA_ERROR) {
 451                 printk(KERN_WARNING
 452                        "%s(%s) : Warning!! - DMA Error during Previous"
 453                        " transfer | status 0x%x\n",
 454                        __FUNCTION__, drive->name, ioc4_dma);
 455                 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
 456                 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 457
 458                 if (ioc4_dma & IOC4_S_DMA_STOP)
 459                         printk(KERN_ERR
 460                                "%s(%s) : IOC4 DMA STOP bit is still 1\n",
 461                                __FUNCTION__, drive->name);
 462         }
 463
 464         /* Address of the Scatter Gather List */
 465         dma_addr = cpu_to_le32(hwif->dmatable_dma);
 466         hwif->OUTL(dma_addr, dma_base + IOC4_DMA_PTR_L * 4);
 467
 468         /* Address of the Ending DMA */
 469         memset((unsigned int *) hwif->dma_base2, 0, IOC4_IDE_CACHELINE_SIZE);
 470         ending_dma_addr = cpu_to_le32(hwif->dma_status);
 471         hwif->OUTL(ending_dma_addr, dma_base + IOC4_DMA_END_ADDR * 4);
 472
 473         hwif->OUTL(dma_direction, dma_base + IOC4_DMA_CTRL * 4);
 474         drive->waiting_for_dma = 1;
 475 }
 476
 477 /* IOC4 Scatter Gather list Format                                       */
 478 /* 128 Bit entries to support 64 bit addresses in the future             */
 479 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format      */
 480 /* --------------------------------------------------------------------- */
 481 /* | Upper 32 bits - Zero           |           Lower 32 bits- address | */
 482 /* --------------------------------------------------------------------- */
 483 /* | Upper 32 bits - Zero           |EOL| 15 unused     | 16 Bit Length| */
 484 /* --------------------------------------------------------------------- */
 485 /* Creates the scatter gather list, DMA Table */
 486 static unsigned int
 487 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
 488 {
 489         ide_hwif_t *hwif = HWIF(drive);
 490         unsigned int *table = hwif->dmatable_cpu;
 491         unsigned int count = 0, i = 1;
 492         struct scatterlist *sg;
 493
 494         hwif->sg_nents = i = ide_build_sglist(drive, rq);
 495
 496         if (!i)
 497                 return 0;       /* sglist of length Zero */
 498
 499         sg = hwif->sg_table;
 500         while (i && sg_dma_len(sg)) {
 501                 dma_addr_t cur_addr;
 502                 int cur_len;
 503                 cur_addr = sg_dma_address(sg);
 504                 cur_len = sg_dma_len(sg);
 505
 506                 while (cur_len) {
 507                         if (count++ >= IOC4_PRD_ENTRIES) {
 508                                 printk(KERN_WARNING
 509                                        "%s: DMA table too small\n",
 510                                        drive->name);
 511                                 goto use_pio_instead;
 512                         } else {
 513                                 u32 xcount, bcount =
 514                                     0x10000 - (cur_addr & 0xffff);
 515
 516                                 if (bcount > cur_len)
 517                                         bcount = cur_len;
 518
 519                                 /* put the addr, length in
 520                                  * the IOC4 dma-table format */
 521                                 *table = 0x0;
 522                                 table++;
 523                                 *table = cpu_to_be32(cur_addr);
 524                                 table++;
 525                                 *table = 0x0;
 526                                 table++;
 527
 528                                 xcount = bcount & 0xffff;
 529                                 *table = cpu_to_be32(xcount);
 530                                 table++;
 531
 532                                 cur_addr += bcount;
 533                                 cur_len -= bcount;
 534                         }
 535                 }
 536
 537                 sg++;
 538                 i--;
 539         }
 540
 541         if (count) {
 542                 table--;
 543                 *table |= cpu_to_be32(0x80000000);
 544                 return count;
 545         }
 546
 547 use_pio_instead:
 548         pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
 549                      hwif->sg_dma_direction);
 550
 551         return 0;               /* revert to PIO for this request */
 552 }
 553
 554 static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
 555 {
 556         struct request *rq = HWGROUP(drive)->rq;
 557         unsigned int count = 0;
 558         int ddir;
 559
 560         if (rq_data_dir(rq))
 561                 ddir = PCI_DMA_TODEVICE;
 562         else
 563                 ddir = PCI_DMA_FROMDEVICE;
 564
 565         if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
 566                 /* try PIO instead of DMA */
 567                 ide_map_sg(drive, rq);
 568                 return 1;
 569         }
 570
 571         if (rq_data_dir(rq))
 572                 /* Writes TO the IOC4 FROM Main Memory */
 573                 ddir = IOC4_DMA_READ;
 574         else
 575                 /* Writes FROM the IOC4 TO Main Memory */
 576                 ddir = IOC4_DMA_WRITE;
 577
 578         sgiioc4_configure_for_dma(ddir, drive);
 579
 580         return 0;
 581 }
 582
 583 static void __devinit
 584 ide_init_sgiioc4(ide_hwif_t * hwif)
 585 {
 586         hwif->mmio = 2;
 587         hwif->autodma = 1;
 588         hwif->atapi_dma = 1;
 589         hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
 590         hwif->mwdma_mask = 0x2; /* Multimode-2 DMA  */
 591         hwif->swdma_mask = 0x2;
 592         hwif->tuneproc = NULL;  /* Sets timing for PIO mode */
 593         hwif->speedproc = NULL; /* Sets timing for DMA &/or PIO modes */
 594         hwif->selectproc = NULL;/* Use the default routine to select drive */
 595         hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
 596         hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
 597         hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
 598                                                 clear interrupts */
 599         hwif->intrproc = NULL;  /* Enable or Disable interrupt from drive */
 600         hwif->maskproc = &sgiioc4_maskproc;     /* Mask on/off NIEN register */
 601         hwif->quirkproc = NULL;
 602         hwif->busproc = NULL;
 603
 604         hwif->dma_setup = &sgiioc4_ide_dma_setup;
 605         hwif->dma_start = &sgiioc4_ide_dma_start;
 606         hwif->ide_dma_end = &sgiioc4_ide_dma_end;
 607         hwif->ide_dma_check = &sgiioc4_ide_dma_check;
 608         hwif->ide_dma_on = &sgiioc4_ide_dma_on;
 609         hwif->ide_dma_off_quietly = &sgiioc4_ide_dma_off_quietly;
 610         hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
 611         hwif->ide_dma_host_on = &sgiioc4_ide_dma_host_on;
 612         hwif->ide_dma_host_off = &sgiioc4_ide_dma_host_off;
 613         hwif->ide_dma_lostirq = &sgiioc4_ide_dma_lostirq;
 614         hwif->ide_dma_timeout = &__ide_dma_timeout;
 615         hwif->INB = &sgiioc4_INB;
 616 }
 617
 618 static int __devinit
 619 sgiioc4_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t * d)
 620 {
 621         unsigned long base, ctl, dma_base, irqport;
 622         ide_hwif_t *hwif;
 623         int h;
 624
 625         for (h = 0; h < MAX_HWIFS; ++h) {
 626                 hwif = &ide_hwifs[h];
 627                 /* Find an empty HWIF */
 628                 if (hwif->chipset == ide_unknown)
 629                         break;
 630         }
 631
 632         /*  Get the CmdBlk and CtrlBlk Base Registers */
 633         base = pci_resource_start(dev, 0) + IOC4_CMD_OFFSET;
 634         ctl = pci_resource_start(dev, 0) + IOC4_CTRL_OFFSET;
 635         irqport = pci_resource_start(dev, 0) + IOC4_INTR_OFFSET;
 636         dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
 637
 638         if (!request_region(base, IOC4_CMD_CTL_BLK_SIZE, hwif->name)) {
 639                 printk(KERN_ERR
 640                         "%s : %s -- ERROR, Port Addresses "
 641                         "0x%p to 0x%p ALREADY in use\n",
 642                        __FUNCTION__, hwif->name, (void *) base,
 643                        (void *) base + IOC4_CMD_CTL_BLK_SIZE);
 644                 return -ENOMEM;
 645         }
 646
 647         if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
 648                 /* Initialize the IO registers */
 649                 sgiioc4_init_hwif_ports(&hwif->hw, base, ctl, irqport);
 650                 memcpy(hwif->io_ports, hwif->hw.io_ports,
 651                        sizeof (hwif->io_ports));
 652                 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
 653         }
 654
 655         hwif->irq = dev->irq;
 656         hwif->chipset = ide_pci;
 657         hwif->pci_dev = dev;
 658         hwif->channel = 0;      /* Single Channel chip */
 659         hwif->cds = (struct ide_pci_device_s *) d;
 660         hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
 661
 662         /* Initializing chipset IRQ Registers */
 663         hwif->OUTL(0x03, irqport + IOC4_INTR_SET * 4);
 664
 665         ide_init_sgiioc4(hwif);
 666
 667         if (dma_base)
 668                 ide_dma_sgiioc4(hwif, dma_base);
 669         else
 670                 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
 671                        hwif->name, d->name);
 672
 673         if (probe_hwif_init(hwif))
 674                 return -EIO;
 675
 676         /* Create /proc/ide entries */
 677         create_proc_ide_interfaces();
 678
 679         return 0;
 680 }
 681
 682 static unsigned int __devinit
 683 pci_init_sgiioc4(struct pci_dev *dev, ide_pci_device_t * d)
 684 {
 685         unsigned int class_rev;
 686         int ret;
 687
 688         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 689         class_rev &= 0xff;
 690         printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
 691                         d->name, pci_name(dev), class_rev);
 692         if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) {
 693                 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
 694                         "firmware is obsolete - please upgrade to revision"
 695                         "46 or higher\n", d->name, pci_name(dev));
 696                 ret = -EAGAIN;
 697                 goto out;
 698         }
 699         ret = sgiioc4_ide_setup_pci_device(dev, d);
 700 out:
 701         return ret;
 702 }
 703
 704 static ide_pci_device_t sgiioc4_chipsets[] __devinitdata = {
 705         {
 706          /* Channel 0 */
 707          .name = "SGIIOC4",
 708          .init_hwif = ide_init_sgiioc4,
 709          .init_dma = ide_dma_sgiioc4,
 710          .channels = 1,
 711          .autodma = AUTODMA,
 712          /* SGI IOC4 doesn't have enablebits. */
 713          .bootable = ON_BOARD,
 714         }
 715 };
 716
 717 int
 718 ioc4_ide_attach_one(struct pci_dev *dev, const struct pci_device_id *id)
 719 {
 720         return pci_init_sgiioc4(dev, &sgiioc4_chipsets[id->driver_data]);
 721 }
 722
 723
 724 MODULE_AUTHOR("Aniket Malatpure - Silicon Graphics Inc. (SGI)");
 725 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
 726 MODULE_LICENSE("GPL");
 727
 728 EXPORT_SYMBOL(ioc4_ide_attach_one);