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   1 /*
   2  *  linux/arch/arm/mm/alignment.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Modifications for ARM processor (c) 1995-2001 Russell King
   6  *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
   7  *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
   8  *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/compiler.h>
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/string.h>
  18 #include <linux/proc_fs.h>
  19 #include <linux/init.h>
  20 #include <linux/uaccess.h>
  21
  22 #include <asm/unaligned.h>
  23
  24 #include "fault.h"
  25
  26 /*
  27  * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
  28  * /proc/sys/debug/alignment, modified and integrated into
  29  * Linux 2.1 by Russell King
  30  *
  31  * Speed optimisations and better fault handling by Russell King.
  32  *
  33  * *** NOTE ***
  34  * This code is not portable to processors with late data abort handling.
  35  */
  36 #define CODING_BITS(i)  (i & 0x0e000000)
  37
  38 #define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
  39 #define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
  40 #define LDST_U_BIT(i)   (i & (1 << 23))         /* Add offset           */
  41 #define LDST_W_BIT(i)   (i & (1 << 21))         /* Writeback            */
  42 #define LDST_L_BIT(i)   (i & (1 << 20))         /* Load                 */
  43
  44 #define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
  45
  46 #define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
  47 #define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
  48
  49 #define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
  50 #define RD_BITS(i)      ((i >> 12) & 15)        /* Rd                   */
  51 #define RM_BITS(i)      (i & 15)                /* Rm                   */
  52
  53 #define REGMASK_BITS(i) (i & 0xffff)
  54 #define OFFSET_BITS(i)  (i & 0x0fff)
  55
  56 #define IS_SHIFT(i)     (i & 0x0ff0)
  57 #define SHIFT_BITS(i)   ((i >> 7) & 0x1f)
  58 #define SHIFT_TYPE(i)   (i & 0x60)
  59 #define SHIFT_LSL       0x00
  60 #define SHIFT_LSR       0x20
  61 #define SHIFT_ASR       0x40
  62 #define SHIFT_RORRRX    0x60
  63
  64 static unsigned long ai_user;
  65 static unsigned long ai_sys;
  66 static unsigned long ai_skipped;
  67 static unsigned long ai_half;
  68 static unsigned long ai_word;
  69 static unsigned long ai_dword;
  70 static unsigned long ai_multi;
  71 static int ai_usermode;
  72
  73 #define UM_WARN         (1 << 0)
  74 #define UM_FIXUP        (1 << 1)
  75 #define UM_SIGNAL       (1 << 2)
  76
  77 #ifdef CONFIG_PROC_FS
  78 static const char *usermode_action[] = {
  79         "ignored",
  80         "warn",
  81         "fixup",
  82         "fixup+warn",
  83         "signal",
  84         "signal+warn"
  85 };
  86
  87 static int
  88 proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
  89                     void *data)
  90 {
  91         char *p = page;
  92         int len;
  93
  94         p += sprintf(p, "User:\t\t%lu\n", ai_user);
  95         p += sprintf(p, "System:\t\t%lu\n", ai_sys);
  96         p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
  97         p += sprintf(p, "Half:\t\t%lu\n", ai_half);
  98         p += sprintf(p, "Word:\t\t%lu\n", ai_word);
  99         if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
 100                 p += sprintf(p, "DWord:\t\t%lu\n", ai_dword);
 101         p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
 102         p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
 103                         usermode_action[ai_usermode]);
 104
 105         len = (p - page) - off;
 106         if (len < 0)
 107                 len = 0;
 108
 109         *eof = (len <= count) ? 1 : 0;
 110         *start = page + off;
 111
 112         return len;
 113 }
 114
 115 static int proc_alignment_write(struct file *file, const char __user *buffer,
 116                                 unsigned long count, void *data)
 117 {
 118         char mode;
 119
 120         if (count > 0) {
 121                 if (get_user(mode, buffer))
 122                         return -EFAULT;
 123                 if (mode >= '0' && mode <= '5')
 124                         ai_usermode = mode - '0';
 125         }
 126         return count;
 127 }
 128
 129 #endif /* CONFIG_PROC_FS */
 130
 131 union offset_union {
 132         unsigned long un;
 133           signed long sn;
 134 };
 135
 136 #define TYPE_ERROR      0
 137 #define TYPE_FAULT      1
 138 #define TYPE_LDST       2
 139 #define TYPE_DONE       3
 140
 141 #ifdef __ARMEB__
 142 #define BE              1
 143 #define FIRST_BYTE_16   "mov    %1, %1, ror #8\n"
 144 #define FIRST_BYTE_32   "mov    %1, %1, ror #24\n"
 145 #define NEXT_BYTE       "ror #24"
 146 #else
 147 #define BE              0
 148 #define FIRST_BYTE_16
 149 #define FIRST_BYTE_32
 150 #define NEXT_BYTE       "lsr #8"
 151 #endif
 152
 153 #define __get8_unaligned_check(ins,val,addr,err)        \
 154         __asm__(                                        \
 155         "1:     "ins"   %1, [%2], #1\n"                 \
 156         "2:\n"                                          \
 157         "       .section .fixup,\"ax\"\n"               \
 158         "       .align  2\n"                            \
 159         "3:     mov     %0, #1\n"                       \
 160         "       b       2b\n"                           \
 161         "       .previous\n"                            \
 162         "       .section __ex_table,\"a\"\n"            \
 163         "       .align  3\n"                            \
 164         "       .long   1b, 3b\n"                       \
 165         "       .previous\n"                            \
 166         : "=r" (err), "=&r" (val), "=r" (addr)          \
 167         : "0" (err), "2" (addr))
 168
 169 #define __get16_unaligned_check(ins,val,addr)                   \
 170         do {                                                    \
 171                 unsigned int err = 0, v, a = addr;              \
 172                 __get8_unaligned_check(ins,v,a,err);            \
 173                 val =  v << ((BE) ? 8 : 0);                     \
 174                 __get8_unaligned_check(ins,v,a,err);            \
 175                 val |= v << ((BE) ? 0 : 8);                     \
 176                 if (err)                                        \
 177                         goto fault;                             \
 178         } while (0)
 179
 180 #define get16_unaligned_check(val,addr) \
 181         __get16_unaligned_check("ldrb",val,addr)
 182
 183 #define get16t_unaligned_check(val,addr) \
 184         __get16_unaligned_check("ldrbt",val,addr)
 185
 186 #define __get32_unaligned_check(ins,val,addr)                   \
 187         do {                                                    \
 188                 unsigned int err = 0, v, a = addr;              \
 189                 __get8_unaligned_check(ins,v,a,err);            \
 190                 val =  v << ((BE) ? 24 :  0);                   \
 191                 __get8_unaligned_check(ins,v,a,err);            \
 192                 val |= v << ((BE) ? 16 :  8);                   \
 193                 __get8_unaligned_check(ins,v,a,err);            \
 194                 val |= v << ((BE) ?  8 : 16);                   \
 195                 __get8_unaligned_check(ins,v,a,err);            \
 196                 val |= v << ((BE) ?  0 : 24);                   \
 197                 if (err)                                        \
 198                         goto fault;                             \
 199         } while (0)
 200
 201 #define get32_unaligned_check(val,addr) \
 202         __get32_unaligned_check("ldrb",val,addr)
 203
 204 #define get32t_unaligned_check(val,addr) \
 205         __get32_unaligned_check("ldrbt",val,addr)
 206
 207 #define __put16_unaligned_check(ins,val,addr)                   \
 208         do {                                                    \
 209                 unsigned int err = 0, v = val, a = addr;        \
 210                 __asm__( FIRST_BYTE_16                          \
 211                 "1:     "ins"   %1, [%2], #1\n"                 \
 212                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 213                 "2:     "ins"   %1, [%2]\n"                     \
 214                 "3:\n"                                          \
 215                 "       .section .fixup,\"ax\"\n"               \
 216                 "       .align  2\n"                            \
 217                 "4:     mov     %0, #1\n"                       \
 218                 "       b       3b\n"                           \
 219                 "       .previous\n"                            \
 220                 "       .section __ex_table,\"a\"\n"            \
 221                 "       .align  3\n"                            \
 222                 "       .long   1b, 4b\n"                       \
 223                 "       .long   2b, 4b\n"                       \
 224                 "       .previous\n"                            \
 225                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 226                 : "0" (err), "1" (v), "2" (a));                 \
 227                 if (err)                                        \
 228                         goto fault;                             \
 229         } while (0)
 230
 231 #define put16_unaligned_check(val,addr)  \
 232         __put16_unaligned_check("strb",val,addr)
 233
 234 #define put16t_unaligned_check(val,addr) \
 235         __put16_unaligned_check("strbt",val,addr)
 236
 237 #define __put32_unaligned_check(ins,val,addr)                   \
 238         do {                                                    \
 239                 unsigned int err = 0, v = val, a = addr;        \
 240                 __asm__( FIRST_BYTE_32                          \
 241                 "1:     "ins"   %1, [%2], #1\n"                 \
 242                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 243                 "2:     "ins"   %1, [%2], #1\n"                 \
 244                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 245                 "3:     "ins"   %1, [%2], #1\n"                 \
 246                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 247                 "4:     "ins"   %1, [%2]\n"                     \
 248                 "5:\n"                                          \
 249                 "       .section .fixup,\"ax\"\n"               \
 250                 "       .align  2\n"                            \
 251                 "6:     mov     %0, #1\n"                       \
 252                 "       b       5b\n"                           \
 253                 "       .previous\n"                            \
 254                 "       .section __ex_table,\"a\"\n"            \
 255                 "       .align  3\n"                            \
 256                 "       .long   1b, 6b\n"                       \
 257                 "       .long   2b, 6b\n"                       \
 258                 "       .long   3b, 6b\n"                       \
 259                 "       .long   4b, 6b\n"                       \
 260                 "       .previous\n"                            \
 261                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 262                 : "0" (err), "1" (v), "2" (a));                 \
 263                 if (err)                                        \
 264                         goto fault;                             \
 265         } while (0)
 266
 267 #define put32_unaligned_check(val,addr) \
 268         __put32_unaligned_check("strb", val, addr)
 269
 270 #define put32t_unaligned_check(val,addr) \
 271         __put32_unaligned_check("strbt", val, addr)
 272
 273 static void
 274 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
 275 {
 276         if (!LDST_U_BIT(instr))
 277                 offset.un = -offset.un;
 278
 279         if (!LDST_P_BIT(instr))
 280                 addr += offset.un;
 281
 282         if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
 283                 regs->uregs[RN_BITS(instr)] = addr;
 284 }
 285
 286 static int
 287 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 288 {
 289         unsigned int rd = RD_BITS(instr);
 290
 291         ai_half += 1;
 292
 293         if (user_mode(regs))
 294                 goto user;
 295
 296         if (LDST_L_BIT(instr)) {
 297                 unsigned long val;
 298                 get16_unaligned_check(val, addr);
 299
 300                 /* signed half-word? */
 301                 if (instr & 0x40)
 302                         val = (signed long)((signed short) val);
 303
 304                 regs->uregs[rd] = val;
 305         } else
 306                 put16_unaligned_check(regs->uregs[rd], addr);
 307
 308         return TYPE_LDST;
 309
 310  user:
 311         if (LDST_L_BIT(instr)) {
 312                 unsigned long val;
 313                 get16t_unaligned_check(val, addr);
 314
 315                 /* signed half-word? */
 316                 if (instr & 0x40)
 317                         val = (signed long)((signed short) val);
 318
 319                 regs->uregs[rd] = val;
 320         } else
 321                 put16t_unaligned_check(regs->uregs[rd], addr);
 322
 323         return TYPE_LDST;
 324
 325  fault:
 326         return TYPE_FAULT;
 327 }
 328
 329 static int
 330 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
 331                       struct pt_regs *regs)
 332 {
 333         unsigned int rd = RD_BITS(instr);
 334
 335         if (((rd & 1) == 1) || (rd == 14))
 336                 goto bad;
 337
 338         ai_dword += 1;
 339
 340         if (user_mode(regs))
 341                 goto user;
 342
 343         if ((instr & 0xf0) == 0xd0) {
 344                 unsigned long val;
 345                 get32_unaligned_check(val, addr);
 346                 regs->uregs[rd] = val;
 347                 get32_unaligned_check(val, addr + 4);
 348                 regs->uregs[rd + 1] = val;
 349         } else {
 350                 put32_unaligned_check(regs->uregs[rd], addr);
 351                 put32_unaligned_check(regs->uregs[rd + 1], addr + 4);
 352         }
 353
 354         return TYPE_LDST;
 355
 356  user:
 357         if ((instr & 0xf0) == 0xd0) {
 358                 unsigned long val;
 359                 get32t_unaligned_check(val, addr);
 360                 regs->uregs[rd] = val;
 361                 get32t_unaligned_check(val, addr + 4);
 362                 regs->uregs[rd + 1] = val;
 363         } else {
 364                 put32t_unaligned_check(regs->uregs[rd], addr);
 365                 put32t_unaligned_check(regs->uregs[rd + 1], addr + 4);
 366         }
 367
 368         return TYPE_LDST;
 369  bad:
 370         return TYPE_ERROR;
 371  fault:
 372         return TYPE_FAULT;
 373 }
 374
 375 static int
 376 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 377 {
 378         unsigned int rd = RD_BITS(instr);
 379
 380         ai_word += 1;
 381
 382         if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
 383                 goto trans;
 384
 385         if (LDST_L_BIT(instr)) {
 386                 unsigned int val;
 387                 get32_unaligned_check(val, addr);
 388                 regs->uregs[rd] = val;
 389         } else
 390                 put32_unaligned_check(regs->uregs[rd], addr);
 391         return TYPE_LDST;
 392
 393  trans:
 394         if (LDST_L_BIT(instr)) {
 395                 unsigned int val;
 396                 get32t_unaligned_check(val, addr);
 397                 regs->uregs[rd] = val;
 398         } else
 399                 put32t_unaligned_check(regs->uregs[rd], addr);
 400         return TYPE_LDST;
 401
 402  fault:
 403         return TYPE_FAULT;
 404 }
 405
 406 /*
 407  * LDM/STM alignment handler.
 408  *
 409  * There are 4 variants of this instruction:
 410  *
 411  * B = rn pointer before instruction, A = rn pointer after instruction
 412  *              ------ increasing address ----->
 413  *              |    | r0 | r1 | ... | rx |    |
 414  * PU = 01             B                    A
 415  * PU = 11        B                    A
 416  * PU = 00        A                    B
 417  * PU = 10             A                    B
 418  */
 419 static int
 420 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 421 {
 422         unsigned int rd, rn, correction, nr_regs, regbits;
 423         unsigned long eaddr, newaddr;
 424
 425         if (LDM_S_BIT(instr))
 426                 goto bad;
 427
 428         correction = 4; /* processor implementation defined */
 429         regs->ARM_pc += correction;
 430
 431         ai_multi += 1;
 432
 433         /* count the number of registers in the mask to be transferred */
 434         nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
 435
 436         rn = RN_BITS(instr);
 437         newaddr = eaddr = regs->uregs[rn];
 438
 439         if (!LDST_U_BIT(instr))
 440                 nr_regs = -nr_regs;
 441         newaddr += nr_regs;
 442         if (!LDST_U_BIT(instr))
 443                 eaddr = newaddr;
 444
 445         if (LDST_P_EQ_U(instr)) /* U = P */
 446                 eaddr += 4;
 447
 448         /*
 449          * For alignment faults on the ARM922T/ARM920T the MMU  makes
 450          * the FSR (and hence addr) equal to the updated base address
 451          * of the multiple access rather than the restored value.
 452          * Switch this message off if we've got a ARM92[02], otherwise
 453          * [ls]dm alignment faults are noisy!
 454          */
 455 #if !(defined CONFIG_CPU_ARM922T)  && !(defined CONFIG_CPU_ARM920T)
 456         /*
 457          * This is a "hint" - we already have eaddr worked out by the
 458          * processor for us.
 459          */
 460         if (addr != eaddr) {
 461                 printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
 462                         "addr = %08lx, eaddr = %08lx\n",
 463                          instruction_pointer(regs), instr, addr, eaddr);
 464                 show_regs(regs);
 465         }
 466 #endif
 467
 468         if (user_mode(regs)) {
 469                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 470                      regbits >>= 1, rd += 1)
 471                         if (regbits & 1) {
 472                                 if (LDST_L_BIT(instr)) {
 473                                         unsigned int val;
 474                                         get32t_unaligned_check(val, eaddr);
 475                                         regs->uregs[rd] = val;
 476                                 } else
 477                                         put32t_unaligned_check(regs->uregs[rd], eaddr);
 478                                 eaddr += 4;
 479                         }
 480         } else {
 481                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 482                      regbits >>= 1, rd += 1)
 483                         if (regbits & 1) {
 484                                 if (LDST_L_BIT(instr)) {
 485                                         unsigned int val;
 486                                         get32_unaligned_check(val, eaddr);
 487                                         regs->uregs[rd] = val;
 488                                 } else
 489                                         put32_unaligned_check(regs->uregs[rd], eaddr);
 490                                 eaddr += 4;
 491                         }
 492         }
 493
 494         if (LDST_W_BIT(instr))
 495                 regs->uregs[rn] = newaddr;
 496         if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
 497                 regs->ARM_pc -= correction;
 498         return TYPE_DONE;
 499
 500 fault:
 501         regs->ARM_pc -= correction;
 502         return TYPE_FAULT;
 503
 504 bad:
 505         printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
 506         return TYPE_ERROR;
 507 }
 508
 509 /*
 510  * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
 511  * we can reuse ARM userland alignment fault fixups for Thumb.
 512  *
 513  * This implementation was initially based on the algorithm found in
 514  * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
 515  * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
 516  *
 517  * NOTES:
 518  * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
 519  * 2. If for some reason we're passed an non-ld/st Thumb instruction to
 520  *    decode, we return 0xdeadc0de. This should never happen under normal
 521  *    circumstances but if it does, we've got other problems to deal with
 522  *    elsewhere and we obviously can't fix those problems here.
 523  */
 524
 525 static unsigned long
 526 thumb2arm(u16 tinstr)
 527 {
 528         u32 L = (tinstr & (1<<11)) >> 11;
 529
 530         switch ((tinstr & 0xf800) >> 11) {
 531         /* 6.5.1 Format 1: */
 532         case 0x6000 >> 11:                              /* 7.1.52 STR(1) */
 533         case 0x6800 >> 11:                              /* 7.1.26 LDR(1) */
 534         case 0x7000 >> 11:                              /* 7.1.55 STRB(1) */
 535         case 0x7800 >> 11:                              /* 7.1.30 LDRB(1) */
 536                 return 0xe5800000 |
 537                         ((tinstr & (1<<12)) << (22-12)) |       /* fixup */
 538                         (L<<20) |                               /* L==1? */
 539                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 540                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 541                         ((tinstr & (31<<6)) >>                  /* immed_5 */
 542                                 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
 543         case 0x8000 >> 11:                              /* 7.1.57 STRH(1) */
 544         case 0x8800 >> 11:                              /* 7.1.32 LDRH(1) */
 545                 return 0xe1c000b0 |
 546                         (L<<20) |                               /* L==1? */
 547                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 548                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 549                         ((tinstr & (7<<6)) >> (6-1)) |   /* immed_5[2:0] */
 550                         ((tinstr & (3<<9)) >> (9-8));    /* immed_5[4:3] */
 551
 552         /* 6.5.1 Format 2: */
 553         case 0x5000 >> 11:
 554         case 0x5800 >> 11:
 555                 {
 556                         static const u32 subset[8] = {
 557                                 0xe7800000,             /* 7.1.53 STR(2) */
 558                                 0xe18000b0,             /* 7.1.58 STRH(2) */
 559                                 0xe7c00000,             /* 7.1.56 STRB(2) */
 560                                 0xe19000d0,             /* 7.1.34 LDRSB */
 561                                 0xe7900000,             /* 7.1.27 LDR(2) */
 562                                 0xe19000b0,             /* 7.1.33 LDRH(2) */
 563                                 0xe7d00000,             /* 7.1.31 LDRB(2) */
 564                                 0xe19000f0              /* 7.1.35 LDRSH */
 565                         };
 566                         return subset[(tinstr & (7<<9)) >> 9] |
 567                             ((tinstr & (7<<0)) << (12-0)) |     /* Rd */
 568                             ((tinstr & (7<<3)) << (16-3)) |     /* Rn */
 569                             ((tinstr & (7<<6)) >> (6-0));       /* Rm */
 570                 }
 571
 572         /* 6.5.1 Format 3: */
 573         case 0x4800 >> 11:                              /* 7.1.28 LDR(3) */
 574                 /* NOTE: This case is not technically possible. We're
 575                  *       loading 32-bit memory data via PC relative
 576                  *       addressing mode. So we can and should eliminate
 577                  *       this case. But I'll leave it here for now.
 578                  */
 579                 return 0xe59f0000 |
 580                     ((tinstr & (7<<8)) << (12-8)) |             /* Rd */
 581                     ((tinstr & 255) << (2-0));                  /* immed_8 */
 582
 583         /* 6.5.1 Format 4: */
 584         case 0x9000 >> 11:                              /* 7.1.54 STR(3) */
 585         case 0x9800 >> 11:                              /* 7.1.29 LDR(4) */
 586                 return 0xe58d0000 |
 587                         (L<<20) |                               /* L==1? */
 588                         ((tinstr & (7<<8)) << (12-8)) |         /* Rd */
 589                         ((tinstr & 255) << 2);                  /* immed_8 */
 590
 591         /* 6.6.1 Format 1: */
 592         case 0xc000 >> 11:                              /* 7.1.51 STMIA */
 593         case 0xc800 >> 11:                              /* 7.1.25 LDMIA */
 594                 {
 595                         u32 Rn = (tinstr & (7<<8)) >> 8;
 596                         u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
 597
 598                         return 0xe8800000 | W | (L<<20) | (Rn<<16) |
 599                                 (tinstr&255);
 600                 }
 601
 602         /* 6.6.1 Format 2: */
 603         case 0xb000 >> 11:                              /* 7.1.48 PUSH */
 604         case 0xb800 >> 11:                              /* 7.1.47 POP */
 605                 if ((tinstr & (3 << 9)) == 0x0400) {
 606                         static const u32 subset[4] = {
 607                                 0xe92d0000,     /* STMDB sp!,{registers} */
 608                                 0xe92d4000,     /* STMDB sp!,{registers,lr} */
 609                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
 610                                 0xe8bd8000      /* LDMIA sp!,{registers,pc} */
 611                         };
 612                         return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
 613                             (tinstr & 255);             /* register_list */
 614                 }
 615                 /* Else fall through for illegal instruction case */
 616
 617         default:
 618                 return 0xdeadc0de;
 619         }
 620 }
 621
 622 static int
 623 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 624 {
 625         union offset_union offset;
 626         unsigned long instr = 0, instrptr;
 627         int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
 628         unsigned int type;
 629         mm_segment_t fs;
 630         unsigned int fault;
 631         u16 tinstr = 0;
 632
 633         instrptr = instruction_pointer(regs);
 634
 635         fs = get_fs();
 636         set_fs(KERNEL_DS);
 637         if (thumb_mode(regs)) {
 638                 fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
 639                 if (!(fault))
 640                         instr = thumb2arm(tinstr);
 641         } else
 642                 fault = __get_user(instr, (u32 *)instrptr);
 643         set_fs(fs);
 644
 645         if (fault) {
 646                 type = TYPE_FAULT;
 647                 goto bad_or_fault;
 648         }
 649
 650         if (user_mode(regs))
 651                 goto user;
 652
 653         ai_sys += 1;
 654
 655  fixup:
 656
 657         regs->ARM_pc += thumb_mode(regs) ? 2 : 4;
 658
 659         switch (CODING_BITS(instr)) {
 660         case 0x00000000:        /* 3.13.4 load/store instruction extensions */
 661                 if (LDSTHD_I_BIT(instr))
 662                         offset.un = (instr & 0xf00) >> 4 | (instr & 15);
 663                 else
 664                         offset.un = regs->uregs[RM_BITS(instr)];
 665
 666                 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
 667                     (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
 668                         handler = do_alignment_ldrhstrh;
 669                 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
 670                          (instr & 0x001000f0) == 0x000000f0)   /* STRD */
 671                         handler = do_alignment_ldrdstrd;
 672                 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
 673                         goto swp;
 674                 else
 675                         goto bad;
 676                 break;
 677
 678         case 0x04000000:        /* ldr or str immediate */
 679                 offset.un = OFFSET_BITS(instr);
 680                 handler = do_alignment_ldrstr;
 681                 break;
 682
 683         case 0x06000000:        /* ldr or str register */
 684                 offset.un = regs->uregs[RM_BITS(instr)];
 685
 686                 if (IS_SHIFT(instr)) {
 687                         unsigned int shiftval = SHIFT_BITS(instr);
 688
 689                         switch(SHIFT_TYPE(instr)) {
 690                         case SHIFT_LSL:
 691                                 offset.un <<= shiftval;
 692                                 break;
 693
 694                         case SHIFT_LSR:
 695                                 offset.un >>= shiftval;
 696                                 break;
 697
 698                         case SHIFT_ASR:
 699                                 offset.sn >>= shiftval;
 700                                 break;
 701
 702                         case SHIFT_RORRRX:
 703                                 if (shiftval == 0) {
 704                                         offset.un >>= 1;
 705                                         if (regs->ARM_cpsr & PSR_C_BIT)
 706                                                 offset.un |= 1 << 31;
 707                                 } else
 708                                         offset.un = offset.un >> shiftval |
 709                                                           offset.un << (32 - shiftval);
 710                                 break;
 711                         }
 712                 }
 713                 handler = do_alignment_ldrstr;
 714                 break;
 715
 716         case 0x08000000:        /* ldm or stm */
 717                 handler = do_alignment_ldmstm;
 718                 break;
 719
 720         default:
 721                 goto bad;
 722         }
 723
 724         type = handler(addr, instr, regs);
 725
 726         if (type == TYPE_ERROR || type == TYPE_FAULT)
 727                 goto bad_or_fault;
 728
 729         if (type == TYPE_LDST)
 730                 do_alignment_finish_ldst(addr, instr, regs, offset);
 731
 732         return 0;
 733
 734  bad_or_fault:
 735         if (type == TYPE_ERROR)
 736                 goto bad;
 737         regs->ARM_pc -= thumb_mode(regs) ? 2 : 4;
 738         /*
 739          * We got a fault - fix it up, or die.
 740          */
 741         do_bad_area(addr, fsr, regs);
 742         return 0;
 743
 744  swp:
 745         printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
 746
 747  bad:
 748         /*
 749          * Oops, we didn't handle the instruction.
 750          */
 751         printk(KERN_ERR "Alignment trap: not handling instruction "
 752                 "%0*lx at [<%08lx>]\n",
 753                 thumb_mode(regs) ? 4 : 8,
 754                 thumb_mode(regs) ? tinstr : instr, instrptr);
 755         ai_skipped += 1;
 756         return 1;
 757
 758  user:
 759         ai_user += 1;
 760
 761         if (ai_usermode & UM_WARN)
 762                 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
 763                        "Address=0x%08lx FSR 0x%03x\n", current->comm,
 764                         task_pid_nr(current), instrptr,
 765                         thumb_mode(regs) ? 4 : 8,
 766                         thumb_mode(regs) ? tinstr : instr,
 767                         addr, fsr);
 768
 769         if (ai_usermode & UM_FIXUP)
 770                 goto fixup;
 771
 772         if (ai_usermode & UM_SIGNAL)
 773                 force_sig(SIGBUS, current);
 774         else
 775                 set_cr(cr_no_alignment);
 776
 777         return 0;
 778 }
 779
 780 /*
 781  * This needs to be done after sysctl_init, otherwise sys/ will be
 782  * overwritten.  Actually, this shouldn't be in sys/ at all since
 783  * it isn't a sysctl, and it doesn't contain sysctl information.
 784  * We now locate it in /proc/cpu/alignment instead.
 785  */
 786 static int __init alignment_init(void)
 787 {
 788 #ifdef CONFIG_PROC_FS
 789         struct proc_dir_entry *res;
 790
 791         res = proc_mkdir("cpu", NULL);
 792         if (!res)
 793                 return -ENOMEM;
 794
 795         res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res);
 796         if (!res)
 797                 return -ENOMEM;
 798
 799         res->read_proc = proc_alignment_read;
 800         res->write_proc = proc_alignment_write;
 801 #endif
 802
 803         /*
 804          * ARMv6 and later CPUs can perform unaligned accesses for
 805          * most single load and store instructions up to word size.
 806          * LDM, STM, LDRD and STRD still need to be handled.
 807          *
 808          * Ignoring the alignment fault is not an option on these
 809          * CPUs since we spin re-faulting the instruction without
 810          * making any progress.
 811          */
 812         if (cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U)) {
 813                 cr_alignment &= ~CR_A;
 814                 cr_no_alignment &= ~CR_A;
 815                 set_cr(cr_alignment);
 816                 ai_usermode = UM_FIXUP;
 817         }
 818
 819         hook_fault_code(1, do_alignment, SIGILL, "alignment exception");
 820         hook_fault_code(3, do_alignment, SIGILL, "alignment exception");
 821
 822         return 0;
 823 }
 824
 825 fs_initcall(alignment_init);