git.oblomov.eu Git - linux-2.6/blob - drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  72         /* required last entry */
  73         {0, }
  74 };
  75
  76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  77
  78 void igb_reset(struct igb_adapter *);
  79 static int igb_setup_all_tx_resources(struct igb_adapter *);
  80 static int igb_setup_all_rx_resources(struct igb_adapter *);
  81 static void igb_free_all_tx_resources(struct igb_adapter *);
  82 static void igb_free_all_rx_resources(struct igb_adapter *);
  83 void igb_update_stats(struct igb_adapter *);
  84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  85 static void __devexit igb_remove(struct pci_dev *pdev);
  86 static int igb_sw_init(struct igb_adapter *);
  87 static int igb_open(struct net_device *);
  88 static int igb_close(struct net_device *);
  89 static void igb_configure_tx(struct igb_adapter *);
  90 static void igb_configure_rx(struct igb_adapter *);
  91 static void igb_setup_rctl(struct igb_adapter *);
  92 static void igb_clean_all_tx_rings(struct igb_adapter *);
  93 static void igb_clean_all_rx_rings(struct igb_adapter *);
  94 static void igb_clean_tx_ring(struct igb_ring *);
  95 static void igb_clean_rx_ring(struct igb_ring *);
  96 static void igb_set_multi(struct net_device *);
  97 static void igb_update_phy_info(unsigned long);
  98 static void igb_watchdog(unsigned long);
  99 static void igb_watchdog_task(struct work_struct *);
 100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
 101                                   struct igb_ring *);
 102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 103 static struct net_device_stats *igb_get_stats(struct net_device *);
 104 static int igb_change_mtu(struct net_device *, int);
 105 static int igb_set_mac(struct net_device *, void *);
 106 static irqreturn_t igb_intr(int irq, void *);
 107 static irqreturn_t igb_intr_msi(int irq, void *);
 108 static irqreturn_t igb_msix_other(int irq, void *);
 109 static irqreturn_t igb_msix_rx(int irq, void *);
 110 static irqreturn_t igb_msix_tx(int irq, void *);
 111 #ifdef CONFIG_IGB_DCA
 112 static void igb_update_rx_dca(struct igb_ring *);
 113 static void igb_update_tx_dca(struct igb_ring *);
 114 static void igb_setup_dca(struct igb_adapter *);
 115 #endif /* CONFIG_IGB_DCA */
 116 static bool igb_clean_tx_irq(struct igb_ring *);
 117 static int igb_poll(struct napi_struct *, int);
 118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 121 static void igb_tx_timeout(struct net_device *);
 122 static void igb_reset_task(struct work_struct *);
 123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 126 static void igb_restore_vlan(struct igb_adapter *);
 127 static void igb_ping_all_vfs(struct igb_adapter *);
 128 static void igb_msg_task(struct igb_adapter *);
 129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
 131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
 132 static void igb_vmm_control(struct igb_adapter *);
 133 static inline void igb_set_vmolr(struct e1000_hw *, int);
 134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
 135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 137
 138 static int igb_suspend(struct pci_dev *, pm_message_t);
 139 #ifdef CONFIG_PM
 140 static int igb_resume(struct pci_dev *);
 141 #endif
 142 static void igb_shutdown(struct pci_dev *);
 143 #ifdef CONFIG_IGB_DCA
 144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 145 static struct notifier_block dca_notifier = {
 146         .notifier_call  = igb_notify_dca,
 147         .next           = NULL,
 148         .priority       = 0
 149 };
 150 #endif
 151 #ifdef CONFIG_NET_POLL_CONTROLLER
 152 /* for netdump / net console */
 153 static void igb_netpoll(struct net_device *);
 154 #endif
 155
 156 #ifdef CONFIG_PCI_IOV
 157 static ssize_t igb_set_num_vfs(struct device *, struct device_attribute *,
 158                                const char *, size_t);
 159 static ssize_t igb_show_num_vfs(struct device *, struct device_attribute *,
 160                                char *);
 161 DEVICE_ATTR(num_vfs, S_IRUGO | S_IWUSR, igb_show_num_vfs, igb_set_num_vfs);
 162 #endif
 163 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 164                      pci_channel_state_t);
 165 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 166 static void igb_io_resume(struct pci_dev *);
 167
 168 static struct pci_error_handlers igb_err_handler = {
 169         .error_detected = igb_io_error_detected,
 170         .slot_reset = igb_io_slot_reset,
 171         .resume = igb_io_resume,
 172 };
 173
 174
 175 static struct pci_driver igb_driver = {
 176         .name     = igb_driver_name,
 177         .id_table = igb_pci_tbl,
 178         .probe    = igb_probe,
 179         .remove   = __devexit_p(igb_remove),
 180 #ifdef CONFIG_PM
 181         /* Power Managment Hooks */
 182         .suspend  = igb_suspend,
 183         .resume   = igb_resume,
 184 #endif
 185         .shutdown = igb_shutdown,
 186         .err_handler = &igb_err_handler
 187 };
 188
 189 static int global_quad_port_a; /* global quad port a indication */
 190
 191 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 192 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 193 MODULE_LICENSE("GPL");
 194 MODULE_VERSION(DRV_VERSION);
 195
 196 /**
 197  * Scale the NIC clock cycle by a large factor so that
 198  * relatively small clock corrections can be added or
 199  * substracted at each clock tick. The drawbacks of a
 200  * large factor are a) that the clock register overflows
 201  * more quickly (not such a big deal) and b) that the
 202  * increment per tick has to fit into 24 bits.
 203  *
 204  * Note that
 205  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 206  *             IGB_TSYNC_SCALE
 207  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 208  *
 209  * The base scale factor is intentionally a power of two
 210  * so that the division in %struct timecounter can be done with
 211  * a shift.
 212  */
 213 #define IGB_TSYNC_SHIFT (19)
 214 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 215
 216 /**
 217  * The duration of one clock cycle of the NIC.
 218  *
 219  * @todo This hard-coded value is part of the specification and might change
 220  * in future hardware revisions. Add revision check.
 221  */
 222 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 223
 224 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 225 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 226 #endif
 227
 228 /**
 229  * igb_read_clock - read raw cycle counter (to be used by time counter)
 230  */
 231 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 232 {
 233         struct igb_adapter *adapter =
 234                 container_of(tc, struct igb_adapter, cycles);
 235         struct e1000_hw *hw = &adapter->hw;
 236         u64 stamp;
 237
 238         stamp =  rd32(E1000_SYSTIML);
 239         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 240
 241         return stamp;
 242 }
 243
 244 #ifdef DEBUG
 245 /**
 246  * igb_get_hw_dev_name - return device name string
 247  * used by hardware layer to print debugging information
 248  **/
 249 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 250 {
 251         struct igb_adapter *adapter = hw->back;
 252         return adapter->netdev->name;
 253 }
 254
 255 /**
 256  * igb_get_time_str - format current NIC and system time as string
 257  */
 258 static char *igb_get_time_str(struct igb_adapter *adapter,
 259                               char buffer[160])
 260 {
 261         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 262         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 263         struct timespec sys;
 264         struct timespec delta;
 265         getnstimeofday(&sys);
 266
 267         delta = timespec_sub(nic, sys);
 268
 269         sprintf(buffer,
 270                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 271                 hw,
 272                 (long)nic.tv_sec, nic.tv_nsec,
 273                 (long)sys.tv_sec, sys.tv_nsec,
 274                 (long)delta.tv_sec, delta.tv_nsec);
 275
 276         return buffer;
 277 }
 278 #endif
 279
 280 /**
 281  * igb_init_module - Driver Registration Routine
 282  *
 283  * igb_init_module is the first routine called when the driver is
 284  * loaded. All it does is register with the PCI subsystem.
 285  **/
 286 static int __init igb_init_module(void)
 287 {
 288         int ret;
 289         printk(KERN_INFO "%s - version %s\n",
 290                igb_driver_string, igb_driver_version);
 291
 292         printk(KERN_INFO "%s\n", igb_copyright);
 293
 294         global_quad_port_a = 0;
 295
 296 #ifdef CONFIG_IGB_DCA
 297         dca_register_notify(&dca_notifier);
 298 #endif
 299
 300         ret = pci_register_driver(&igb_driver);
 301         return ret;
 302 }
 303
 304 module_init(igb_init_module);
 305
 306 /**
 307  * igb_exit_module - Driver Exit Cleanup Routine
 308  *
 309  * igb_exit_module is called just before the driver is removed
 310  * from memory.
 311  **/
 312 static void __exit igb_exit_module(void)
 313 {
 314 #ifdef CONFIG_IGB_DCA
 315         dca_unregister_notify(&dca_notifier);
 316 #endif
 317         pci_unregister_driver(&igb_driver);
 318 }
 319
 320 module_exit(igb_exit_module);
 321
 322 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 323 /**
 324  * igb_cache_ring_register - Descriptor ring to register mapping
 325  * @adapter: board private structure to initialize
 326  *
 327  * Once we know the feature-set enabled for the device, we'll cache
 328  * the register offset the descriptor ring is assigned to.
 329  **/
 330 static void igb_cache_ring_register(struct igb_adapter *adapter)
 331 {
 332         int i;
 333         unsigned int rbase_offset = adapter->vfs_allocated_count;
 334
 335         switch (adapter->hw.mac.type) {
 336         case e1000_82576:
 337                 /* The queues are allocated for virtualization such that VF 0
 338                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 339                  * In order to avoid collision we start at the first free queue
 340                  * and continue consuming queues in the same sequence
 341                  */
 342                 for (i = 0; i < adapter->num_rx_queues; i++)
 343                         adapter->rx_ring[i].reg_idx = rbase_offset +
 344                                                       Q_IDX_82576(i);
 345                 for (i = 0; i < adapter->num_tx_queues; i++)
 346                         adapter->tx_ring[i].reg_idx = rbase_offset +
 347                                                       Q_IDX_82576(i);
 348                 break;
 349         case e1000_82575:
 350         default:
 351                 for (i = 0; i < adapter->num_rx_queues; i++)
 352                         adapter->rx_ring[i].reg_idx = i;
 353                 for (i = 0; i < adapter->num_tx_queues; i++)
 354                         adapter->tx_ring[i].reg_idx = i;
 355                 break;
 356         }
 357 }
 358
 359 /**
 360  * igb_alloc_queues - Allocate memory for all rings
 361  * @adapter: board private structure to initialize
 362  *
 363  * We allocate one ring per queue at run-time since we don't know the
 364  * number of queues at compile-time.
 365  **/
 366 static int igb_alloc_queues(struct igb_adapter *adapter)
 367 {
 368         int i;
 369
 370         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 371                                    sizeof(struct igb_ring), GFP_KERNEL);
 372         if (!adapter->tx_ring)
 373                 return -ENOMEM;
 374
 375         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 376                                    sizeof(struct igb_ring), GFP_KERNEL);
 377         if (!adapter->rx_ring) {
 378                 kfree(adapter->tx_ring);
 379                 return -ENOMEM;
 380         }
 381
 382         adapter->rx_ring->buddy = adapter->tx_ring;
 383
 384         for (i = 0; i < adapter->num_tx_queues; i++) {
 385                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 386                 ring->count = adapter->tx_ring_count;
 387                 ring->adapter = adapter;
 388                 ring->queue_index = i;
 389         }
 390         for (i = 0; i < adapter->num_rx_queues; i++) {
 391                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 392                 ring->count = adapter->rx_ring_count;
 393                 ring->adapter = adapter;
 394                 ring->queue_index = i;
 395                 ring->itr_register = E1000_ITR;
 396
 397                 /* set a default napi handler for each rx_ring */
 398                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 399         }
 400
 401         igb_cache_ring_register(adapter);
 402         return 0;
 403 }
 404
 405 static void igb_free_queues(struct igb_adapter *adapter)
 406 {
 407         int i;
 408
 409         for (i = 0; i < adapter->num_rx_queues; i++)
 410                 netif_napi_del(&adapter->rx_ring[i].napi);
 411
 412         kfree(adapter->tx_ring);
 413         kfree(adapter->rx_ring);
 414 }
 415
 416 #define IGB_N0_QUEUE -1
 417 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 418                               int tx_queue, int msix_vector)
 419 {
 420         u32 msixbm = 0;
 421         struct e1000_hw *hw = &adapter->hw;
 422         u32 ivar, index;
 423
 424         switch (hw->mac.type) {
 425         case e1000_82575:
 426                 /* The 82575 assigns vectors using a bitmask, which matches the
 427                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 428                    or more queues to a vector, we write the appropriate bits
 429                    into the MSIXBM register for that vector. */
 430                 if (rx_queue > IGB_N0_QUEUE) {
 431                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 432                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 433                 }
 434                 if (tx_queue > IGB_N0_QUEUE) {
 435                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 436                         adapter->tx_ring[tx_queue].eims_value =
 437                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 438                 }
 439                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 440                 break;
 441         case e1000_82576:
 442                 /* 82576 uses a table-based method for assigning vectors.
 443                    Each queue has a single entry in the table to which we write
 444                    a vector number along with a "valid" bit.  Sadly, the layout
 445                    of the table is somewhat counterintuitive. */
 446                 if (rx_queue > IGB_N0_QUEUE) {
 447                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 448                         ivar = array_rd32(E1000_IVAR0, index);
 449                         if (rx_queue & 0x1) {
 450                                 /* vector goes into third byte of register */
 451                                 ivar = ivar & 0xFF00FFFF;
 452                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 453                         } else {
 454                                 /* vector goes into low byte of register */
 455                                 ivar = ivar & 0xFFFFFF00;
 456                                 ivar |= msix_vector | E1000_IVAR_VALID;
 457                         }
 458                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 459                         array_wr32(E1000_IVAR0, index, ivar);
 460                 }
 461                 if (tx_queue > IGB_N0_QUEUE) {
 462                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 463                         ivar = array_rd32(E1000_IVAR0, index);
 464                         if (tx_queue & 0x1) {
 465                                 /* vector goes into high byte of register */
 466                                 ivar = ivar & 0x00FFFFFF;
 467                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 468                         } else {
 469                                 /* vector goes into second byte of register */
 470                                 ivar = ivar & 0xFFFF00FF;
 471                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 472                         }
 473                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 474                         array_wr32(E1000_IVAR0, index, ivar);
 475                 }
 476                 break;
 477         default:
 478                 BUG();
 479                 break;
 480         }
 481 }
 482
 483 /**
 484  * igb_configure_msix - Configure MSI-X hardware
 485  *
 486  * igb_configure_msix sets up the hardware to properly
 487  * generate MSI-X interrupts.
 488  **/
 489 static void igb_configure_msix(struct igb_adapter *adapter)
 490 {
 491         u32 tmp;
 492         int i, vector = 0;
 493         struct e1000_hw *hw = &adapter->hw;
 494
 495         adapter->eims_enable_mask = 0;
 496         if (hw->mac.type == e1000_82576)
 497                 /* Turn on MSI-X capability first, or our settings
 498                  * won't stick.  And it will take days to debug. */
 499                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 500                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 501                                    E1000_GPIE_NSICR);
 502
 503         for (i = 0; i < adapter->num_tx_queues; i++) {
 504                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 505                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 506                 adapter->eims_enable_mask |= tx_ring->eims_value;
 507                 if (tx_ring->itr_val)
 508                         writel(tx_ring->itr_val,
 509                                hw->hw_addr + tx_ring->itr_register);
 510                 else
 511                         writel(1, hw->hw_addr + tx_ring->itr_register);
 512         }
 513
 514         for (i = 0; i < adapter->num_rx_queues; i++) {
 515                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 516                 rx_ring->buddy = NULL;
 517                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 518                 adapter->eims_enable_mask |= rx_ring->eims_value;
 519                 if (rx_ring->itr_val)
 520                         writel(rx_ring->itr_val,
 521                                hw->hw_addr + rx_ring->itr_register);
 522                 else
 523                         writel(1, hw->hw_addr + rx_ring->itr_register);
 524         }
 525
 526
 527         /* set vector for other causes, i.e. link changes */
 528         switch (hw->mac.type) {
 529         case e1000_82575:
 530                 array_wr32(E1000_MSIXBM(0), vector++,
 531                                       E1000_EIMS_OTHER);
 532
 533                 tmp = rd32(E1000_CTRL_EXT);
 534                 /* enable MSI-X PBA support*/
 535                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 536
 537                 /* Auto-Mask interrupts upon ICR read. */
 538                 tmp |= E1000_CTRL_EXT_EIAME;
 539                 tmp |= E1000_CTRL_EXT_IRCA;
 540
 541                 wr32(E1000_CTRL_EXT, tmp);
 542                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 543                 adapter->eims_other = E1000_EIMS_OTHER;
 544
 545                 break;
 546
 547         case e1000_82576:
 548                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 549                 wr32(E1000_IVAR_MISC, tmp);
 550
 551                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 552                 adapter->eims_other = 1 << (vector - 1);
 553                 break;
 554         default:
 555                 /* do nothing, since nothing else supports MSI-X */
 556                 break;
 557         } /* switch (hw->mac.type) */
 558         wrfl();
 559 }
 560
 561 /**
 562  * igb_request_msix - Initialize MSI-X interrupts
 563  *
 564  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 565  * kernel.
 566  **/
 567 static int igb_request_msix(struct igb_adapter *adapter)
 568 {
 569         struct net_device *netdev = adapter->netdev;
 570         int i, err = 0, vector = 0;
 571
 572         vector = 0;
 573
 574         for (i = 0; i < adapter->num_tx_queues; i++) {
 575                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 576                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 577                 err = request_irq(adapter->msix_entries[vector].vector,
 578                                   &igb_msix_tx, 0, ring->name,
 579                                   &(adapter->tx_ring[i]));
 580                 if (err)
 581                         goto out;
 582                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 583                 ring->itr_val = 976; /* ~4000 ints/sec */
 584                 vector++;
 585         }
 586         for (i = 0; i < adapter->num_rx_queues; i++) {
 587                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 588                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 589                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 590                 else
 591                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 592                 err = request_irq(adapter->msix_entries[vector].vector,
 593                                   &igb_msix_rx, 0, ring->name,
 594                                   &(adapter->rx_ring[i]));
 595                 if (err)
 596                         goto out;
 597                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 598                 ring->itr_val = adapter->itr;
 599                 vector++;
 600         }
 601
 602         err = request_irq(adapter->msix_entries[vector].vector,
 603                           &igb_msix_other, 0, netdev->name, netdev);
 604         if (err)
 605                 goto out;
 606
 607         igb_configure_msix(adapter);
 608         return 0;
 609 out:
 610         return err;
 611 }
 612
 613 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 614 {
 615         if (adapter->msix_entries) {
 616                 pci_disable_msix(adapter->pdev);
 617                 kfree(adapter->msix_entries);
 618                 adapter->msix_entries = NULL;
 619         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 620                 pci_disable_msi(adapter->pdev);
 621         return;
 622 }
 623
 624
 625 /**
 626  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 627  *
 628  * Attempt to configure interrupts using the best available
 629  * capabilities of the hardware and kernel.
 630  **/
 631 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 632 {
 633         int err;
 634         int numvecs, i;
 635
 636         /* Number of supported queues. */
 637         /* Having more queues than CPUs doesn't make sense. */
 638         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 639         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 640
 641         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 642         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 643                                         GFP_KERNEL);
 644         if (!adapter->msix_entries)
 645                 goto msi_only;
 646
 647         for (i = 0; i < numvecs; i++)
 648                 adapter->msix_entries[i].entry = i;
 649
 650         err = pci_enable_msix(adapter->pdev,
 651                               adapter->msix_entries,
 652                               numvecs);
 653         if (err == 0)
 654                 goto out;
 655
 656         igb_reset_interrupt_capability(adapter);
 657
 658         /* If we can't do MSI-X, try MSI */
 659 msi_only:
 660         adapter->num_rx_queues = 1;
 661         adapter->num_tx_queues = 1;
 662         if (!pci_enable_msi(adapter->pdev))
 663                 adapter->flags |= IGB_FLAG_HAS_MSI;
 664 out:
 665         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 666         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 667         return;
 668 }
 669
 670 /**
 671  * igb_request_irq - initialize interrupts
 672  *
 673  * Attempts to configure interrupts using the best available
 674  * capabilities of the hardware and kernel.
 675  **/
 676 static int igb_request_irq(struct igb_adapter *adapter)
 677 {
 678         struct net_device *netdev = adapter->netdev;
 679         struct e1000_hw *hw = &adapter->hw;
 680         int err = 0;
 681
 682         if (adapter->msix_entries) {
 683                 err = igb_request_msix(adapter);
 684                 if (!err)
 685                         goto request_done;
 686                 /* fall back to MSI */
 687                 igb_reset_interrupt_capability(adapter);
 688                 if (!pci_enable_msi(adapter->pdev))
 689                         adapter->flags |= IGB_FLAG_HAS_MSI;
 690                 igb_free_all_tx_resources(adapter);
 691                 igb_free_all_rx_resources(adapter);
 692                 adapter->num_rx_queues = 1;
 693                 igb_alloc_queues(adapter);
 694         } else {
 695                 switch (hw->mac.type) {
 696                 case e1000_82575:
 697                         wr32(E1000_MSIXBM(0),
 698                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 699                         break;
 700                 case e1000_82576:
 701                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 702                         break;
 703                 default:
 704                         break;
 705                 }
 706         }
 707
 708         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 709                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 710                                   netdev->name, netdev);
 711                 if (!err)
 712                         goto request_done;
 713                 /* fall back to legacy interrupts */
 714                 igb_reset_interrupt_capability(adapter);
 715                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 716         }
 717
 718         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 719                           netdev->name, netdev);
 720
 721         if (err)
 722                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 723                         err);
 724
 725 request_done:
 726         return err;
 727 }
 728
 729 static void igb_free_irq(struct igb_adapter *adapter)
 730 {
 731         struct net_device *netdev = adapter->netdev;
 732
 733         if (adapter->msix_entries) {
 734                 int vector = 0, i;
 735
 736                 for (i = 0; i < adapter->num_tx_queues; i++)
 737                         free_irq(adapter->msix_entries[vector++].vector,
 738                                 &(adapter->tx_ring[i]));
 739                 for (i = 0; i < adapter->num_rx_queues; i++)
 740                         free_irq(adapter->msix_entries[vector++].vector,
 741                                 &(adapter->rx_ring[i]));
 742
 743                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 744                 return;
 745         }
 746
 747         free_irq(adapter->pdev->irq, netdev);
 748 }
 749
 750 /**
 751  * igb_irq_disable - Mask off interrupt generation on the NIC
 752  * @adapter: board private structure
 753  **/
 754 static void igb_irq_disable(struct igb_adapter *adapter)
 755 {
 756         struct e1000_hw *hw = &adapter->hw;
 757
 758         if (adapter->msix_entries) {
 759                 wr32(E1000_EIAM, 0);
 760                 wr32(E1000_EIMC, ~0);
 761                 wr32(E1000_EIAC, 0);
 762         }
 763
 764         wr32(E1000_IAM, 0);
 765         wr32(E1000_IMC, ~0);
 766         wrfl();
 767         synchronize_irq(adapter->pdev->irq);
 768 }
 769
 770 /**
 771  * igb_irq_enable - Enable default interrupt generation settings
 772  * @adapter: board private structure
 773  **/
 774 static void igb_irq_enable(struct igb_adapter *adapter)
 775 {
 776         struct e1000_hw *hw = &adapter->hw;
 777
 778         if (adapter->msix_entries) {
 779                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 780                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 781                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 782                 if (adapter->vfs_allocated_count)
 783                         wr32(E1000_MBVFIMR, 0xFF);
 784                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 785                                  E1000_IMS_DOUTSYNC));
 786         } else {
 787                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 788                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 789         }
 790 }
 791
 792 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 793 {
 794         struct net_device *netdev = adapter->netdev;
 795         u16 vid = adapter->hw.mng_cookie.vlan_id;
 796         u16 old_vid = adapter->mng_vlan_id;
 797         if (adapter->vlgrp) {
 798                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 799                         if (adapter->hw.mng_cookie.status &
 800                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 801                                 igb_vlan_rx_add_vid(netdev, vid);
 802                                 adapter->mng_vlan_id = vid;
 803                         } else
 804                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 805
 806                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 807                                         (vid != old_vid) &&
 808                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 809                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 810                 } else
 811                         adapter->mng_vlan_id = vid;
 812         }
 813 }
 814
 815 /**
 816  * igb_release_hw_control - release control of the h/w to f/w
 817  * @adapter: address of board private structure
 818  *
 819  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 820  * For ASF and Pass Through versions of f/w this means that the
 821  * driver is no longer loaded.
 822  *
 823  **/
 824 static void igb_release_hw_control(struct igb_adapter *adapter)
 825 {
 826         struct e1000_hw *hw = &adapter->hw;
 827         u32 ctrl_ext;
 828
 829         /* Let firmware take over control of h/w */
 830         ctrl_ext = rd32(E1000_CTRL_EXT);
 831         wr32(E1000_CTRL_EXT,
 832                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 833 }
 834
 835
 836 /**
 837  * igb_get_hw_control - get control of the h/w from f/w
 838  * @adapter: address of board private structure
 839  *
 840  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 841  * For ASF and Pass Through versions of f/w this means that
 842  * the driver is loaded.
 843  *
 844  **/
 845 static void igb_get_hw_control(struct igb_adapter *adapter)
 846 {
 847         struct e1000_hw *hw = &adapter->hw;
 848         u32 ctrl_ext;
 849
 850         /* Let firmware know the driver has taken over */
 851         ctrl_ext = rd32(E1000_CTRL_EXT);
 852         wr32(E1000_CTRL_EXT,
 853                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 854 }
 855
 856 /**
 857  * igb_configure - configure the hardware for RX and TX
 858  * @adapter: private board structure
 859  **/
 860 static void igb_configure(struct igb_adapter *adapter)
 861 {
 862         struct net_device *netdev = adapter->netdev;
 863         int i;
 864
 865         igb_get_hw_control(adapter);
 866         igb_set_multi(netdev);
 867
 868         igb_restore_vlan(adapter);
 869
 870         igb_configure_tx(adapter);
 871         igb_setup_rctl(adapter);
 872         igb_configure_rx(adapter);
 873
 874         igb_rx_fifo_flush_82575(&adapter->hw);
 875
 876         /* call IGB_DESC_UNUSED which always leaves
 877          * at least 1 descriptor unused to make sure
 878          * next_to_use != next_to_clean */
 879         for (i = 0; i < adapter->num_rx_queues; i++) {
 880                 struct igb_ring *ring = &adapter->rx_ring[i];
 881                 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
 882         }
 883
 884
 885         adapter->tx_queue_len = netdev->tx_queue_len;
 886 }
 887
 888
 889 /**
 890  * igb_up - Open the interface and prepare it to handle traffic
 891  * @adapter: board private structure
 892  **/
 893
 894 int igb_up(struct igb_adapter *adapter)
 895 {
 896         struct e1000_hw *hw = &adapter->hw;
 897         int i;
 898
 899         /* hardware has been reset, we need to reload some things */
 900         igb_configure(adapter);
 901
 902         clear_bit(__IGB_DOWN, &adapter->state);
 903
 904         for (i = 0; i < adapter->num_rx_queues; i++)
 905                 napi_enable(&adapter->rx_ring[i].napi);
 906         if (adapter->msix_entries)
 907                 igb_configure_msix(adapter);
 908
 909         igb_vmm_control(adapter);
 910         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 911         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 912
 913         /* Clear any pending interrupts. */
 914         rd32(E1000_ICR);
 915         igb_irq_enable(adapter);
 916
 917         /* Fire a link change interrupt to start the watchdog. */
 918         wr32(E1000_ICS, E1000_ICS_LSC);
 919         return 0;
 920 }
 921
 922 void igb_down(struct igb_adapter *adapter)
 923 {
 924         struct e1000_hw *hw = &adapter->hw;
 925         struct net_device *netdev = adapter->netdev;
 926         u32 tctl, rctl;
 927         int i;
 928
 929         /* signal that we're down so the interrupt handler does not
 930          * reschedule our watchdog timer */
 931         set_bit(__IGB_DOWN, &adapter->state);
 932
 933         /* disable receives in the hardware */
 934         rctl = rd32(E1000_RCTL);
 935         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
 936         /* flush and sleep below */
 937
 938         netif_tx_stop_all_queues(netdev);
 939
 940         /* disable transmits in the hardware */
 941         tctl = rd32(E1000_TCTL);
 942         tctl &= ~E1000_TCTL_EN;
 943         wr32(E1000_TCTL, tctl);
 944         /* flush both disables and wait for them to finish */
 945         wrfl();
 946         msleep(10);
 947
 948         for (i = 0; i < adapter->num_rx_queues; i++)
 949                 napi_disable(&adapter->rx_ring[i].napi);
 950
 951         igb_irq_disable(adapter);
 952
 953         del_timer_sync(&adapter->watchdog_timer);
 954         del_timer_sync(&adapter->phy_info_timer);
 955
 956         netdev->tx_queue_len = adapter->tx_queue_len;
 957         netif_carrier_off(netdev);
 958
 959         /* record the stats before reset*/
 960         igb_update_stats(adapter);
 961
 962         adapter->link_speed = 0;
 963         adapter->link_duplex = 0;
 964
 965         if (!pci_channel_offline(adapter->pdev))
 966                 igb_reset(adapter);
 967         igb_clean_all_tx_rings(adapter);
 968         igb_clean_all_rx_rings(adapter);
 969 }
 970
 971 void igb_reinit_locked(struct igb_adapter *adapter)
 972 {
 973         WARN_ON(in_interrupt());
 974         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 975                 msleep(1);
 976         igb_down(adapter);
 977         igb_up(adapter);
 978         clear_bit(__IGB_RESETTING, &adapter->state);
 979 }
 980
 981 void igb_reset(struct igb_adapter *adapter)
 982 {
 983         struct e1000_hw *hw = &adapter->hw;
 984         struct e1000_mac_info *mac = &hw->mac;
 985         struct e1000_fc_info *fc = &hw->fc;
 986         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
 987         u16 hwm;
 988
 989         /* Repartition Pba for greater than 9k mtu
 990          * To take effect CTRL.RST is required.
 991          */
 992         switch (mac->type) {
 993         case e1000_82576:
 994                 pba = E1000_PBA_64K;
 995                 break;
 996         case e1000_82575:
 997         default:
 998                 pba = E1000_PBA_34K;
 999                 break;
1000         }
1001
1002         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1003             (mac->type < e1000_82576)) {
1004                 /* adjust PBA for jumbo frames */
1005                 wr32(E1000_PBA, pba);
1006
1007                 /* To maintain wire speed transmits, the Tx FIFO should be
1008                  * large enough to accommodate two full transmit packets,
1009                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1010                  * the Rx FIFO should be large enough to accommodate at least
1011                  * one full receive packet and is similarly rounded up and
1012                  * expressed in KB. */
1013                 pba = rd32(E1000_PBA);
1014                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1015                 tx_space = pba >> 16;
1016                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1017                 pba &= 0xffff;
1018                 /* the tx fifo also stores 16 bytes of information about the tx
1019                  * but don't include ethernet FCS because hardware appends it */
1020                 min_tx_space = (adapter->max_frame_size +
1021                                 sizeof(union e1000_adv_tx_desc) -
1022                                 ETH_FCS_LEN) * 2;
1023                 min_tx_space = ALIGN(min_tx_space, 1024);
1024                 min_tx_space >>= 10;
1025                 /* software strips receive CRC, so leave room for it */
1026                 min_rx_space = adapter->max_frame_size;
1027                 min_rx_space = ALIGN(min_rx_space, 1024);
1028                 min_rx_space >>= 10;
1029
1030                 /* If current Tx allocation is less than the min Tx FIFO size,
1031                  * and the min Tx FIFO size is less than the current Rx FIFO
1032                  * allocation, take space away from current Rx allocation */
1033                 if (tx_space < min_tx_space &&
1034                     ((min_tx_space - tx_space) < pba)) {
1035                         pba = pba - (min_tx_space - tx_space);
1036
1037                         /* if short on rx space, rx wins and must trump tx
1038                          * adjustment */
1039                         if (pba < min_rx_space)
1040                                 pba = min_rx_space;
1041                 }
1042                 wr32(E1000_PBA, pba);
1043         }
1044
1045         /* flow control settings */
1046         /* The high water mark must be low enough to fit one full frame
1047          * (or the size used for early receive) above it in the Rx FIFO.
1048          * Set it to the lower of:
1049          * - 90% of the Rx FIFO size, or
1050          * - the full Rx FIFO size minus one full frame */
1051         hwm = min(((pba << 10) * 9 / 10),
1052                         ((pba << 10) - 2 * adapter->max_frame_size));
1053
1054         if (mac->type < e1000_82576) {
1055                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1056                 fc->low_water = fc->high_water - 8;
1057         } else {
1058                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1059                 fc->low_water = fc->high_water - 16;
1060         }
1061         fc->pause_time = 0xFFFF;
1062         fc->send_xon = 1;
1063         fc->type = fc->original_type;
1064
1065         /* disable receive for all VFs and wait one second */
1066         if (adapter->vfs_allocated_count) {
1067                 int i;
1068                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1069                         adapter->vf_data[i].clear_to_send = false;
1070
1071                 /* ping all the active vfs to let them know we are going down */
1072                         igb_ping_all_vfs(adapter);
1073
1074                 /* disable transmits and receives */
1075                 wr32(E1000_VFRE, 0);
1076                 wr32(E1000_VFTE, 0);
1077         }
1078
1079         /* Allow time for pending master requests to run */
1080         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1081         wr32(E1000_WUC, 0);
1082
1083         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1084                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1085
1086         igb_update_mng_vlan(adapter);
1087
1088         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1089         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1090
1091         igb_reset_adaptive(&adapter->hw);
1092         igb_get_phy_info(&adapter->hw);
1093 }
1094
1095 static const struct net_device_ops igb_netdev_ops = {
1096         .ndo_open               = igb_open,
1097         .ndo_stop               = igb_close,
1098         .ndo_start_xmit         = igb_xmit_frame_adv,
1099         .ndo_get_stats          = igb_get_stats,
1100         .ndo_set_multicast_list = igb_set_multi,
1101         .ndo_set_mac_address    = igb_set_mac,
1102         .ndo_change_mtu         = igb_change_mtu,
1103         .ndo_do_ioctl           = igb_ioctl,
1104         .ndo_tx_timeout         = igb_tx_timeout,
1105         .ndo_validate_addr      = eth_validate_addr,
1106         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1107         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1108         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1109 #ifdef CONFIG_NET_POLL_CONTROLLER
1110         .ndo_poll_controller    = igb_netpoll,
1111 #endif
1112 };
1113
1114 /**
1115  * igb_probe - Device Initialization Routine
1116  * @pdev: PCI device information struct
1117  * @ent: entry in igb_pci_tbl
1118  *
1119  * Returns 0 on success, negative on failure
1120  *
1121  * igb_probe initializes an adapter identified by a pci_dev structure.
1122  * The OS initialization, configuring of the adapter private structure,
1123  * and a hardware reset occur.
1124  **/
1125 static int __devinit igb_probe(struct pci_dev *pdev,
1126                                const struct pci_device_id *ent)
1127 {
1128         struct net_device *netdev;
1129         struct igb_adapter *adapter;
1130         struct e1000_hw *hw;
1131         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1132         unsigned long mmio_start, mmio_len;
1133         int err, pci_using_dac;
1134         u16 eeprom_data = 0;
1135         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1136         u32 part_num;
1137
1138         err = pci_enable_device_mem(pdev);
1139         if (err)
1140                 return err;
1141
1142         pci_using_dac = 0;
1143         err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1144         if (!err) {
1145                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1146                 if (!err)
1147                         pci_using_dac = 1;
1148         } else {
1149                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1150                 if (err) {
1151                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1152                         if (err) {
1153                                 dev_err(&pdev->dev, "No usable DMA "
1154                                         "configuration, aborting\n");
1155                                 goto err_dma;
1156                         }
1157                 }
1158         }
1159
1160         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1161                                            IORESOURCE_MEM),
1162                                            igb_driver_name);
1163         if (err)
1164                 goto err_pci_reg;
1165
1166         err = pci_enable_pcie_error_reporting(pdev);
1167         if (err) {
1168                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1169                         "0x%x\n", err);
1170                 /* non-fatal, continue */
1171         }
1172
1173         pci_set_master(pdev);
1174         pci_save_state(pdev);
1175
1176         err = -ENOMEM;
1177         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1178                                    IGB_ABS_MAX_TX_QUEUES);
1179         if (!netdev)
1180                 goto err_alloc_etherdev;
1181
1182         SET_NETDEV_DEV(netdev, &pdev->dev);
1183
1184         pci_set_drvdata(pdev, netdev);
1185         adapter = netdev_priv(netdev);
1186         adapter->netdev = netdev;
1187         adapter->pdev = pdev;
1188         hw = &adapter->hw;
1189         hw->back = adapter;
1190         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1191
1192         mmio_start = pci_resource_start(pdev, 0);
1193         mmio_len = pci_resource_len(pdev, 0);
1194
1195         err = -EIO;
1196         hw->hw_addr = ioremap(mmio_start, mmio_len);
1197         if (!hw->hw_addr)
1198                 goto err_ioremap;
1199
1200         netdev->netdev_ops = &igb_netdev_ops;
1201         igb_set_ethtool_ops(netdev);
1202         netdev->watchdog_timeo = 5 * HZ;
1203
1204         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1205
1206         netdev->mem_start = mmio_start;
1207         netdev->mem_end = mmio_start + mmio_len;
1208
1209         /* PCI config space info */
1210         hw->vendor_id = pdev->vendor;
1211         hw->device_id = pdev->device;
1212         hw->revision_id = pdev->revision;
1213         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1214         hw->subsystem_device_id = pdev->subsystem_device;
1215
1216         /* setup the private structure */
1217         hw->back = adapter;
1218         /* Copy the default MAC, PHY and NVM function pointers */
1219         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1220         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1221         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1222         /* Initialize skew-specific constants */
1223         err = ei->get_invariants(hw);
1224         if (err)
1225                 goto err_sw_init;
1226
1227         /* setup the private structure */
1228         err = igb_sw_init(adapter);
1229         if (err)
1230                 goto err_sw_init;
1231
1232         igb_get_bus_info_pcie(hw);
1233
1234         /* set flags */
1235         switch (hw->mac.type) {
1236         case e1000_82575:
1237                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1238                 break;
1239         case e1000_82576:
1240         default:
1241                 break;
1242         }
1243
1244         hw->phy.autoneg_wait_to_complete = false;
1245         hw->mac.adaptive_ifs = true;
1246
1247         /* Copper options */
1248         if (hw->phy.media_type == e1000_media_type_copper) {
1249                 hw->phy.mdix = AUTO_ALL_MODES;
1250                 hw->phy.disable_polarity_correction = false;
1251                 hw->phy.ms_type = e1000_ms_hw_default;
1252         }
1253
1254         if (igb_check_reset_block(hw))
1255                 dev_info(&pdev->dev,
1256                         "PHY reset is blocked due to SOL/IDER session.\n");
1257
1258         netdev->features = NETIF_F_SG |
1259                            NETIF_F_IP_CSUM |
1260                            NETIF_F_HW_VLAN_TX |
1261                            NETIF_F_HW_VLAN_RX |
1262                            NETIF_F_HW_VLAN_FILTER;
1263
1264         netdev->features |= NETIF_F_IPV6_CSUM;
1265         netdev->features |= NETIF_F_TSO;
1266         netdev->features |= NETIF_F_TSO6;
1267
1268         netdev->features |= NETIF_F_GRO;
1269
1270         netdev->vlan_features |= NETIF_F_TSO;
1271         netdev->vlan_features |= NETIF_F_TSO6;
1272         netdev->vlan_features |= NETIF_F_IP_CSUM;
1273         netdev->vlan_features |= NETIF_F_SG;
1274
1275         if (pci_using_dac)
1276                 netdev->features |= NETIF_F_HIGHDMA;
1277
1278         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1279
1280         /* before reading the NVM, reset the controller to put the device in a
1281          * known good starting state */
1282         hw->mac.ops.reset_hw(hw);
1283
1284         /* make sure the NVM is good */
1285         if (igb_validate_nvm_checksum(hw) < 0) {
1286                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1287                 err = -EIO;
1288                 goto err_eeprom;
1289         }
1290
1291         /* copy the MAC address out of the NVM */
1292         if (hw->mac.ops.read_mac_addr(hw))
1293                 dev_err(&pdev->dev, "NVM Read Error\n");
1294
1295         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1296         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1297
1298         if (!is_valid_ether_addr(netdev->perm_addr)) {
1299                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1300                 err = -EIO;
1301                 goto err_eeprom;
1302         }
1303
1304         init_timer(&adapter->watchdog_timer);
1305         adapter->watchdog_timer.function = &igb_watchdog;
1306         adapter->watchdog_timer.data = (unsigned long) adapter;
1307
1308         init_timer(&adapter->phy_info_timer);
1309         adapter->phy_info_timer.function = &igb_update_phy_info;
1310         adapter->phy_info_timer.data = (unsigned long) adapter;
1311
1312         INIT_WORK(&adapter->reset_task, igb_reset_task);
1313         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1314
1315         /* Initialize link properties that are user-changeable */
1316         adapter->fc_autoneg = true;
1317         hw->mac.autoneg = true;
1318         hw->phy.autoneg_advertised = 0x2f;
1319
1320         hw->fc.original_type = e1000_fc_default;
1321         hw->fc.type = e1000_fc_default;
1322
1323         adapter->itr_setting = IGB_DEFAULT_ITR;
1324         adapter->itr = IGB_START_ITR;
1325
1326         igb_validate_mdi_setting(hw);
1327
1328         adapter->rx_csum = 1;
1329
1330         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1331          * enable the ACPI Magic Packet filter
1332          */
1333
1334         if (hw->bus.func == 0)
1335                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1336         else if (hw->bus.func == 1)
1337                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1338
1339         if (eeprom_data & eeprom_apme_mask)
1340                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1341
1342         /* now that we have the eeprom settings, apply the special cases where
1343          * the eeprom may be wrong or the board simply won't support wake on
1344          * lan on a particular port */
1345         switch (pdev->device) {
1346         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1347                 adapter->eeprom_wol = 0;
1348                 break;
1349         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1350         case E1000_DEV_ID_82576_FIBER:
1351         case E1000_DEV_ID_82576_SERDES:
1352                 /* Wake events only supported on port A for dual fiber
1353                  * regardless of eeprom setting */
1354                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1355                         adapter->eeprom_wol = 0;
1356                 break;
1357         case E1000_DEV_ID_82576_QUAD_COPPER:
1358                 /* if quad port adapter, disable WoL on all but port A */
1359                 if (global_quad_port_a != 0)
1360                         adapter->eeprom_wol = 0;
1361                 else
1362                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1363                 /* Reset for multiple quad port adapters */
1364                 if (++global_quad_port_a == 4)
1365                         global_quad_port_a = 0;
1366                 break;
1367         }
1368
1369         /* initialize the wol settings based on the eeprom settings */
1370         adapter->wol = adapter->eeprom_wol;
1371         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1372
1373         /* reset the hardware with the new settings */
1374         igb_reset(adapter);
1375
1376         /* let the f/w know that the h/w is now under the control of the
1377          * driver. */
1378         igb_get_hw_control(adapter);
1379
1380         /* tell the stack to leave us alone until igb_open() is called */
1381         netif_carrier_off(netdev);
1382         netif_tx_stop_all_queues(netdev);
1383
1384         strcpy(netdev->name, "eth%d");
1385         err = register_netdev(netdev);
1386         if (err)
1387                 goto err_register;
1388
1389 #ifdef CONFIG_PCI_IOV
1390         /* since iov functionality isn't critical to base device function we
1391          * can accept failure.  If it fails we don't allow iov to be enabled */
1392         if (hw->mac.type == e1000_82576) {
1393                 err = pci_enable_sriov(pdev, 0);
1394                 if (!err)
1395                         err = device_create_file(&netdev->dev,
1396                                                  &dev_attr_num_vfs);
1397                 if (err)
1398                         dev_err(&pdev->dev, "Failed to initialize IOV\n");
1399         }
1400
1401 #endif
1402 #ifdef CONFIG_IGB_DCA
1403         if (dca_add_requester(&pdev->dev) == 0) {
1404                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1405                 dev_info(&pdev->dev, "DCA enabled\n");
1406                 /* Always use CB2 mode, difference is masked
1407                  * in the CB driver. */
1408                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
1409                 igb_setup_dca(adapter);
1410         }
1411 #endif
1412
1413         /*
1414          * Initialize hardware timer: we keep it running just in case
1415          * that some program needs it later on.
1416          */
1417         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1418         adapter->cycles.read = igb_read_clock;
1419         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1420         adapter->cycles.mult = 1;
1421         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1422         wr32(E1000_TIMINCA,
1423              (1<<24) |
1424              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1425 #if 0
1426         /*
1427          * Avoid rollover while we initialize by resetting the time counter.
1428          */
1429         wr32(E1000_SYSTIML, 0x00000000);
1430         wr32(E1000_SYSTIMH, 0x00000000);
1431 #else
1432         /*
1433          * Set registers so that rollover occurs soon to test this.
1434          */
1435         wr32(E1000_SYSTIML, 0x00000000);
1436         wr32(E1000_SYSTIMH, 0xFF800000);
1437 #endif
1438         wrfl();
1439         timecounter_init(&adapter->clock,
1440                          &adapter->cycles,
1441                          ktime_to_ns(ktime_get_real()));
1442
1443         /*
1444          * Synchronize our NIC clock against system wall clock. NIC
1445          * time stamp reading requires ~3us per sample, each sample
1446          * was pretty stable even under load => only require 10
1447          * samples for each offset comparison.
1448          */
1449         memset(&adapter->compare, 0, sizeof(adapter->compare));
1450         adapter->compare.source = &adapter->clock;
1451         adapter->compare.target = ktime_get_real;
1452         adapter->compare.num_samples = 10;
1453         timecompare_update(&adapter->compare, 0);
1454
1455 #ifdef DEBUG
1456         {
1457                 char buffer[160];
1458                 printk(KERN_DEBUG
1459                         "igb: %s: hw %p initialized timer\n",
1460                         igb_get_time_str(adapter, buffer),
1461                         &adapter->hw);
1462         }
1463 #endif
1464
1465         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1466         /* print bus type/speed/width info */
1467         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1468                  netdev->name,
1469                  ((hw->bus.speed == e1000_bus_speed_2500)
1470                   ? "2.5Gb/s" : "unknown"),
1471                  ((hw->bus.width == e1000_bus_width_pcie_x4)
1472                   ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1473                   ? "Width x1" : "unknown"),
1474                  netdev->dev_addr);
1475
1476         igb_read_part_num(hw, &part_num);
1477         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1478                 (part_num >> 8), (part_num & 0xff));
1479
1480         dev_info(&pdev->dev,
1481                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1482                 adapter->msix_entries ? "MSI-X" :
1483                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1484                 adapter->num_rx_queues, adapter->num_tx_queues);
1485
1486         return 0;
1487
1488 err_register:
1489         igb_release_hw_control(adapter);
1490 err_eeprom:
1491         if (!igb_check_reset_block(hw))
1492                 igb_reset_phy(hw);
1493
1494         if (hw->flash_address)
1495                 iounmap(hw->flash_address);
1496
1497         igb_free_queues(adapter);
1498 err_sw_init:
1499         iounmap(hw->hw_addr);
1500 err_ioremap:
1501         free_netdev(netdev);
1502 err_alloc_etherdev:
1503         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1504                                      IORESOURCE_MEM));
1505 err_pci_reg:
1506 err_dma:
1507         pci_disable_device(pdev);
1508         return err;
1509 }
1510
1511 /**
1512  * igb_remove - Device Removal Routine
1513  * @pdev: PCI device information struct
1514  *
1515  * igb_remove is called by the PCI subsystem to alert the driver
1516  * that it should release a PCI device.  The could be caused by a
1517  * Hot-Plug event, or because the driver is going to be removed from
1518  * memory.
1519  **/
1520 static void __devexit igb_remove(struct pci_dev *pdev)
1521 {
1522         struct net_device *netdev = pci_get_drvdata(pdev);
1523         struct igb_adapter *adapter = netdev_priv(netdev);
1524         struct e1000_hw *hw = &adapter->hw;
1525         int err;
1526
1527         /* flush_scheduled work may reschedule our watchdog task, so
1528          * explicitly disable watchdog tasks from being rescheduled  */
1529         set_bit(__IGB_DOWN, &adapter->state);
1530         del_timer_sync(&adapter->watchdog_timer);
1531         del_timer_sync(&adapter->phy_info_timer);
1532
1533         flush_scheduled_work();
1534
1535 #ifdef CONFIG_IGB_DCA
1536         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1537                 dev_info(&pdev->dev, "DCA disabled\n");
1538                 dca_remove_requester(&pdev->dev);
1539                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1540                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1541         }
1542 #endif
1543
1544         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1545          * would have already happened in close and is redundant. */
1546         igb_release_hw_control(adapter);
1547
1548         unregister_netdev(netdev);
1549
1550         if (!igb_check_reset_block(&adapter->hw))
1551                 igb_reset_phy(&adapter->hw);
1552
1553         igb_reset_interrupt_capability(adapter);
1554
1555         igb_free_queues(adapter);
1556
1557 #ifdef CONFIG_PCI_IOV
1558         /* reclaim resources allocated to VFs */
1559         if (adapter->vf_data) {
1560                 /* disable iov and allow time for transactions to clear */
1561                 pci_disable_sriov(pdev);
1562                 msleep(500);
1563
1564                 kfree(adapter->vf_data);
1565                 adapter->vf_data = NULL;
1566                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1567                 msleep(100);
1568                 dev_info(&pdev->dev, "IOV Disabled\n");
1569         }
1570 #endif
1571         iounmap(hw->hw_addr);
1572         if (hw->flash_address)
1573                 iounmap(hw->flash_address);
1574         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1575                                      IORESOURCE_MEM));
1576
1577         free_netdev(netdev);
1578
1579         err = pci_disable_pcie_error_reporting(pdev);
1580         if (err)
1581                 dev_err(&pdev->dev,
1582                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1583
1584         pci_disable_device(pdev);
1585 }
1586
1587 /**
1588  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1589  * @adapter: board private structure to initialize
1590  *
1591  * igb_sw_init initializes the Adapter private data structure.
1592  * Fields are initialized based on PCI device information and
1593  * OS network device settings (MTU size).
1594  **/
1595 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1596 {
1597         struct e1000_hw *hw = &adapter->hw;
1598         struct net_device *netdev = adapter->netdev;
1599         struct pci_dev *pdev = adapter->pdev;
1600
1601         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1602
1603         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1604         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1605         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1606         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1607         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1608         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1609
1610         /* This call may decrease the number of queues depending on
1611          * interrupt mode. */
1612         igb_set_interrupt_capability(adapter);
1613
1614         if (igb_alloc_queues(adapter)) {
1615                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1616                 return -ENOMEM;
1617         }
1618
1619         /* Explicitly disable IRQ since the NIC can be in any state. */
1620         igb_irq_disable(adapter);
1621
1622         set_bit(__IGB_DOWN, &adapter->state);
1623         return 0;
1624 }
1625
1626 /**
1627  * igb_open - Called when a network interface is made active
1628  * @netdev: network interface device structure
1629  *
1630  * Returns 0 on success, negative value on failure
1631  *
1632  * The open entry point is called when a network interface is made
1633  * active by the system (IFF_UP).  At this point all resources needed
1634  * for transmit and receive operations are allocated, the interrupt
1635  * handler is registered with the OS, the watchdog timer is started,
1636  * and the stack is notified that the interface is ready.
1637  **/
1638 static int igb_open(struct net_device *netdev)
1639 {
1640         struct igb_adapter *adapter = netdev_priv(netdev);
1641         struct e1000_hw *hw = &adapter->hw;
1642         int err;
1643         int i;
1644
1645         /* disallow open during test */
1646         if (test_bit(__IGB_TESTING, &adapter->state))
1647                 return -EBUSY;
1648
1649         /* allocate transmit descriptors */
1650         err = igb_setup_all_tx_resources(adapter);
1651         if (err)
1652                 goto err_setup_tx;
1653
1654         /* allocate receive descriptors */
1655         err = igb_setup_all_rx_resources(adapter);
1656         if (err)
1657                 goto err_setup_rx;
1658
1659         /* e1000_power_up_phy(adapter); */
1660
1661         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1662         if ((adapter->hw.mng_cookie.status &
1663              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1664                 igb_update_mng_vlan(adapter);
1665
1666         /* before we allocate an interrupt, we must be ready to handle it.
1667          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1668          * as soon as we call pci_request_irq, so we have to setup our
1669          * clean_rx handler before we do so.  */
1670         igb_configure(adapter);
1671
1672         igb_vmm_control(adapter);
1673         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1674         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1675
1676         err = igb_request_irq(adapter);
1677         if (err)
1678                 goto err_req_irq;
1679
1680         /* From here on the code is the same as igb_up() */
1681         clear_bit(__IGB_DOWN, &adapter->state);
1682
1683         for (i = 0; i < adapter->num_rx_queues; i++)
1684                 napi_enable(&adapter->rx_ring[i].napi);
1685
1686         /* Clear any pending interrupts. */
1687         rd32(E1000_ICR);
1688
1689         igb_irq_enable(adapter);
1690
1691         netif_tx_start_all_queues(netdev);
1692
1693         /* Fire a link status change interrupt to start the watchdog. */
1694         wr32(E1000_ICS, E1000_ICS_LSC);
1695
1696         return 0;
1697
1698 err_req_irq:
1699         igb_release_hw_control(adapter);
1700         /* e1000_power_down_phy(adapter); */
1701         igb_free_all_rx_resources(adapter);
1702 err_setup_rx:
1703         igb_free_all_tx_resources(adapter);
1704 err_setup_tx:
1705         igb_reset(adapter);
1706
1707         return err;
1708 }
1709
1710 /**
1711  * igb_close - Disables a network interface
1712  * @netdev: network interface device structure
1713  *
1714  * Returns 0, this is not allowed to fail
1715  *
1716  * The close entry point is called when an interface is de-activated
1717  * by the OS.  The hardware is still under the driver's control, but
1718  * needs to be disabled.  A global MAC reset is issued to stop the
1719  * hardware, and all transmit and receive resources are freed.
1720  **/
1721 static int igb_close(struct net_device *netdev)
1722 {
1723         struct igb_adapter *adapter = netdev_priv(netdev);
1724
1725         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1726         igb_down(adapter);
1727
1728         igb_free_irq(adapter);
1729
1730         igb_free_all_tx_resources(adapter);
1731         igb_free_all_rx_resources(adapter);
1732
1733         /* kill manageability vlan ID if supported, but not if a vlan with
1734          * the same ID is registered on the host OS (let 8021q kill it) */
1735         if ((adapter->hw.mng_cookie.status &
1736                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1737              !(adapter->vlgrp &&
1738                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1739                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1740
1741         return 0;
1742 }
1743
1744 /**
1745  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1746  * @adapter: board private structure
1747  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1748  *
1749  * Return 0 on success, negative on failure
1750  **/
1751 int igb_setup_tx_resources(struct igb_adapter *adapter,
1752                            struct igb_ring *tx_ring)
1753 {
1754         struct pci_dev *pdev = adapter->pdev;
1755         int size;
1756
1757         size = sizeof(struct igb_buffer) * tx_ring->count;
1758         tx_ring->buffer_info = vmalloc(size);
1759         if (!tx_ring->buffer_info)
1760                 goto err;
1761         memset(tx_ring->buffer_info, 0, size);
1762
1763         /* round up to nearest 4K */
1764         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1765         tx_ring->size = ALIGN(tx_ring->size, 4096);
1766
1767         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1768                                              &tx_ring->dma);
1769
1770         if (!tx_ring->desc)
1771                 goto err;
1772
1773         tx_ring->adapter = adapter;
1774         tx_ring->next_to_use = 0;
1775         tx_ring->next_to_clean = 0;
1776         return 0;
1777
1778 err:
1779         vfree(tx_ring->buffer_info);
1780         dev_err(&adapter->pdev->dev,
1781                 "Unable to allocate memory for the transmit descriptor ring\n");
1782         return -ENOMEM;
1783 }
1784
1785 /**
1786  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1787  *                                (Descriptors) for all queues
1788  * @adapter: board private structure
1789  *
1790  * Return 0 on success, negative on failure
1791  **/
1792 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1793 {
1794         int i, err = 0;
1795         int r_idx;
1796
1797         for (i = 0; i < adapter->num_tx_queues; i++) {
1798                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1799                 if (err) {
1800                         dev_err(&adapter->pdev->dev,
1801                                 "Allocation for Tx Queue %u failed\n", i);
1802                         for (i--; i >= 0; i--)
1803                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1804                         break;
1805                 }
1806         }
1807
1808         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1809                 r_idx = i % adapter->num_tx_queues;
1810                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1811         }
1812         return err;
1813 }
1814
1815 /**
1816  * igb_configure_tx - Configure transmit Unit after Reset
1817  * @adapter: board private structure
1818  *
1819  * Configure the Tx unit of the MAC after a reset.
1820  **/
1821 static void igb_configure_tx(struct igb_adapter *adapter)
1822 {
1823         u64 tdba;
1824         struct e1000_hw *hw = &adapter->hw;
1825         u32 tctl;
1826         u32 txdctl, txctrl;
1827         int i, j;
1828
1829         for (i = 0; i < adapter->num_tx_queues; i++) {
1830                 struct igb_ring *ring = &adapter->tx_ring[i];
1831                 j = ring->reg_idx;
1832                 wr32(E1000_TDLEN(j),
1833                      ring->count * sizeof(union e1000_adv_tx_desc));
1834                 tdba = ring->dma;
1835                 wr32(E1000_TDBAL(j),
1836                      tdba & 0x00000000ffffffffULL);
1837                 wr32(E1000_TDBAH(j), tdba >> 32);
1838
1839                 ring->head = E1000_TDH(j);
1840                 ring->tail = E1000_TDT(j);
1841                 writel(0, hw->hw_addr + ring->tail);
1842                 writel(0, hw->hw_addr + ring->head);
1843                 txdctl = rd32(E1000_TXDCTL(j));
1844                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1845                 wr32(E1000_TXDCTL(j), txdctl);
1846
1847                 /* Turn off Relaxed Ordering on head write-backs.  The
1848                  * writebacks MUST be delivered in order or it will
1849                  * completely screw up our bookeeping.
1850                  */
1851                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1852                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1853                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1854         }
1855
1856         /* disable queue 0 to prevent tail bump w/o re-configuration */
1857         if (adapter->vfs_allocated_count)
1858                 wr32(E1000_TXDCTL(0), 0);
1859
1860         /* Program the Transmit Control Register */
1861         tctl = rd32(E1000_TCTL);
1862         tctl &= ~E1000_TCTL_CT;
1863         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1864                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1865
1866         igb_config_collision_dist(hw);
1867
1868         /* Setup Transmit Descriptor Settings for eop descriptor */
1869         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1870
1871         /* Enable transmits */
1872         tctl |= E1000_TCTL_EN;
1873
1874         wr32(E1000_TCTL, tctl);
1875 }
1876
1877 /**
1878  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1879  * @adapter: board private structure
1880  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1881  *
1882  * Returns 0 on success, negative on failure
1883  **/
1884 int igb_setup_rx_resources(struct igb_adapter *adapter,
1885                            struct igb_ring *rx_ring)
1886 {
1887         struct pci_dev *pdev = adapter->pdev;
1888         int size, desc_len;
1889
1890         size = sizeof(struct igb_buffer) * rx_ring->count;
1891         rx_ring->buffer_info = vmalloc(size);
1892         if (!rx_ring->buffer_info)
1893                 goto err;
1894         memset(rx_ring->buffer_info, 0, size);
1895
1896         desc_len = sizeof(union e1000_adv_rx_desc);
1897
1898         /* Round up to nearest 4K */
1899         rx_ring->size = rx_ring->count * desc_len;
1900         rx_ring->size = ALIGN(rx_ring->size, 4096);
1901
1902         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1903                                              &rx_ring->dma);
1904
1905         if (!rx_ring->desc)
1906                 goto err;
1907
1908         rx_ring->next_to_clean = 0;
1909         rx_ring->next_to_use = 0;
1910
1911         rx_ring->adapter = adapter;
1912
1913         return 0;
1914
1915 err:
1916         vfree(rx_ring->buffer_info);
1917         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1918                 "the receive descriptor ring\n");
1919         return -ENOMEM;
1920 }
1921
1922 /**
1923  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1924  *                                (Descriptors) for all queues
1925  * @adapter: board private structure
1926  *
1927  * Return 0 on success, negative on failure
1928  **/
1929 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1930 {
1931         int i, err = 0;
1932
1933         for (i = 0; i < adapter->num_rx_queues; i++) {
1934                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1935                 if (err) {
1936                         dev_err(&adapter->pdev->dev,
1937                                 "Allocation for Rx Queue %u failed\n", i);
1938                         for (i--; i >= 0; i--)
1939                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1940                         break;
1941                 }
1942         }
1943
1944         return err;
1945 }
1946
1947 /**
1948  * igb_setup_rctl - configure the receive control registers
1949  * @adapter: Board private structure
1950  **/
1951 static void igb_setup_rctl(struct igb_adapter *adapter)
1952 {
1953         struct e1000_hw *hw = &adapter->hw;
1954         u32 rctl;
1955         u32 srrctl = 0;
1956         int i, j;
1957
1958         rctl = rd32(E1000_RCTL);
1959
1960         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1961         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1962
1963         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1964                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1965
1966         /*
1967          * enable stripping of CRC. It's unlikely this will break BMC
1968          * redirection as it did with e1000. Newer features require
1969          * that the HW strips the CRC.
1970          */
1971         rctl |= E1000_RCTL_SECRC;
1972
1973         /*
1974          * disable store bad packets and clear size bits.
1975          */
1976         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
1977
1978         /* enable LPE when to prevent packets larger than max_frame_size */
1979                 rctl |= E1000_RCTL_LPE;
1980
1981         /* Setup buffer sizes */
1982         switch (adapter->rx_buffer_len) {
1983         case IGB_RXBUFFER_256:
1984                 rctl |= E1000_RCTL_SZ_256;
1985                 break;
1986         case IGB_RXBUFFER_512:
1987                 rctl |= E1000_RCTL_SZ_512;
1988                 break;
1989         default:
1990                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1991                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1992                 break;
1993         }
1994
1995         /* 82575 and greater support packet-split where the protocol
1996          * header is placed in skb->data and the packet data is
1997          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1998          * In the case of a non-split, skb->data is linearly filled,
1999          * followed by the page buffers.  Therefore, skb->data is
2000          * sized to hold the largest protocol header.
2001          */
2002         /* allocations using alloc_page take too long for regular MTU
2003          * so only enable packet split for jumbo frames */
2004         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2005                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2006                 srrctl |= adapter->rx_ps_hdr_size <<
2007                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2008                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2009         } else {
2010                 adapter->rx_ps_hdr_size = 0;
2011                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2012         }
2013
2014         /* Attention!!!  For SR-IOV PF driver operations you must enable
2015          * queue drop for all VF and PF queues to prevent head of line blocking
2016          * if an un-trusted VF does not provide descriptors to hardware.
2017          */
2018         if (adapter->vfs_allocated_count) {
2019                 u32 vmolr;
2020
2021                 j = adapter->rx_ring[0].reg_idx;
2022
2023                 /* set all queue drop enable bits */
2024                 wr32(E1000_QDE, ALL_QUEUES);
2025                 srrctl |= E1000_SRRCTL_DROP_EN;
2026
2027                 /* disable queue 0 to prevent tail write w/o re-config */
2028                 wr32(E1000_RXDCTL(0), 0);
2029
2030                 vmolr = rd32(E1000_VMOLR(j));
2031                 if (rctl & E1000_RCTL_LPE)
2032                         vmolr |= E1000_VMOLR_LPE;
2033                 if (adapter->num_rx_queues > 0)
2034                         vmolr |= E1000_VMOLR_RSSE;
2035                 wr32(E1000_VMOLR(j), vmolr);
2036         }
2037
2038         for (i = 0; i < adapter->num_rx_queues; i++) {
2039                 j = adapter->rx_ring[i].reg_idx;
2040                 wr32(E1000_SRRCTL(j), srrctl);
2041         }
2042
2043         wr32(E1000_RCTL, rctl);
2044 }
2045
2046 /**
2047  * igb_rlpml_set - set maximum receive packet size
2048  * @adapter: board private structure
2049  *
2050  * Configure maximum receivable packet size.
2051  **/
2052 static void igb_rlpml_set(struct igb_adapter *adapter)
2053 {
2054         u32 max_frame_size = adapter->max_frame_size;
2055         struct e1000_hw *hw = &adapter->hw;
2056         u16 pf_id = adapter->vfs_allocated_count;
2057
2058         if (adapter->vlgrp)
2059                 max_frame_size += VLAN_TAG_SIZE;
2060
2061         /* if vfs are enabled we set RLPML to the largest possible request
2062          * size and set the VMOLR RLPML to the size we need */
2063         if (pf_id) {
2064                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2065                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2066         }
2067
2068         wr32(E1000_RLPML, max_frame_size);
2069 }
2070
2071 /**
2072  * igb_configure_vt_default_pool - Configure VT default pool
2073  * @adapter: board private structure
2074  *
2075  * Configure the default pool
2076  **/
2077 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2078 {
2079         struct e1000_hw *hw = &adapter->hw;
2080         u16 pf_id = adapter->vfs_allocated_count;
2081         u32 vtctl;
2082
2083         /* not in sr-iov mode - do nothing */
2084         if (!pf_id)
2085                 return;
2086
2087         vtctl = rd32(E1000_VT_CTL);
2088         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2089                    E1000_VT_CTL_DISABLE_DEF_POOL);
2090         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2091         wr32(E1000_VT_CTL, vtctl);
2092 }
2093
2094 /**
2095  * igb_configure_rx - Configure receive Unit after Reset
2096  * @adapter: board private structure
2097  *
2098  * Configure the Rx unit of the MAC after a reset.
2099  **/
2100 static void igb_configure_rx(struct igb_adapter *adapter)
2101 {
2102         u64 rdba;
2103         struct e1000_hw *hw = &adapter->hw;
2104         u32 rctl, rxcsum;
2105         u32 rxdctl;
2106         int i;
2107
2108         /* disable receives while setting up the descriptors */
2109         rctl = rd32(E1000_RCTL);
2110         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2111         wrfl();
2112         mdelay(10);
2113
2114         if (adapter->itr_setting > 3)
2115                 wr32(E1000_ITR, adapter->itr);
2116
2117         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2118          * the Base and Length of the Rx Descriptor Ring */
2119         for (i = 0; i < adapter->num_rx_queues; i++) {
2120                 struct igb_ring *ring = &adapter->rx_ring[i];
2121                 int j = ring->reg_idx;
2122                 rdba = ring->dma;
2123                 wr32(E1000_RDBAL(j),
2124                      rdba & 0x00000000ffffffffULL);
2125                 wr32(E1000_RDBAH(j), rdba >> 32);
2126                 wr32(E1000_RDLEN(j),
2127                      ring->count * sizeof(union e1000_adv_rx_desc));
2128
2129                 ring->head = E1000_RDH(j);
2130                 ring->tail = E1000_RDT(j);
2131                 writel(0, hw->hw_addr + ring->tail);
2132                 writel(0, hw->hw_addr + ring->head);
2133
2134                 rxdctl = rd32(E1000_RXDCTL(j));
2135                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2136                 rxdctl &= 0xFFF00000;
2137                 rxdctl |= IGB_RX_PTHRESH;
2138                 rxdctl |= IGB_RX_HTHRESH << 8;
2139                 rxdctl |= IGB_RX_WTHRESH << 16;
2140                 wr32(E1000_RXDCTL(j), rxdctl);
2141         }
2142
2143         if (adapter->num_rx_queues > 1) {
2144                 u32 random[10];
2145                 u32 mrqc;
2146                 u32 j, shift;
2147                 union e1000_reta {
2148                         u32 dword;
2149                         u8  bytes[4];
2150                 } reta;
2151
2152                 get_random_bytes(&random[0], 40);
2153
2154                 if (hw->mac.type >= e1000_82576)
2155                         shift = 0;
2156                 else
2157                         shift = 6;
2158                 for (j = 0; j < (32 * 4); j++) {
2159                         reta.bytes[j & 3] =
2160                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2161                         if ((j & 3) == 3)
2162                                 writel(reta.dword,
2163                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2164                 }
2165                 if (adapter->vfs_allocated_count)
2166                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2167                 else
2168                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2169
2170                 /* Fill out hash function seeds */
2171                 for (j = 0; j < 10; j++)
2172                         array_wr32(E1000_RSSRK(0), j, random[j]);
2173
2174                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2175                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2176                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2177                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2178                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2179                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2180                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2181                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2182
2183
2184                 wr32(E1000_MRQC, mrqc);
2185
2186                 /* Multiqueue and raw packet checksumming are mutually
2187                  * exclusive.  Note that this not the same as TCP/IP
2188                  * checksumming, which works fine. */
2189                 rxcsum = rd32(E1000_RXCSUM);
2190                 rxcsum |= E1000_RXCSUM_PCSD;
2191                 wr32(E1000_RXCSUM, rxcsum);
2192         } else {
2193                 /* Enable multi-queue for sr-iov */
2194                 if (adapter->vfs_allocated_count)
2195                         wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2196                 /* Enable Receive Checksum Offload for TCP and UDP */
2197                 rxcsum = rd32(E1000_RXCSUM);
2198                 if (adapter->rx_csum)
2199                         rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2200                 else
2201                         rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2202
2203                 wr32(E1000_RXCSUM, rxcsum);
2204         }
2205
2206         /* Set the default pool for the PF's first queue */
2207         igb_configure_vt_default_pool(adapter);
2208
2209         igb_rlpml_set(adapter);
2210
2211         /* Enable Receives */
2212         wr32(E1000_RCTL, rctl);
2213 }
2214
2215 /**
2216  * igb_free_tx_resources - Free Tx Resources per Queue
2217  * @tx_ring: Tx descriptor ring for a specific queue
2218  *
2219  * Free all transmit software resources
2220  **/
2221 void igb_free_tx_resources(struct igb_ring *tx_ring)
2222 {
2223         struct pci_dev *pdev = tx_ring->adapter->pdev;
2224
2225         igb_clean_tx_ring(tx_ring);
2226
2227         vfree(tx_ring->buffer_info);
2228         tx_ring->buffer_info = NULL;
2229
2230         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2231
2232         tx_ring->desc = NULL;
2233 }
2234
2235 /**
2236  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2237  * @adapter: board private structure
2238  *
2239  * Free all transmit software resources
2240  **/
2241 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2242 {
2243         int i;
2244
2245         for (i = 0; i < adapter->num_tx_queues; i++)
2246                 igb_free_tx_resources(&adapter->tx_ring[i]);
2247 }
2248
2249 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2250                                            struct igb_buffer *buffer_info)
2251 {
2252         if (buffer_info->dma) {
2253                 pci_unmap_page(adapter->pdev,
2254                                 buffer_info->dma,
2255                                 buffer_info->length,
2256                                 PCI_DMA_TODEVICE);
2257                 buffer_info->dma = 0;
2258         }
2259         if (buffer_info->skb) {
2260                 dev_kfree_skb_any(buffer_info->skb);
2261                 buffer_info->skb = NULL;
2262         }
2263         buffer_info->time_stamp = 0;
2264         buffer_info->next_to_watch = 0;
2265         /* buffer_info must be completely set up in the transmit path */
2266 }
2267
2268 /**
2269  * igb_clean_tx_ring - Free Tx Buffers
2270  * @tx_ring: ring to be cleaned
2271  **/
2272 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2273 {
2274         struct igb_adapter *adapter = tx_ring->adapter;
2275         struct igb_buffer *buffer_info;
2276         unsigned long size;
2277         unsigned int i;
2278
2279         if (!tx_ring->buffer_info)
2280                 return;
2281         /* Free all the Tx ring sk_buffs */
2282
2283         for (i = 0; i < tx_ring->count; i++) {
2284                 buffer_info = &tx_ring->buffer_info[i];
2285                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2286         }
2287
2288         size = sizeof(struct igb_buffer) * tx_ring->count;
2289         memset(tx_ring->buffer_info, 0, size);
2290
2291         /* Zero out the descriptor ring */
2292
2293         memset(tx_ring->desc, 0, tx_ring->size);
2294
2295         tx_ring->next_to_use = 0;
2296         tx_ring->next_to_clean = 0;
2297
2298         writel(0, adapter->hw.hw_addr + tx_ring->head);
2299         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2300 }
2301
2302 /**
2303  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2304  * @adapter: board private structure
2305  **/
2306 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2307 {
2308         int i;
2309
2310         for (i = 0; i < adapter->num_tx_queues; i++)
2311                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2312 }
2313
2314 /**
2315  * igb_free_rx_resources - Free Rx Resources
2316  * @rx_ring: ring to clean the resources from
2317  *
2318  * Free all receive software resources
2319  **/
2320 void igb_free_rx_resources(struct igb_ring *rx_ring)
2321 {
2322         struct pci_dev *pdev = rx_ring->adapter->pdev;
2323
2324         igb_clean_rx_ring(rx_ring);
2325
2326         vfree(rx_ring->buffer_info);
2327         rx_ring->buffer_info = NULL;
2328
2329         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2330
2331         rx_ring->desc = NULL;
2332 }
2333
2334 /**
2335  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2336  * @adapter: board private structure
2337  *
2338  * Free all receive software resources
2339  **/
2340 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2341 {
2342         int i;
2343
2344         for (i = 0; i < adapter->num_rx_queues; i++)
2345                 igb_free_rx_resources(&adapter->rx_ring[i]);
2346 }
2347
2348 /**
2349  * igb_clean_rx_ring - Free Rx Buffers per Queue
2350  * @rx_ring: ring to free buffers from
2351  **/
2352 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2353 {
2354         struct igb_adapter *adapter = rx_ring->adapter;
2355         struct igb_buffer *buffer_info;
2356         struct pci_dev *pdev = adapter->pdev;
2357         unsigned long size;
2358         unsigned int i;
2359
2360         if (!rx_ring->buffer_info)
2361                 return;
2362         /* Free all the Rx ring sk_buffs */
2363         for (i = 0; i < rx_ring->count; i++) {
2364                 buffer_info = &rx_ring->buffer_info[i];
2365                 if (buffer_info->dma) {
2366                         if (adapter->rx_ps_hdr_size)
2367                                 pci_unmap_single(pdev, buffer_info->dma,
2368                                                  adapter->rx_ps_hdr_size,
2369                                                  PCI_DMA_FROMDEVICE);
2370                         else
2371                                 pci_unmap_single(pdev, buffer_info->dma,
2372                                                  adapter->rx_buffer_len,
2373                                                  PCI_DMA_FROMDEVICE);
2374                         buffer_info->dma = 0;
2375                 }
2376
2377                 if (buffer_info->skb) {
2378                         dev_kfree_skb(buffer_info->skb);
2379                         buffer_info->skb = NULL;
2380                 }
2381                 if (buffer_info->page) {
2382                         if (buffer_info->page_dma)
2383                                 pci_unmap_page(pdev, buffer_info->page_dma,
2384                                                PAGE_SIZE / 2,
2385                                                PCI_DMA_FROMDEVICE);
2386                         put_page(buffer_info->page);
2387                         buffer_info->page = NULL;
2388                         buffer_info->page_dma = 0;
2389                         buffer_info->page_offset = 0;
2390                 }
2391         }
2392
2393         size = sizeof(struct igb_buffer) * rx_ring->count;
2394         memset(rx_ring->buffer_info, 0, size);
2395
2396         /* Zero out the descriptor ring */
2397         memset(rx_ring->desc, 0, rx_ring->size);
2398
2399         rx_ring->next_to_clean = 0;
2400         rx_ring->next_to_use = 0;
2401
2402         writel(0, adapter->hw.hw_addr + rx_ring->head);
2403         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2404 }
2405
2406 /**
2407  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2408  * @adapter: board private structure
2409  **/
2410 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2411 {
2412         int i;
2413
2414         for (i = 0; i < adapter->num_rx_queues; i++)
2415                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2416 }
2417
2418 /**
2419  * igb_set_mac - Change the Ethernet Address of the NIC
2420  * @netdev: network interface device structure
2421  * @p: pointer to an address structure
2422  *
2423  * Returns 0 on success, negative on failure
2424  **/
2425 static int igb_set_mac(struct net_device *netdev, void *p)
2426 {
2427         struct igb_adapter *adapter = netdev_priv(netdev);
2428         struct e1000_hw *hw = &adapter->hw;
2429         struct sockaddr *addr = p;
2430
2431         if (!is_valid_ether_addr(addr->sa_data))
2432                 return -EADDRNOTAVAIL;
2433
2434         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2435         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2436
2437         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2438
2439         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2440
2441         return 0;
2442 }
2443
2444 /**
2445  * igb_set_multi - Multicast and Promiscuous mode set
2446  * @netdev: network interface device structure
2447  *
2448  * The set_multi entry point is called whenever the multicast address
2449  * list or the network interface flags are updated.  This routine is
2450  * responsible for configuring the hardware for proper multicast,
2451  * promiscuous mode, and all-multi behavior.
2452  **/
2453 static void igb_set_multi(struct net_device *netdev)
2454 {
2455         struct igb_adapter *adapter = netdev_priv(netdev);
2456         struct e1000_hw *hw = &adapter->hw;
2457         struct e1000_mac_info *mac = &hw->mac;
2458         struct dev_mc_list *mc_ptr;
2459         u8  *mta_list;
2460         u32 rctl;
2461         int i;
2462
2463         /* Check for Promiscuous and All Multicast modes */
2464
2465         rctl = rd32(E1000_RCTL);
2466
2467         if (netdev->flags & IFF_PROMISC) {
2468                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2469                 rctl &= ~E1000_RCTL_VFE;
2470         } else {
2471                 if (netdev->flags & IFF_ALLMULTI) {
2472                         rctl |= E1000_RCTL_MPE;
2473                         rctl &= ~E1000_RCTL_UPE;
2474                 } else
2475                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2476                 rctl |= E1000_RCTL_VFE;
2477         }
2478         wr32(E1000_RCTL, rctl);
2479
2480         if (!netdev->mc_count) {
2481                 /* nothing to program, so clear mc list */
2482                 igb_update_mc_addr_list(hw, NULL, 0, 1,
2483                                         mac->rar_entry_count);
2484                 return;
2485         }
2486
2487         mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2488         if (!mta_list)
2489                 return;
2490
2491         /* The shared function expects a packed array of only addresses. */
2492         mc_ptr = netdev->mc_list;
2493
2494         for (i = 0; i < netdev->mc_count; i++) {
2495                 if (!mc_ptr)
2496                         break;
2497                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2498                 mc_ptr = mc_ptr->next;
2499         }
2500         igb_update_mc_addr_list(hw, mta_list, i,
2501                                 adapter->vfs_allocated_count + 1,
2502                                 mac->rar_entry_count);
2503
2504         igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2505         igb_restore_vf_multicasts(adapter);
2506
2507         kfree(mta_list);
2508 }
2509
2510 /* Need to wait a few seconds after link up to get diagnostic information from
2511  * the phy */
2512 static void igb_update_phy_info(unsigned long data)
2513 {
2514         struct igb_adapter *adapter = (struct igb_adapter *) data;
2515         igb_get_phy_info(&adapter->hw);
2516 }
2517
2518 /**
2519  * igb_has_link - check shared code for link and determine up/down
2520  * @adapter: pointer to driver private info
2521  **/
2522 static bool igb_has_link(struct igb_adapter *adapter)
2523 {
2524         struct e1000_hw *hw = &adapter->hw;
2525         bool link_active = false;
2526         s32 ret_val = 0;
2527
2528         /* get_link_status is set on LSC (link status) interrupt or
2529          * rx sequence error interrupt.  get_link_status will stay
2530          * false until the e1000_check_for_link establishes link
2531          * for copper adapters ONLY
2532          */
2533         switch (hw->phy.media_type) {
2534         case e1000_media_type_copper:
2535                 if (hw->mac.get_link_status) {
2536                         ret_val = hw->mac.ops.check_for_link(hw);
2537                         link_active = !hw->mac.get_link_status;
2538                 } else {
2539                         link_active = true;
2540                 }
2541                 break;
2542         case e1000_media_type_fiber:
2543                 ret_val = hw->mac.ops.check_for_link(hw);
2544                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2545                 break;
2546         case e1000_media_type_internal_serdes:
2547                 ret_val = hw->mac.ops.check_for_link(hw);
2548                 link_active = hw->mac.serdes_has_link;
2549                 break;
2550         default:
2551         case e1000_media_type_unknown:
2552                 break;
2553         }
2554
2555         return link_active;
2556 }
2557
2558 /**
2559  * igb_watchdog - Timer Call-back
2560  * @data: pointer to adapter cast into an unsigned long
2561  **/
2562 static void igb_watchdog(unsigned long data)
2563 {
2564         struct igb_adapter *adapter = (struct igb_adapter *)data;
2565         /* Do the rest outside of interrupt context */
2566         schedule_work(&adapter->watchdog_task);
2567 }
2568
2569 static void igb_watchdog_task(struct work_struct *work)
2570 {
2571         struct igb_adapter *adapter = container_of(work,
2572                                         struct igb_adapter, watchdog_task);
2573         struct e1000_hw *hw = &adapter->hw;
2574         struct net_device *netdev = adapter->netdev;
2575         struct igb_ring *tx_ring = adapter->tx_ring;
2576         u32 link;
2577         u32 eics = 0;
2578         int i;
2579
2580         link = igb_has_link(adapter);
2581         if ((netif_carrier_ok(netdev)) && link)
2582                 goto link_up;
2583
2584         if (link) {
2585                 if (!netif_carrier_ok(netdev)) {
2586                         u32 ctrl;
2587                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2588                                                    &adapter->link_speed,
2589                                                    &adapter->link_duplex);
2590
2591                         ctrl = rd32(E1000_CTRL);
2592                         /* Links status message must follow this format */
2593                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2594                                  "Flow Control: %s\n",
2595                                  netdev->name,
2596                                  adapter->link_speed,
2597                                  adapter->link_duplex == FULL_DUPLEX ?
2598                                  "Full Duplex" : "Half Duplex",
2599                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2600                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2601                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2602                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2603
2604                         /* tweak tx_queue_len according to speed/duplex and
2605                          * adjust the timeout factor */
2606                         netdev->tx_queue_len = adapter->tx_queue_len;
2607                         adapter->tx_timeout_factor = 1;
2608                         switch (adapter->link_speed) {
2609                         case SPEED_10:
2610                                 netdev->tx_queue_len = 10;
2611                                 adapter->tx_timeout_factor = 14;
2612                                 break;
2613                         case SPEED_100:
2614                                 netdev->tx_queue_len = 100;
2615                                 /* maybe add some timeout factor ? */
2616                                 break;
2617                         }
2618
2619                         netif_carrier_on(netdev);
2620                         netif_tx_wake_all_queues(netdev);
2621
2622                         igb_ping_all_vfs(adapter);
2623
2624                         /* link state has changed, schedule phy info update */
2625                         if (!test_bit(__IGB_DOWN, &adapter->state))
2626                                 mod_timer(&adapter->phy_info_timer,
2627                                           round_jiffies(jiffies + 2 * HZ));
2628                 }
2629         } else {
2630                 if (netif_carrier_ok(netdev)) {
2631                         adapter->link_speed = 0;
2632                         adapter->link_duplex = 0;
2633                         /* Links status message must follow this format */
2634                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2635                                netdev->name);
2636                         netif_carrier_off(netdev);
2637                         netif_tx_stop_all_queues(netdev);
2638
2639                         igb_ping_all_vfs(adapter);
2640
2641                         /* link state has changed, schedule phy info update */
2642                         if (!test_bit(__IGB_DOWN, &adapter->state))
2643                                 mod_timer(&adapter->phy_info_timer,
2644                                           round_jiffies(jiffies + 2 * HZ));
2645                 }
2646         }
2647
2648 link_up:
2649         igb_update_stats(adapter);
2650
2651         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2652         adapter->tpt_old = adapter->stats.tpt;
2653         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2654         adapter->colc_old = adapter->stats.colc;
2655
2656         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2657         adapter->gorc_old = adapter->stats.gorc;
2658         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2659         adapter->gotc_old = adapter->stats.gotc;
2660
2661         igb_update_adaptive(&adapter->hw);
2662
2663         if (!netif_carrier_ok(netdev)) {
2664                 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2665                         /* We've lost link, so the controller stops DMA,
2666                          * but we've got queued Tx work that's never going
2667                          * to get done, so reset controller to flush Tx.
2668                          * (Do the reset outside of interrupt context). */
2669                         adapter->tx_timeout_count++;
2670                         schedule_work(&adapter->reset_task);
2671                 }
2672         }
2673
2674         /* Cause software interrupt to ensure rx ring is cleaned */
2675         if (adapter->msix_entries) {
2676                 for (i = 0; i < adapter->num_rx_queues; i++)
2677                         eics |= adapter->rx_ring[i].eims_value;
2678                 wr32(E1000_EICS, eics);
2679         } else {
2680                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2681         }
2682
2683         /* Force detection of hung controller every watchdog period */
2684         tx_ring->detect_tx_hung = true;
2685
2686         /* Reset the timer */
2687         if (!test_bit(__IGB_DOWN, &adapter->state))
2688                 mod_timer(&adapter->watchdog_timer,
2689                           round_jiffies(jiffies + 2 * HZ));
2690 }
2691
2692 enum latency_range {
2693         lowest_latency = 0,
2694         low_latency = 1,
2695         bulk_latency = 2,
2696         latency_invalid = 255
2697 };
2698
2699
2700 /**
2701  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2702  *
2703  *      Stores a new ITR value based on strictly on packet size.  This
2704  *      algorithm is less sophisticated than that used in igb_update_itr,
2705  *      due to the difficulty of synchronizing statistics across multiple
2706  *      receive rings.  The divisors and thresholds used by this fuction
2707  *      were determined based on theoretical maximum wire speed and testing
2708  *      data, in order to minimize response time while increasing bulk
2709  *      throughput.
2710  *      This functionality is controlled by the InterruptThrottleRate module
2711  *      parameter (see igb_param.c)
2712  *      NOTE:  This function is called only when operating in a multiqueue
2713  *             receive environment.
2714  * @rx_ring: pointer to ring
2715  **/
2716 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2717 {
2718         int new_val = rx_ring->itr_val;
2719         int avg_wire_size = 0;
2720         struct igb_adapter *adapter = rx_ring->adapter;
2721
2722         if (!rx_ring->total_packets)
2723                 goto clear_counts; /* no packets, so don't do anything */
2724
2725         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2726          * ints/sec - ITR timer value of 120 ticks.
2727          */
2728         if (adapter->link_speed != SPEED_1000) {
2729                 new_val = 120;
2730                 goto set_itr_val;
2731         }
2732         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2733
2734         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2735         avg_wire_size += 24;
2736
2737         /* Don't starve jumbo frames */
2738         avg_wire_size = min(avg_wire_size, 3000);
2739
2740         /* Give a little boost to mid-size frames */
2741         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2742                 new_val = avg_wire_size / 3;
2743         else
2744                 new_val = avg_wire_size / 2;
2745
2746 set_itr_val:
2747         if (new_val != rx_ring->itr_val) {
2748                 rx_ring->itr_val = new_val;
2749                 rx_ring->set_itr = 1;
2750         }
2751 clear_counts:
2752         rx_ring->total_bytes = 0;
2753         rx_ring->total_packets = 0;
2754 }
2755
2756 /**
2757  * igb_update_itr - update the dynamic ITR value based on statistics
2758  *      Stores a new ITR value based on packets and byte
2759  *      counts during the last interrupt.  The advantage of per interrupt
2760  *      computation is faster updates and more accurate ITR for the current
2761  *      traffic pattern.  Constants in this function were computed
2762  *      based on theoretical maximum wire speed and thresholds were set based
2763  *      on testing data as well as attempting to minimize response time
2764  *      while increasing bulk throughput.
2765  *      this functionality is controlled by the InterruptThrottleRate module
2766  *      parameter (see igb_param.c)
2767  *      NOTE:  These calculations are only valid when operating in a single-
2768  *             queue environment.
2769  * @adapter: pointer to adapter
2770  * @itr_setting: current adapter->itr
2771  * @packets: the number of packets during this measurement interval
2772  * @bytes: the number of bytes during this measurement interval
2773  **/
2774 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2775                                    int packets, int bytes)
2776 {
2777         unsigned int retval = itr_setting;
2778
2779         if (packets == 0)
2780                 goto update_itr_done;
2781
2782         switch (itr_setting) {
2783         case lowest_latency:
2784                 /* handle TSO and jumbo frames */
2785                 if (bytes/packets > 8000)
2786                         retval = bulk_latency;
2787                 else if ((packets < 5) && (bytes > 512))
2788                         retval = low_latency;
2789                 break;
2790         case low_latency:  /* 50 usec aka 20000 ints/s */
2791                 if (bytes > 10000) {
2792                         /* this if handles the TSO accounting */
2793                         if (bytes/packets > 8000) {
2794                                 retval = bulk_latency;
2795                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2796                                 retval = bulk_latency;
2797                         } else if ((packets > 35)) {
2798                                 retval = lowest_latency;
2799                         }
2800                 } else if (bytes/packets > 2000) {
2801                         retval = bulk_latency;
2802                 } else if (packets <= 2 && bytes < 512) {
2803                         retval = lowest_latency;
2804                 }
2805                 break;
2806         case bulk_latency: /* 250 usec aka 4000 ints/s */
2807                 if (bytes > 25000) {
2808                         if (packets > 35)
2809                                 retval = low_latency;
2810                 } else if (bytes < 1500) {
2811                         retval = low_latency;
2812                 }
2813                 break;
2814         }
2815
2816 update_itr_done:
2817         return retval;
2818 }
2819
2820 static void igb_set_itr(struct igb_adapter *adapter)
2821 {
2822         u16 current_itr;
2823         u32 new_itr = adapter->itr;
2824
2825         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2826         if (adapter->link_speed != SPEED_1000) {
2827                 current_itr = 0;
2828                 new_itr = 4000;
2829                 goto set_itr_now;
2830         }
2831
2832         adapter->rx_itr = igb_update_itr(adapter,
2833                                     adapter->rx_itr,
2834                                     adapter->rx_ring->total_packets,
2835                                     adapter->rx_ring->total_bytes);
2836
2837         if (adapter->rx_ring->buddy) {
2838                 adapter->tx_itr = igb_update_itr(adapter,
2839                                             adapter->tx_itr,
2840                                             adapter->tx_ring->total_packets,
2841                                             adapter->tx_ring->total_bytes);
2842                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2843         } else {
2844                 current_itr = adapter->rx_itr;
2845         }
2846
2847         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2848         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2849                 current_itr = low_latency;
2850
2851         switch (current_itr) {
2852         /* counts and packets in update_itr are dependent on these numbers */
2853         case lowest_latency:
2854                 new_itr = 70000;
2855                 break;
2856         case low_latency:
2857                 new_itr = 20000; /* aka hwitr = ~200 */
2858                 break;
2859         case bulk_latency:
2860                 new_itr = 4000;
2861                 break;
2862         default:
2863                 break;
2864         }
2865
2866 set_itr_now:
2867         adapter->rx_ring->total_bytes = 0;
2868         adapter->rx_ring->total_packets = 0;
2869         if (adapter->rx_ring->buddy) {
2870                 adapter->rx_ring->buddy->total_bytes = 0;
2871                 adapter->rx_ring->buddy->total_packets = 0;
2872         }
2873
2874         if (new_itr != adapter->itr) {
2875                 /* this attempts to bias the interrupt rate towards Bulk
2876                  * by adding intermediate steps when interrupt rate is
2877                  * increasing */
2878                 new_itr = new_itr > adapter->itr ?
2879                              min(adapter->itr + (new_itr >> 2), new_itr) :
2880                              new_itr;
2881                 /* Don't write the value here; it resets the adapter's
2882                  * internal timer, and causes us to delay far longer than
2883                  * we should between interrupts.  Instead, we write the ITR
2884                  * value at the beginning of the next interrupt so the timing
2885                  * ends up being correct.
2886                  */
2887                 adapter->itr = new_itr;
2888                 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2889                 adapter->rx_ring->set_itr = 1;
2890         }
2891
2892         return;
2893 }
2894
2895
2896 #define IGB_TX_FLAGS_CSUM               0x00000001
2897 #define IGB_TX_FLAGS_VLAN               0x00000002
2898 #define IGB_TX_FLAGS_TSO                0x00000004
2899 #define IGB_TX_FLAGS_IPV4               0x00000008
2900 #define IGB_TX_FLAGS_TSTAMP             0x00000010
2901 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2902 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2903
2904 static inline int igb_tso_adv(struct igb_adapter *adapter,
2905                               struct igb_ring *tx_ring,
2906                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2907 {
2908         struct e1000_adv_tx_context_desc *context_desc;
2909         unsigned int i;
2910         int err;
2911         struct igb_buffer *buffer_info;
2912         u32 info = 0, tu_cmd = 0;
2913         u32 mss_l4len_idx, l4len;
2914         *hdr_len = 0;
2915
2916         if (skb_header_cloned(skb)) {
2917                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2918                 if (err)
2919                         return err;
2920         }
2921
2922         l4len = tcp_hdrlen(skb);
2923         *hdr_len += l4len;
2924
2925         if (skb->protocol == htons(ETH_P_IP)) {
2926                 struct iphdr *iph = ip_hdr(skb);
2927                 iph->tot_len = 0;
2928                 iph->check = 0;
2929                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2930                                                          iph->daddr, 0,
2931                                                          IPPROTO_TCP,
2932                                                          0);
2933         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2934                 ipv6_hdr(skb)->payload_len = 0;
2935                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2936                                                        &ipv6_hdr(skb)->daddr,
2937                                                        0, IPPROTO_TCP, 0);
2938         }
2939
2940         i = tx_ring->next_to_use;
2941
2942         buffer_info = &tx_ring->buffer_info[i];
2943         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2944         /* VLAN MACLEN IPLEN */
2945         if (tx_flags & IGB_TX_FLAGS_VLAN)
2946                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2947         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2948         *hdr_len += skb_network_offset(skb);
2949         info |= skb_network_header_len(skb);
2950         *hdr_len += skb_network_header_len(skb);
2951         context_desc->vlan_macip_lens = cpu_to_le32(info);
2952
2953         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2954         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2955
2956         if (skb->protocol == htons(ETH_P_IP))
2957                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2958         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2959
2960         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2961
2962         /* MSS L4LEN IDX */
2963         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2964         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2965
2966         /* For 82575, context index must be unique per ring. */
2967         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2968                 mss_l4len_idx |= tx_ring->queue_index << 4;
2969
2970         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2971         context_desc->seqnum_seed = 0;
2972
2973         buffer_info->time_stamp = jiffies;
2974         buffer_info->next_to_watch = i;
2975         buffer_info->dma = 0;
2976         i++;
2977         if (i == tx_ring->count)
2978                 i = 0;
2979
2980         tx_ring->next_to_use = i;
2981
2982         return true;
2983 }
2984
2985 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2986                                         struct igb_ring *tx_ring,
2987                                         struct sk_buff *skb, u32 tx_flags)
2988 {
2989         struct e1000_adv_tx_context_desc *context_desc;
2990         unsigned int i;
2991         struct igb_buffer *buffer_info;
2992         u32 info = 0, tu_cmd = 0;
2993
2994         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2995             (tx_flags & IGB_TX_FLAGS_VLAN)) {
2996                 i = tx_ring->next_to_use;
2997                 buffer_info = &tx_ring->buffer_info[i];
2998                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2999
3000                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3001                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3002                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3003                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3004                         info |= skb_network_header_len(skb);
3005
3006                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3007
3008                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3009
3010                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3011                         switch (skb->protocol) {
3012                         case cpu_to_be16(ETH_P_IP):
3013                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3014                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3015                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3016                                 break;
3017                         case cpu_to_be16(ETH_P_IPV6):
3018                                 /* XXX what about other V6 headers?? */
3019                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3020                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3021                                 break;
3022                         default:
3023                                 if (unlikely(net_ratelimit()))
3024                                         dev_warn(&adapter->pdev->dev,
3025                                             "partial checksum but proto=%x!\n",
3026                                             skb->protocol);
3027                                 break;
3028                         }
3029                 }
3030
3031                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3032                 context_desc->seqnum_seed = 0;
3033                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3034                         context_desc->mss_l4len_idx =
3035                                 cpu_to_le32(tx_ring->queue_index << 4);
3036                 else
3037                         context_desc->mss_l4len_idx = 0;
3038
3039                 buffer_info->time_stamp = jiffies;
3040                 buffer_info->next_to_watch = i;
3041                 buffer_info->dma = 0;
3042
3043                 i++;
3044                 if (i == tx_ring->count)
3045                         i = 0;
3046                 tx_ring->next_to_use = i;
3047
3048                 return true;
3049         }
3050         return false;
3051 }
3052
3053 #define IGB_MAX_TXD_PWR 16
3054 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3055
3056 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3057                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3058                                  unsigned int first)
3059 {
3060         struct igb_buffer *buffer_info;
3061         unsigned int len = skb_headlen(skb);
3062         unsigned int count = 0, i;
3063         unsigned int f;
3064
3065         i = tx_ring->next_to_use;
3066
3067         buffer_info = &tx_ring->buffer_info[i];
3068         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3069         buffer_info->length = len;
3070         /* set time_stamp *before* dma to help avoid a possible race */
3071         buffer_info->time_stamp = jiffies;
3072         buffer_info->next_to_watch = i;
3073         buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
3074                                           PCI_DMA_TODEVICE);
3075         count++;
3076         i++;
3077         if (i == tx_ring->count)
3078                 i = 0;
3079
3080         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3081                 struct skb_frag_struct *frag;
3082
3083                 frag = &skb_shinfo(skb)->frags[f];
3084                 len = frag->size;
3085
3086                 buffer_info = &tx_ring->buffer_info[i];
3087                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3088                 buffer_info->length = len;
3089                 buffer_info->time_stamp = jiffies;
3090                 buffer_info->next_to_watch = i;
3091                 buffer_info->dma = pci_map_page(adapter->pdev,
3092                                                 frag->page,
3093                                                 frag->page_offset,
3094                                                 len,
3095                                                 PCI_DMA_TODEVICE);
3096
3097                 count++;
3098                 i++;
3099                 if (i == tx_ring->count)
3100                         i = 0;
3101         }
3102
3103         i = ((i == 0) ? tx_ring->count - 1 : i - 1);
3104         tx_ring->buffer_info[i].skb = skb;
3105         tx_ring->buffer_info[first].next_to_watch = i;
3106
3107         return count;
3108 }
3109
3110 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3111                                     struct igb_ring *tx_ring,
3112                                     int tx_flags, int count, u32 paylen,
3113                                     u8 hdr_len)
3114 {
3115         union e1000_adv_tx_desc *tx_desc = NULL;
3116         struct igb_buffer *buffer_info;
3117         u32 olinfo_status = 0, cmd_type_len;
3118         unsigned int i;
3119
3120         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3121                         E1000_ADVTXD_DCMD_DEXT);
3122
3123         if (tx_flags & IGB_TX_FLAGS_VLAN)
3124                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3125
3126         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3127                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3128
3129         if (tx_flags & IGB_TX_FLAGS_TSO) {
3130                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3131
3132                 /* insert tcp checksum */
3133                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3134
3135                 /* insert ip checksum */
3136                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3137                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3138
3139         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3140                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3141         }
3142
3143         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3144             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3145                          IGB_TX_FLAGS_VLAN)))
3146                 olinfo_status |= tx_ring->queue_index << 4;
3147
3148         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3149
3150         i = tx_ring->next_to_use;
3151         while (count--) {
3152                 buffer_info = &tx_ring->buffer_info[i];
3153                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3154                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3155                 tx_desc->read.cmd_type_len =
3156                         cpu_to_le32(cmd_type_len | buffer_info->length);
3157                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3158                 i++;
3159                 if (i == tx_ring->count)
3160                         i = 0;
3161         }
3162
3163         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3164         /* Force memory writes to complete before letting h/w
3165          * know there are new descriptors to fetch.  (Only
3166          * applicable for weak-ordered memory model archs,
3167          * such as IA-64). */
3168         wmb();
3169
3170         tx_ring->next_to_use = i;
3171         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3172         /* we need this if more than one processor can write to our tail
3173          * at a time, it syncronizes IO on IA64/Altix systems */
3174         mmiowb();
3175 }
3176
3177 static int __igb_maybe_stop_tx(struct net_device *netdev,
3178                                struct igb_ring *tx_ring, int size)
3179 {
3180         struct igb_adapter *adapter = netdev_priv(netdev);
3181
3182         netif_stop_subqueue(netdev, tx_ring->queue_index);
3183
3184         /* Herbert's original patch had:
3185          *  smp_mb__after_netif_stop_queue();
3186          * but since that doesn't exist yet, just open code it. */
3187         smp_mb();
3188
3189         /* We need to check again in a case another CPU has just
3190          * made room available. */
3191         if (IGB_DESC_UNUSED(tx_ring) < size)
3192                 return -EBUSY;
3193
3194         /* A reprieve! */
3195         netif_wake_subqueue(netdev, tx_ring->queue_index);
3196         ++adapter->restart_queue;
3197         return 0;
3198 }
3199
3200 static int igb_maybe_stop_tx(struct net_device *netdev,
3201                              struct igb_ring *tx_ring, int size)
3202 {
3203         if (IGB_DESC_UNUSED(tx_ring) >= size)
3204                 return 0;
3205         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3206 }
3207
3208 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3209                                    struct net_device *netdev,
3210                                    struct igb_ring *tx_ring)
3211 {
3212         struct igb_adapter *adapter = netdev_priv(netdev);
3213         unsigned int first;
3214         unsigned int tx_flags = 0;
3215         u8 hdr_len = 0;
3216         int tso = 0;
3217         union skb_shared_tx *shtx;
3218
3219         if (test_bit(__IGB_DOWN, &adapter->state)) {
3220                 dev_kfree_skb_any(skb);
3221                 return NETDEV_TX_OK;
3222         }
3223
3224         if (skb->len <= 0) {
3225                 dev_kfree_skb_any(skb);
3226                 return NETDEV_TX_OK;
3227         }
3228
3229         /* need: 1 descriptor per page,
3230          *       + 2 desc gap to keep tail from touching head,
3231          *       + 1 desc for skb->data,
3232          *       + 1 desc for context descriptor,
3233          * otherwise try next time */
3234         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3235                 /* this is a hard error */
3236                 return NETDEV_TX_BUSY;
3237         }
3238
3239         /*
3240          * TODO: check that there currently is no other packet with
3241          * time stamping in the queue
3242          *
3243          * When doing time stamping, keep the connection to the socket
3244          * a while longer: it is still needed by skb_hwtstamp_tx(),
3245          * called either in igb_tx_hwtstamp() or by our caller when
3246          * doing software time stamping.
3247          */
3248         shtx = skb_tx(skb);
3249         if (unlikely(shtx->hardware)) {
3250                 shtx->in_progress = 1;
3251                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3252         }
3253
3254         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3255                 tx_flags |= IGB_TX_FLAGS_VLAN;
3256                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3257         }
3258
3259         if (skb->protocol == htons(ETH_P_IP))
3260                 tx_flags |= IGB_TX_FLAGS_IPV4;
3261
3262         first = tx_ring->next_to_use;
3263         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3264                                               &hdr_len) : 0;
3265
3266         if (tso < 0) {
3267                 dev_kfree_skb_any(skb);
3268                 return NETDEV_TX_OK;
3269         }
3270
3271         if (tso)
3272                 tx_flags |= IGB_TX_FLAGS_TSO;
3273         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3274                  (skb->ip_summed == CHECKSUM_PARTIAL))
3275                 tx_flags |= IGB_TX_FLAGS_CSUM;
3276
3277         igb_tx_queue_adv(adapter, tx_ring, tx_flags,
3278                          igb_tx_map_adv(adapter, tx_ring, skb, first),
3279                          skb->len, hdr_len);
3280
3281         netdev->trans_start = jiffies;
3282
3283         /* Make sure there is space in the ring for the next send. */
3284         igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3285
3286         return NETDEV_TX_OK;
3287 }
3288
3289 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3290 {
3291         struct igb_adapter *adapter = netdev_priv(netdev);
3292         struct igb_ring *tx_ring;
3293
3294         int r_idx = 0;
3295         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3296         tx_ring = adapter->multi_tx_table[r_idx];
3297
3298         /* This goes back to the question of how to logically map a tx queue
3299          * to a flow.  Right now, performance is impacted slightly negatively
3300          * if using multiple tx queues.  If the stack breaks away from a
3301          * single qdisc implementation, we can look at this again. */
3302         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3303 }
3304
3305 /**
3306  * igb_tx_timeout - Respond to a Tx Hang
3307  * @netdev: network interface device structure
3308  **/
3309 static void igb_tx_timeout(struct net_device *netdev)
3310 {
3311         struct igb_adapter *adapter = netdev_priv(netdev);
3312         struct e1000_hw *hw = &adapter->hw;
3313
3314         /* Do the reset outside of interrupt context */
3315         adapter->tx_timeout_count++;
3316         schedule_work(&adapter->reset_task);
3317         wr32(E1000_EICS,
3318              (adapter->eims_enable_mask & ~adapter->eims_other));
3319 }
3320
3321 static void igb_reset_task(struct work_struct *work)
3322 {
3323         struct igb_adapter *adapter;
3324         adapter = container_of(work, struct igb_adapter, reset_task);
3325
3326         igb_reinit_locked(adapter);
3327 }
3328
3329 /**
3330  * igb_get_stats - Get System Network Statistics
3331  * @netdev: network interface device structure
3332  *
3333  * Returns the address of the device statistics structure.
3334  * The statistics are actually updated from the timer callback.
3335  **/
3336 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3337 {
3338         struct igb_adapter *adapter = netdev_priv(netdev);
3339
3340         /* only return the current stats */
3341         return &adapter->net_stats;
3342 }
3343
3344 /**
3345  * igb_change_mtu - Change the Maximum Transfer Unit
3346  * @netdev: network interface device structure
3347  * @new_mtu: new value for maximum frame size
3348  *
3349  * Returns 0 on success, negative on failure
3350  **/
3351 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3352 {
3353         struct igb_adapter *adapter = netdev_priv(netdev);
3354         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3355
3356         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3357             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3358                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3359                 return -EINVAL;
3360         }
3361
3362         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3363                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3364                 return -EINVAL;
3365         }
3366
3367         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3368                 msleep(1);
3369
3370         /* igb_down has a dependency on max_frame_size */
3371         adapter->max_frame_size = max_frame;
3372         if (netif_running(netdev))
3373                 igb_down(adapter);
3374
3375         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3376          * means we reserve 2 more, this pushes us to allocate from the next
3377          * larger slab size.
3378          * i.e. RXBUFFER_2048 --> size-4096 slab
3379          */
3380
3381         if (max_frame <= IGB_RXBUFFER_256)
3382                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3383         else if (max_frame <= IGB_RXBUFFER_512)
3384                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3385         else if (max_frame <= IGB_RXBUFFER_1024)
3386                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3387         else if (max_frame <= IGB_RXBUFFER_2048)
3388                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3389         else
3390 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3391                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3392 #else
3393                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3394 #endif
3395
3396         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3397         if (adapter->vfs_allocated_count &&
3398             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3399                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3400
3401         /* adjust allocation if LPE protects us, and we aren't using SBP */
3402         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3403              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3404                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3405
3406         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3407                  netdev->mtu, new_mtu);
3408         netdev->mtu = new_mtu;
3409
3410         if (netif_running(netdev))
3411                 igb_up(adapter);
3412         else
3413                 igb_reset(adapter);
3414
3415         clear_bit(__IGB_RESETTING, &adapter->state);
3416
3417         return 0;
3418 }
3419
3420 /**
3421  * igb_update_stats - Update the board statistics counters
3422  * @adapter: board private structure
3423  **/
3424
3425 void igb_update_stats(struct igb_adapter *adapter)
3426 {
3427         struct e1000_hw *hw = &adapter->hw;
3428         struct pci_dev *pdev = adapter->pdev;
3429         u16 phy_tmp;
3430
3431 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3432
3433         /*
3434          * Prevent stats update while adapter is being reset, or if the pci
3435          * connection is down.
3436          */
3437         if (adapter->link_speed == 0)
3438                 return;
3439         if (pci_channel_offline(pdev))
3440                 return;
3441
3442         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3443         adapter->stats.gprc += rd32(E1000_GPRC);
3444         adapter->stats.gorc += rd32(E1000_GORCL);
3445         rd32(E1000_GORCH); /* clear GORCL */
3446         adapter->stats.bprc += rd32(E1000_BPRC);
3447         adapter->stats.mprc += rd32(E1000_MPRC);
3448         adapter->stats.roc += rd32(E1000_ROC);
3449
3450         adapter->stats.prc64 += rd32(E1000_PRC64);
3451         adapter->stats.prc127 += rd32(E1000_PRC127);
3452         adapter->stats.prc255 += rd32(E1000_PRC255);
3453         adapter->stats.prc511 += rd32(E1000_PRC511);
3454         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3455         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3456         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3457         adapter->stats.sec += rd32(E1000_SEC);
3458
3459         adapter->stats.mpc += rd32(E1000_MPC);
3460         adapter->stats.scc += rd32(E1000_SCC);
3461         adapter->stats.ecol += rd32(E1000_ECOL);
3462         adapter->stats.mcc += rd32(E1000_MCC);
3463         adapter->stats.latecol += rd32(E1000_LATECOL);
3464         adapter->stats.dc += rd32(E1000_DC);
3465         adapter->stats.rlec += rd32(E1000_RLEC);
3466         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3467         adapter->stats.xontxc += rd32(E1000_XONTXC);
3468         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3469         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3470         adapter->stats.fcruc += rd32(E1000_FCRUC);
3471         adapter->stats.gptc += rd32(E1000_GPTC);
3472         adapter->stats.gotc += rd32(E1000_GOTCL);
3473         rd32(E1000_GOTCH); /* clear GOTCL */
3474         adapter->stats.rnbc += rd32(E1000_RNBC);
3475         adapter->stats.ruc += rd32(E1000_RUC);
3476         adapter->stats.rfc += rd32(E1000_RFC);
3477         adapter->stats.rjc += rd32(E1000_RJC);
3478         adapter->stats.tor += rd32(E1000_TORH);
3479         adapter->stats.tot += rd32(E1000_TOTH);
3480         adapter->stats.tpr += rd32(E1000_TPR);
3481
3482         adapter->stats.ptc64 += rd32(E1000_PTC64);
3483         adapter->stats.ptc127 += rd32(E1000_PTC127);
3484         adapter->stats.ptc255 += rd32(E1000_PTC255);
3485         adapter->stats.ptc511 += rd32(E1000_PTC511);
3486         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3487         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3488
3489         adapter->stats.mptc += rd32(E1000_MPTC);
3490         adapter->stats.bptc += rd32(E1000_BPTC);
3491
3492         /* used for adaptive IFS */
3493
3494         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3495         adapter->stats.tpt += hw->mac.tx_packet_delta;
3496         hw->mac.collision_delta = rd32(E1000_COLC);
3497         adapter->stats.colc += hw->mac.collision_delta;
3498
3499         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3500         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3501         adapter->stats.tncrs += rd32(E1000_TNCRS);
3502         adapter->stats.tsctc += rd32(E1000_TSCTC);
3503         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3504
3505         adapter->stats.iac += rd32(E1000_IAC);
3506         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3507         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3508         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3509         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3510         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3511         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3512         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3513         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3514
3515         /* Fill out the OS statistics structure */
3516         adapter->net_stats.multicast = adapter->stats.mprc;
3517         adapter->net_stats.collisions = adapter->stats.colc;
3518
3519         /* Rx Errors */
3520
3521         /* RLEC on some newer hardware can be incorrect so build
3522         * our own version based on RUC and ROC */
3523         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3524                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3525                 adapter->stats.ruc + adapter->stats.roc +
3526                 adapter->stats.cexterr;
3527         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3528                                               adapter->stats.roc;
3529         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3530         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3531         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3532
3533         /* Tx Errors */
3534         adapter->net_stats.tx_errors = adapter->stats.ecol +
3535                                        adapter->stats.latecol;
3536         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3537         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3538         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3539
3540         /* Tx Dropped needs to be maintained elsewhere */
3541
3542         /* Phy Stats */
3543         if (hw->phy.media_type == e1000_media_type_copper) {
3544                 if ((adapter->link_speed == SPEED_1000) &&
3545                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3546                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3547                         adapter->phy_stats.idle_errors += phy_tmp;
3548                 }
3549         }
3550
3551         /* Management Stats */
3552         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3553         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3554         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3555 }
3556
3557 static irqreturn_t igb_msix_other(int irq, void *data)
3558 {
3559         struct net_device *netdev = data;
3560         struct igb_adapter *adapter = netdev_priv(netdev);
3561         struct e1000_hw *hw = &adapter->hw;
3562         u32 icr = rd32(E1000_ICR);
3563
3564         /* reading ICR causes bit 31 of EICR to be cleared */
3565
3566         if(icr & E1000_ICR_DOUTSYNC) {
3567                 /* HW is reporting DMA is out of sync */
3568                 adapter->stats.doosync++;
3569         }
3570
3571         /* Check for a mailbox event */
3572         if (icr & E1000_ICR_VMMB)
3573                 igb_msg_task(adapter);
3574
3575         if (icr & E1000_ICR_LSC) {
3576                 hw->mac.get_link_status = 1;
3577                 /* guard against interrupt when we're going down */
3578                 if (!test_bit(__IGB_DOWN, &adapter->state))
3579                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3580         }
3581
3582         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3583         wr32(E1000_EIMS, adapter->eims_other);
3584
3585         return IRQ_HANDLED;
3586 }
3587
3588 static irqreturn_t igb_msix_tx(int irq, void *data)
3589 {
3590         struct igb_ring *tx_ring = data;
3591         struct igb_adapter *adapter = tx_ring->adapter;
3592         struct e1000_hw *hw = &adapter->hw;
3593
3594 #ifdef CONFIG_IGB_DCA
3595         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3596                 igb_update_tx_dca(tx_ring);
3597 #endif
3598
3599         tx_ring->total_bytes = 0;
3600         tx_ring->total_packets = 0;
3601
3602         /* auto mask will automatically reenable the interrupt when we write
3603          * EICS */
3604         if (!igb_clean_tx_irq(tx_ring))
3605                 /* Ring was not completely cleaned, so fire another interrupt */
3606                 wr32(E1000_EICS, tx_ring->eims_value);
3607         else
3608                 wr32(E1000_EIMS, tx_ring->eims_value);
3609
3610         return IRQ_HANDLED;
3611 }
3612
3613 static void igb_write_itr(struct igb_ring *ring)
3614 {
3615         struct e1000_hw *hw = &ring->adapter->hw;
3616         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3617                 switch (hw->mac.type) {
3618                 case e1000_82576:
3619                         wr32(ring->itr_register, ring->itr_val |
3620                              0x80000000);
3621                         break;
3622                 default:
3623                         wr32(ring->itr_register, ring->itr_val |
3624                              (ring->itr_val << 16));
3625                         break;
3626                 }
3627                 ring->set_itr = 0;
3628         }
3629 }
3630
3631 static irqreturn_t igb_msix_rx(int irq, void *data)
3632 {
3633         struct igb_ring *rx_ring = data;
3634
3635         /* Write the ITR value calculated at the end of the
3636          * previous interrupt.
3637          */
3638
3639         igb_write_itr(rx_ring);
3640
3641         if (napi_schedule_prep(&rx_ring->napi))
3642                 __napi_schedule(&rx_ring->napi);
3643
3644 #ifdef CONFIG_IGB_DCA
3645         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3646                 igb_update_rx_dca(rx_ring);
3647 #endif
3648                 return IRQ_HANDLED;
3649 }
3650
3651 #ifdef CONFIG_IGB_DCA
3652 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3653 {
3654         u32 dca_rxctrl;
3655         struct igb_adapter *adapter = rx_ring->adapter;
3656         struct e1000_hw *hw = &adapter->hw;
3657         int cpu = get_cpu();
3658         int q = rx_ring->reg_idx;
3659
3660         if (rx_ring->cpu != cpu) {
3661                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3662                 if (hw->mac.type == e1000_82576) {
3663                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3664                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3665                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3666                 } else {
3667                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3668                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3669                 }
3670                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3671                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3672                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3673                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3674                 rx_ring->cpu = cpu;
3675         }
3676         put_cpu();
3677 }
3678
3679 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3680 {
3681         u32 dca_txctrl;
3682         struct igb_adapter *adapter = tx_ring->adapter;
3683         struct e1000_hw *hw = &adapter->hw;
3684         int cpu = get_cpu();
3685         int q = tx_ring->reg_idx;
3686
3687         if (tx_ring->cpu != cpu) {
3688                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3689                 if (hw->mac.type == e1000_82576) {
3690                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3691                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3692                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3693                 } else {
3694                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3695                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3696                 }
3697                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3698                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3699                 tx_ring->cpu = cpu;
3700         }
3701         put_cpu();
3702 }
3703
3704 static void igb_setup_dca(struct igb_adapter *adapter)
3705 {
3706         int i;
3707
3708         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3709                 return;
3710
3711         for (i = 0; i < adapter->num_tx_queues; i++) {
3712                 adapter->tx_ring[i].cpu = -1;
3713                 igb_update_tx_dca(&adapter->tx_ring[i]);
3714         }
3715         for (i = 0; i < adapter->num_rx_queues; i++) {
3716                 adapter->rx_ring[i].cpu = -1;
3717                 igb_update_rx_dca(&adapter->rx_ring[i]);
3718         }
3719 }
3720
3721 static int __igb_notify_dca(struct device *dev, void *data)
3722 {
3723         struct net_device *netdev = dev_get_drvdata(dev);
3724         struct igb_adapter *adapter = netdev_priv(netdev);
3725         struct e1000_hw *hw = &adapter->hw;
3726         unsigned long event = *(unsigned long *)data;
3727
3728         switch (event) {
3729         case DCA_PROVIDER_ADD:
3730                 /* if already enabled, don't do it again */
3731                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3732                         break;
3733                 /* Always use CB2 mode, difference is masked
3734                  * in the CB driver. */
3735                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3736                 if (dca_add_requester(dev) == 0) {
3737                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3738                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3739                         igb_setup_dca(adapter);
3740                         break;
3741                 }
3742                 /* Fall Through since DCA is disabled. */
3743         case DCA_PROVIDER_REMOVE:
3744                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3745                         /* without this a class_device is left
3746                          * hanging around in the sysfs model */
3747                         dca_remove_requester(dev);
3748                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3749                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3750                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3751                 }
3752                 break;
3753         }
3754
3755         return 0;
3756 }
3757
3758 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3759                           void *p)
3760 {
3761         int ret_val;
3762
3763         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3764                                          __igb_notify_dca);
3765
3766         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3767 }
3768 #endif /* CONFIG_IGB_DCA */
3769
3770 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3771 {
3772         struct e1000_hw *hw = &adapter->hw;
3773         u32 ping;
3774         int i;
3775
3776         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3777                 ping = E1000_PF_CONTROL_MSG;
3778                 if (adapter->vf_data[i].clear_to_send)
3779                         ping |= E1000_VT_MSGTYPE_CTS;
3780                 igb_write_mbx(hw, &ping, 1, i);
3781         }
3782 }
3783
3784 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3785                                   u32 *msgbuf, u32 vf)
3786 {
3787         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3788         u16 *hash_list = (u16 *)&msgbuf[1];
3789         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3790         int i;
3791
3792         /* only up to 30 hash values supported */
3793         if (n > 30)
3794                 n = 30;
3795
3796         /* salt away the number of multi cast addresses assigned
3797          * to this VF for later use to restore when the PF multi cast
3798          * list changes
3799          */
3800         vf_data->num_vf_mc_hashes = n;
3801
3802         /* VFs are limited to using the MTA hash table for their multicast
3803          * addresses */
3804         for (i = 0; i < n; i++)
3805                 vf_data->vf_mc_hashes[i] = hash_list[i];;
3806
3807         /* Flush and reset the mta with the new values */
3808         igb_set_multi(adapter->netdev);
3809
3810         return 0;
3811 }
3812
3813 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3814 {
3815         struct e1000_hw *hw = &adapter->hw;
3816         struct vf_data_storage *vf_data;
3817         int i, j;
3818
3819         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3820                 vf_data = &adapter->vf_data[i];
3821                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3822                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3823         }
3824 }
3825
3826 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3827 {
3828         struct e1000_hw *hw = &adapter->hw;
3829         u32 pool_mask, reg, vid;
3830         int i;
3831
3832         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3833
3834         /* Find the vlan filter for this id */
3835         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3836                 reg = rd32(E1000_VLVF(i));
3837
3838                 /* remove the vf from the pool */
3839                 reg &= ~pool_mask;
3840
3841                 /* if pool is empty then remove entry from vfta */
3842                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3843                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3844                         reg = 0;
3845                         vid = reg & E1000_VLVF_VLANID_MASK;
3846                         igb_vfta_set(hw, vid, false);
3847                 }
3848
3849                 wr32(E1000_VLVF(i), reg);
3850         }
3851 }
3852
3853 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3854 {
3855         struct e1000_hw *hw = &adapter->hw;
3856         u32 reg, i;
3857
3858         /* It is an error to call this function when VFs are not enabled */
3859         if (!adapter->vfs_allocated_count)
3860                 return -1;
3861
3862         /* Find the vlan filter for this id */
3863         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3864                 reg = rd32(E1000_VLVF(i));
3865                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3866                     vid == (reg & E1000_VLVF_VLANID_MASK))
3867                         break;
3868         }
3869
3870         if (add) {
3871                 if (i == E1000_VLVF_ARRAY_SIZE) {
3872                         /* Did not find a matching VLAN ID entry that was
3873                          * enabled.  Search for a free filter entry, i.e.
3874                          * one without the enable bit set
3875                          */
3876                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3877                                 reg = rd32(E1000_VLVF(i));
3878                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3879                                         break;
3880                         }
3881                 }
3882                 if (i < E1000_VLVF_ARRAY_SIZE) {
3883                         /* Found an enabled/available entry */
3884                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3885
3886                         /* if !enabled we need to set this up in vfta */
3887                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3888                                 /* add VID to filter table, if bit already set
3889                                  * PF must have added it outside of table */
3890                                 if (igb_vfta_set(hw, vid, true))
3891                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3892                                                 adapter->vfs_allocated_count);
3893                                 reg |= E1000_VLVF_VLANID_ENABLE;
3894                         }
3895                         reg &= ~E1000_VLVF_VLANID_MASK;
3896                         reg |= vid;
3897
3898                         wr32(E1000_VLVF(i), reg);
3899                         return 0;
3900                 }
3901         } else {
3902                 if (i < E1000_VLVF_ARRAY_SIZE) {
3903                         /* remove vf from the pool */
3904                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3905                         /* if pool is empty then remove entry from vfta */
3906                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3907                                 reg = 0;
3908                                 igb_vfta_set(hw, vid, false);
3909                         }
3910                         wr32(E1000_VLVF(i), reg);
3911                         return 0;
3912                 }
3913         }
3914         return -1;
3915 }
3916
3917 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3918 {
3919         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3920         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3921
3922         return igb_vlvf_set(adapter, vid, add, vf);
3923 }
3924
3925 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3926 {
3927         struct e1000_hw *hw = &adapter->hw;
3928
3929         /* disable mailbox functionality for vf */
3930         adapter->vf_data[vf].clear_to_send = false;
3931
3932         /* reset offloads to defaults */
3933         igb_set_vmolr(hw, vf);
3934
3935         /* reset vlans for device */
3936         igb_clear_vf_vfta(adapter, vf);
3937
3938         /* reset multicast table array for vf */
3939         adapter->vf_data[vf].num_vf_mc_hashes = 0;
3940
3941         /* Flush and reset the mta with the new values */
3942         igb_set_multi(adapter->netdev);
3943 }
3944
3945 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
3946 {
3947         struct e1000_hw *hw = &adapter->hw;
3948         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
3949         u32 reg, msgbuf[3];
3950         u8 *addr = (u8 *)(&msgbuf[1]);
3951
3952         /* process all the same items cleared in a function level reset */
3953         igb_vf_reset_event(adapter, vf);
3954
3955         /* set vf mac address */
3956         igb_rar_set(hw, vf_mac, vf + 1);
3957         igb_set_rah_pool(hw, vf, vf + 1);
3958
3959         /* enable transmit and receive for vf */
3960         reg = rd32(E1000_VFTE);
3961         wr32(E1000_VFTE, reg | (1 << vf));
3962         reg = rd32(E1000_VFRE);
3963         wr32(E1000_VFRE, reg | (1 << vf));
3964
3965         /* enable mailbox functionality for vf */
3966         adapter->vf_data[vf].clear_to_send = true;
3967
3968         /* reply to reset with ack and vf mac address */
3969         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
3970         memcpy(addr, vf_mac, 6);
3971         igb_write_mbx(hw, msgbuf, 3, vf);
3972 }
3973
3974 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
3975 {
3976                 unsigned char *addr = (char *)&msg[1];
3977                 int err = -1;
3978
3979                 if (is_valid_ether_addr(addr))
3980                         err = igb_set_vf_mac(adapter, vf, addr);
3981
3982                 return err;
3983
3984 }
3985
3986 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
3987 {
3988         struct e1000_hw *hw = &adapter->hw;
3989         u32 msg = E1000_VT_MSGTYPE_NACK;
3990
3991         /* if device isn't clear to send it shouldn't be reading either */
3992         if (!adapter->vf_data[vf].clear_to_send)
3993                 igb_write_mbx(hw, &msg, 1, vf);
3994 }
3995
3996
3997 static void igb_msg_task(struct igb_adapter *adapter)
3998 {
3999         struct e1000_hw *hw = &adapter->hw;
4000         u32 vf;
4001
4002         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4003                 /* process any reset requests */
4004                 if (!igb_check_for_rst(hw, vf)) {
4005                         adapter->vf_data[vf].clear_to_send = false;
4006                         igb_vf_reset_event(adapter, vf);
4007                 }
4008
4009                 /* process any messages pending */
4010                 if (!igb_check_for_msg(hw, vf))
4011                         igb_rcv_msg_from_vf(adapter, vf);
4012
4013                 /* process any acks */
4014                 if (!igb_check_for_ack(hw, vf))
4015                         igb_rcv_ack_from_vf(adapter, vf);
4016
4017         }
4018 }
4019
4020 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4021 {
4022         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4023         u32 msgbuf[mbx_size];
4024         struct e1000_hw *hw = &adapter->hw;
4025         s32 retval;
4026
4027         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4028
4029         if (retval)
4030                 dev_err(&adapter->pdev->dev,
4031                         "Error receiving message from VF\n");
4032
4033         /* this is a message we already processed, do nothing */
4034         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4035                 return retval;
4036
4037         /*
4038          * until the vf completes a reset it should not be
4039          * allowed to start any configuration.
4040          */
4041
4042         if (msgbuf[0] == E1000_VF_RESET) {
4043                 igb_vf_reset_msg(adapter, vf);
4044
4045                 return retval;
4046         }
4047
4048         if (!adapter->vf_data[vf].clear_to_send) {
4049                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4050                 igb_write_mbx(hw, msgbuf, 1, vf);
4051                 return retval;
4052         }
4053
4054         switch ((msgbuf[0] & 0xFFFF)) {
4055         case E1000_VF_SET_MAC_ADDR:
4056                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4057                 break;
4058         case E1000_VF_SET_MULTICAST:
4059                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4060                 break;
4061         case E1000_VF_SET_LPE:
4062                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4063                 break;
4064         case E1000_VF_SET_VLAN:
4065                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4066                 break;
4067         default:
4068                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4069                 retval = -1;
4070                 break;
4071         }
4072
4073         /* notify the VF of the results of what it sent us */
4074         if (retval)
4075                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4076         else
4077                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4078
4079         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4080
4081         igb_write_mbx(hw, msgbuf, 1, vf);
4082
4083         return retval;
4084 }
4085
4086 /**
4087  * igb_intr_msi - Interrupt Handler
4088  * @irq: interrupt number
4089  * @data: pointer to a network interface device structure
4090  **/
4091 static irqreturn_t igb_intr_msi(int irq, void *data)
4092 {
4093         struct net_device *netdev = data;
4094         struct igb_adapter *adapter = netdev_priv(netdev);
4095         struct e1000_hw *hw = &adapter->hw;
4096         /* read ICR disables interrupts using IAM */
4097         u32 icr = rd32(E1000_ICR);
4098
4099         igb_write_itr(adapter->rx_ring);
4100
4101         if(icr & E1000_ICR_DOUTSYNC) {
4102                 /* HW is reporting DMA is out of sync */
4103                 adapter->stats.doosync++;
4104         }
4105
4106         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4107                 hw->mac.get_link_status = 1;
4108                 if (!test_bit(__IGB_DOWN, &adapter->state))
4109                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4110         }
4111
4112         napi_schedule(&adapter->rx_ring[0].napi);
4113
4114         return IRQ_HANDLED;
4115 }
4116
4117 /**
4118  * igb_intr - Legacy Interrupt Handler
4119  * @irq: interrupt number
4120  * @data: pointer to a network interface device structure
4121  **/
4122 static irqreturn_t igb_intr(int irq, void *data)
4123 {
4124         struct net_device *netdev = data;
4125         struct igb_adapter *adapter = netdev_priv(netdev);
4126         struct e1000_hw *hw = &adapter->hw;
4127         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4128          * need for the IMC write */
4129         u32 icr = rd32(E1000_ICR);
4130         if (!icr)
4131                 return IRQ_NONE;  /* Not our interrupt */
4132
4133         igb_write_itr(adapter->rx_ring);
4134
4135         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4136          * not set, then the adapter didn't send an interrupt */
4137         if (!(icr & E1000_ICR_INT_ASSERTED))
4138                 return IRQ_NONE;
4139
4140         if(icr & E1000_ICR_DOUTSYNC) {
4141                 /* HW is reporting DMA is out of sync */
4142                 adapter->stats.doosync++;
4143         }
4144
4145         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4146                 hw->mac.get_link_status = 1;
4147                 /* guard against interrupt when we're going down */
4148                 if (!test_bit(__IGB_DOWN, &adapter->state))
4149                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4150         }
4151
4152         napi_schedule(&adapter->rx_ring[0].napi);
4153
4154         return IRQ_HANDLED;
4155 }
4156
4157 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4158 {
4159         struct igb_adapter *adapter = rx_ring->adapter;
4160         struct e1000_hw *hw = &adapter->hw;
4161
4162         if (adapter->itr_setting & 3) {
4163                 if (adapter->num_rx_queues == 1)
4164                         igb_set_itr(adapter);
4165                 else
4166                         igb_update_ring_itr(rx_ring);
4167         }
4168
4169         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4170                 if (adapter->msix_entries)
4171                         wr32(E1000_EIMS, rx_ring->eims_value);
4172                 else
4173                         igb_irq_enable(adapter);
4174         }
4175 }
4176
4177 /**
4178  * igb_poll - NAPI Rx polling callback
4179  * @napi: napi polling structure
4180  * @budget: count of how many packets we should handle
4181  **/
4182 static int igb_poll(struct napi_struct *napi, int budget)
4183 {
4184         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4185         int work_done = 0;
4186
4187 #ifdef CONFIG_IGB_DCA
4188         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4189                 igb_update_rx_dca(rx_ring);
4190 #endif
4191         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4192
4193         if (rx_ring->buddy) {
4194 #ifdef CONFIG_IGB_DCA
4195                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4196                         igb_update_tx_dca(rx_ring->buddy);
4197 #endif
4198                 if (!igb_clean_tx_irq(rx_ring->buddy))
4199                         work_done = budget;
4200         }
4201
4202         /* If not enough Rx work done, exit the polling mode */
4203         if (work_done < budget) {
4204                 napi_complete(napi);
4205                 igb_rx_irq_enable(rx_ring);
4206         }
4207
4208         return work_done;
4209 }
4210
4211 /**
4212  * igb_hwtstamp - utility function which checks for TX time stamp
4213  * @adapter: board private structure
4214  * @skb: packet that was just sent
4215  *
4216  * If we were asked to do hardware stamping and such a time stamp is
4217  * available, then it must have been for this skb here because we only
4218  * allow only one such packet into the queue.
4219  */
4220 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4221 {
4222         union skb_shared_tx *shtx = skb_tx(skb);
4223         struct e1000_hw *hw = &adapter->hw;
4224
4225         if (unlikely(shtx->hardware)) {
4226                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4227                 if (valid) {
4228                         u64 regval = rd32(E1000_TXSTMPL);
4229                         u64 ns;
4230                         struct skb_shared_hwtstamps shhwtstamps;
4231
4232                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4233                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4234                         ns = timecounter_cyc2time(&adapter->clock,
4235                                                   regval);
4236                         timecompare_update(&adapter->compare, ns);
4237                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4238                         shhwtstamps.syststamp =
4239                                 timecompare_transform(&adapter->compare, ns);
4240                         skb_tstamp_tx(skb, &shhwtstamps);
4241                 }
4242         }
4243 }
4244
4245 /**
4246  * igb_clean_tx_irq - Reclaim resources after transmit completes
4247  * @adapter: board private structure
4248  * returns true if ring is completely cleaned
4249  **/
4250 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4251 {
4252         struct igb_adapter *adapter = tx_ring->adapter;
4253         struct net_device *netdev = adapter->netdev;
4254         struct e1000_hw *hw = &adapter->hw;
4255         struct igb_buffer *buffer_info;
4256         struct sk_buff *skb;
4257         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4258         unsigned int total_bytes = 0, total_packets = 0;
4259         unsigned int i, eop, count = 0;
4260         bool cleaned = false;
4261
4262         i = tx_ring->next_to_clean;
4263         eop = tx_ring->buffer_info[i].next_to_watch;
4264         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4265
4266         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4267                (count < tx_ring->count)) {
4268                 for (cleaned = false; !cleaned; count++) {
4269                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4270                         buffer_info = &tx_ring->buffer_info[i];
4271                         cleaned = (i == eop);
4272                         skb = buffer_info->skb;
4273
4274                         if (skb) {
4275                                 unsigned int segs, bytecount;
4276                                 /* gso_segs is currently only valid for tcp */
4277                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4278                                 /* multiply data chunks by size of headers */
4279                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4280                                             skb->len;
4281                                 total_packets += segs;
4282                                 total_bytes += bytecount;
4283
4284                                 igb_tx_hwtstamp(adapter, skb);
4285                         }
4286
4287                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4288                         tx_desc->wb.status = 0;
4289
4290                         i++;
4291                         if (i == tx_ring->count)
4292                                 i = 0;
4293                 }
4294                 eop = tx_ring->buffer_info[i].next_to_watch;
4295                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4296         }
4297
4298         tx_ring->next_to_clean = i;
4299
4300         if (unlikely(count &&
4301                      netif_carrier_ok(netdev) &&
4302                      IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4303                 /* Make sure that anybody stopping the queue after this
4304                  * sees the new next_to_clean.
4305                  */
4306                 smp_mb();
4307                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4308                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4309                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4310                         ++adapter->restart_queue;
4311                 }
4312         }
4313
4314         if (tx_ring->detect_tx_hung) {
4315                 /* Detect a transmit hang in hardware, this serializes the
4316                  * check with the clearing of time_stamp and movement of i */
4317                 tx_ring->detect_tx_hung = false;
4318                 if (tx_ring->buffer_info[i].time_stamp &&
4319                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4320                                (adapter->tx_timeout_factor * HZ))
4321                     && !(rd32(E1000_STATUS) &
4322                          E1000_STATUS_TXOFF)) {
4323
4324                         /* detected Tx unit hang */
4325                         dev_err(&adapter->pdev->dev,
4326                                 "Detected Tx Unit Hang\n"
4327                                 "  Tx Queue             <%d>\n"
4328                                 "  TDH                  <%x>\n"
4329                                 "  TDT                  <%x>\n"
4330                                 "  next_to_use          <%x>\n"
4331                                 "  next_to_clean        <%x>\n"
4332                                 "buffer_info[next_to_clean]\n"
4333                                 "  time_stamp           <%lx>\n"
4334                                 "  next_to_watch        <%x>\n"
4335                                 "  jiffies              <%lx>\n"
4336                                 "  desc.status          <%x>\n",
4337                                 tx_ring->queue_index,
4338                                 readl(adapter->hw.hw_addr + tx_ring->head),
4339                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4340                                 tx_ring->next_to_use,
4341                                 tx_ring->next_to_clean,
4342                                 tx_ring->buffer_info[i].time_stamp,
4343                                 eop,
4344                                 jiffies,
4345                                 eop_desc->wb.status);
4346                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4347                 }
4348         }
4349         tx_ring->total_bytes += total_bytes;
4350         tx_ring->total_packets += total_packets;
4351         tx_ring->tx_stats.bytes += total_bytes;
4352         tx_ring->tx_stats.packets += total_packets;
4353         adapter->net_stats.tx_bytes += total_bytes;
4354         adapter->net_stats.tx_packets += total_packets;
4355         return (count < tx_ring->count);
4356 }
4357
4358 /**
4359  * igb_receive_skb - helper function to handle rx indications
4360  * @ring: pointer to receive ring receving this packet
4361  * @status: descriptor status field as written by hardware
4362  * @rx_desc: receive descriptor containing vlan and type information.
4363  * @skb: pointer to sk_buff to be indicated to stack
4364  **/
4365 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4366                             union e1000_adv_rx_desc * rx_desc,
4367                             struct sk_buff *skb)
4368 {
4369         struct igb_adapter * adapter = ring->adapter;
4370         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4371
4372         skb_record_rx_queue(skb, ring->queue_index);
4373         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
4374                 if (vlan_extracted)
4375                         vlan_gro_receive(&ring->napi, adapter->vlgrp,
4376                                          le16_to_cpu(rx_desc->wb.upper.vlan),
4377                                          skb);
4378                 else
4379                         napi_gro_receive(&ring->napi, skb);
4380         } else {
4381                 if (vlan_extracted)
4382                         vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4383                                           le16_to_cpu(rx_desc->wb.upper.vlan));
4384                 else
4385                         netif_receive_skb(skb);
4386         }
4387 }
4388
4389 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4390                                        u32 status_err, struct sk_buff *skb)
4391 {
4392         skb->ip_summed = CHECKSUM_NONE;
4393
4394         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4395         if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4396                 return;
4397         /* TCP/UDP checksum error bit is set */
4398         if (status_err &
4399             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4400                 /* let the stack verify checksum errors */
4401                 adapter->hw_csum_err++;
4402                 return;
4403         }
4404         /* It must be a TCP or UDP packet with a valid checksum */
4405         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4406                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4407
4408         adapter->hw_csum_good++;
4409 }
4410
4411 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4412                                  int *work_done, int budget)
4413 {
4414         struct igb_adapter *adapter = rx_ring->adapter;
4415         struct net_device *netdev = adapter->netdev;
4416         struct e1000_hw *hw = &adapter->hw;
4417         struct pci_dev *pdev = adapter->pdev;
4418         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4419         struct igb_buffer *buffer_info , *next_buffer;
4420         struct sk_buff *skb;
4421         bool cleaned = false;
4422         int cleaned_count = 0;
4423         unsigned int total_bytes = 0, total_packets = 0;
4424         unsigned int i;
4425         u32 length, hlen, staterr;
4426
4427         i = rx_ring->next_to_clean;
4428         buffer_info = &rx_ring->buffer_info[i];
4429         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4430         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4431
4432         while (staterr & E1000_RXD_STAT_DD) {
4433                 if (*work_done >= budget)
4434                         break;
4435                 (*work_done)++;
4436
4437                 skb = buffer_info->skb;
4438                 prefetch(skb->data - NET_IP_ALIGN);
4439                 buffer_info->skb = NULL;
4440
4441                 i++;
4442                 if (i == rx_ring->count)
4443                         i = 0;
4444                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4445                 prefetch(next_rxd);
4446                 next_buffer = &rx_ring->buffer_info[i];
4447
4448                 length = le16_to_cpu(rx_desc->wb.upper.length);
4449                 cleaned = true;
4450                 cleaned_count++;
4451
4452                 if (!adapter->rx_ps_hdr_size) {
4453                         pci_unmap_single(pdev, buffer_info->dma,
4454                                          adapter->rx_buffer_len +
4455                                            NET_IP_ALIGN,
4456                                          PCI_DMA_FROMDEVICE);
4457                         skb_put(skb, length);
4458                         goto send_up;
4459                 }
4460
4461                 /* HW will not DMA in data larger than the given buffer, even
4462                  * if it parses the (NFS, of course) header to be larger.  In
4463                  * that case, it fills the header buffer and spills the rest
4464                  * into the page.
4465                  */
4466                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4467                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4468                 if (hlen > adapter->rx_ps_hdr_size)
4469                         hlen = adapter->rx_ps_hdr_size;
4470
4471                 if (!skb_shinfo(skb)->nr_frags) {
4472                         pci_unmap_single(pdev, buffer_info->dma,
4473                                          adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4474                                          PCI_DMA_FROMDEVICE);
4475                         skb_put(skb, hlen);
4476                 }
4477
4478                 if (length) {
4479                         pci_unmap_page(pdev, buffer_info->page_dma,
4480                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4481                         buffer_info->page_dma = 0;
4482
4483                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4484                                                 buffer_info->page,
4485                                                 buffer_info->page_offset,
4486                                                 length);
4487
4488                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4489                             (page_count(buffer_info->page) != 1))
4490                                 buffer_info->page = NULL;
4491                         else
4492                                 get_page(buffer_info->page);
4493
4494                         skb->len += length;
4495                         skb->data_len += length;
4496
4497                         skb->truesize += length;
4498                 }
4499
4500                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4501                         buffer_info->skb = next_buffer->skb;
4502                         buffer_info->dma = next_buffer->dma;
4503                         next_buffer->skb = skb;
4504                         next_buffer->dma = 0;
4505                         goto next_desc;
4506                 }
4507 send_up:
4508                 /*
4509                  * If this bit is set, then the RX registers contain
4510                  * the time stamp. No other packet will be time
4511                  * stamped until we read these registers, so read the
4512                  * registers to make them available again. Because
4513                  * only one packet can be time stamped at a time, we
4514                  * know that the register values must belong to this
4515                  * one here and therefore we don't need to compare
4516                  * any of the additional attributes stored for it.
4517                  *
4518                  * If nothing went wrong, then it should have a
4519                  * skb_shared_tx that we can turn into a
4520                  * skb_shared_hwtstamps.
4521                  *
4522                  * TODO: can time stamping be triggered (thus locking
4523                  * the registers) without the packet reaching this point
4524                  * here? In that case RX time stamping would get stuck.
4525                  *
4526                  * TODO: in "time stamp all packets" mode this bit is
4527                  * not set. Need a global flag for this mode and then
4528                  * always read the registers. Cannot be done without
4529                  * a race condition.
4530                  */
4531                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4532                         u64 regval;
4533                         u64 ns;
4534                         struct skb_shared_hwtstamps *shhwtstamps =
4535                                 skb_hwtstamps(skb);
4536
4537                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4538                              "igb: no RX time stamp available for time stamped packet");
4539                         regval = rd32(E1000_RXSTMPL);
4540                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4541                         ns = timecounter_cyc2time(&adapter->clock, regval);
4542                         timecompare_update(&adapter->compare, ns);
4543                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4544                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4545                         shhwtstamps->syststamp =
4546                                 timecompare_transform(&adapter->compare, ns);
4547                 }
4548
4549                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4550                         dev_kfree_skb_irq(skb);
4551                         goto next_desc;
4552                 }
4553
4554                 total_bytes += skb->len;
4555                 total_packets++;
4556
4557                 igb_rx_checksum_adv(adapter, staterr, skb);
4558
4559                 skb->protocol = eth_type_trans(skb, netdev);
4560
4561                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4562
4563 next_desc:
4564                 rx_desc->wb.upper.status_error = 0;
4565
4566                 /* return some buffers to hardware, one at a time is too slow */
4567                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4568                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4569                         cleaned_count = 0;
4570                 }
4571
4572                 /* use prefetched values */
4573                 rx_desc = next_rxd;
4574                 buffer_info = next_buffer;
4575                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4576         }
4577
4578         rx_ring->next_to_clean = i;
4579         cleaned_count = IGB_DESC_UNUSED(rx_ring);
4580
4581         if (cleaned_count)
4582                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4583
4584         rx_ring->total_packets += total_packets;
4585         rx_ring->total_bytes += total_bytes;
4586         rx_ring->rx_stats.packets += total_packets;
4587         rx_ring->rx_stats.bytes += total_bytes;
4588         adapter->net_stats.rx_bytes += total_bytes;
4589         adapter->net_stats.rx_packets += total_packets;
4590         return cleaned;
4591 }
4592
4593 /**
4594  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4595  * @adapter: address of board private structure
4596  **/
4597 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4598                                      int cleaned_count)
4599 {
4600         struct igb_adapter *adapter = rx_ring->adapter;
4601         struct net_device *netdev = adapter->netdev;
4602         struct pci_dev *pdev = adapter->pdev;
4603         union e1000_adv_rx_desc *rx_desc;
4604         struct igb_buffer *buffer_info;
4605         struct sk_buff *skb;
4606         unsigned int i;
4607         int bufsz;
4608
4609         i = rx_ring->next_to_use;
4610         buffer_info = &rx_ring->buffer_info[i];
4611
4612         if (adapter->rx_ps_hdr_size)
4613                 bufsz = adapter->rx_ps_hdr_size;
4614         else
4615                 bufsz = adapter->rx_buffer_len;
4616         bufsz += NET_IP_ALIGN;
4617
4618         while (cleaned_count--) {
4619                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4620
4621                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4622                         if (!buffer_info->page) {
4623                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4624                                 if (!buffer_info->page) {
4625                                         adapter->alloc_rx_buff_failed++;
4626                                         goto no_buffers;
4627                                 }
4628                                 buffer_info->page_offset = 0;
4629                         } else {
4630                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4631                         }
4632                         buffer_info->page_dma =
4633                                 pci_map_page(pdev, buffer_info->page,
4634                                              buffer_info->page_offset,
4635                                              PAGE_SIZE / 2,
4636                                              PCI_DMA_FROMDEVICE);
4637                 }
4638
4639                 if (!buffer_info->skb) {
4640                         skb = netdev_alloc_skb(netdev, bufsz);
4641                         if (!skb) {
4642                                 adapter->alloc_rx_buff_failed++;
4643                                 goto no_buffers;
4644                         }
4645
4646                         /* Make buffer alignment 2 beyond a 16 byte boundary
4647                          * this will result in a 16 byte aligned IP header after
4648                          * the 14 byte MAC header is removed
4649                          */
4650                         skb_reserve(skb, NET_IP_ALIGN);
4651
4652                         buffer_info->skb = skb;
4653                         buffer_info->dma = pci_map_single(pdev, skb->data,
4654                                                           bufsz,
4655                                                           PCI_DMA_FROMDEVICE);
4656                 }
4657                 /* Refresh the desc even if buffer_addrs didn't change because
4658                  * each write-back erases this info. */
4659                 if (adapter->rx_ps_hdr_size) {
4660                         rx_desc->read.pkt_addr =
4661                              cpu_to_le64(buffer_info->page_dma);
4662                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4663                 } else {
4664                         rx_desc->read.pkt_addr =
4665                              cpu_to_le64(buffer_info->dma);
4666                         rx_desc->read.hdr_addr = 0;
4667                 }
4668
4669                 i++;
4670                 if (i == rx_ring->count)
4671                         i = 0;
4672                 buffer_info = &rx_ring->buffer_info[i];
4673         }
4674
4675 no_buffers:
4676         if (rx_ring->next_to_use != i) {
4677                 rx_ring->next_to_use = i;
4678                 if (i == 0)
4679                         i = (rx_ring->count - 1);
4680                 else
4681                         i--;
4682
4683                 /* Force memory writes to complete before letting h/w
4684                  * know there are new descriptors to fetch.  (Only
4685                  * applicable for weak-ordered memory model archs,
4686                  * such as IA-64). */
4687                 wmb();
4688                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4689         }
4690 }
4691
4692 /**
4693  * igb_mii_ioctl -
4694  * @netdev:
4695  * @ifreq:
4696  * @cmd:
4697  **/
4698 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4699 {
4700         struct igb_adapter *adapter = netdev_priv(netdev);
4701         struct mii_ioctl_data *data = if_mii(ifr);
4702
4703         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4704                 return -EOPNOTSUPP;
4705
4706         switch (cmd) {
4707         case SIOCGMIIPHY:
4708                 data->phy_id = adapter->hw.phy.addr;
4709                 break;
4710         case SIOCGMIIREG:
4711                 if (!capable(CAP_NET_ADMIN))
4712                         return -EPERM;
4713                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4714                                      &data->val_out))
4715                         return -EIO;
4716                 break;
4717         case SIOCSMIIREG:
4718         default:
4719                 return -EOPNOTSUPP;
4720         }
4721         return 0;
4722 }
4723
4724 /**
4725  * igb_hwtstamp_ioctl - control hardware time stamping
4726  * @netdev:
4727  * @ifreq:
4728  * @cmd:
4729  *
4730  * Outgoing time stamping can be enabled and disabled. Play nice and
4731  * disable it when requested, although it shouldn't case any overhead
4732  * when no packet needs it. At most one packet in the queue may be
4733  * marked for time stamping, otherwise it would be impossible to tell
4734  * for sure to which packet the hardware time stamp belongs.
4735  *
4736  * Incoming time stamping has to be configured via the hardware
4737  * filters. Not all combinations are supported, in particular event
4738  * type has to be specified. Matching the kind of event packet is
4739  * not supported, with the exception of "all V2 events regardless of
4740  * level 2 or 4".
4741  *
4742  **/
4743 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4744                               struct ifreq *ifr, int cmd)
4745 {
4746         struct igb_adapter *adapter = netdev_priv(netdev);
4747         struct e1000_hw *hw = &adapter->hw;
4748         struct hwtstamp_config config;
4749         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4750         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4751         u32 tsync_rx_ctl_type = 0;
4752         u32 tsync_rx_cfg = 0;
4753         int is_l4 = 0;
4754         int is_l2 = 0;
4755         short port = 319; /* PTP */
4756         u32 regval;
4757
4758         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4759                 return -EFAULT;
4760
4761         /* reserved for future extensions */
4762         if (config.flags)
4763                 return -EINVAL;
4764
4765         switch (config.tx_type) {
4766         case HWTSTAMP_TX_OFF:
4767                 tsync_tx_ctl_bit = 0;
4768                 break;
4769         case HWTSTAMP_TX_ON:
4770                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4771                 break;
4772         default:
4773                 return -ERANGE;
4774         }
4775
4776         switch (config.rx_filter) {
4777         case HWTSTAMP_FILTER_NONE:
4778                 tsync_rx_ctl_bit = 0;
4779                 break;
4780         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4781         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4782         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4783         case HWTSTAMP_FILTER_ALL:
4784                 /*
4785                  * register TSYNCRXCFG must be set, therefore it is not
4786                  * possible to time stamp both Sync and Delay_Req messages
4787                  * => fall back to time stamping all packets
4788                  */
4789                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4790                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4791                 break;
4792         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4793                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4794                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4795                 is_l4 = 1;
4796                 break;
4797         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4798                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4799                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4800                 is_l4 = 1;
4801                 break;
4802         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4803         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4804                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4805                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4806                 is_l2 = 1;
4807                 is_l4 = 1;
4808                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4809                 break;
4810         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4811         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4812                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4813                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4814                 is_l2 = 1;
4815                 is_l4 = 1;
4816                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4817                 break;
4818         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4819         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4820         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4821                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4822                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4823                 is_l2 = 1;
4824                 break;
4825         default:
4826                 return -ERANGE;
4827         }
4828
4829         /* enable/disable TX */
4830         regval = rd32(E1000_TSYNCTXCTL);
4831         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4832         wr32(E1000_TSYNCTXCTL, regval);
4833
4834         /* enable/disable RX, define which PTP packets are time stamped */
4835         regval = rd32(E1000_TSYNCRXCTL);
4836         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4837         regval = (regval & ~0xE) | tsync_rx_ctl_type;
4838         wr32(E1000_TSYNCRXCTL, regval);
4839         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4840
4841         /*
4842          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4843          *                                          (Ethertype to filter on)
4844          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4845          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4846          */
4847         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4848
4849         /* L4 Queue Filter[0]: only filter by source and destination port */
4850         wr32(E1000_SPQF0, htons(port));
4851         wr32(E1000_IMIREXT(0), is_l4 ?
4852              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4853         wr32(E1000_IMIR(0), is_l4 ?
4854              (htons(port)
4855               | (0<<16) /* immediate interrupt disabled */
4856               | 0 /* (1<<17) bit cleared: do not bypass
4857                      destination port check */)
4858                 : 0);
4859         wr32(E1000_FTQF0, is_l4 ?
4860              (0x11 /* UDP */
4861               | (1<<15) /* VF not compared */
4862               | (1<<27) /* Enable Timestamping */
4863               | (7<<28) /* only source port filter enabled,
4864                            source/target address and protocol
4865                            masked */)
4866              : ((1<<15) | (15<<28) /* all mask bits set = filter not
4867                                       enabled */));
4868
4869         wrfl();
4870
4871         adapter->hwtstamp_config = config;
4872
4873         /* clear TX/RX time stamp registers, just to be sure */
4874         regval = rd32(E1000_TXSTMPH);
4875         regval = rd32(E1000_RXSTMPH);
4876
4877         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4878                 -EFAULT : 0;
4879 }
4880
4881 /**
4882  * igb_ioctl -
4883  * @netdev:
4884  * @ifreq:
4885  * @cmd:
4886  **/
4887 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4888 {
4889         switch (cmd) {
4890         case SIOCGMIIPHY:
4891         case SIOCGMIIREG:
4892         case SIOCSMIIREG:
4893                 return igb_mii_ioctl(netdev, ifr, cmd);
4894         case SIOCSHWTSTAMP:
4895                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4896         default:
4897                 return -EOPNOTSUPP;
4898         }
4899 }
4900
4901 static void igb_vlan_rx_register(struct net_device *netdev,
4902                                  struct vlan_group *grp)
4903 {
4904         struct igb_adapter *adapter = netdev_priv(netdev);
4905         struct e1000_hw *hw = &adapter->hw;
4906         u32 ctrl, rctl;
4907
4908         igb_irq_disable(adapter);
4909         adapter->vlgrp = grp;
4910
4911         if (grp) {
4912                 /* enable VLAN tag insert/strip */
4913                 ctrl = rd32(E1000_CTRL);
4914                 ctrl |= E1000_CTRL_VME;
4915                 wr32(E1000_CTRL, ctrl);
4916
4917                 /* enable VLAN receive filtering */
4918                 rctl = rd32(E1000_RCTL);
4919                 rctl &= ~E1000_RCTL_CFIEN;
4920                 wr32(E1000_RCTL, rctl);
4921                 igb_update_mng_vlan(adapter);
4922         } else {
4923                 /* disable VLAN tag insert/strip */
4924                 ctrl = rd32(E1000_CTRL);
4925                 ctrl &= ~E1000_CTRL_VME;
4926                 wr32(E1000_CTRL, ctrl);
4927
4928                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4929                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4930                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4931                 }
4932         }
4933
4934         igb_rlpml_set(adapter);
4935
4936         if (!test_bit(__IGB_DOWN, &adapter->state))
4937                 igb_irq_enable(adapter);
4938 }
4939
4940 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4941 {
4942         struct igb_adapter *adapter = netdev_priv(netdev);
4943         struct e1000_hw *hw = &adapter->hw;
4944         int pf_id = adapter->vfs_allocated_count;
4945
4946         if ((hw->mng_cookie.status &
4947              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4948             (vid == adapter->mng_vlan_id))
4949                 return;
4950
4951         /* add vid to vlvf if sr-iov is enabled,
4952          * if that fails add directly to filter table */
4953         if (igb_vlvf_set(adapter, vid, true, pf_id))
4954                 igb_vfta_set(hw, vid, true);
4955
4956 }
4957
4958 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4959 {
4960         struct igb_adapter *adapter = netdev_priv(netdev);
4961         struct e1000_hw *hw = &adapter->hw;
4962         int pf_id = adapter->vfs_allocated_count;
4963
4964         igb_irq_disable(adapter);
4965         vlan_group_set_device(adapter->vlgrp, vid, NULL);
4966
4967         if (!test_bit(__IGB_DOWN, &adapter->state))
4968                 igb_irq_enable(adapter);
4969
4970         if ((adapter->hw.mng_cookie.status &
4971              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4972             (vid == adapter->mng_vlan_id)) {
4973                 /* release control to f/w */
4974                 igb_release_hw_control(adapter);
4975                 return;
4976         }
4977
4978         /* remove vid from vlvf if sr-iov is enabled,
4979          * if not in vlvf remove from vfta */
4980         if (igb_vlvf_set(adapter, vid, false, pf_id))
4981                 igb_vfta_set(hw, vid, false);
4982 }
4983
4984 static void igb_restore_vlan(struct igb_adapter *adapter)
4985 {
4986         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4987
4988         if (adapter->vlgrp) {
4989                 u16 vid;
4990                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4991                         if (!vlan_group_get_device(adapter->vlgrp, vid))
4992                                 continue;
4993                         igb_vlan_rx_add_vid(adapter->netdev, vid);
4994                 }
4995         }
4996 }
4997
4998 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4999 {
5000         struct e1000_mac_info *mac = &adapter->hw.mac;
5001
5002         mac->autoneg = 0;
5003
5004         /* Fiber NICs only allow 1000 gbps Full duplex */
5005         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5006                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5007                 dev_err(&adapter->pdev->dev,
5008                         "Unsupported Speed/Duplex configuration\n");
5009                 return -EINVAL;
5010         }
5011
5012         switch (spddplx) {
5013         case SPEED_10 + DUPLEX_HALF:
5014                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5015                 break;
5016         case SPEED_10 + DUPLEX_FULL:
5017                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5018                 break;
5019         case SPEED_100 + DUPLEX_HALF:
5020                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5021                 break;
5022         case SPEED_100 + DUPLEX_FULL:
5023                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5024                 break;
5025         case SPEED_1000 + DUPLEX_FULL:
5026                 mac->autoneg = 1;
5027                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5028                 break;
5029         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5030         default:
5031                 dev_err(&adapter->pdev->dev,
5032                         "Unsupported Speed/Duplex configuration\n");
5033                 return -EINVAL;
5034         }
5035         return 0;
5036 }
5037
5038 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5039 {
5040         struct net_device *netdev = pci_get_drvdata(pdev);
5041         struct igb_adapter *adapter = netdev_priv(netdev);
5042         struct e1000_hw *hw = &adapter->hw;
5043         u32 ctrl, rctl, status;
5044         u32 wufc = adapter->wol;
5045 #ifdef CONFIG_PM
5046         int retval = 0;
5047 #endif
5048
5049         netif_device_detach(netdev);
5050
5051         if (netif_running(netdev))
5052                 igb_close(netdev);
5053
5054         igb_reset_interrupt_capability(adapter);
5055
5056         igb_free_queues(adapter);
5057
5058 #ifdef CONFIG_PM
5059         retval = pci_save_state(pdev);
5060         if (retval)
5061                 return retval;
5062 #endif
5063
5064         status = rd32(E1000_STATUS);
5065         if (status & E1000_STATUS_LU)
5066                 wufc &= ~E1000_WUFC_LNKC;
5067
5068         if (wufc) {
5069                 igb_setup_rctl(adapter);
5070                 igb_set_multi(netdev);
5071
5072                 /* turn on all-multi mode if wake on multicast is enabled */
5073                 if (wufc & E1000_WUFC_MC) {
5074                         rctl = rd32(E1000_RCTL);
5075                         rctl |= E1000_RCTL_MPE;
5076                         wr32(E1000_RCTL, rctl);
5077                 }
5078
5079                 ctrl = rd32(E1000_CTRL);
5080                 /* advertise wake from D3Cold */
5081                 #define E1000_CTRL_ADVD3WUC 0x00100000
5082                 /* phy power management enable */
5083                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5084                 ctrl |= E1000_CTRL_ADVD3WUC;
5085                 wr32(E1000_CTRL, ctrl);
5086
5087                 /* Allow time for pending master requests to run */
5088                 igb_disable_pcie_master(&adapter->hw);
5089
5090                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5091                 wr32(E1000_WUFC, wufc);
5092         } else {
5093                 wr32(E1000_WUC, 0);
5094                 wr32(E1000_WUFC, 0);
5095         }
5096
5097         /* make sure adapter isn't asleep if manageability/wol is enabled */
5098         if (wufc || adapter->en_mng_pt) {
5099                 pci_enable_wake(pdev, PCI_D3hot, 1);
5100                 pci_enable_wake(pdev, PCI_D3cold, 1);
5101         } else {
5102                 igb_shutdown_fiber_serdes_link_82575(hw);
5103                 pci_enable_wake(pdev, PCI_D3hot, 0);
5104                 pci_enable_wake(pdev, PCI_D3cold, 0);
5105         }
5106
5107         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5108          * would have already happened in close and is redundant. */
5109         igb_release_hw_control(adapter);
5110
5111         pci_disable_device(pdev);
5112
5113         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5114
5115         return 0;
5116 }
5117
5118 #ifdef CONFIG_PM
5119 static int igb_resume(struct pci_dev *pdev)
5120 {
5121         struct net_device *netdev = pci_get_drvdata(pdev);
5122         struct igb_adapter *adapter = netdev_priv(netdev);
5123         struct e1000_hw *hw = &adapter->hw;
5124         u32 err;
5125
5126         pci_set_power_state(pdev, PCI_D0);
5127         pci_restore_state(pdev);
5128
5129         err = pci_enable_device_mem(pdev);
5130         if (err) {
5131                 dev_err(&pdev->dev,
5132                         "igb: Cannot enable PCI device from suspend\n");
5133                 return err;
5134         }
5135         pci_set_master(pdev);
5136
5137         pci_enable_wake(pdev, PCI_D3hot, 0);
5138         pci_enable_wake(pdev, PCI_D3cold, 0);
5139
5140         igb_set_interrupt_capability(adapter);
5141
5142         if (igb_alloc_queues(adapter)) {
5143                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5144                 return -ENOMEM;
5145         }
5146
5147         /* e1000_power_up_phy(adapter); */
5148
5149         igb_reset(adapter);
5150
5151         /* let the f/w know that the h/w is now under the control of the
5152          * driver. */
5153         igb_get_hw_control(adapter);
5154
5155         wr32(E1000_WUS, ~0);
5156
5157         if (netif_running(netdev)) {
5158                 err = igb_open(netdev);
5159                 if (err)
5160                         return err;
5161         }
5162
5163         netif_device_attach(netdev);
5164
5165         return 0;
5166 }
5167 #endif
5168
5169 static void igb_shutdown(struct pci_dev *pdev)
5170 {
5171         igb_suspend(pdev, PMSG_SUSPEND);
5172 }
5173
5174 #ifdef CONFIG_NET_POLL_CONTROLLER
5175 /*
5176  * Polling 'interrupt' - used by things like netconsole to send skbs
5177  * without having to re-enable interrupts. It's not called while
5178  * the interrupt routine is executing.
5179  */
5180 static void igb_netpoll(struct net_device *netdev)
5181 {
5182         struct igb_adapter *adapter = netdev_priv(netdev);
5183         struct e1000_hw *hw = &adapter->hw;
5184         int i;
5185
5186         if (!adapter->msix_entries) {
5187                 igb_irq_disable(adapter);
5188                 napi_schedule(&adapter->rx_ring[0].napi);
5189                 return;
5190         }
5191
5192         for (i = 0; i < adapter->num_tx_queues; i++) {
5193                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5194                 wr32(E1000_EIMC, tx_ring->eims_value);
5195                 igb_clean_tx_irq(tx_ring);
5196                 wr32(E1000_EIMS, tx_ring->eims_value);
5197         }
5198
5199         for (i = 0; i < adapter->num_rx_queues; i++) {
5200                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5201                 wr32(E1000_EIMC, rx_ring->eims_value);
5202                 napi_schedule(&rx_ring->napi);
5203         }
5204 }
5205 #endif /* CONFIG_NET_POLL_CONTROLLER */
5206
5207 /**
5208  * igb_io_error_detected - called when PCI error is detected
5209  * @pdev: Pointer to PCI device
5210  * @state: The current pci connection state
5211  *
5212  * This function is called after a PCI bus error affecting
5213  * this device has been detected.
5214  */
5215 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5216                                               pci_channel_state_t state)
5217 {
5218         struct net_device *netdev = pci_get_drvdata(pdev);
5219         struct igb_adapter *adapter = netdev_priv(netdev);
5220
5221         netif_device_detach(netdev);
5222
5223         if (netif_running(netdev))
5224                 igb_down(adapter);
5225         pci_disable_device(pdev);
5226
5227         /* Request a slot slot reset. */
5228         return PCI_ERS_RESULT_NEED_RESET;
5229 }
5230
5231 /**
5232  * igb_io_slot_reset - called after the pci bus has been reset.
5233  * @pdev: Pointer to PCI device
5234  *
5235  * Restart the card from scratch, as if from a cold-boot. Implementation
5236  * resembles the first-half of the igb_resume routine.
5237  */
5238 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5239 {
5240         struct net_device *netdev = pci_get_drvdata(pdev);
5241         struct igb_adapter *adapter = netdev_priv(netdev);
5242         struct e1000_hw *hw = &adapter->hw;
5243         pci_ers_result_t result;
5244         int err;
5245
5246         if (pci_enable_device_mem(pdev)) {
5247                 dev_err(&pdev->dev,
5248                         "Cannot re-enable PCI device after reset.\n");
5249                 result = PCI_ERS_RESULT_DISCONNECT;
5250         } else {
5251                 pci_set_master(pdev);
5252                 pci_restore_state(pdev);
5253
5254                 pci_enable_wake(pdev, PCI_D3hot, 0);
5255                 pci_enable_wake(pdev, PCI_D3cold, 0);
5256
5257                 igb_reset(adapter);
5258                 wr32(E1000_WUS, ~0);
5259                 result = PCI_ERS_RESULT_RECOVERED;
5260         }
5261
5262         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5263         if (err) {
5264                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5265                         "failed 0x%0x\n", err);
5266                 /* non-fatal, continue */
5267         }
5268
5269         return result;
5270 }
5271
5272 /**
5273  * igb_io_resume - called when traffic can start flowing again.
5274  * @pdev: Pointer to PCI device
5275  *
5276  * This callback is called when the error recovery driver tells us that
5277  * its OK to resume normal operation. Implementation resembles the
5278  * second-half of the igb_resume routine.
5279  */
5280 static void igb_io_resume(struct pci_dev *pdev)
5281 {
5282         struct net_device *netdev = pci_get_drvdata(pdev);
5283         struct igb_adapter *adapter = netdev_priv(netdev);
5284
5285         if (netif_running(netdev)) {
5286                 if (igb_up(adapter)) {
5287                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5288                         return;
5289                 }
5290         }
5291
5292         netif_device_attach(netdev);
5293
5294         /* let the f/w know that the h/w is now under the control of the
5295          * driver. */
5296         igb_get_hw_control(adapter);
5297 }
5298
5299 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5300 {
5301         u32 reg_data;
5302
5303         reg_data = rd32(E1000_VMOLR(vfn));
5304         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
5305                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
5306                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
5307                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
5308                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5309         wr32(E1000_VMOLR(vfn), reg_data);
5310 }
5311
5312 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5313                                  int vfn)
5314 {
5315         struct e1000_hw *hw = &adapter->hw;
5316         u32 vmolr;
5317
5318         vmolr = rd32(E1000_VMOLR(vfn));
5319         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5320         vmolr |= size | E1000_VMOLR_LPE;
5321         wr32(E1000_VMOLR(vfn), vmolr);
5322
5323         return 0;
5324 }
5325
5326 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5327 {
5328         u32 reg_data;
5329
5330         reg_data = rd32(E1000_RAH(entry));
5331         reg_data &= ~E1000_RAH_POOL_MASK;
5332         reg_data |= E1000_RAH_POOL_1 << pool;;
5333         wr32(E1000_RAH(entry), reg_data);
5334 }
5335
5336 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5337                                   int entry_count, u16 total_rar_filters)
5338 {
5339         struct e1000_hw *hw = &adapter->hw;
5340         int i = adapter->vfs_allocated_count + 1;
5341
5342         if ((i + entry_count) < total_rar_filters)
5343                 total_rar_filters = i + entry_count;
5344
5345         for (; i < total_rar_filters; i++)
5346                 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5347 }
5348
5349 static int igb_set_vf_mac(struct igb_adapter *adapter,
5350                           int vf, unsigned char *mac_addr)
5351 {
5352         struct e1000_hw *hw = &adapter->hw;
5353         int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5354
5355         igb_rar_set(hw, mac_addr, rar_entry);
5356
5357         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5358
5359         igb_set_rah_pool(hw, vf, rar_entry);
5360
5361         return 0;
5362 }
5363
5364 static void igb_vmm_control(struct igb_adapter *adapter)
5365 {
5366         struct e1000_hw *hw = &adapter->hw;
5367         u32 reg_data;
5368
5369         if (!adapter->vfs_allocated_count)
5370                 return;
5371
5372         /* VF's need PF reset indication before they
5373          * can send/receive mail */
5374         reg_data = rd32(E1000_CTRL_EXT);
5375         reg_data |= E1000_CTRL_EXT_PFRSTD;
5376         wr32(E1000_CTRL_EXT, reg_data);
5377
5378         igb_vmdq_set_loopback_pf(hw, true);
5379         igb_vmdq_set_replication_pf(hw, true);
5380 }
5381
5382 #ifdef CONFIG_PCI_IOV
5383 static ssize_t igb_show_num_vfs(struct device *dev,
5384                                 struct device_attribute *attr, char *buf)
5385 {
5386         struct igb_adapter *adapter = netdev_priv(to_net_dev(dev));
5387
5388         return sprintf(buf, "%d\n", adapter->vfs_allocated_count);
5389 }
5390
5391 static ssize_t igb_set_num_vfs(struct device *dev,
5392                                struct device_attribute *attr,
5393                                const char *buf, size_t count)
5394 {
5395         struct net_device *netdev = to_net_dev(dev);
5396         struct igb_adapter *adapter = netdev_priv(netdev);
5397         struct e1000_hw *hw = &adapter->hw;
5398         struct pci_dev *pdev = adapter->pdev;
5399         unsigned int num_vfs, i;
5400         unsigned char mac_addr[ETH_ALEN];
5401         int err;
5402
5403         sscanf(buf, "%u", &num_vfs);
5404
5405         if (num_vfs > 7)
5406                 num_vfs = 7;
5407
5408         /* value unchanged do nothing */
5409         if (num_vfs == adapter->vfs_allocated_count)
5410                 return count;
5411
5412         if (netdev->flags & IFF_UP)
5413                 igb_close(netdev);
5414
5415         igb_reset_interrupt_capability(adapter);
5416         igb_free_queues(adapter);
5417         adapter->tx_ring = NULL;
5418         adapter->rx_ring = NULL;
5419         adapter->vfs_allocated_count = 0;
5420
5421         /* reclaim resources allocated to VFs since we are changing count */
5422         if (adapter->vf_data) {
5423                 /* disable iov and allow time for transactions to clear */
5424                 pci_disable_sriov(pdev);
5425                 msleep(500);
5426
5427                 kfree(adapter->vf_data);
5428                 adapter->vf_data = NULL;
5429                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
5430                 msleep(100);
5431                 dev_info(&pdev->dev, "IOV Disabled\n");
5432         }
5433
5434         if (num_vfs) {
5435                 adapter->vf_data = kcalloc(num_vfs,
5436                                            sizeof(struct vf_data_storage),
5437                                            GFP_KERNEL);
5438                 if (!adapter->vf_data) {
5439                         dev_err(&pdev->dev, "Could not allocate VF private "
5440                                 "data - IOV enable failed\n");
5441                 } else {
5442                         err = pci_enable_sriov(pdev, num_vfs);
5443                         if (!err) {
5444                                 adapter->vfs_allocated_count = num_vfs;
5445                                 dev_info(&pdev->dev, "%d vfs allocated\n", num_vfs);
5446                                 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5447                                         random_ether_addr(mac_addr);
5448                                         igb_set_vf_mac(adapter, i, mac_addr);
5449                                 }
5450                         } else {
5451                                 kfree(adapter->vf_data);
5452                                 adapter->vf_data = NULL;
5453                         }
5454                 }
5455         }
5456
5457         igb_set_interrupt_capability(adapter);
5458         igb_alloc_queues(adapter);
5459         igb_reset(adapter);
5460
5461         if (netdev->flags & IFF_UP)
5462                 igb_open(netdev);
5463
5464         return count;
5465 }
5466 #endif /* CONFIG_PCI_IOV */
5467 /* igb_main.c */