2 * arch/arm/mach-at91/at91cap9.c
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
15 #include <linux/module.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/arch/at91cap9.h>
20 #include <asm/arch/at91_pmc.h>
21 #include <asm/arch/at91_rstc.h>
26 static struct map_desc at91cap9_io_desc[] __initdata = {
28 .virtual = AT91_VA_BASE_SYS,
29 .pfn = __phys_to_pfn(AT91_BASE_SYS),
33 .virtual = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE,
34 .pfn = __phys_to_pfn(AT91CAP9_SRAM_BASE),
35 .length = AT91CAP9_SRAM_SIZE,
40 /* --------------------------------------------------------------------
42 * -------------------------------------------------------------------- */
45 * The peripheral clocks.
47 static struct clk pioABCD_clk = {
48 .name = "pioABCD_clk",
49 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
50 .type = CLK_TYPE_PERIPHERAL,
52 static struct clk mpb0_clk = {
54 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
55 .type = CLK_TYPE_PERIPHERAL,
57 static struct clk mpb1_clk = {
59 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
60 .type = CLK_TYPE_PERIPHERAL,
62 static struct clk mpb2_clk = {
64 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
65 .type = CLK_TYPE_PERIPHERAL,
67 static struct clk mpb3_clk = {
69 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
70 .type = CLK_TYPE_PERIPHERAL,
72 static struct clk mpb4_clk = {
74 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
75 .type = CLK_TYPE_PERIPHERAL,
77 static struct clk usart0_clk = {
79 .pmc_mask = 1 << AT91CAP9_ID_US0,
80 .type = CLK_TYPE_PERIPHERAL,
82 static struct clk usart1_clk = {
84 .pmc_mask = 1 << AT91CAP9_ID_US1,
85 .type = CLK_TYPE_PERIPHERAL,
87 static struct clk usart2_clk = {
89 .pmc_mask = 1 << AT91CAP9_ID_US2,
90 .type = CLK_TYPE_PERIPHERAL,
92 static struct clk mmc0_clk = {
94 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
95 .type = CLK_TYPE_PERIPHERAL,
97 static struct clk mmc1_clk = {
99 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
100 .type = CLK_TYPE_PERIPHERAL,
102 static struct clk can_clk = {
104 .pmc_mask = 1 << AT91CAP9_ID_CAN,
105 .type = CLK_TYPE_PERIPHERAL,
107 static struct clk twi_clk = {
109 .pmc_mask = 1 << AT91CAP9_ID_TWI,
110 .type = CLK_TYPE_PERIPHERAL,
112 static struct clk spi0_clk = {
114 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
115 .type = CLK_TYPE_PERIPHERAL,
117 static struct clk spi1_clk = {
119 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
120 .type = CLK_TYPE_PERIPHERAL,
122 static struct clk ssc0_clk = {
124 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
125 .type = CLK_TYPE_PERIPHERAL,
127 static struct clk ssc1_clk = {
129 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
130 .type = CLK_TYPE_PERIPHERAL,
132 static struct clk ac97_clk = {
134 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
135 .type = CLK_TYPE_PERIPHERAL,
137 static struct clk tcb_clk = {
139 .pmc_mask = 1 << AT91CAP9_ID_TCB,
140 .type = CLK_TYPE_PERIPHERAL,
142 static struct clk pwmc_clk = {
144 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
145 .type = CLK_TYPE_PERIPHERAL,
147 static struct clk macb_clk = {
149 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
150 .type = CLK_TYPE_PERIPHERAL,
152 static struct clk aestdes_clk = {
153 .name = "aestdes_clk",
154 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
155 .type = CLK_TYPE_PERIPHERAL,
157 static struct clk adc_clk = {
159 .pmc_mask = 1 << AT91CAP9_ID_ADC,
160 .type = CLK_TYPE_PERIPHERAL,
162 static struct clk isi_clk = {
164 .pmc_mask = 1 << AT91CAP9_ID_ISI,
165 .type = CLK_TYPE_PERIPHERAL,
167 static struct clk lcdc_clk = {
169 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
170 .type = CLK_TYPE_PERIPHERAL,
172 static struct clk dma_clk = {
174 .pmc_mask = 1 << AT91CAP9_ID_DMA,
175 .type = CLK_TYPE_PERIPHERAL,
177 static struct clk udphs_clk = {
179 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
180 .type = CLK_TYPE_PERIPHERAL,
182 static struct clk ohci_clk = {
184 .pmc_mask = 1 << AT91CAP9_ID_UHP,
185 .type = CLK_TYPE_PERIPHERAL,
188 static struct clk *periph_clocks[] __initdata = {
221 * The four programmable clocks.
222 * You must configure pin multiplexing to bring these signals out.
224 static struct clk pck0 = {
226 .pmc_mask = AT91_PMC_PCK0,
227 .type = CLK_TYPE_PROGRAMMABLE,
230 static struct clk pck1 = {
232 .pmc_mask = AT91_PMC_PCK1,
233 .type = CLK_TYPE_PROGRAMMABLE,
236 static struct clk pck2 = {
238 .pmc_mask = AT91_PMC_PCK2,
239 .type = CLK_TYPE_PROGRAMMABLE,
242 static struct clk pck3 = {
244 .pmc_mask = AT91_PMC_PCK3,
245 .type = CLK_TYPE_PROGRAMMABLE,
249 static void __init at91cap9_register_clocks(void)
253 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
254 clk_register(periph_clocks[i]);
262 /* --------------------------------------------------------------------
264 * -------------------------------------------------------------------- */
266 static struct at91_gpio_bank at91cap9_gpio[] = {
268 .id = AT91CAP9_ID_PIOABCD,
270 .clock = &pioABCD_clk,
272 .id = AT91CAP9_ID_PIOABCD,
274 .clock = &pioABCD_clk,
276 .id = AT91CAP9_ID_PIOABCD,
278 .clock = &pioABCD_clk,
280 .id = AT91CAP9_ID_PIOABCD,
282 .clock = &pioABCD_clk,
286 static void at91cap9_reset(void)
288 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
291 /* --------------------------------------------------------------------
292 * AT91CAP9 processor initialization
293 * -------------------------------------------------------------------- */
295 void __init at91cap9_initialize(unsigned long main_clock)
297 /* Map peripherals */
298 iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
300 at91_arch_reset = at91cap9_reset;
301 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
303 /* Init clock subsystem */
304 at91_clock_init(main_clock);
306 /* Register the processor-specific clocks */
307 at91cap9_register_clocks();
309 /* Register GPIO subsystem */
310 at91_gpio_init(at91cap9_gpio, 4);
313 /* --------------------------------------------------------------------
314 * Interrupt initialization
315 * -------------------------------------------------------------------- */
318 * The default interrupt priority levels (0 = lowest, 7 = highest).
320 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
321 7, /* Advanced Interrupt Controller (FIQ) */
322 7, /* System Peripherals */
323 1, /* Parallel IO Controller A, B, C and D */
324 0, /* MP Block Peripheral 0 */
325 0, /* MP Block Peripheral 1 */
326 0, /* MP Block Peripheral 2 */
327 0, /* MP Block Peripheral 3 */
328 0, /* MP Block Peripheral 4 */
332 0, /* Multimedia Card Interface 0 */
333 0, /* Multimedia Card Interface 1 */
335 6, /* Two-Wire Interface */
336 5, /* Serial Peripheral Interface 0 */
337 5, /* Serial Peripheral Interface 1 */
338 4, /* Serial Synchronous Controller 0 */
339 4, /* Serial Synchronous Controller 1 */
340 5, /* AC97 Controller */
341 0, /* Timer Counter 0, 1 and 2 */
342 0, /* Pulse Width Modulation Controller */
344 0, /* Advanced Encryption Standard, Triple DES*/
345 0, /* Analog-to-Digital Converter */
346 0, /* Image Sensor Interface */
347 3, /* LCD Controller */
348 0, /* DMA Controller */
349 2, /* USB Device Port */
350 2, /* USB Host port */
351 0, /* Advanced Interrupt Controller (IRQ0) */
352 0, /* Advanced Interrupt Controller (IRQ1) */
355 void __init at91cap9_init_interrupts(unsigned int priority[NR_AIC_IRQS])
358 priority = at91cap9_default_irq_priority;
360 /* Initialize the AIC interrupt controller */
361 at91_aic_init(priority);
363 /* Enable GPIO interrupts */
364 at91_gpio_irq_setup();