git.oblomov.eu Git - linux-2.6/blob - drivers/net/ucc_geth.h

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *
   6  * Description:
   7  * Internal header file for UCC Gigabit Ethernet unit routines.
   8  *
   9  * Changelog:
  10  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  11  * - Rearrange code and style fixes
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18 #ifndef __UCC_GETH_H__
  19 #define __UCC_GETH_H__
  20
  21 #include <linux/kernel.h>
  22 #include <linux/list.h>
  23 #include <linux/fsl_devices.h>
  24
  25 #include <asm/immap_qe.h>
  26 #include <asm/qe.h>
  27
  28 #include <asm/ucc.h>
  29 #include <asm/ucc_fast.h>
  30
  31 #include "ucc_geth_mii.h"
  32
  33 #define DRV_DESC "QE UCC Gigabit Ethernet Controller"
  34 #define DRV_NAME "ucc_geth"
  35 #define DRV_VERSION "1.1"
  36
  37 #define NUM_TX_QUEUES                   8
  38 #define NUM_RX_QUEUES                   8
  39 #define NUM_BDS_IN_PREFETCHED_BDS       4
  40 #define TX_IP_OFFSET_ENTRY_MAX          8
  41 #define NUM_OF_PADDRS                   4
  42 #define ENET_INIT_PARAM_MAX_ENTRIES_RX  9
  43 #define ENET_INIT_PARAM_MAX_ENTRIES_TX  8
  44
  45 struct ucc_geth {
  46         struct ucc_fast uccf;
  47         u8 res0[0x100 - sizeof(struct ucc_fast)];
  48
  49         u32 maccfg1;            /* mac configuration reg. 1 */
  50         u32 maccfg2;            /* mac configuration reg. 2 */
  51         u32 ipgifg;             /* interframe gap reg.  */
  52         u32 hafdup;             /* half-duplex reg.  */
  53         u8 res1[0x10];
  54         u8 miimng[0x18];        /* MII management structure moved to _mii.h */
  55         u32 ifctl;              /* interface control reg */
  56         u32 ifstat;             /* interface statux reg */
  57         u32 macstnaddr1;        /* mac station address part 1 reg */
  58         u32 macstnaddr2;        /* mac station address part 2 reg */
  59         u8 res2[0x8];
  60         u32 uempr;              /* UCC Ethernet Mac parameter reg */
  61         u32 utbipar;            /* UCC tbi address reg */
  62         u16 uescr;              /* UCC Ethernet statistics control reg */
  63         u8 res3[0x180 - 0x15A];
  64         u32 tx64;               /* Total number of frames (including bad
  65                                    frames) transmitted that were exactly of the
  66                                    minimal length (64 for un tagged, 68 for
  67                                    tagged, or with length exactly equal to the
  68                                    parameter MINLength */
  69         u32 tx127;              /* Total number of frames (including bad
  70                                    frames) transmitted that were between
  71                                    MINLength (Including FCS length==4) and 127
  72                                    octets */
  73         u32 tx255;              /* Total number of frames (including bad
  74                                    frames) transmitted that were between 128
  75                                    (Including FCS length==4) and 255 octets */
  76         u32 rx64;               /* Total number of frames received including
  77                                    bad frames that were exactly of the mninimal
  78                                    length (64 bytes) */
  79         u32 rx127;              /* Total number of frames (including bad
  80                                    frames) received that were between MINLength
  81                                    (Including FCS length==4) and 127 octets */
  82         u32 rx255;              /* Total number of frames (including bad
  83                                    frames) received that were between 128
  84                                    (Including FCS length==4) and 255 octets */
  85         u32 txok;               /* Total number of octets residing in frames
  86                                    that where involved in succesfull
  87                                    transmission */
  88         u16 txcf;               /* Total number of PAUSE control frames
  89                                    transmitted by this MAC */
  90         u8 res4[0x2];
  91         u32 tmca;               /* Total number of frames that were transmitted
  92                                    succesfully with the group address bit set
  93                                    that are not broadcast frames */
  94         u32 tbca;               /* Total number of frames transmitted
  95                                    succesfully that had destination address
  96                                    field equal to the broadcast address */
  97         u32 rxfok;              /* Total number of frames received OK */
  98         u32 rxbok;              /* Total number of octets received OK */
  99         u32 rbyt;               /* Total number of octets received including
 100                                    octets in bad frames. Must be implemented in
 101                                    HW because it includes octets in frames that
 102                                    never even reach the UCC */
 103         u32 rmca;               /* Total number of frames that were received
 104                                    succesfully with the group address bit set
 105                                    that are not broadcast frames */
 106         u32 rbca;               /* Total number of frames received succesfully
 107                                    that had destination address equal to the
 108                                    broadcast address */
 109         u32 scar;               /* Statistics carry register */
 110         u32 scam;               /* Statistics caryy mask register */
 111         u8 res5[0x200 - 0x1c4];
 112 } __attribute__ ((packed));
 113
 114 /* UCC GETH TEMODR Register */
 115 #define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100  /* enable Tx statistics
 116                                                          */
 117 #define TEMODER_SCHEDULER_ENABLE                0x2000  /* enable scheduler */
 118 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400  /* generate IPv4
 119                                                            checksums */
 120 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200  /* enable performance
 121                                                            optimization
 122                                                            enhancement (mode1) */
 123 #define TEMODER_RMON_STATISTICS                 0x0100  /* enable tx statistics
 124                                                          */
 125 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15) /* Number of queues <<
 126                                                            shift */
 127
 128 /* UCC GETH TEMODR Register */
 129 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000      /* enable Rx
 130                                                                    statistics */
 131 #define REMODER_RX_EXTENDED_FEATURES            0x80000000      /* enable
 132                                                                    extended
 133                                                                    features */
 134 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 ) /* vlan operation
 135                                                            tagged << shift */
 136 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
 137                                                            tagged << shift */
 138 #define REMODER_RX_QOS_MODE_SHIFT               (31-15) /* rx QoS mode << shift
 139                                                          */
 140 #define REMODER_RMON_STATISTICS                 0x00001000      /* enable rx
 141                                                                    statistics */
 142 #define REMODER_RX_EXTENDED_FILTERING           0x00000800      /* extended
 143                                                                    filtering
 144                                                                    vs.
 145                                                                    mpc82xx-like
 146                                                                    filtering */
 147 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23) /* Number of queues <<
 148                                                            shift */
 149 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008      /* enable
 150                                                                    dynamic max
 151                                                                    frame length
 152                                                                  */
 153 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004      /* enable
 154                                                                    dynamic min
 155                                                                    frame length
 156                                                                  */
 157 #define REMODER_IP_CHECKSUM_CHECK               0x00000002      /* check IPv4
 158                                                                    checksums */
 159 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001      /* align ip
 160                                                                    address to
 161                                                                    4-byte
 162                                                                    boundary */
 163
 164 /* UCC GETH Event Register */
 165 #define UCCE_TXB   (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
 166                     UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
 167                     UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
 168                     UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
 169
 170 #define UCCE_RXB   (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
 171                     UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
 172                     UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
 173                     UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
 174
 175 #define UCCE_RXF   (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
 176                     UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
 177                     UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
 178                     UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
 179
 180 #define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
 181                     UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
 182                     UCC_GETH_UCCE_RXC  | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
 183
 184 #define UCCE_RX_EVENTS  (UCCE_RXF | UCC_GETH_UCCE_BSY)
 185 #define UCCE_TX_EVENTS  (UCCE_TXB | UCC_GETH_UCCE_TXE)
 186
 187 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
 188 #define MACCFG1_FLOW_RX                         0x00000020      /* Flow Control
 189                                                                    Rx */
 190 #define MACCFG1_FLOW_TX                         0x00000010      /* Flow Control
 191                                                                    Tx */
 192 #define MACCFG1_ENABLE_SYNCHED_RX               0x00000008      /* Rx Enable
 193                                                                    synchronized
 194                                                                    to Rx stream
 195                                                                  */
 196 #define MACCFG1_ENABLE_RX                       0x00000004      /* Enable Rx */
 197 #define MACCFG1_ENABLE_SYNCHED_TX               0x00000002      /* Tx Enable
 198                                                                    synchronized
 199                                                                    to Tx stream
 200                                                                  */
 201 #define MACCFG1_ENABLE_TX                       0x00000001      /* Enable Tx */
 202
 203 /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
 204 #define MACCFG2_PREL_SHIFT                      (31 - 19)       /* Preamble
 205                                                                    Length <<
 206                                                                    shift */
 207 #define MACCFG2_PREL_MASK                       0x0000f000      /* Preamble
 208                                                                    Length mask */
 209 #define MACCFG2_SRP                             0x00000080      /* Soft Receive
 210                                                                    Preamble */
 211 #define MACCFG2_STP                             0x00000040      /* Soft
 212                                                                    Transmit
 213                                                                    Preamble */
 214 #define MACCFG2_RESERVED_1                      0x00000020      /* Reserved -
 215                                                                    must be set
 216                                                                    to 1 */
 217 #define MACCFG2_LC                              0x00000010      /* Length Check
 218                                                                  */
 219 #define MACCFG2_MPE                             0x00000008      /* Magic packet
 220                                                                    detect */
 221 #define MACCFG2_FDX                             0x00000001      /* Full Duplex */
 222 #define MACCFG2_FDX_MASK                        0x00000001      /* Full Duplex
 223                                                                    mask */
 224 #define MACCFG2_PAD_CRC                         0x00000004
 225 #define MACCFG2_CRC_EN                          0x00000002
 226 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000      /* Neither
 227                                                                    Padding
 228                                                                    short frames
 229                                                                    nor CRC */
 230 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002      /* Append CRC
 231                                                                    only */
 232 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
 233 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100      /* nibble mode
 234                                                                    (MII/RMII/RGMII
 235                                                                    10/100bps) */
 236 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200      /* byte mode
 237                                                                    (GMII/TBI/RTB/RGMII
 238                                                                    1000bps ) */
 239 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300      /* mask
 240                                                                    covering all
 241                                                                    relevant
 242                                                                    bits */
 243
 244 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
 245 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 -  7)       /* Non
 246                                                                    back-to-back
 247                                                                    inter frame
 248                                                                    gap part 1.
 249                                                                    << shift */
 250 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)       /* Non
 251                                                                    back-to-back
 252                                                                    inter frame
 253                                                                    gap part 2.
 254                                                                    << shift */
 255 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT    (31 - 23)       /* Mimimum IFG
 256                                                                    Enforcement
 257                                                                    << shift */
 258 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT           (31 - 31)       /* back-to-back
 259                                                                    inter frame
 260                                                                    gap << shift
 261                                                                  */
 262 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX   127     /* Non back-to-back
 263                                                            inter frame gap part
 264                                                            1. max val */
 265 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX   127     /* Non back-to-back
 266                                                            inter frame gap part
 267                                                            2. max val */
 268 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX      255     /* Mimimum IFG
 269                                                            Enforcement max val */
 270 #define IPGIFG_BACK_TO_BACK_IFG_MAX             127     /* back-to-back inter
 271                                                            frame gap max val */
 272 #define IPGIFG_NBTB_CS_IPG_MASK                 0x7F000000
 273 #define IPGIFG_NBTB_IPG_MASK                    0x007F0000
 274 #define IPGIFG_MIN_IFG_MASK                     0x0000FF00
 275 #define IPGIFG_BTB_IPG_MASK                     0x0000007F
 276
 277 /* UCC GETH HAFDUP (Half Duplex Register) */
 278 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT        (31 - 11)       /* Alternate
 279                                                                    Binary
 280                                                                    Exponential
 281                                                                    Backoff
 282                                                                    Truncation
 283                                                                    << shift */
 284 #define HALFDUP_ALT_BEB_TRUNCATION_MAX          0xf     /* Alternate Binary
 285                                                            Exponential Backoff
 286                                                            Truncation max val */
 287 #define HALFDUP_ALT_BEB                         0x00080000      /* Alternate
 288                                                                    Binary
 289                                                                    Exponential
 290                                                                    Backoff */
 291 #define HALFDUP_BACK_PRESSURE_NO_BACKOFF        0x00040000      /* Back
 292                                                                    pressure no
 293                                                                    backoff */
 294 #define HALFDUP_NO_BACKOFF                      0x00020000      /* No Backoff */
 295 #define HALFDUP_EXCESSIVE_DEFER                 0x00010000      /* Excessive
 296                                                                    Defer */
 297 #define HALFDUP_MAX_RETRANSMISSION_SHIFT        (31 - 19)       /* Maximum
 298                                                                    Retransmission
 299                                                                    << shift */
 300 #define HALFDUP_MAX_RETRANSMISSION_MAX          0xf     /* Maximum
 301                                                            Retransmission max
 302                                                            val */
 303 #define HALFDUP_COLLISION_WINDOW_SHIFT          (31 - 31)       /* Collision
 304                                                                    Window <<
 305                                                                    shift */
 306 #define HALFDUP_COLLISION_WINDOW_MAX            0x3f    /* Collision Window max
 307                                                            val */
 308 #define HALFDUP_ALT_BEB_TR_MASK                 0x00F00000
 309 #define HALFDUP_RETRANS_MASK                    0x0000F000
 310 #define HALFDUP_COL_WINDOW_MASK                 0x0000003F
 311
 312 /* UCC GETH UCCS (Ethernet Status Register) */
 313 #define UCCS_BPR                                0x02    /* Back pressure (in
 314                                                            half duplex mode) */
 315 #define UCCS_PAU                                0x02    /* Pause state (in full
 316                                                            duplex mode) */
 317 #define UCCS_MPD                                0x01    /* Magic Packet
 318                                                            Detected */
 319
 320 /* UCC GETH IFSTAT (Interface Status Register) */
 321 #define IFSTAT_EXCESS_DEFER                     0x00000200      /* Excessive
 322                                                                    transmission
 323                                                                    defer */
 324
 325 /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
 326 #define MACSTNADDR1_OCTET_6_SHIFT               (31 -  7)       /* Station
 327                                                                    address 6th
 328                                                                    octet <<
 329                                                                    shift */
 330 #define MACSTNADDR1_OCTET_5_SHIFT               (31 - 15)       /* Station
 331                                                                    address 5th
 332                                                                    octet <<
 333                                                                    shift */
 334 #define MACSTNADDR1_OCTET_4_SHIFT               (31 - 23)       /* Station
 335                                                                    address 4th
 336                                                                    octet <<
 337                                                                    shift */
 338 #define MACSTNADDR1_OCTET_3_SHIFT               (31 - 31)       /* Station
 339                                                                    address 3rd
 340                                                                    octet <<
 341                                                                    shift */
 342
 343 /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
 344 #define MACSTNADDR2_OCTET_2_SHIFT               (31 -  7)       /* Station
 345                                                                    address 2nd
 346                                                                    octet <<
 347                                                                    shift */
 348 #define MACSTNADDR2_OCTET_1_SHIFT               (31 - 15)       /* Station
 349                                                                    address 1st
 350                                                                    octet <<
 351                                                                    shift */
 352
 353 /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
 354 #define UEMPR_PAUSE_TIME_VALUE_SHIFT            (31 - 15)       /* Pause time
 355                                                                    value <<
 356                                                                    shift */
 357 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT   (31 - 31)       /* Extended
 358                                                                    pause time
 359                                                                    value <<
 360                                                                    shift */
 361
 362 /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
 363 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)       /* Phy address
 364                                                                    << shift */
 365 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f      /* Phy address
 366                                                                    mask */
 367
 368 /* UCC GETH UESCR (Ethernet Statistics Control Register) */
 369 #define UESCR_AUTOZ                             0x8000  /* Automatically zero
 370                                                            addressed
 371                                                            statistical counter
 372                                                            values */
 373 #define UESCR_CLRCNT                            0x4000  /* Clear all statistics
 374                                                            counters */
 375 #define UESCR_MAXCOV_SHIFT                      (15 -  7)       /* Max
 376                                                                    Coalescing
 377                                                                    Value <<
 378                                                                    shift */
 379 #define UESCR_SCOV_SHIFT                        (15 - 15)       /* Status
 380                                                                    Coalescing
 381                                                                    Value <<
 382                                                                    shift */
 383
 384 /* UCC GETH UDSR (Data Synchronization Register) */
 385 #define UDSR_MAGIC                              0x067E
 386
 387 struct ucc_geth_thread_data_tx {
 388         u8 res0[104];
 389 } __attribute__ ((packed));
 390
 391 struct ucc_geth_thread_data_rx {
 392         u8 res0[40];
 393 } __attribute__ ((packed));
 394
 395 /* Send Queue Queue-Descriptor */
 396 struct ucc_geth_send_queue_qd {
 397         u32 bd_ring_base;       /* pointer to BD ring base address */
 398         u8 res0[0x8];
 399         u32 last_bd_completed_address;/* initialize to last entry in BD ring */
 400         u8 res1[0x30];
 401 } __attribute__ ((packed));
 402
 403 struct ucc_geth_send_queue_mem_region {
 404         struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
 405 } __attribute__ ((packed));
 406
 407 struct ucc_geth_thread_tx_pram {
 408         u8 res0[64];
 409 } __attribute__ ((packed));
 410
 411 struct ucc_geth_thread_rx_pram {
 412         u8 res0[128];
 413 } __attribute__ ((packed));
 414
 415 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64
 416 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64
 417 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96
 418
 419 struct ucc_geth_scheduler {
 420         u16 cpucount0;          /* CPU packet counter */
 421         u16 cpucount1;          /* CPU packet counter */
 422         u16 cecount0;           /* QE packet counter */
 423         u16 cecount1;           /* QE packet counter */
 424         u16 cpucount2;          /* CPU packet counter */
 425         u16 cpucount3;          /* CPU packet counter */
 426         u16 cecount2;           /* QE packet counter */
 427         u16 cecount3;           /* QE packet counter */
 428         u16 cpucount4;          /* CPU packet counter */
 429         u16 cpucount5;          /* CPU packet counter */
 430         u16 cecount4;           /* QE packet counter */
 431         u16 cecount5;           /* QE packet counter */
 432         u16 cpucount6;          /* CPU packet counter */
 433         u16 cpucount7;          /* CPU packet counter */
 434         u16 cecount6;           /* QE packet counter */
 435         u16 cecount7;           /* QE packet counter */
 436         u32 weightstatus[NUM_TX_QUEUES];        /* accumulated weight factor */
 437         u32 rtsrshadow;         /* temporary variable handled by QE */
 438         u32 time;               /* temporary variable handled by QE */
 439         u32 ttl;                /* temporary variable handled by QE */
 440         u32 mblinterval;        /* max burst length interval */
 441         u16 nortsrbytetime;     /* normalized value of byte time in tsr units */
 442         u8 fracsiz;             /* radix 2 log value of denom. of
 443                                    NorTSRByteTime */
 444         u8 res0[1];
 445         u8 strictpriorityq;     /* Strict Priority Mask register */
 446         u8 txasap;              /* Transmit ASAP register */
 447         u8 extrabw;             /* Extra BandWidth register */
 448         u8 oldwfqmask;          /* temporary variable handled by QE */
 449         u8 weightfactor[NUM_TX_QUEUES];
 450                                       /**< weight factor for queues   */
 451         u32 minw;               /* temporary variable handled by QE */
 452         u8 res1[0x70 - 0x64];
 453 } __attribute__ ((packed));
 454
 455 struct ucc_geth_tx_firmware_statistics_pram {
 456         u32 sicoltx;            /* single collision */
 457         u32 mulcoltx;           /* multiple collision */
 458         u32 latecoltxfr;        /* late collision */
 459         u32 frabortduecol;      /* frames aborted due to transmit collision */
 460         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 461                                    transmission that are not counted on any
 462                                    other counter */
 463         u32 carriersenseertx;   /* carrier sense error */
 464         u32 frtxok;             /* frames transmitted OK */
 465         u32 txfrexcessivedefer; /* frames with defferal time greater than
 466                                    specified threshold */
 467         u32 txpkts256;          /* total packets (including bad) between 256
 468                                    and 511 octets */
 469         u32 txpkts512;          /* total packets (including bad) between 512
 470                                    and 1023 octets */
 471         u32 txpkts1024;         /* total packets (including bad) between 1024
 472                                    and 1518 octets */
 473         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 474                                    and MAXLength octets */
 475 } __attribute__ ((packed));
 476
 477 struct ucc_geth_rx_firmware_statistics_pram {
 478         u32 frrxfcser;          /* frames with crc error */
 479         u32 fraligner;          /* frames with alignment error */
 480         u32 inrangelenrxer;     /* in range length error */
 481         u32 outrangelenrxer;    /* out of range length error */
 482         u32 frtoolong;          /* frame too long */
 483         u32 runt;               /* runt */
 484         u32 verylongevent;      /* very long event */
 485         u32 symbolerror;        /* symbol error */
 486         u32 dropbsy;            /* drop because of BD not ready */
 487         u8 res0[0x8];
 488         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 489                                    or type mismatch) */
 490         u32 underpkts;          /* total frames less than 64 octets */
 491         u32 pkts256;            /* total frames (including bad) between 256 and
 492                                    511 octets */
 493         u32 pkts512;            /* total frames (including bad) between 512 and
 494                                    1023 octets */
 495         u32 pkts1024;           /* total frames (including bad) between 1024
 496                                    and 1518 octets */
 497         u32 pktsjumbo;          /* total frames (including bad) between 1024
 498                                    and MAXLength octets */
 499         u32 frlossinmacer;      /* frames lost because of internal MAC error
 500                                    that is not counted in any other counter */
 501         u32 pausefr;            /* pause frames */
 502         u8 res1[0x4];
 503         u32 removevlan;         /* total frames that had their VLAN tag removed
 504                                  */
 505         u32 replacevlan;        /* total frames that had their VLAN tag
 506                                    replaced */
 507         u32 insertvlan;         /* total frames that had their VLAN tag
 508                                    inserted */
 509 } __attribute__ ((packed));
 510
 511 struct ucc_geth_rx_interrupt_coalescing_entry {
 512         u32 interruptcoalescingmaxvalue;        /* interrupt coalescing max
 513                                                    value */
 514         u32 interruptcoalescingcounter; /* interrupt coalescing counter,
 515                                            initialize to
 516                                            interruptcoalescingmaxvalue */
 517 } __attribute__ ((packed));
 518
 519 struct ucc_geth_rx_interrupt_coalescing_table {
 520         struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
 521                                        /**< interrupt coalescing entry */
 522 } __attribute__ ((packed));
 523
 524 struct ucc_geth_rx_prefetched_bds {
 525         struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS];     /* prefetched bd */
 526 } __attribute__ ((packed));
 527
 528 struct ucc_geth_rx_bd_queues_entry {
 529         u32 bdbaseptr;          /* BD base pointer */
 530         u32 bdptr;              /* BD pointer */
 531         u32 externalbdbaseptr;  /* external BD base pointer */
 532         u32 externalbdptr;      /* external BD pointer */
 533 } __attribute__ ((packed));
 534
 535 struct ucc_geth_tx_global_pram {
 536         u16 temoder;
 537         u8 res0[0x38 - 0x02];
 538         u32 sqptr;              /* a base pointer to send queue memory region */
 539         u32 schedulerbasepointer;       /* a base pointer to scheduler memory
 540                                            region */
 541         u32 txrmonbaseptr;      /* base pointer to Tx RMON statistics counter */
 542         u32 tstate;             /* tx internal state. High byte contains
 543                                    function code */
 544         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
 545         u32 vtagtable[0x8];     /* 8 4-byte VLAN tags */
 546         u32 tqptr;              /* a base pointer to the Tx Queues Memory
 547                                    Region */
 548         u8 res2[0x80 - 0x74];
 549 } __attribute__ ((packed));
 550
 551 /* structure representing Extended Filtering Global Parameters in PRAM */
 552 struct ucc_geth_exf_global_pram {
 553         u32 l2pcdptr;           /* individual address filter, high */
 554         u8 res0[0x10 - 0x04];
 555 } __attribute__ ((packed));
 556
 557 struct ucc_geth_rx_global_pram {
 558         u32 remoder;            /* ethernet mode reg. */
 559         u32 rqptr;              /* base pointer to the Rx Queues Memory Region*/
 560         u32 res0[0x1];
 561         u8 res1[0x20 - 0xC];
 562         u16 typeorlen;          /* cutoff point less than which, type/len field
 563                                    is considered length */
 564         u8 res2[0x1];
 565         u8 rxgstpack;           /* acknowledgement on GRACEFUL STOP RX command*/
 566         u32 rxrmonbaseptr;      /* base pointer to Rx RMON statistics counter */
 567         u8 res3[0x30 - 0x28];
 568         u32 intcoalescingptr;   /* Interrupt coalescing table pointer */
 569         u8 res4[0x36 - 0x34];
 570         u8 rstate;              /* rx internal state. High byte contains
 571                                    function code */
 572         u8 res5[0x46 - 0x37];
 573         u16 mrblr;              /* max receive buffer length reg. */
 574         u32 rbdqptr;            /* base pointer to RxBD parameter table
 575                                    description */
 576         u16 mflr;               /* max frame length reg. */
 577         u16 minflr;             /* min frame length reg. */
 578         u16 maxd1;              /* max dma1 length reg. */
 579         u16 maxd2;              /* max dma2 length reg. */
 580         u32 ecamptr;            /* external CAM address */
 581         u32 l2qt;               /* VLAN priority mapping table. */
 582         u32 l3qt[0x8];          /* IP priority mapping table. */
 583         u16 vlantype;           /* vlan type */
 584         u16 vlantci;            /* default vlan tci */
 585         u8 addressfiltering[64];        /* address filtering data structure */
 586         u32 exfGlobalParam;     /* base address for extended filtering global
 587                                    parameters */
 588         u8 res6[0x100 - 0xC4];  /* Initialize to zero */
 589 } __attribute__ ((packed));
 590
 591 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 592
 593 /* structure representing InitEnet command */
 594 struct ucc_geth_init_pram {
 595         u8 resinit1;
 596         u8 resinit2;
 597         u8 resinit3;
 598         u8 resinit4;
 599         u16 resinit5;
 600         u8 res1[0x1];
 601         u8 largestexternallookupkeysize;
 602         u32 rgftgfrxglobal;
 603         u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX];   /* rx threads */
 604         u8 res2[0x38 - 0x30];
 605         u32 txglobal;           /* tx global */
 606         u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];   /* tx threads */
 607         u8 res3[0x1];
 608 } __attribute__ ((packed));
 609
 610 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
 611 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
 612
 613 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
 614 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
 615 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
 616 #define ENET_INIT_PARAM_SNUM_SHIFT              24
 617
 618 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x06
 619 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0x30
 620 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0xff
 621 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x00
 622 #define ENET_INIT_PARAM_MAGIC_RES_INIT5         0x0400
 623
 624 /* structure representing 82xx Address Filtering Enet Address in PRAM */
 625 struct ucc_geth_82xx_enet_address {
 626         u8 res1[0x2];
 627         u16 h;                  /* address (MSB) */
 628         u16 m;                  /* address */
 629         u16 l;                  /* address (LSB) */
 630 } __attribute__ ((packed));
 631
 632 /* structure representing 82xx Address Filtering PRAM */
 633 struct ucc_geth_82xx_address_filtering_pram {
 634         u32 iaddr_h;            /* individual address filter, high */
 635         u32 iaddr_l;            /* individual address filter, low */
 636         u32 gaddr_h;            /* group address filter, high */
 637         u32 gaddr_l;            /* group address filter, low */
 638         struct ucc_geth_82xx_enet_address __iomem taddr;
 639         struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
 640         u8 res0[0x40 - 0x38];
 641 } __attribute__ ((packed));
 642
 643 /* GETH Tx firmware statistics structure, used when calling
 644    UCC_GETH_GetStatistics. */
 645 struct ucc_geth_tx_firmware_statistics {
 646         u32 sicoltx;            /* single collision */
 647         u32 mulcoltx;           /* multiple collision */
 648         u32 latecoltxfr;        /* late collision */
 649         u32 frabortduecol;      /* frames aborted due to transmit collision */
 650         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 651                                    transmission that are not counted on any
 652                                    other counter */
 653         u32 carriersenseertx;   /* carrier sense error */
 654         u32 frtxok;             /* frames transmitted OK */
 655         u32 txfrexcessivedefer; /* frames with defferal time greater than
 656                                    specified threshold */
 657         u32 txpkts256;          /* total packets (including bad) between 256
 658                                    and 511 octets */
 659         u32 txpkts512;          /* total packets (including bad) between 512
 660                                    and 1023 octets */
 661         u32 txpkts1024;         /* total packets (including bad) between 1024
 662                                    and 1518 octets */
 663         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 664                                    and MAXLength octets */
 665 } __attribute__ ((packed));
 666
 667 /* GETH Rx firmware statistics structure, used when calling
 668    UCC_GETH_GetStatistics. */
 669 struct ucc_geth_rx_firmware_statistics {
 670         u32 frrxfcser;          /* frames with crc error */
 671         u32 fraligner;          /* frames with alignment error */
 672         u32 inrangelenrxer;     /* in range length error */
 673         u32 outrangelenrxer;    /* out of range length error */
 674         u32 frtoolong;          /* frame too long */
 675         u32 runt;               /* runt */
 676         u32 verylongevent;      /* very long event */
 677         u32 symbolerror;        /* symbol error */
 678         u32 dropbsy;            /* drop because of BD not ready */
 679         u8 res0[0x8];
 680         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 681                                    or type mismatch) */
 682         u32 underpkts;          /* total frames less than 64 octets */
 683         u32 pkts256;            /* total frames (including bad) between 256 and
 684                                    511 octets */
 685         u32 pkts512;            /* total frames (including bad) between 512 and
 686                                    1023 octets */
 687         u32 pkts1024;           /* total frames (including bad) between 1024
 688                                    and 1518 octets */
 689         u32 pktsjumbo;          /* total frames (including bad) between 1024
 690                                    and MAXLength octets */
 691         u32 frlossinmacer;      /* frames lost because of internal MAC error
 692                                    that is not counted in any other counter */
 693         u32 pausefr;            /* pause frames */
 694         u8 res1[0x4];
 695         u32 removevlan;         /* total frames that had their VLAN tag removed
 696                                  */
 697         u32 replacevlan;        /* total frames that had their VLAN tag
 698                                    replaced */
 699         u32 insertvlan;         /* total frames that had their VLAN tag
 700                                    inserted */
 701 } __attribute__ ((packed));
 702
 703 /* GETH hardware statistics structure, used when calling
 704    UCC_GETH_GetStatistics. */
 705 struct ucc_geth_hardware_statistics {
 706         u32 tx64;               /* Total number of frames (including bad
 707                                    frames) transmitted that were exactly of the
 708                                    minimal length (64 for un tagged, 68 for
 709                                    tagged, or with length exactly equal to the
 710                                    parameter MINLength */
 711         u32 tx127;              /* Total number of frames (including bad
 712                                    frames) transmitted that were between
 713                                    MINLength (Including FCS length==4) and 127
 714                                    octets */
 715         u32 tx255;              /* Total number of frames (including bad
 716                                    frames) transmitted that were between 128
 717                                    (Including FCS length==4) and 255 octets */
 718         u32 rx64;               /* Total number of frames received including
 719                                    bad frames that were exactly of the mninimal
 720                                    length (64 bytes) */
 721         u32 rx127;              /* Total number of frames (including bad
 722                                    frames) received that were between MINLength
 723                                    (Including FCS length==4) and 127 octets */
 724         u32 rx255;              /* Total number of frames (including bad
 725                                    frames) received that were between 128
 726                                    (Including FCS length==4) and 255 octets */
 727         u32 txok;               /* Total number of octets residing in frames
 728                                    that where involved in succesfull
 729                                    transmission */
 730         u16 txcf;               /* Total number of PAUSE control frames
 731                                    transmitted by this MAC */
 732         u32 tmca;               /* Total number of frames that were transmitted
 733                                    succesfully with the group address bit set
 734                                    that are not broadcast frames */
 735         u32 tbca;               /* Total number of frames transmitted
 736                                    succesfully that had destination address
 737                                    field equal to the broadcast address */
 738         u32 rxfok;              /* Total number of frames received OK */
 739         u32 rxbok;              /* Total number of octets received OK */
 740         u32 rbyt;               /* Total number of octets received including
 741                                    octets in bad frames. Must be implemented in
 742                                    HW because it includes octets in frames that
 743                                    never even reach the UCC */
 744         u32 rmca;               /* Total number of frames that were received
 745                                    succesfully with the group address bit set
 746                                    that are not broadcast frames */
 747         u32 rbca;               /* Total number of frames received succesfully
 748                                    that had destination address equal to the
 749                                    broadcast address */
 750 } __attribute__ ((packed));
 751
 752 /* UCC GETH Tx errors returned via TxConf callback */
 753 #define TX_ERRORS_DEF      0x0200
 754 #define TX_ERRORS_EXDEF    0x0100
 755 #define TX_ERRORS_LC       0x0080
 756 #define TX_ERRORS_RL       0x0040
 757 #define TX_ERRORS_RC_MASK  0x003C
 758 #define TX_ERRORS_RC_SHIFT 2
 759 #define TX_ERRORS_UN       0x0002
 760 #define TX_ERRORS_CSL      0x0001
 761
 762 /* UCC GETH Rx errors returned via RxStore callback */
 763 #define RX_ERRORS_CMR      0x0200
 764 #define RX_ERRORS_M        0x0100
 765 #define RX_ERRORS_BC       0x0080
 766 #define RX_ERRORS_MC       0x0040
 767
 768 /* Transmit BD. These are in addition to values defined in uccf. */
 769 #define T_VID      0x003c0000   /* insert VLAN id index mask. */
 770 #define T_DEF      (((u32) TX_ERRORS_DEF     ) << 16)
 771 #define T_EXDEF    (((u32) TX_ERRORS_EXDEF   ) << 16)
 772 #define T_LC       (((u32) TX_ERRORS_LC      ) << 16)
 773 #define T_RL       (((u32) TX_ERRORS_RL      ) << 16)
 774 #define T_RC_MASK  (((u32) TX_ERRORS_RC_MASK ) << 16)
 775 #define T_UN       (((u32) TX_ERRORS_UN      ) << 16)
 776 #define T_CSL      (((u32) TX_ERRORS_CSL     ) << 16)
 777 #define T_ERRORS_REPORT  (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
 778                 | T_UN | T_CSL) /* transmit errors to report */
 779
 780 /* Receive BD. These are in addition to values defined in uccf. */
 781 #define R_LG    0x00200000      /* Frame length violation.  */
 782 #define R_NO    0x00100000      /* Non-octet aligned frame.  */
 783 #define R_SH    0x00080000      /* Short frame.  */
 784 #define R_CR    0x00040000      /* CRC error.  */
 785 #define R_OV    0x00020000      /* Overrun.  */
 786 #define R_IPCH  0x00010000      /* IP checksum check failed. */
 787 #define R_CMR   (((u32) RX_ERRORS_CMR  ) << 16)
 788 #define R_M     (((u32) RX_ERRORS_M    ) << 16)
 789 #define R_BC    (((u32) RX_ERRORS_BC   ) << 16)
 790 #define R_MC    (((u32) RX_ERRORS_MC   ) << 16)
 791 #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC)     /* receive errors to
 792                                                            report */
 793 #define R_ERRORS_FATAL  (R_LG  | R_NO | R_SH | R_CR | \
 794                 R_OV | R_IPCH)  /* receive errors to discard */
 795
 796 /* Alignments */
 797 #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT       256
 798 #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT       128
 799 #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT       128
 800 #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT       64
 801 #define UCC_GETH_THREAD_DATA_ALIGNMENT          256     /* spec gives values
 802                                                            based on num of
 803                                                            threads, but always
 804                                                            using the maximum is
 805                                                            easier */
 806 #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT  32
 807 #define UCC_GETH_SCHEDULER_ALIGNMENT            4       /* This is a guess */
 808 #define UCC_GETH_TX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 809 #define UCC_GETH_RX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 810 #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT      64
 811 #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT         8       /* This is a guess */
 812 #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT    128     /* This is a guess */
 813 #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4    /* This
 814                                                                            is a
 815                                                                            guess
 816                                                                          */
 817 #define UCC_GETH_RX_BD_RING_ALIGNMENT           32
 818 #define UCC_GETH_TX_BD_RING_ALIGNMENT           32
 819 #define UCC_GETH_MRBLR_ALIGNMENT                128
 820 #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT      4
 821 #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT       32
 822 #define UCC_GETH_RX_DATA_BUF_ALIGNMENT          64
 823
 824 #define UCC_GETH_TAD_EF                         0x80
 825 #define UCC_GETH_TAD_V                          0x40
 826 #define UCC_GETH_TAD_REJ                        0x20
 827 #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT        2
 828 #define UCC_GETH_TAD_VTAG_OP_SHIFT              6
 829 #define UCC_GETH_TAD_V_NON_VTAG_OP              0x20
 830 #define UCC_GETH_TAD_RQOS_SHIFT                 0
 831 #define UCC_GETH_TAD_V_PRIORITY_SHIFT           5
 832 #define UCC_GETH_TAD_CFI                        0x10
 833
 834 #define UCC_GETH_VLAN_PRIORITY_MAX              8
 835 #define UCC_GETH_IP_PRIORITY_MAX                64
 836 #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX        8
 837 #define UCC_GETH_RX_BD_RING_SIZE_MIN            8
 838 #define UCC_GETH_TX_BD_RING_SIZE_MIN            2
 839 #define UCC_GETH_BD_RING_SIZE_MAX               0xffff
 840
 841 #define UCC_GETH_SIZE_OF_BD                     QE_SIZEOF_BD
 842
 843 /* Driver definitions */
 844 #define TX_BD_RING_LEN                          0x10
 845 #define RX_BD_RING_LEN                          0x10
 846 #define UCC_GETH_DEV_WEIGHT                     TX_BD_RING_LEN
 847
 848 #define TX_RING_MOD_MASK(size)                  (size-1)
 849 #define RX_RING_MOD_MASK(size)                  (size-1)
 850
 851 #define ENET_NUM_OCTETS_PER_ADDRESS             6
 852 #define ENET_GROUP_ADDR                         0x01    /* Group address mask
 853                                                            for ethernet
 854                                                            addresses */
 855
 856 #define TX_TIMEOUT                              (1*HZ)
 857 #define SKB_ALLOC_TIMEOUT                       100000
 858 #define PHY_INIT_TIMEOUT                        100000
 859 #define PHY_CHANGE_TIME                         2
 860
 861 /* Fast Ethernet (10/100 Mbps) */
 862 #define UCC_GETH_URFS_INIT                      512     /* Rx virtual FIFO size
 863                                                          */
 864 #define UCC_GETH_URFET_INIT                     256     /* 1/2 urfs */
 865 #define UCC_GETH_URFSET_INIT                    384     /* 3/4 urfs */
 866 #define UCC_GETH_UTFS_INIT                      512     /* Tx virtual FIFO size
 867                                                          */
 868 #define UCC_GETH_UTFET_INIT                     256     /* 1/2 utfs */
 869 #define UCC_GETH_UTFTT_INIT                     128
 870 /* Gigabit Ethernet (1000 Mbps) */
 871 #define UCC_GETH_URFS_GIGA_INIT                 4096/*2048*/    /* Rx virtual
 872                                                                    FIFO size */
 873 #define UCC_GETH_URFET_GIGA_INIT                2048/*1024*/    /* 1/2 urfs */
 874 #define UCC_GETH_URFSET_GIGA_INIT               3072/*1536*/    /* 3/4 urfs */
 875 #define UCC_GETH_UTFS_GIGA_INIT                 8192/*2048*/    /* Tx virtual
 876                                                                    FIFO size */
 877 #define UCC_GETH_UTFET_GIGA_INIT                4096/*1024*/    /* 1/2 utfs */
 878 #define UCC_GETH_UTFTT_GIGA_INIT                0x400/*0x40*/   /* */
 879
 880 #define UCC_GETH_REMODER_INIT                   0       /* bits that must be
 881                                                            set */
 882 #define UCC_GETH_TEMODER_INIT                   0xC000  /* bits that must */
 883
 884 /* Initial value for UPSMR */
 885 #define UCC_GETH_UPSMR_INIT                     UCC_GETH_UPSMR_RES1
 886
 887 #define UCC_GETH_MACCFG1_INIT                   0
 888 #define UCC_GETH_MACCFG2_INIT                   (MACCFG2_RESERVED_1)
 889
 890 /* Ethernet Address Type. */
 891 enum enet_addr_type {
 892         ENET_ADDR_TYPE_INDIVIDUAL,
 893         ENET_ADDR_TYPE_GROUP,
 894         ENET_ADDR_TYPE_BROADCAST
 895 };
 896
 897 /* UCC GETH 82xx Ethernet Address Recognition Location */
 898 enum ucc_geth_enet_address_recognition_location {
 899         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
 900                                                                       address */
 901         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
 902                                                                    station
 903                                                                    address
 904                                                                    paddr1 */
 905         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2,      /* additional
 906                                                                    station
 907                                                                    address
 908                                                                    paddr2 */
 909         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3,      /* additional
 910                                                                    station
 911                                                                    address
 912                                                                    paddr3 */
 913         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST,  /* additional
 914                                                                    station
 915                                                                    address
 916                                                                    paddr4 */
 917         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,  /* group hash */
 918         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
 919                                                                       hash */
 920 };
 921
 922 /* UCC GETH vlan operation tagged */
 923 enum ucc_geth_vlan_operation_tagged {
 924         UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,       /* Tagged - nop */
 925         UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
 926                 = 0x1,  /* Tagged - replace vid portion of q tag */
 927         UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
 928                 = 0x2,  /* Tagged - if vid0 replace vid with default value  */
 929         UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
 930                 = 0x3   /* Tagged - extract q tag from frame */
 931 };
 932
 933 /* UCC GETH vlan operation non-tagged */
 934 enum ucc_geth_vlan_operation_non_tagged {
 935         UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,   /* Non tagged - nop */
 936         UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1   /* Non tagged -
 937                                                                    q tag insert
 938                                                                  */
 939 };
 940
 941 /* UCC GETH Rx Quality of Service Mode */
 942 enum ucc_geth_qos_mode {
 943         UCC_GETH_QOS_MODE_DEFAULT = 0x0,        /* default queue */
 944         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1,     /* queue
 945                                                                    determined
 946                                                                    by L2
 947                                                                    criteria */
 948         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2      /* queue
 949                                                                    determined
 950                                                                    by L3
 951                                                                    criteria */
 952 };
 953
 954 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
 955    for combined functionality */
 956 enum ucc_geth_statistics_gathering_mode {
 957         UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,   /* No
 958                                                                    statistics
 959                                                                    gathering */
 960         UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
 961                                                                     hardware
 962                                                                     statistics
 963                                                                     gathering
 964                                                                   */
 965         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
 966                                                                       firmware
 967                                                                       tx
 968                                                                       statistics
 969                                                                       gathering
 970                                                                      */
 971         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
 972                                                                       firmware
 973                                                                       rx
 974                                                                       statistics
 975                                                                       gathering
 976                                                                     */
 977 };
 978
 979 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
 980 enum ucc_geth_maccfg2_pad_and_crc_mode {
 981         UCC_GETH_PAD_AND_CRC_MODE_NONE
 982                 = MACCFG2_PAD_AND_CRC_MODE_NONE,        /* Neither Padding
 983                                                            short frames
 984                                                            nor CRC */
 985         UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
 986                 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY,    /* Append
 987                                                            CRC only */
 988         UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
 989             MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
 990 };
 991
 992 /* UCC GETH upsmr Flow Control Mode */
 993 enum ucc_geth_flow_control_mode {
 994         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,    /* No automatic
 995                                                                    flow control
 996                                                                  */
 997         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
 998                 = 0x00004000    /* Send pause frame when RxFIFO reaches its
 999                                    emergency threshold */
1000 };
1001
1002 /* UCC GETH number of threads */
1003 enum ucc_geth_num_of_threads {
1004         UCC_GETH_NUM_OF_THREADS_1 = 0x1,        /* 1 */
1005         UCC_GETH_NUM_OF_THREADS_2 = 0x2,        /* 2 */
1006         UCC_GETH_NUM_OF_THREADS_4 = 0x0,        /* 4 */
1007         UCC_GETH_NUM_OF_THREADS_6 = 0x3,        /* 6 */
1008         UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1009 };
1010
1011 /* UCC GETH number of station addresses */
1012 enum ucc_geth_num_of_station_addresses {
1013         UCC_GETH_NUM_OF_STATION_ADDRESSES_1,    /* 1 */
1014         UCC_GETH_NUM_OF_STATION_ADDRESSES_5     /* 5 */
1015 };
1016
1017 /* UCC GETH 82xx Ethernet Address Container */
1018 struct enet_addr_container {
1019         u8 address[ENET_NUM_OCTETS_PER_ADDRESS];        /* ethernet address */
1020         enum ucc_geth_enet_address_recognition_location location;       /* location in
1021                                                                    82xx address
1022                                                                    recognition
1023                                                                    hardware */
1024         struct list_head node;
1025 };
1026
1027 #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1028
1029 /* UCC GETH Termination Action Descriptor (TAD) structure. */
1030 struct ucc_geth_tad_params {
1031         int rx_non_dynamic_extended_features_mode;
1032         int reject_frame;
1033         enum ucc_geth_vlan_operation_tagged vtag_op;
1034         enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1035         enum ucc_geth_qos_mode rqos;
1036         u8 vpri;
1037         u16 vid;
1038 };
1039
1040 /* GETH protocol initialization structure */
1041 struct ucc_geth_info {
1042         struct ucc_fast_info uf_info;
1043         u8 numQueuesTx;
1044         u8 numQueuesRx;
1045         int ipCheckSumCheck;
1046         int ipCheckSumGenerate;
1047         int rxExtendedFiltering;
1048         u32 extendedFilteringChainPointer;
1049         u16 typeorlen;
1050         int dynamicMaxFrameLength;
1051         int dynamicMinFrameLength;
1052         u8 nonBackToBackIfgPart1;
1053         u8 nonBackToBackIfgPart2;
1054         u8 miminumInterFrameGapEnforcement;
1055         u8 backToBackInterFrameGap;
1056         int ipAddressAlignment;
1057         int lengthCheckRx;
1058         u32 mblinterval;
1059         u16 nortsrbytetime;
1060         u8 fracsiz;
1061         u8 strictpriorityq;
1062         u8 txasap;
1063         u8 extrabw;
1064         int miiPreambleSupress;
1065         u8 altBebTruncation;
1066         int altBeb;
1067         int backPressureNoBackoff;
1068         int noBackoff;
1069         int excessDefer;
1070         u8 maxRetransmission;
1071         u8 collisionWindow;
1072         int pro;
1073         int cap;
1074         int rsh;
1075         int rlpb;
1076         int cam;
1077         int bro;
1078         int ecm;
1079         int receiveFlowControl;
1080         int transmitFlowControl;
1081         u8 maxGroupAddrInHash;
1082         u8 maxIndAddrInHash;
1083         u8 prel;
1084         u16 maxFrameLength;
1085         u16 minFrameLength;
1086         u16 maxD1Length;
1087         u16 maxD2Length;
1088         u16 vlantype;
1089         u16 vlantci;
1090         u32 ecamptr;
1091         u32 eventRegMask;
1092         u16 pausePeriod;
1093         u16 extensionField;
1094         u8 phy_address;
1095         char mdio_bus[MII_BUS_ID_SIZE];
1096         u8 weightfactor[NUM_TX_QUEUES];
1097         u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1098         u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1099         u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1100         u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1101         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1102         u16 bdRingLenTx[NUM_TX_QUEUES];
1103         u16 bdRingLenRx[NUM_RX_QUEUES];
1104         enum ucc_geth_num_of_station_addresses numStationAddresses;
1105         enum qe_fltr_largest_external_tbl_lookup_key_size
1106             largestexternallookupkeysize;
1107         enum ucc_geth_statistics_gathering_mode statisticsMode;
1108         enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1109         enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1110         enum ucc_geth_qos_mode rxQoSMode;
1111         enum ucc_geth_flow_control_mode aufc;
1112         enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1113         enum ucc_geth_num_of_threads numThreadsTx;
1114         enum ucc_geth_num_of_threads numThreadsRx;
1115         enum qe_risc_allocation riscTx;
1116         enum qe_risc_allocation riscRx;
1117 };
1118
1119 /* structure representing UCC GETH */
1120 struct ucc_geth_private {
1121         struct ucc_geth_info *ug_info;
1122         struct ucc_fast_private *uccf;
1123         struct net_device *dev;
1124         struct napi_struct napi;
1125         struct work_struct timeout_work;
1126         struct ucc_geth __iomem *ug_regs;
1127         struct ucc_geth_init_pram *p_init_enet_param_shadow;
1128         struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1129         u32 exf_glbl_param_offset;
1130         struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1131         u32 rx_glbl_pram_offset;
1132         struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1133         u32 tx_glbl_pram_offset;
1134         struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1135         u32 send_q_mem_reg_offset;
1136         struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1137         u32 thread_dat_tx_offset;
1138         struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1139         u32 thread_dat_rx_offset;
1140         struct ucc_geth_scheduler __iomem *p_scheduler;
1141         u32 scheduler_offset;
1142         struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1143         u32 tx_fw_statistics_pram_offset;
1144         struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1145         u32 rx_fw_statistics_pram_offset;
1146         struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1147         u32 rx_irq_coalescing_tbl_offset;
1148         struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1149         u32 rx_bd_qs_tbl_offset;
1150         u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1151         u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1152         u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1153         u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1154         u8 __iomem *confBd[NUM_TX_QUEUES];
1155         u8 __iomem *txBd[NUM_TX_QUEUES];
1156         u8 __iomem *rxBd[NUM_RX_QUEUES];
1157         int badFrame[NUM_RX_QUEUES];
1158         u16 cpucount[NUM_TX_QUEUES];
1159         u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1160         int indAddrRegUsed[NUM_OF_PADDRS];
1161         u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS];   /* ethernet address */
1162         u8 numGroupAddrInHash;
1163         u8 numIndAddrInHash;
1164         u8 numIndAddrInReg;
1165         int rx_extended_features;
1166         int rx_non_dynamic_extended_features;
1167         struct list_head conf_skbs;
1168         struct list_head group_hash_q;
1169         struct list_head ind_hash_q;
1170         u32 saved_uccm;
1171         spinlock_t lock;
1172         /* pointers to arrays of skbuffs for tx and rx */
1173         struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1174         struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1175         /* indices pointing to the next free sbk in skb arrays */
1176         u16 skb_curtx[NUM_TX_QUEUES];
1177         u16 skb_currx[NUM_RX_QUEUES];
1178         /* index of the first skb which hasn't been transmitted yet. */
1179         u16 skb_dirtytx[NUM_TX_QUEUES];
1180
1181         struct ugeth_mii_info *mii_info;
1182         struct phy_device *phydev;
1183         phy_interface_t phy_interface;
1184         int max_speed;
1185         uint32_t msg_enable;
1186         int oldspeed;
1187         int oldduplex;
1188         int oldlink;
1189
1190         struct device_node *node;
1191 };
1192
1193 void uec_set_ethtool_ops(struct net_device *netdev);
1194 int init_flow_control_params(u32 automatic_flow_control_mode,
1195                 int rx_flow_control_enable, int tx_flow_control_enable,
1196                 u16 pause_period, u16 extension_field,
1197                 u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1198                 u32 __iomem *maccfg1_register);
1199
1200
1201 #endif                          /* __UCC_GETH_H__ */